PRELIMINARY CM3121 Dual Linear Voltage Regulator for DDR-I and DDR-II Memory Features Product Description • The CM3121 provides an integrated power solution for DDR-I and DDR-II memory systems in consumer electronics applications. The CM3121 is ideal for a 2.8V to 3.6V supply for DDR-I memory and 2.2V to 2.8V for DDR-II memory. The CM3121 features two independent linear regulators for VDDQ and VTT supply regulation. The default voltage for VDDQ is 2.5V. The VDDQ regulator SENSE pin allows for setting VDDQ in the 2.2V to 2.8V range, or DDR-II memories from 1.7V to 1.9V. The VTT regulator output is always half the VDDQ voltage, derived internally. A capacitor should be connected to each of the two outputs. • • • • • • • Fully integrated power solution for DDR memory ICs Ideal for DDR-I (2.5VDDQ) and DDR-II (1.8VDDQ) Lowest system cost and smallest footprint with just two external output capacitors Two linear regulators: - VDDQ regulator with a maximum output current of 1.5A shared by DRAM and VTT regulator - source-sink VTT regulator with maximum output current of 0.5A (DDR-I) or 0.3A (DDR-II) Fault output indicates overcurrent condition in either regulator, under voltage lock-out and overtemperature condition Reverse current protection if host is powered off PSOP-8 package with integrated heat spreader Lead-free versions available Applications • When EN_DDR is set high, the two DDR regulators are disabled to minimize overall system power dissipation such as when memory is in standby. The FAULT pin goes low whenever either of the two regulators goes into current limit mode, the input voltage drops too far or if overtemp occurs. The CM3121 is available in a PSOP-8 package that has excellent thermal dissipation. It is available with optional lead-free finishing. DDR-I and DDR-II memory power for: − Set Top Boxes, DVD Players, Games − Digital TVs, Flat Panel Displays − Printers, Digital Projectors − Embedded systems − Communications systems . Typical Application Circuit Circuit Schematic 2.8V to 3.3V VCC VDDQ REGULATOR VCC CCC Enable DDR Memory # VREF VREF VDDQ REGULATOR VDDQ SENSE VDDQ EN_DDR VDDQ VDDQ = 2.5V SENSE VDDQ EN_DDR CDDQ DDR MEMORY R VTT R VTT=1.25V SENSE VTT CURRENT LIMIT OVERTEMP LOW INPUT VTT R SENSE VTT CTT FAULT CPU CORE + I/O SENSE_ VDDQ VTT REGULATOR R VTT REGULATOR VDDQ CURRENT LIMIT OVERTEMP LOW INPUT VTT SENSE_VTT FAULT GND GND © 2004 California Micro Devices Corp. All rights reserved. 11/12/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 1 PRELIMINARY CM3121 Functional Description The CM3121 provides power for DDR-I/DDR-II memories from two voltage regulators on-chip. There is an over-temperature thermal shutdown if any of the regulators overheat. Each regulator also has reverse current protection in the event of any being shut down. The VDDQ linear regulator can provide 2.5V/1.8V for DDR-I/-II memory at up to 1.5A. An external feedback resistor divider R1 and R2, when connected to the SENSE_VDDQ pin, enables selection of VDDQ output voltages from 2.2V to 2.8V for use with DDR-I memories requiring other than 2.5V for VDDQ (see Figure 5). In this mode, the voltage on VDDQ is detemined as follows: (R1+R2) VDDQ = 1.25V x ---------------------R2 When SENSE_VDDQ is connected to GND or left open, VDDQ is fixed at 2.50V (and VTT at 1.25V). For DDR-II operation, VDDQ can be set from 1.7V to 1.9V. The VTT regulator is a linear source-sink regulator powered from the VDDQ output that supplies the VTT supply required by DDR-I memory termination resistors. This regulator sinks or sources up to 0.5A. The VTT output voltage accurately tracks VDDQ/2 to 1%. When there is no VCC provided, VTT is powered down and its output is 0V. This regulator has overload current limiting of 0.6A minimum. The EN_DDR pin when set active low enables the CM3121 to operate in normal mode with VDDQ and VTT active. When EN_DDR is high, the CM3121 is disabled and both VDDQ and VTT are set to 0V. The FAULT output is normally at logic high but when an overcurrent occurs on either VDDQ or VTT outputs, FAULT goes active low, and remains low as long as the overcurrent fault persists. Also if the chip goes into thermal overload, or the input voltage VCC drops sufficiently that the chip goes into Under Voltage Lock-Out mode (UVLO), FAULT goes active low, and remains low as long as the condition persists. PACKAGE / PINOUT DIAGRAM TOP VIEW VCC 1 8 SENSE_VDDQ VDDQ 2 7 FAULT VTT 3 6 SENSE_VTT GND 4 5 EN_DDR 8-Lead PSOP Note: This drawing is not to scale. PIN DESCRIPTIONS LEAD NAME 1 VCC Input supply. 2 VDDQ VDDQ output. 3 VTT 4 GND 5 EN_DDR 6 SENSE_VTT 7 FAULT 8 SENSE_VDDQ PAD GND DESCRIPTION VTT output for termination resistors or VREF Ground reference. Enable DDR power. Active low input. Sense input for VTT rail adjustment. Overcurrent Fault / UVLO indication, active low output. Sense input for VDDQ rail adjustment. Tied to ground reference. © 2004 California Micro Devices Corp. All rights reserved. 2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 11/12/04 PRELIMINARY CM3121 Ordering Information PART NUMBERING INFORMATION Standard Finish Leads Package Ordering Part Number1 8 PSOP-8 CM3121-02SB Lead-free Finish Part Marking Ordering Part Number1 Part Marking CM3121 02SB CM3121-02SH CM3121 02SH Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS ±2000 V [GND - 0.6] to [+6.5] [GND - 0.6] to [VCC + 0.6] V V Storage Temperature Range -40 to +150 °C Operating Temperature Range Ambient Junction -40 to +85 0 to +125 °C °C ESD (Human Body Model) Pin Voltages VCC EN_DDR, SENSE_VDDQ, SENSE_VTT STANDARD OPERATING CONDITIONS PARAMETER RATING UNITS -40 to +85 °C DDR-I Supply Voltage VCC [VDDQ + 0.3] to 3.6 V DDR-II Supply Voltage VCC 2.2 to 2.8 V Load Current (note 1) 0 to 1500 mA 10, 10 µF DDR-I Supply Voltage VDDQ 2.3 to 2.8 V DDR-II Supply Voltage VDDQ 1.7 to 1.9 V DDR-I Load Current 0 to ±500 mA DDR-II Load Current 0 to ±300 mA 47 µF Ambient Operating Temperature Range 1. VDDQ Regulator CCC, CDDQ 2. VTT Regulator CTT Note 1: The VDDQ regulator provides power for both the memory load and the VTT regulator, supplying a total of 1.5A to the VDDQ and VTT outputs. For example, if the VDDQ load current is 1.2A, then the maximum VTT load current will be 0.3A, regardless of the actual VTT output current rating. © 2004 California Micro Devices Corp. All rights reserved. 11/12/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 3 PRELIMINARY CM3121 Specifications (cont’d) DDR-I Specifications ELECTRICAL OPERATING CHARACTERISTICS SYMBOL PARAMETER CONDITIONS (SEE NOTE1) MIN TYP MAX UNITS - 150 - °C - 25 - °C General Parameters TOVER Shutdown Junction Temperature THYST Junction Temp Hysterisis IC in shutdown ICCN Normal Mode VCC Supply Current EN_DDR = logic "0", EN_CORE =logic "0" 700 1100 µA ICCQ Shutdown Mode VCC Supply Current EN_DDR = logic "1", VDDQ = 0V, VTT = 0V 2 10 µA VIH EN_DDR Input High Threshold VCC =3.3V VIL EN_DDR Input Low Threshold VCC =3.3V 0.4 V UVLO Under Voltage Lock-Out IDDQ = 10mA 1.8 V tRISE VDDQ Rise TIme VCC = 3.3V, CDDQ = 10µF 2.0 V 0.5 ms VDDQ Regulator Parameters Input Voltage VDDQ = 2.5V, IDDQ = 1.5A, SENSE_VDDQ = 0V, Note 2 2.80 VDDQ DEF Default Output Voltage Range IDDQ = 0.01A, 2.8V ≤ VCC ≤ 3.6V, SENSE_VDDQ = 0V, Note 2 2.45 VDDQ ADJ Adjustable Output Voltage Range VCC = 3.6V, SENSE_VDDQ tied to external resistors R1 and R2, Note 2 1.6 VDDQ LD Load Regulation TA = 25°C, VCC = 3.3V, VDDQ LINE Line Regulation VCC MIN V 2.50 2.55 V 2.8 V - - 2.5 % -1.0 - 1.0 % 0.01A ≤ IDDQ ≤ 1.0A, Note 2 TA = 25°C, IDDQ = 0.01A, 2.8V ≤ VCC ≤ 3.6V, Note 2 eN DDQ Output Noise Voltage BW = 10Hz - 100kHz, CDDQ = 10µF IDDQ LIM Current Limit Note 2 IDDQ SC Short Circuit Current VDDQ < 0.3V 1.7 49 µVrms 2.0 A 0.5 A www.calmicro.com 11/12/04 © 2004 California Micro Devices Corp. All rights reserved. 4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● PRELIMINARY CM3121 ELECTRICAL OPERATING CHARACTERISTICS (CONT’D) (SEE NOTE1) VTT Regulator Parameters VTT Output Voltage Range VDDQ = 2.5V, ITT = 0.01A, 1.20 1.25 1.30 V VTT REF Output Voltage Range VDDQ = 2.500V, ITT = 0.01A 1.225 1.250 1.275 V VTT LD Load Regulation TA = 25°C, VDDQ = 2.5V, -1.0 - 1.0 % VTT LINE Line Regulation TA = 25°C, ITT = 0.01A, -1.0 - 1.0 % 0.01A ≤ ITT ≤ ±0.5A 2.8V ≤ VCC ≤ 3.6V, Note 2 eN TT Output Noise Voltage ITT LIM Current Limit ITT SC Short Circuit Current BW = 10Hz - 100kHz, CTT = 10µF 0.6 VTT < 0.3V 51 µVrms 0.8 A 0.3 A Note 1: All parameters specified at TA = -40°C to +85°C unless otherwise noted. Note 2: Note that the IDDQ current specified is the load current output from the VDDQ pin. VDDQ also supplies current internally to the VTT regulator when it is sourcing current. The maximum source current can be up to 0.5A. So the maximum total current from the VDDQ regulator is the external VDDQ current IDDQ added to the maximum VTT sourcing current ITT. All load currents are specified as such, but the VDDQ current limit is specified at a current just above the total maximum current. DDR-II Specifications ELECTRICAL OPERATING CHARACTERISTICS SYMBOL PARAMETER CONDITIONS (SEE NOTE 3) MIN TYP MAX UNITS - 150 - °C - 25 - °C General Parameters TOVER Shutdown Junction Temperature THYST Junction Temp Hysterisis IC in shutdown ICCN Normal Mode VCC Supply Current EN_DDR = logic "0", 700 1100 µA ICCQ Shutdown Mode VCC Supply Current EN_DDR = logic "1", VDDQ = 0V, VTT = 0V 2 10 µA VIH EN_DDR Input High Threshold VCC =3.3V VIL EN_DDR Input Low Threshold VCC =3.3V 0.4 V UVLO Under Voltage Lock-Out IDDQ = 10mA 1.8 V tRISE VDDQ Rise TIme VCC = 3.3V, CDDQ = 10µF 2.0 V 0.5 ms © 2004 California Micro Devices Corp. All rights reserved. 11/12/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 5 PRELIMINARY CM3121 ELECTRICAL OPERATING CHARACTERISTICS (CONT’D) (SEE NOTE 3) VDDQ Regulator Parameters Input Voltage VDDQ = 2.5V, IDDQ = 1.5A, SENSE_VDDQ = 0V, Note 4 2.2 Default Output Voltage Range IDDQ = 0.01A,VCC = 3.3V, SENSE_VDDQ = 0V, Note 4 1.75 VDDQ ADJ Adjustable Output Voltage Range VCC = 3.3V, SENSE_VDDQ tied to external resistors R1 and R2, Note 4 1.6 VDDQ LD Load Regulation TA = 25°C, VCC = 2.5V, VDDQ LINE Line Regulation VCC MIN VDDQ V 1.80 1.85 V 2.8 V - - 2.5 % -1.0 - 1.0 % 0.01A ≤ IDDQ ≤ 1.0A, Note 4 TA = 25°C, IDDQ = 0.01A, 2.2V ≤ VCC ≤ 2.8V, Note 4 eN DDQ Output Noise Voltage BW = 10Hz - 100kHz, CDDQ = 10µF IDDQ LIM Current Limit Note 4 IDDQ SC Short Circuit Current VDDQ < 0.3V 1.7 49 µVrms 2.0 A 0.5 A VTT Regulator Parameters VTT Output Voltage Range VDDQ = 1.8V, ITT = 0.01A, 0.86 0.90 0.94 V VTT LD Load Regulation TA = 25°C, VDDQ = 1.8V, -1.0 - 1.0 % VTT LINE Line Regulation TA = 25°C, ITT = 0A, -1.0 - 1.0 % 0.01A ≤ ITT ≤ ±0.3A 2.2V ≤ VCC ≤ 2.8V eN TT Output Noise Voltage ITT LIM Current Limit ITT SC Short Circuit Current BW = 10Hz - 100kHz, CTT = 10µF 0.4 VTT < 0.3V 51 µVrms 0.6 A 0.3 A Note 3: All parameters specified at TA = -40°C to +85°C unless otherwise noted. Note 4: Note that the IDDQ current specified is the load current output from the VDDQ pin. VDDQ also supplies current internally to the VTT regulator when it is sourcing current. The maximum source current can be up to 0.5A. So the maximum total current from the VDDQ regulator is the external VDDQ current IDDQ added to the maximum VTT sourcing current ITT. All load currents are specified as such, but the VDDQ current limit is specified at a current just above the total maximum current. VCC(1) EN_DDR VDDQ OUT VTT OUT 2.8V to 3.6V Low VDDQ VDDQ / 2 X High 0V 0V Table 1: Truth Table for CM3121 © 2004 California Micro Devices Corp. All rights reserved. 6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 11/12/04 PRELIMINARY CM3121 Performance Information Power Supply Ripple Rejection CCC = 10µF, VCC = 3.3V, ILOAD = 50mA, PSRR measured with 50mV pk-pk sin wave on VCC. 50 45 40 PSRR (dB) 35 30 25 20 15 10 5 0 10 100 1000 10000 100000 Frequency (Hz) Figure 1. VDDQ PSRR (VDDQ = 2.5V) 60 50 PSRR (dB) 40 30 20 10 0 10 100 1000 10000 100000 Frequency (Hz) Figure 2. VTT PSRR (VTT = 1.25V) © 2004 California Micro Devices Corp. All rights reserved. 11/12/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 7 PRELIMINARY CM3121 Performance Information (cont’d) Typical Thermal Characteristics PCB Layout Considerations The overall junction to ambient thermal resistance (θJA) for device power dissipation (PD) consists primarily of two paths in series. The first path is the junction to the case (θJC) which is defined by the package style, and the second path is case to ambient (θCA) thermal resistance which is dependent on board layout. The final operating junction temperature for any set of conditions can be estimated by the following thermal equation: The CM3121-02SB/SH has a heat spreader attached to the bottom of the PSOP-8 package in order for heat to be transferred more easily from the package to the PCB. The heat spreader is a copper pad of dimensions just smaller than the package itself. By positioning the matching pad on the PCB top layer to connect to the spreader during manufacturing, the heat will be transferred between the two pads. The drawing below shows the recommended PCB layout. Note that there are six vias on either side to allow the heat to dissipate into the ground and power planes on the inner layers of the PCB. Vias can be placed underneath the chip, but this can cause blockage of the solder. The ground and power planes should be at least 2 sq in. of copper by the vias. It also helps dissipation if the chip is positioned away from the edge of the PCB, and not near other heat-dissipating devices. A good thermal link from the PCB pad to the rest of the PCB will assure the best heat transfer from the CM3121 package to ambient, θJA, of around 40°C/W. TJUNC = TAMB + PD ( θJC ) + PD ( θCA ) = TAMB + PD ( θJA) When a CM3121-02SB/SH (PSOP-8) is mounted on a double-sided printed circuit board with two square inches of copper allocated for "heat spreading," the resulting θJA is 40°C/W. Based on the over temperature limit of 150° C with an ambient of 70°C, the available power of this package will be: 150° C – 70° C PD = --------------------------------------- = 2W 40° C/ W Figure 3. Recommended Heat Sink PCB Layout © 2004 California Micro Devices Corp. All rights reserved. 8 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 11/12/04 PRELIMINARY CM3121 Application Information Other Applications The CM3121 can be used without any external resistors if a VDDQ voltage of 2.5V is required by connecting the SENSE_VDDQ pin to GND. Also in applications where a reference voltage (VREF) is required, a PCB trace directly from the VTT pin can be used. The VTT output pin has an error relative to VDDQ/2 of up to +/-25mV, which is well within most DDR system specs of +/-50mV. This is because the . VCC 2.8V to 3.6V CCC Enable DDR Memory # VTT output internally tracks the VDDQ output very closely due to the matched on-chip resistors R that tap down from the VDDQ rail, and the low offset voltage of the VTT regulator. It is recommended that the VREF trace be connected directly to the VTT pin, to eliminate noise and ripple on the VTT line caused by current switching VDDQ REGULATOR VREF VDDQ SENSE VDDQ EN_DDR CDDQ DDR MEMORY VTT REGULATOR R VTT R VREF=1.25V VTT=1.25V SENSE VTT CURRENT LIMIT OVERTEMP LOW INPUT CTT FAULT CPU CORE + I/O GND Figure 4. Typical Application for the CM3121 © 2004 California Micro Devices Corp. All rights reserved. 11/12/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 9 PRELIMINARY CM3121 Application Information (cont’d) DDR-II Application For DDR-II applications, it is recommended that a lower input voltage than 3.3V be applied to reduce overall power dissipation. The input voltage can be as low as 2.1V worst case, so an input voltage of 2.4V ±10% would be the best input voltage for the least power dissipation. Also to obtain a VDDQ voltage of 1.8V, a resistor divider comprising R1 = 56K and R2 = 130K would result in an output voltage of 1.79V for VDDQ, and a VTT of 0.895V. . * VDDQ = 1.25V x VCC 2.15V to 3.6V CCC Enable DDR Memory # The maximum current IDDQ for the CM3121 in a DDRII application is 1.5V, and the maximum for ITT is 0.3V. This should be satisfactory for most DDR- II applications because the DDR- II memories do not require a VTT, so the only current needed is for either a reference voltage or a controller input. VREF R1 + R2 ---------------------R2 VDDQ REGULATOR VDDQ=1.8V* VDDQ SENSE VDDQ EN_DDR R1 CDDQ DDR MEMORY R2 R VTT REGULATOR VTT R VTT=0.90V SENSE VTT CURRENT LIMIT OVERTEMP LOW INPUT CTT FAULT CPU CORE + I/O GND Figure 5. Minimal CM3132 DDR-II power solution. © 2004 California Micro Devices Corp. All rights reserved. 10 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 11/12/04 PRELIMINARY CM3121 Mechanical Details PSOP-8 Mechanical Specifications Dimensions for CM3121 devices packaged in an 8lead PSOP package with a heatspreader are shown below. Mechanical Package Diagrams TOP VIEW D PACKAGE DIMENSIONS Package PSOP-8 Leads 8 Dimensions Millimeters 8 7 6 5 Inches H Min Max Min Max A 1.30 1.62 0.051 0.064 A1 0.03 0.10 0.001 0.004 B 0.33 0.51 0.013 0.020 C 0.18 0.25 0.007 0.010 D 4.83 5.00 0.190 0.197 E 3.81 3.99 0.150 0.157 e 1.02 1.52 0.040 0.060 H 5.79 6.20 0.228 0.244 L 0.41 1.27 0.016 0.050 x** 3.30 3.81 0.130 0.150 y** 2.29 2.79 0.090 0.110 # per tube 100 pieces* # per tape and reel 2500 pieces Pin 1 Marking 1 2 3 E 4 BOTTOM VIEW D 1 2 3 4 Heat Slug x H y x/2 8 Controlling dimension: inches * This is an approximate number which may vary. 7 E y/2 6 5 SIDE VIEW ** Centered on package centerline. A SEATING PLANE A1 e B END VIEW C L Package Dimensions for PSOP-8 © 2004 California Micro Devices Corp. All rights reserved. 11/12/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 11