TI TPS54873

Typical Size
6,4 mm X 9,7 mm
TPS54873
www.ti.com
SLVS444 – OCTOBER 2002
4-V TO 6-V INPUT, 8-A OUTPUT SYNCHRONOUS BUCK
SWITCHER WITH DISABLED SINKING DURING START-UP
FEATURES
D 30-mΩ, 12-A Peak MOSFET Switches for High
D
D
D
D
D
D
Efficiency at 8-A Continuous Output Source
or Sink Current
Disabled Current Sinking During Start-Up
0.9-V to 3.3-V Adjustable Output Voltage
Range With 1.0% Accuracy
Wide PWM Frequency:
Fixed 350 kHz, 550 kHz or
Adjustable 280 kHz to 700 kHz
Synchronizable to 700 kHz
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Component Count
APPLICATIONS
D Low-Voltage, High-Density Distributed Power
D
D
D
Systems
Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs and
Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
Power PC Series Processors
DESCRIPTION
As a member of the SWIFT family of dc/dc regulators,
the TPS54873 low-input voltage high-output current
synchronous buck PWM converter integrates all
required active components. Included on the substrate
with the listed features are a true, high performance,
voltage error amplifier that enables maximum
performance and flexibility in choosing the output filter
L and C components; an under-voltage-lockout circuit
to prevent start-up until the input voltage reaches 4 V;
an internally or externally set slow-start circuit to limit
inrush currents; and a power good output useful for
processor/logic reset, fault signaling, and supply
sequencing.
For reliable power up in output precharge applications,
the TPS54873 is designed to only source current during
startup.
The TPS54873 is available in a thermally enhanced
28-pin TSSOP (PWP) PowerPAD package, which
eliminates bulky heatsinks. TI provides evaluation
modules and the SWIFT designer software tool to aid
in quickly achieving high-performance power supply
designs to meet aggressive equipment development
cycles.
TYPICAL APPLICATION
*
*
*
I/O Supply
*
START-UP WAVEFORM
Core Supply
VIN
VI = 5 V
PH
PGND
VSENSE
VBIAS
AGND COMP
* Optional
1 V/div
TPS54873
BOOT
VO = 3.3 V
5.0 ms/div
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and SWIFT are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright  2002, Texas Instruments Incorporated
TPS54873
www.ti.com
SLVS444 – OCTOBER 2002
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
– 40°C to 85°C
OUTPUT VOLTAGE
0.9 V to 3.3 V
PACKAGE
Plastic HTSSOP (PWP)(1)
PART NUMBER
TPS54873PWP
(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54873PWPR). See the application section of
the data sheet for PowerPAD drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS54873
Input voltage range,
range VI
VIN, SS/ENA, SYNC
–0.3 V to 7 V
RT
–0.3 V to 6 V
VSENSE
–0.3 V to 4V
BOOT
Output voltage range,
range VO
Source current
current, IO
–0.3 V to 17 V
VBIAS, COMP, PWRGD
–0.3 V to 7 V
PH
–0.6 V to 10 V
PH
Internally limited
COMP, VBIAS
Sink current, IS
Voltage differential
6 mA
PH
12 A
COMP
6 mA
SS/ENA, PWRGD
10 mA
±0.3 V
AGND to PGND
Operating virtual junction temperature range, TJ
–40°C to 125°C
Storage temperature, Tstg
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
300°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
Input voltage, VI
Operating junction temperature, TJ
NOM
MAX
UNIT
4
6
V
–40
125
°C
DISSIPATION RATINGS(1)(2)
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
28 Pin PWP with solder
18.2 °C/W
5.49 W(3)
3.02 W
2.20 W
28 Pin PWP without solder
40.5 °C/W
2.48 W
1.36 W
0.99 W
(1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
(2) Test board conditions:
1. 3” x 3”, 4 layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. 0.5 oz. copper ground planes on the 2 internal layers
5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)
(3) Maximum power dissipation may be limited by over current protection.
2
TPS54873
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SLVS444 – OCTOBER 2002
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE, VIN
Input voltage range, VIN
I(Q)
Quiescent current
4.0
6.0
fs = 350 kHz, SYNC ≤ 0.8 V, RT open,
PH pin open
11
15.8
fs = 550 kHz, SYNC ≥ 2.5 V, RT open,
PH pin open
16
23.5
1
1.4
3.8
3.85
Shutdown, SS/ENA = 0 V
V
mA
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
V
Stop threshold voltage, UVLO
3.40
3.50
V
Hysteresis voltage, UVLO
0.14
0.16
V
2.5
µs
Rising and falling edge deglitch, UVLO(1)
BIAS VOLTAGE
Output voltage, VBIAS
I(VBIAS) = 0
2.70
2.80
Output current, VBIAS (2)
2.90
V
100
µA
CUMULATIVE REFERENCE
Vref
Accuracy
REGULATION
Lineregulation
Line
regulation(1)(3)
Loadregulation
Load
regulation(1)(3)
0.882
0.891
0.900
IL = 3 A, fs = 350 kHz, TJ = 85°C
IL = 3 A, fs = 550 kHz, TJ = 85°C
IL = 0 A to 6 A, fs = 350 kHz, TJ = 85°C
0.04
IL = 0 A to 6 A, fs = 550 kHz, TJ = 85°C
0.03
0.04
0.03
V
%/V
%/A
OSCILLATOR
Internally set—free
set free running frequency
Externally set
set—free
free running frequency range
High level threshold, SYNC
SYNC ≤ 0.8 V,
RT open
280
350
420
SYNC ≥ 2.5 V,
RT open
440
550
660
RT = 180 kΩ (1% resistor to AGND)
252
280
308
RT = 100 kΩ (1% resistor to AGND)
460
500
540
RT = 68 kΩ (1% resistor to AGND)
663
700
762
2.5
0.8
50
Ramp amplitude (peak-to-peak)(1)
Minimum controllable on time(1)
Maximum duty cycle
V
ns
330
Ramp valley(1)
kHz
V
Low level threshold, SYNC
Pulse duration, external synchronization, SYNC(1)
Frequency range, SYNC(1)
kHz
700
kHz
0.75
V
1
V
200
ns
90%
(1) Specified by design
(2) Static resistive loads only
(3) Specified by the circuit used in Figure 9
3
TPS54873
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SLVS444 – OCTOBER 2002
ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
90
110
3
5
MAX
UNIT
ERROR AMPLIFIER
Error amplifier open loop voltage gain
1 kΩ COMP to AGND(1)
Error amplifier unity gain bandwidth
Error amplifier common mode input voltage range
Parallel 10 kΩ, 160 pF COMP to AGND(1)
Powered by internal LDO(1)
Input bias current, VSENSE
VSENSE = Vref
Output voltage slew rate (symmetric), COMP
0
VBIAS
60
1.0
dB
MHz
250
1.4
V
nA
V/µs
PWM COMPARATOR
PWM comparator propagation delay time,
PWM comparator input to PH pin (excluding
deadtime)
10-mV overdrive(1)
70
85
ns
1.20
1.40
V
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
0.82
Enable hysteresis voltage, SS/ENA
Falling edge deglitch, SS/ENA(1)
0.03
V
µs
2.5
Internal slow-start time
Charge current, SS/ENA
SS/ENA = 0 V
Discharge current, SS/ENA
SS/ENA = 1.3 V, VI = 1.5 V
2.6
3.35
4.1
ms
3
5
8
µA
2.0
2.3
4.0
mA
POWER GOOD
Power good threshold voltage
VSENSE falling
90
Power good hysteresis voltage(1)
Power good falling edge deglitch(1)
Output saturation voltage, PWRGD
Leakage current, PWRGD
I(sink) = 2.5 mA
VI = 5.5 V
3
%Vref
%Vref
35
µs
0.18
0.3
V
1
µA
CURRENT LIMIT
Current limit trip point
VI = 4.5 V Output shorted(1)
VI = 6 V Output shorted(1)
9
10
11
12
A
Current limit leading edge blanking time
100
ns
Current limit total response time
200
ns
THERMAL SHUTDOWN
Thermal shutdown trip point(1)
Thermal shutdown hysteresis(1)
135
150
165
°C
°C
10
OUTPUT POWER MOSFETS
rDS(on)
Power MOSFET switches
VI = 6 V(4)
VI = 4.5 V(4)
(1) Specified by design
(2) Static resistive loads only
(3) Specified by the circuit used in Figure 9
(4) Matched MOSFETs low-side rDS(on) production tested, high-side rDS(on) specified by design
4
26
47
30
60
mΩ
TPS54873
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SLVS444 – OCTOBER 2002
PWP PACKAGE
(TOP VIEW)
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
THERMAL 22
PAD
21
20
19
18
17
16
15
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
DESCRIPTION
AGND
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and
SYNC pin. Connect PowerPAD to AGND.
BOOT
5
Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP
3
Error amplifier output. Connect frequency compensation network from COMP to VSENSE
PGND
15–19
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas
to the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection
to AGND is recommended.
PH
6–14
Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD
4
Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low when
SS/ENA is low, or the internal shutdown signal is active.
RT
28
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. When using the
SYNC pin, set the RT value for a frequency at or slightly lower than the external oscillator frequency.
SS/ENA
26
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
SYNC
27
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select
between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be
connected to the RT pin.
VBIAS
25
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high
quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
20–24
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device
package with a high quality, low-ESR 10-µF ceramic capacitor.
VIN
VSENSE
2
Error amplifier inverting input. Connect to output voltage through compensation network/output divider.
5
TPS54873
www.ti.com
SLVS444 – OCTOBER 2002
INTERNAL BLOCK DIAGRAM
VBIAS
AGND
VIN
Enable
Comparator
SS/ENA
Falling
Edge
Deglitch
1.2 V
Hysteresis: 0.03 V
2.5 µs
VIN UVLO
Comparator
VIN
2.95 V
Hysteresis: 0.16 V
Thermal
Shutdown
150°C
3–6V
Leading
Edge
Blanking
100 ns
SHUTDOWN
BOOT
2.5 µs
30 mΩ
Start-Up
Driver
Suppression
SS_DIS
PH
+
–
R Q
Error
Amplifier
Reference
VREF = 0.891 V
VIN
ILIM
Comparator
Falling
and
Rising
Edge
Deglitch
Internal/External
Slow-start
(Internal Slow-Start Time = 3.35 ms)
REG
VBIAS
SHUTDOWN
S
PWM
Comparator
LOUT
CO
Adaptive Dead-Time
and
Control Logic
VIN
30 mΩ
PGND
OSC
Powergood
Comparator
PWRGD
VSENSE
Falling
Edge
Deglitch
0.90 Vref
TPS54873
Hysteresis: 0.03 Vref
VSENSE
COMP
RT
SHUTDOWN
35 µs
SYNC
ADDITIONAL 6A SWIFT DEVICES, (REFER TO SLVS397 AND SLVS400)
DEVICE
OUTPUT VOLTAGE
DEVICE
OUTPUT VOLTAGE
DEVICE
OUTPUT VOLTAGE
TPS54611
0.9 V
TPS54614
1.8 V
TPS54672
Active termination
TPS54612
1.2 V
TPS54615
2.5 V
TPS54610
Adjustable
TPS54613
1.5 V
TPS54616
3.3 V
TPS54680
Sequencing
RELATED DC/DC PRODUCTS
D TPS54673 – DC/DC Converter (integrated switch)
D TPS40000 – DC/DC Controller
D TPS40002 – DC/DC Controller
6
VO
TPS54873
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SLVS444 – OCTOBER 2002
TYPICAL CHARACTERISTICS
INTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
f – Internally Set Oscillator Frequency – kHz
Drain Source On-State Reststance – m Ω
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
60
50
VI = 5 V,
IO = 8 A
40
30
20
10
0
–40
–15
10
35
60
85
110
135
750
650
SYNC ≥ 2.5 V
550
450
SYNC ≤ 0.8 V
350
250
–40
TJ – Junction Temperature – °C
0
25
Figure 1
0.895
5
TJ = 125°C
fs = 700 kHz
4.5
RT = 68 k
600
500
RT = 100 k
400
300
0.893
Device Power Losses – W
700
V ref – Voltage Reference – V
0.891
0.889
0.887
0.885
25
85
125
TJ – Junction Temperature – °C
0
25
85
TJ – Junction Temperature – °C
Figure 3
RL = 10 kΩ,
CL = 160 pF,
TA = 25°C
120
0.893
100
1
2
3
Gain – dB
0.891
0.889
80
Phase
Gain
20
0.887
0
5.4
VI – Input Voltage – V
5.7
6
1
10
100
–80
–140
–200
1 k 10 k 100 k 1 M 10 M
f – Frequency – Hz
Figure 7
8
3.80
–40
–180
–20
7
–20
–160
0.885
6
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
–120
40
5
Figure 5
–100
60
4
IL – Load Current – A
–60
Figure 6
VI = 5 V
1
0
125
0
140
5.1
2
1.5
ERROR AMPLIFIER
OPEN LOOP RESPONSE
0.895
4.8
3
2.5
Figure 4
OUTPUT VOLTAGE REGULATION
vs
INPUT VOLTAGE
4.5
3.5
0
–40
Phase – Degrees
0
4
0.5
RT = 180 k
Internal Slow-Start Time – ms
f – Externally Set Oscillator Frequency – kHz
DEVICE POWER LOSSES
vs
LOAD CURRENT
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
800
200
–40
125
Figure 2
EXTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
VO – Output Voltage Regulation – V
85
TJ – Junction Temperature – °C
3.65
3.50
3.35
3.20
3.05
2.90
2.75
–40
0
25
85
125
TJ – Junction Temperature – °C
Figure 8
7
TPS54873
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SLVS444 – OCTOBER 2002
APPLICATION INFORMATION
Figure 9 shows the schematic diagram for a typical
TPS54873 application. The TPS54873 (U1) can provide
up to 8 A of output current at a nominal output voltage of
0.9 V to 3.3 V, and for this application, the output voltage
is set at 3.3 V. For proper operation, the PowerPAD
underneath the integrated circuit TPS54873 must be
soldered properly to the printed-circuit board.
U1
TPS54873
R6
28
71.5 kΩ
RT
VIN
VIN
27
SYNCH
C6
26
R1
R3
10 kΩ
C1
470 pF
R2
10 kΩ
C2
SS/ENA
VIN
PH
25
1 µF
VIN
VIN
10 kΩ
R5
VBIAS
PH
PH
4
PWRGD
PH
PH
3
C4
PH
COMP/NC
PH
470 pF
PH
12 pF
301 Ω
VIN
23
22
21
C10
C12
10 µF
10 µF
20
14
0.047 µF
C3
VIN
24
PH
2
VSENSE
BOOT
PGND
R4
3.74 kΩ
PGND
PGND
1
ANGND
PGND
PGND
PowerPAD
13
12
11
10
9
8
1 A, 200 V
D1
7
6
19
18
1 A, 200 V
D2
C9
5
0.047 µF
17
1 A, 200 V
D3
16
15
1 A, 200 V
D4
VOUT
R7
C13
C5
C7
C8
0.1 µF
22 µF
22 µF
22 µF
L1
0.65 µH
2.4 kΩ
C11
3300 pF
Figure 9. Application Circuit
COMPONENT SELECTION
The values for the components used in this design
example are selected for low output ripple and small PCB
area. Ceramic capacitors are utilized in the output filter
circuit. A small size, small value output inductor is also
used. Compensation network components are chosen to
maximize closed loop bandwidth and provide good
transient response characteristics. Additional design
information is available at www.ti.com.
INPUT VOLTAGE
The input voltage is a nominal 5. VDC. The input filter
(C12) is a 10-µF ceramic capacitor (Taiyo Yuden). C10,
also a 10-µF ceramic capacitor (Taiyo Yuden) that
provides high frequency decoupling of the TPS54873 from
8
the input supply, must be located as close as possible to
the device. Ripple current is carried in both C10 and C12,
and the return path to PGND should avoid the current
circulating in the output capacitors C5, C7, C8, and C13.
FEEDBACK CIRCUIT
The values for these components are selected to provide
fast transient response times. R1, R2, R3, R4, C1, C2, and
C4 forms the loop-compensation network for the circuit.
For this design, a Type 3 topology is used. The transfer
function of the feedback network is chosen to provide
maximum closed loop gain available with open loop
characteristics of the internal error amplifier. Closed loop
crossover frequency is typically between 80 kHz and
135 kHz for input from 3 V to 6 V.
TPS54873
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SLVS444 – OCTOBER 2002
OPERATING FREQUENCY
In the application circuit, the RT pin is grounded through a
71.5-kΩ resistor (R6) to select the operating frequency of
700 kHz. To set a different frequency, place a 68-kΩ to
180-kΩ resistor between RT (pin 28) and analog ground or
leave RT floating to select the default of 350 kHz. The
resistance can be approximated using the following
equation:
R+
500 kHz
Switching Frequency
100 [kW]
(1)
OUTPUT FILTER
The output filter is composed of a 0.65-µH inductor (L1)
and 3 x 22-µF capacitors (C5, C7 and C8). The inductor is
a low dc resistance (.017 Ω) type, Pulse PA0277 0.65 µH.
The capacitors used are 22-µF, 6.3-V ceramic types with
X5R dielectric. An additional high frequency bypass
capacitor, C13 is also used.
directly to AGND. Noise injected between the two grounds
can degrade the performance of the TPS54873,
particularly at higher output currents. However, ground
noise on an analog ground plane can also cause problems
with some of the control and bias signals. For these
reasons, separate analog and power ground areas are
recommended. The analog ground area should be tied to
the power ground area directly at the IC to reduce noise
between the two grounds. The only components that
should tie directly to the power ground area are the input
capacitor, the output capacitor, the input voltage
decoupling capacitor, and the PGND pins of the
TPS54873. The power ground areas as well as the
PowerPAD mounting area should be tied to any internal
ground planes using multiple vias. The layout of the
TPS54873 evaluation module is representative of a
recommended layout for a 4-layer board with the two
internal layers representing the system ground plane.
Documentation for the TPS54873 evaluation module can
be found on the Texas Instruments web site under the
TPS54873 product folder.
PRECHARGE CIRCUIT
VIN precharges the output of the application circuit
through series diodes (D1 and D2) during start-up. As the
input voltage increases at start-up, the output is
precharged to VIN minus the forward bias voltage of the
two diodes. When the internal reference has ramped up to
a value greater than the voltage fed back to the VSENSE
pin, the output of the internal error amplifier begins to
increase. When this output reaches the maximum ramp
amplitude, the output of the PWM comparator reaches 100
percent duty cycle and the internal logic enables the
high-side FET driver and switching begins. The output
tracks the internal reference until the preset output voltage
is reached. Under no circumstances should the precharge
voltage be allowed to increase above the preset output
value.
GROUNDING AND POWERPAD LAYOUT
The TPS54873 has two internal grounds (analog and
power). Inside the TPS54873, the analog ground ties to all
of the noise sensitive signals, while the power ground ties
to the noisier power signals. The PowerPAD must be tied
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog ground
plane must provide adequate heat dissipating area. A 3
inch by 3 inch plane of 1 ounce copper is recommended,
though not mandatory, depending on ambient temperature
and airflow. Most applications have larger areas of internal
ground plane available, and the PowerPAD should be
connected to the largest area available. Additional areas
on the top or bottom layers also help dissipate heat, and
any area available should be used when 6 A or greater
operation is desired. Connection from the exposed area of
the PowerPAD to the analog ground plane layer should be
made using 0.013 inch diameter vias to avoid solder
wicking through the vias. Eight vias should be in the
PowerPAD area with four additional vias located under the
device package. The size of the vias under the package,
but not in the exposed thermal pad area, can be increased
to 0.018. Additional vias beyond the ten recommended
that enhance thermal performance should be included in
areas not under the device package.
9
TPS54873
www.ti.com
SLVS444 – OCTOBER 2002
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
Powerpad Area 4 x 0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
8 PL Ø 0.0130
4 PL
Ø 0.0180
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
0.06
0.0150
0.0339
0.0650
0.0500
0.3820 0.3478 0.0500
0.2090
0.0500
0.0256
0.0650
0.0339
Minimum Recommended Exposed
Copper Area for Powerpad. 5-mm
Stencils May Require 10 Percent
Larger Area
0.1700
0.1340
Minimum Recommended Top
Side Analog Ground Area
0.0630
0.0400
Figure 10. Recommended Land Pattern for 28-Pin PWP PowerPAD
PERFORMANCE GRAPHS
EFFICIENCY
vs
OUTPUT CURRENT
VI = 5 V,
VO = 3.3 V
VO – Output Voltage – V
Efficiency – %
90
85
80
75
70
65
3.32
3.32
3.315
3.315
VO – Output Voltage – V
100
95
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.31
3.305
3.3
3.295
3.29
60
50
1
2
3
4
5
6
7
IO – Output Current – A
Figure 11
10
8
9
IO = 0
3.3
IO = 8
3.295
IO = 4
3.29
3.28
3.28
0
3.305
3.285
3.285
55
3.31
0
1
2
3
4
5
6
7
IO – Output Current – A
Figure 12
8
9
4
5.5
4.5
5
VI – Input Voltage – V
Figure 13
6
TPS54873
www.ti.com
SLVS444 – OCTOBER 2002
AMBIENT TEMPERATURE
vs
OUTPUT CURRENT
LOOP RESPONSE
Gain – dB
40
20
180
135
Phase
Gain
TJ = 25°C
fs = 700 kHz
115
90
0
125
T A – Ambient Temperature – ° C
VI = 5 V,
VO = 3.3 V,
IO = 6 A,
TA = 25°C,
FS = 550 kHz
Phase –Degrees
60
45
105
VI = 5 V
95
85
75
65
55
45
35
–20
100
0
1M
1k
10 k
100 k
f – Frequency – Hz
25
0
1
Figure 14
2
3
4
5
6
IO – Output Current – A
7
8
Figure 15
OUTPUT RIPPLE VOLTAGE
START-UP WAVEFORM
LOAD TRANSIENT RESPONSE
VI = 5 V
1 V/div
50 mV/div
Output Ripple Voltage – 10 mV/div
VI = 5 V,
1A to 5A,
Time – 1 µs/div
100 µs/div
Figure 16
Figure 17
VO = 3.3 V
5.0 ms/div
Figure 18
DETAILED DESCRIPTION
DISABLED SINKING DURING START-UP
(DSDS)
The DSDS feature enables minimal voltage drooping of
output precharge capacitors at start-up. The TPS54873
is designed to disable the low-side MOSFET to prevent
sinking current from a precharge output capacitor during
start-up. Once the high-side MOSFET has been turned on
to the maximum duty cycle limit, the low-side MOSFET is
allowed to switch. Once the maximum duty cycle condition
is met, the converter functions as a sourcing converter until
the SS/ENA is pulled low.
UNDERVOLTAGE LOCK OUT (UVLO)
The TPS54873 incorporates an under voltage lockout
circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are
held inactive until VIN exceeds the nominal UVLO
threshold voltage of 3.8 V. Once the UVLO start threshold
is reached, device start-up begins. The device operates
until VIN falls below the nominal UVLO stop threshold of
3.5 V. Hysteresis in the UVLO comparator and a 2.5-µs
rising and falling edge deglitch circuit reduce the likelihood
of shutting the device down due to noise on VIN.
SLOW-START/ENABLE (SS/ENA)
The slow-start/enable pin provides two functions. First, the
pin acts as an enable (shutdown) control by keeping the
device turned off until the voltage exceeds the start
threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start-up begins. The
reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the
converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs
falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.
11
TPS54873
www.ti.com
SLVS444 – OCTOBER 2002
The second function of the SS/ENA pin provides an
external means of extending the slow-start time with a
low-value capacitor connected between SS/ENA and
AGND.
Adding a capacitor to the SS/ENA pin has two effects on
start-up. First, a delay occurs between release of the
SS/ENA pin and start-up of the output. The delay is
proportional to the slow-start capacitor value and lasts
until the SS/ENA pin reaches the enable threshold. The
start-up delay is approximately:
t +C
d
(SS)
1.2 V
5 mA
(2)
Second, as the output becomes active, a brief ramp-up at
the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output
rises at a rate proportional to the slow-start capacitor. The
slow-start time set by the capacitor is approximately:
t
(SS)
+C
(SS)
0.7 V
5 mA
(3)
The actual slow-start time is likely to be less than the above
approximation due to the brief ramp-up at the internal rate.
The low side MOSFET is off during the slow-start
sequence.
VBIAS REGULATOR (VBIAS)
The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality,
low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are
recommended because their values are more stable over
temperature. The bypass capacitor must be placed close
to the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution that
internal circuits require a minimum VBIAS of 2.70 V, and
external loads on VBIAS with ac or digital switching noise
may degrade performance. The VBIAS pin may be useful
as a reference voltage for external circuits.
VOLTAGE REFERENCE
The voltage reference system produces a precise Vref
signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and
scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected
as a voltage follower. The trim procedure adds to the high
precision regulation of the TPS54873, since it cancels
offset errors in the scale and error amplifier circuits.
OSCILLATOR AND PWM RAMP
The oscillator frequency can be set to internally fixed
values of 350 kHz or 550 kHz using the SYNC pin as a
static digital input. If a different frequency of operation is
required for the application, the oscillator frequency can be
12
externally adjusted from 280 to 700 kHz by connecting a
resistor between the RT pin and AGND and floating the
SYNC pin. The switching frequency is approximated by
the following equation, where R is the resistance from RT
to AGND:
(4)
Switching Frequency + 100 kW 500 [kHz]
R
External synchronization of the PWM ramp is possible
over the frequency range of 330 kHz to 700 kHz by driving
a synchronization signal into SYNC and connecting a
resistor from RT to AGND. Choose a resistor between the
RT and AGND which sets the free running frequency to
80% of the synchronization signal. The following table
summarizes the frequency selection configurations:
SWITCHING
FREQUENCY
SYNC PIN
RT PIN
350 kHz, internally set
Float or AGND
Float
550 kHz, internally set
≥ 2.5 V
Float
Externally set 280 kHz
to 700 kHz
Float
R = 180 kΩ to 68 kΩ
Externally
synchronized
frequency
Synchronization
signal
R = RT value for 80%
of external synchronization frequency
ERROR AMPLIFIER
The high performance, wide bandwidth, voltage error
amplifier sets the TPS54873 apart from most dc/dc
converters. The user is given the flexibility to use a wide
range of output L and C filter components to suit the
particular application needs. Type 2 or type 3
compensation can be employed using external
compensation components.
PWM CONTROL
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic
block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator
pulse train alternately reset and set the PWM latch. Once
the PWM latch is reset, the low-side FET remains on for a
minimum duration set by the oscillator pulse width. During
this period, the PWM ramp discharges rapidly to its valley
voltage. When the ramp begins to charge back up, the
low-side FET turns off and high-side FET turns on. As the
PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latch is never reset, and the high-side FET remains on until
the oscillator pulse signals the control logic to turn the
TPS54873
www.ti.com
SLVS444 – OCTOBER 2002
high-side FET off and the low-side FET on. The device
operates at its maximum duty cycle until the output voltage
rises to the regulation set-point, setting VSENSE to
approximately the same voltage as VREF. If the error
amplifier output is low, the PWM latch is continually reset
and the high-side FET does not turn on. The low-side FET
remains on until the VSENSE voltage decreases to a
range that allows the PWM comparator to change states.
The TPS54873 is capable of sinking current continuously
until the output reaches the regulation set-point.
If the current limit comparator trips for longer than 100 ns,
the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high-side FET turns off and
low-side FET turns on to decrease the energy in the output
inductor and consequently the output current. This
process is repeated each cycle in which the current limit
comparator is tripped.
DEAD-TIME CONTROL AND MOSFET
DRIVERS
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the
turnon times of the MOSFET drivers. The high-side driver
does not turn on until the voltage at the gate of the low-side
FET is below 2 V. While the low-side driver does not turn
on until the voltage at the gate of the high-side MOSFET
is below 2 V.
The high-side and low-side drivers are designed with
300-mA source and sink capability to quickly drive the
power MOSFETs gates. The low-side driver is supplied
from VIN, while the high-side drive is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT
capacitor and an internal 2.5-Ω bootstrap switch
connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive efficiency and
reduces external component count.
The high side MOSFET is turned off within 200 ns of
reaching the current limit threshold. A 100-ns leading edge
blanking circuit prevents current limit false tripping.
Current limit detection occurs only when current flows from
VIN to PH when sourcing current to the output filter. Load
protection during current sink operation is provided by
thermal shutdown.
THERMAL SHUTDOWN
The device uses the thermal shutdown to turn off the power
MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from
shutdown automatically when the junction temperature
decreases to 10°C below the thermal shutdown trip point,
and starts up under control of the slow-start circuit.
Thermal shutdown provides protection when an overload
condition is sustained for several milliseconds. With a
persistent fault condition, the device cycles continuously;
starting up by control of the soft-start circuit, heating up due
to the fault condition, and then shutting down upon
reaching the thermal shutdown trip point. This sequence
repeats until the fault condition is removed.
POWER-GOOD (PWRGD)
The power good circuit monitors for under voltage
conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open-drain PWRGD
output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold or SS/ENA is low, or a
thermal shutdown occurs. When VIN ≥ UVLO threshold,
SS/ENA ≥ enable threshold, and VSENSE > 90% of Vref,
the open drain output of the PWRGD pin is high. A
hysteresis voltage equal to 3% of Vref and a 35 µs falling
edge deglitch circuit prevent tripping of the power good
comparator due to high frequency noise.
OVERCURRENT PROTECTION
The cycle-by-cycle current limiting is achieved by sensing
the current flowing through the high-side MOSFET and
comparing this signal to a preset overcurrent threshold.
13
TPS54873
www.ti.com
SLVS444 – OCTOBER 2002
MECHANICAL DATA
PWP (R-PDSO-G**)
POWERPAD PLASTIC SMALL-OUTLINE
20 PINS SHOWN
0,30
0,19
0,65
20
0,10 M
11
Thermal Pad
(See Note D)
4,50
4,30
0,15 NOM
6,60
6,20
Gage Plane
1
10
0,25
A
0°–ā8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
5,10
5,10
6,60
7,90
9,80
A MIN
4,90
4,90
6,40
7,70
9,60
DIM
4073225/F 10/98
NOTES:A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusions.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
14
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