BUF01900 BUF01901 SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006 Programmable Voltage Source with Memory FEATURES DESCRIPTION D D D D D D D D The BUF01900 and BUF01901 provide a programmable voltage output with 10-bit resolution. Programming of the output occurs through an industry-standard, two-wire serial interface. Once the correct VCOM voltage is established it can easily be stored into the integrated nonvolatile memory. 10-BIT RESOLUTION RAIL-TO-RAIL OUTPUT ONBOARD NONVOLATILE MEMORY IOUT: 100mA LOW SUPPLY CURRENT: 900µA An initial output voltage and adjustment range can be set by an external resistor-divider. With its large output current capability (up to 100mA), the BUF01900 and BUF01901 are ideally suited as programmable VCOM calibrators in LCD panels. SUPPLY VOLTAGE: 7V to 18V DIGITAL SUPPLY: 2.0V to 5.5V INDUSTRY-STANDARD, TWO-WIRE INTERFACE The BUF01901 has the digital-to-analog converter (DAC) output brought out directly. It has a slightly lower cost than the BUF01900, and works very well with the integrated VCOM in traditional gamma buffers such as the BUFxx702, BUFxx703, BUFxx704 and BUF11705. D HIGH ESD RATING: 2kV HBM, 500V CDM The BUF01900 and BUF01901 are both available in TSSOP-8 and 3mm x 3mm DFN-10 packages. The DFN-10 package (only 0.9mm in height) is especially well-suited for notebook computers. Both devices are specified from −40°C to +85°C. APPLICATIONS D LCD PANEL VCOM CALIBRATION D LCD PANEL BRIGHTNESS AND CONTRAST CONTROL POTENTIOMETER REPLACEMENT Digital 2V to 5.5V MOTOR DRIVE Analog 7V to 18V BIAS PROGRAMMABLE POWER SUPPLY BUF01900 PROGRAMMABLE OFFSET ADJUSTMENT ACTUATOR CONTROL BUF01900, BUF01901 RELATED PRODUCTS FEATURES PRODUCT 22V High Supply Voltage Gamma Buffers BUF11705 12--Channel Programmable Buffer, 10-Bit, VCOM BUF12800 20-Channel Programmable Buffer, 10-Bit, VCOM BUF20800 16-Channel Programmable Buffer with Memory BUF16820 20-Channel Programmable Buffer with Memory BUF20820 Program Command D D D D D Voltage Regulator 250kΩ 4 x OTP ROM Switch Control 10−Bit DAC Buffer VCOM Input Control Logic SDA SCL A0 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. Copyright 2006, Texas Instruments Incorporated ! ! www.ti.com "#$%&$$ "#$%&$% www.ti.com SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage, VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20V Supply Voltage, VSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V Signal Input Terminals, BIAS: Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to VS +0.5V SCL, SDA, A0, A1: Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to +6V Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Output Short Circuit(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to +95°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C ESD Rating: Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V Charged-Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Short-circuit to ground. ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING BUF01900 DFN-10 DRC BOO BUF01900 TSSOP-8 PW F01900 BUF01901 DFN-10 DRC BOP BUF01901 TSSOP-8 PW F01901 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. PIN CONFIGURATIONS BUF01901 BUF01900 VS 1 VCOM 2 BIAS 3 GND 4 DGND 5 Exposed Thermal Die Pad on Underside SDA VS 1 9 SCL NC 2 8 A0 BIAS 3 7 A1 GND 4 6 VSD DGND 5 Exposed Thermal Die Pad on Underside DFN−10 DFN−10 BUF01900 BUF01901 VS 1 8 SDA VC OM 2 7 SCL BIAS 3 6 A0 GND 4 5 VSD GND TSSOP−8 2 10 NC = No connection 10 SDA 9 SCL 8 A0 7 A1 6 V SD VS 1 8 SDA NC 2 7 SCL BIAS 3 6 A0 4 5 VSD TSSOP−8 "#$%&$$ "#$%&$% www.ti.com SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006 ELECTRICAL CHARACTERISTICS Boldface limits apply over the specified temperature range, TA = −40°C to +85°C. At TA = +25°C, VS = 18V, VSD = 5V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted. BUF01900, BUF01901 PARAMETER ANALOG VCOM Output Swing(1) VCOM Output Reset and Power-Up Value(1) Nominal VBIAS Output Impedance Program to Out Delay Output Accuracy Load Regulation VCOM(1) Offset Offset Drift Common-Mode Range Common-Mode Rejection Slew Rate VBIAS Integral Nonlinearity Differential Nonlinearity Gain Error Accuracy ANALOG POWER SUPPLY Operating Range(2) Total Analog Supply Current over Temperature DIGITAL Logic 1 Input Voltage Logic 0 Input Voltage Logic 0 Output Voltage Input Leakage Clock Frequency DIGITAL POWER SUPPLY Operating Voltage Range Digital Supply Current(2) over Temperature TEMPERATURE Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Resistance TSSOP-8 DFN-10 CONDITIONS MIN TYP Sourcing 10mA, Code 1023 Sinking 10mA, Code 00 Sourcing 100mA, Code 1023 Sinking 100mA, Code 00 OTP not programmed, Code 512 No Load on VBIAS, VCOM 17.7 17.8 0.6 16 0.75 VS/2 250 5 20 0.5 15 tD REG 1V < VCOM < 17.7 VOUT = VS/2, IOUT = +50mA to −50mA Step −25°C to +100°C CMR 0.8V < VIN < 17.9V MAX 1 1 50 1.5 UNIT V V V V V kΩ µs mV mV/mA ±5 5 0.8 to 18 85 5 ±25 mV µV/°C V dB V/µs 0.1 0.1 0.1 20 2 2 1 50 LSB LSB %FSC mV 0.9 18 1.5 1.5 V mA mA 0.15 ±0.01 0.3 × VSD 0.4 ±10 400 3.4 V V V µA kHz MHz No Load on VBIAS INL DNL VS IS 7 Output at Reset Values, No Load 0.7 × VSD VIH VIL VOL fCLK ISINK = 3mA Standard/Fast Mode High-Speed Mode VSD ISD 2.0 25 100 Junction Temperature < 125°C −40 −40 −65 5.5 50 V µA µA +85 +95 +150 °C °C °C qJA 150 47 °C/W °C/W (1) BUF01900 only. (2) Minimum analog supply voltage is 8.5V when programming OTP memory. 3 "#$%&$$ "#$%&$% www.ti.com SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS At TA = +25°C, VS = 18V, VSD = 5V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted. ANALOG SUPPLY CURRENT vs TEMPERATURE DIGITAL SUPPLY CURRENT vs TEMPERATURE 50 Digital Supply Current (µA) Analog Supply Current (mA) 1.5 VS = 18V 1.0 VSD = 8V 0.5 40 VSD = 5V 30 20 VSD = 2V 10 0 0 −40 −20 0 20 40 60 80 −40 100 −20 0 Temperature (_ C) Figure 1 PDS limits are ±25mV 16 10 14 5 12 0 −5 6 4 −20 Sourcing, Code = 3FFh 8 −15 2 0 20 40 60 80 Sinking, Code = 000h 0 100 0 Temperature (_C) 25 75 100 Figure 4 DIFFERENTIAL NONLINEARITY ERROR vs INPUT CODE INTEGRAL NONLINEARITY ERROR vs INPUT CODE 1.5 1.5 1.0 1.0 DNL Error (LSB) INL Error (LSB) 50 IOUT (mA) Figure 3 0.5 0 −0.5 −1.0 0.5 0 −0.5 −1.0 10 Typical Units Shown 10 Typical Units Shown −1.5 −1.5 0 128 256 384 512 640 Input Code Figure 5 4 100 10 −10 −20 80 VS = 18V 18 15 −25 −40 60 OUTPUT VOLTAGE vs OUTPUT CURRENT 20 VOUT (V) VOS (mV) 20 40 Figure 2 BUFFER OFFSET VOLTAGE vs TEMPERATURE (VS = 18V, VSD = 5V) 25 20 Temperature (_ C) 768 896 1024 0 128 256 384 512 640 Input Decimal Code Figure 6 768 896 1024 "#$%&$$ "#$%&$% www.ti.com SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS (cont) At TA = +25°C, VS = 18V, VSD = 5V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted. VCOM BUFFER SLEW RATE BUFFER LARGE SIGNAL STEP RESPONSE (2) VCOM (1) VBIAS (1) VBIAS 5V/div 5V/div (2) VCOM 1 2 1 Time (1µs/div) Time (1µs/div) Figure 7 Figure 8 LOAD REGULATION vs CAPACITANCE LOAD REGULATION vs CAPACITANCE 1 1 C 10 Ω 100mA/div 100mA/div 2.7nF 2 2 .7 nF C C = 1µF 500mV/div C = 0.1µF 500mV/div 2 C = 1µF 1 C = 10µF 2 C = 0.1µF C = 10µF C = 1µF 1 C = 10µF Time (1µs/div) Time (1µs/div) Figure 9 Figure 10 LOAD REGULATION WITH 100µF CAPACITOR LOAD REGULATION WITH 10µF CAPACITOR 1 1 2.7nF 100mA/div 100 µ F 50mV/div 20mV/div 100mA/div 2.7nF 1 Time (1µs/div) Figure 11 10 µ F 1 Time (1µs/div) Figure 12 5 "#$%&$$ "#$%&$% www.ti.com SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS (cont) At TA = +25°C, VS = 18V, VSD = 5V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted. LOAD REGULATION WITH 1µF CAPACITOR (C = 1µF, RS = 0, 100mV Res.) 1 100mV/div 100mA/div 2. 7nF 1µF 1 Time (1µs/div) Figure 13 6 "#$%&$$ "#$%&$% www.ti.com SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006 APPLICATIONS INFORMATION BUF01900: ON-CHIP BUFFER OVERVIEW Unlike many programmable VCOM calibrators on the market, the BUF01900 offers an integrated VCOM buffer with high current output drive capability. The output is capable of delivering peak currents over 100mA to within 4V from the positive supply and to within 2V from the negative supply. Using this option is very cost-effective and convenient in systems that do not use multi-channel gamma buffers with integrated VCOM drive. Figure 15 shows the BUF01900 in a typical configuration. The BUF0190x family of products consists of a 10-bit digital-to-analog converter (DAC) that is programmed through an industry-standard two-wire interface. It contains onchip nonvolatile memory that stores a specific DAC value that is read at power-up. The BUF0190x family consists of two devices: The BUF01900 contains a voltage buffer that is capable of driving high-current; the BUF01901 is a lower-cost version without the buffer. The BUF0190x is especially well-suited for VCOM calibration in LCD panels; however, it can also be used in many other applications. Figure 14 shows the BUF01900 in a typical configuration. VS 0.1µF BUF01900 10µF + VS SDA 2 VCOM SCL 7 3 VBIAS A0 6 4 GND VSD 5 1 8 Timing Controller (1) VCOM (2) VS (2) 10kΩ 10kΩ VSD 0.1µF NOTES: (1) Optional −may be needed for stability. (2) Optional −see application text for component selection. Figure 14. Typical Application Diagram Digital 2V to 5.5V Analog 7V to 18V R2 R1 BIAS Program Command BUF01900 Voltage Regulator 250kΩ 4 x OTP ROM Switch Control 10−Bit DAC VCOM Buffer VCOM Panel Input Control Logic SDA SCL A0 Figure 15. BUF01900 Typical Configuration 7 "#$%&$$ "#$%&$% www.ti.com SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006 BUF01901: USING EXTERNAL VCOM BUFFER Many LCD panel modules use gamma buffers, such as TI’s BUFxx704, BUFxx703, BUF11702 and the new BUF11705, that already include an integrated VCOM driver. Some other LCD modules use more complicated compensation schemes that require an external high-speed VCOM op amp. BUF01901 is optimized for lowest cost and is intended to be used with an external VCOM buffer or op amp. Figure 16 illustrates a typical configuration of the BUF01901 with the BUF11705. ON-CHIP NONVOLATILE MEMORY The BUF0190x is optimized for the smallest die size available and consequently the lowest cost to support high vol- ume production. The on-chip OTP (one-time-programmable) memory helps to achieve significant die size reduction over EEPROM memory technology. This reduction is partly because of the smaller area of the OTP memory cell, but also a result of the fact that an EEPROM requires a high programming voltage typically generated with an onboard charge pump. OTP memory technology does not require the higher programming voltage; consequently, no charge pump is needed, resulting in a smaller and lower-cost solution. During production, the VCOM voltage is typically adjusted only once. However, to allow for programming errors and rework, the BUF0190x supports a total of four write cycles to the OTP memory. This capacity means that the previously programmed code in the OTP can be overwritten a total of three times. BUF11704 Gamma References Digital 2V to 5.5V Analog 7V to 18V Program Command BUF01901 Voltage Regulator R1 250kΩ 4 x OTP ROM Switch Control 10−Bit DAC BIAS VCOM R2 Input Control Logic SDA SCL A0 Figure 16. BUF01901 Typical Configuration 8 "#$%&$$ "#$%&$% www.ti.com SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006 POWER-SUPPLY VOLTAGE The BUF0190x can be powered using an analog supply voltage from 7V to 18V, and a digital supply from 2V to 5.5V. The digital supply must be applied prior to the analog supply to avoid excessive current and power consumption. During programming of the OTP, the analog power supply must be at least 8.5V. BUFFER INPUT AND OUTPUT RANGE The integrated buffer has a single p-channel input stage. The input range includes the positive supply and extends down to typically 0.8V above the negative supply (GND). In a typical LCD application, this is normally sufficient because the nominal VCOM level is often close to V2/2 and, therefore, fairly far away from either supply rail. In addition, the adjustment range is usually not much larger than 1V in either direction of the nominal VCOM voltage. In applications requiring a wider output swing, the output voltage to the buffer should be limited to approximately 0.8V above the negative power supply to keep the buffer input stage in its linear operating region. For lower input voltages, the output results might not be valid; however, they will also not lead to damage of the device. The Rail-to-Rail output stage is designed to drive large peak currents greater than 100mA. TWO-WIRE BUS OVERVIEW The BUF0190x communicates through an industry-standard, two-wire interface to receive data in slave mode. This standard uses a two-wire, open-drain interface that supports multiple devices on a single bus. Bus lines are driven to a logic low level only. The device that initiates the communication is called a master, and the devices controlled by the master are slaves. The master generates the serial clock on the clock signal line (SCL), controls the bus access, and generates START and STOP conditions. To address a specific device, the master initiates a START condition by pulling the data signal line (SDA) from a HIGH to LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge and pulling SDA LOW. Data transfer is then initiated and eight bits of data are sent, followed by an Acknowledge bit. During data transfer, SDA must remain stable while SCL is HIGH. Any change in SDA while SCL is HIGH will be interpreted as a START or STOP condition. Once all data has been transferred, the master generates a STOP condition, indicated by pulling SDA from LOW to HIGH while SCL is HIGH. The BUF0190x can act only as a slave device; therefore, it never drives SCL. The SCL is only an input for the BUF0190x. ADDRESSING THE BUF01900 AND BUF01901 The address of the BUF0190x in the TSSOP-8 package is 111011x, where x is the state of the A0 pin. When the A0 pin is LOW, the device acknowledges on address 76h. If the A0 pin is HIGH, the device acknowledges on address 77h. Table 1 summarizes device addresses. Table 1. Quick-Reference Table of Addresses DEVICE/COMPONENT ADDRESS TSSOP Package: A0 pin is LOW (device will acknowledge on address 76h) 1110110 A0 pin is HIGH (device will acknowledge on address 77h) 1110111 DFN Package: A0 pin is LOW, A1 is LOW (device will acknowledge on address 74h) 1110100 A0 pin is HIGH, A1 is LOW (device will acknowledge on address 75h) 1110101 A0 pin is LOW, A1 is HIGH (device will acknowledge on address 76h) 1110110 A0 pin is HIGH, A1 is HIGH (device will acknowledge on address 77h) 1110111 The address of the BUF0190x in the DFN-10 package is 11101yx, where x is the state of the A0 pin and y is the state of the A1 pin. When the A0 and A1 pins are both LOW, the device acknowledges on address 74h. If the A0 is HIGH and A1 is LOW, the device acknowledges on address 75h. When the A0 is LOW, and A1 is HIGH, the device acknowledges on address 76h. If the A0 and A1 pins are both HIGH, the device address is 77h. Other addresses are possible through a simple mask change. Contact your TI representative for ordering information and availability. 9 "#$%&$$ "#$%&$% www.ti.com SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006 DATA RATES READ/WRITE OPERATIONS: The two-wire bus operates in one of three speed modes: Read commands are performed by setting the read/write bit HIGH. Setting the read/write bit LOW performs a write transaction. D D D Standard: allows a clock frequency of up to 100kHz; Fast: allows a clock frequency of up to 400kHz; and High-speed mode (or Hs mode): allows a clock frequency of up to 3.4MHz. Figure 17 and Figure 18 show the timing diagrams for read and write operations. Writing: The BUF0190x is fully compatible with all three modes. No special action is required to use the device in Standard or Fast modes, but High-speed mode must be activated. To activate High-speed mode, send a special address byte of 00001xxx, with SCL ≤ 400kHz, following the START condition; xxx are bits unique to the Hs-capable master, which can be any value. This byte is called the Hs master code. (Note that this is different from normal address bytes—the low bit does not indicate read/write status.) The BUF0190x will respond to the High-speed command regardless of the value of these last three bits. The BUF0190x does not acknowledge this byte; the communication protocol prohibits acknowledgment of the Hs master code. On receiving a master code, the BUF0190x switches on its Hs mode filters, and communicates at up to 3.4MHz. Additional high-speed transfers may be initiated without resending the Hs mode byte by generating a repeat START without a STOP. The BUF0190x switches out of Hs mode with the next STOP condition. To write to the DAC register: 1. Send a START condition on the bus. 2. Send the device address and read/write bit = LOW. The BUF01900/BUF01901 will acknowledge this byte. 3. Send two bytes of data for the DAC register. Begin by sending the most significant byte (bits D15—D8; only bits D9 and D8 are used, and D15—D13 must not be 010 or 001), followed by the least significant byte (bits D7—D0). The register is updated after receiving the second byte. 4. Send a STOP condition on the bus. The BUF0190x acknowledges each data byte. If the master terminates communication early by sending a STOP or START condition on the bus, the DAC output will not update. Reading: To read the register of the DAC: GENERAL CALL RESET AND POWER-UP The BUF0190x responds to a General Call Reset, which is an address byte of 00h (0000 0000) followed by a data byte of 06h (0000 0110). The BUF0190x acknowledges both bytes. Upon receiving a General Call Reset, the BUF0190x performs a full internal reset, as though it had been powered off and then on. It always acknowledges the General Call address byte of 00h (0000 0000), but does not acknowledge any General Call data bytes other than 06h (0000 0110). The BUF0190x automatically performs a reset upon power-up. As part of the reset, the BUF0190x is configured for the output to change to the programmed OTP memory value, or to mid-scale, ‘1000000000’, if the OTP value has not been programmed. Table 2 provides a summary of command codes. Table 2. Quick-Reference Table of Command Codes COMMAND CODE General Call Reset Address byte of 00h followed by a data byte of 06h. High-Speed Mode 00001xxx, with SCL ≤ 400kHz; where xxx are bits unique to the Hs-capable master. This byte is called the Hs master code. 10 1. Send a START condition on the bus. 2. Send the device address and read/write bit = HIGH. The BUF0190x will acknowledge this byte. 3. Receive two bytes of data. The first received byte is the most significant byte (bits D15—D8; only bits D9 and D8 have meaning, and bits D15—D12 will show the programming status of the OTP memory). See Table 3. The next byte is the least significant byte (bits D7—D0). 4. Acknowledge after receiving the first byte only. 5. Do not acknowledge the second byte of data or send a STOP condition on the bus. Communication may be terminated by the master by sending a premature STOP or START condition on the bus, or by not sending the Acknowledge. Table 3. OTP Memory Status CODE (Bits D15 − D12) OTP PROGRAMMING STATUS 0000 OTP has not been programmed. 0001 OPT has been programmed once. 0011 OTP has programmed twice. 0111 OPT has programmed three times. 1111 OTP has programmed all four times. "#$%&$$ "#$%&$% www.ti.com SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006 ACQUIRE OF OTP MEMORY An acquire command updates the DAC output to the value stored in OTP memory. If the OTP memory has not been programmed, the DAC output code is ‘0000000000’. Write commands are performed by setting the read/write bit LOW. To write to OTP memory: 1. Send a START condition on the bus. Figure 19 shows the timing diagram for the acquire command. 2. Send the device address and read/write bit = LOW. The BUF0190x acknowledges this byte. Acquire Command 3. Send two bytes of data for the OTP memory. Begin by sending the most significant byte first (bits D15—D8, of which only bits D9 and D8 are data bits, and bits D15—D13 must be 010), followed by the least significant byte (bits D7—D0). The register updates after receiving the second byte. 4. Send a STOP condition on the bus. 1. Send a START condition on the bus. 2. Send the device address and read/write bit = LOW. The device will acknowledge this byte. 3. Send the acquire command. Bits D7—D5 must be set to 001. Bits D4—D0 do not have meaning. This byte will be acknowledged. 4. Send a STOP condition on the bus. Writing OTP Memory The BUF0190x is able to write to the OTP memory a maximum of four times. Writing to the OTP memory a fourth time uses all available memory and disables the ability to perform additional writes (see table 3). A reset or acquire command updates the DAC output to the most recently written OTP memory value. When programming the OTP memory, the analog supply voltage must be between 8.5V and 18V. The BUF0190x acknowledges each data byte. If the master terminates communication early by sending a STOP or START condition on the bus, the specified OTP register will not be updated. Writing an OTP register updates the DAC output voltage. Programming timing is taken from the two-wire bus. Therefore, the master must provide correct timing on the bus to ensure data is successfully written into OTP memory. Figure 20 shows the timing requirements for timing when the OTP write supply and OTP write signal are active. 11 12 Figure 17. Timing Diagram for Write DAC Register A4 A3 A2 A1 A0 A2 A2 A1 A1 A0 A0 Write W Ackn Ackn A6 A6 SDA_in Device_out SCL A5 A5 A4 A4 A3 A2 A1 A0 R R Ackn Ackn D15 D15 CODE 0000 0001 0011 0111 1111 D15 D15 Ackn A3 A3 W Read operation Device address A5 A4 Start A6 Device_out A5 Read DAC Register. A6 SDA_in SCL D13 D13 D12 D12 D11 D11 D10 D10 D14 D14 D12 D12 D11 D11 D10 D10 OTP Programming Status OTP has not been programmed OTP has been programmed once OTP has been programmed twice. OTP has been programmed three times. OTP has been programmed four times. D13 D13 D9 D9 D9 D9 DAC MSbyte. D15 −D12 show the program status. D14 D14 DAC MSbyte. D15 −D13 = ’000’D12 −D10 have no meaning. Write operation Ackn Write Start Device address Write DAC Register. D8 D8 D8 D8 D7 D7 Ackn D7 D7 Ackn Ackn Ackn Ackn Ackn D5 D5 D6 D6 D5 D5 DAC LSbyte. D6 D6 DAC LSbyte. D4 D4 D4 D4 D3 D3 D3 D3 D2 D2 D2 D2 D0 D0 Ackn Ackn D1 D1 D0 D0 Stop Stop No Ackn No Ackn The entire DAC Register D9 −D0 is updated in this moment. D1 D1 Ackn "#$%&$$ "#$%&$% SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006 www.ti.com Figure 18. Timing Diagram for Read DAC Register Figure 19. Timing Diagram for Acquire Command A3 A2 A0 A2 A6 A6 SDA_in Device_out SCL A5 A5 A4 A4 A1 A0 A3 A2 A1 A0 W W Ackn Ackn A1 A0 W W Ackn Ackn D15 D7 D14 D6 D15 D15 D14 D14 D13 D13 D12 D12 D11 D11 D10 D10 D9 D9 D8 D8 D13 D5 Ackn Ackn Ackn D12 D4 D7 D7 D11 D3 D6 D6 D8 D0 Ackn Ackn Ackn D5 D5 D4 D4 Stop D3 D3 D2 D2 D0 D0 t1 Ackn Ackn Ackn t2 Stop The OTP Register D9 −D0 is updated in this moment. t1: > 20µs before falling edge of clock. t2: minimum 100µs, maximum 2ms. D1 D1 Write supply active Write signal active DAC output is updated in this moment. D9 D1 DAC LSbyte. D10 D2 D15 −D13 must be ’001’. D12 −D8 have no meaning. DAC MSbyte. D15 −D13 must be 010. D12 −D10 have no meaning. Ackn Write A3 Start A1 A4 A4 Write operation A2 A5 A5 Write OTP memory. A3 A6 Device_out Device address A6 SDA_in SCL Write operation Ackn Write Start Device address Acquire command. "#$%&$$ "#$%&$% www.ti.com SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006 Figure 20. Timing Diagram for Write OTP Register 13 "#$%&$$ "#$%&$% www.ti.com SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006 VCOM CALIBRATION The BUF0190x provides a simple, time- and cost-efficient means to adjust the flicker performance of LCD panels either manually or automatically during the final stages of the LCD panel manufacturing process. The 10-bit adjustment resolution of the BUF0190x exceeds the typical adjustment resolution of existing VCOM calibrators significantly. As with a traditional VCOM adjustment, which uses a mechanical potentiometer and a voltage divider for adjustment (see Figure 21), the BUF0190x uses an external voltage divider that is used to set the initial VCOM voltage as well as the adjustment range. (a) Code 00h equivalent circuit. BUF0190x VS R1 (1) VCOM VBIAS 250kΩ R2 (b) Code 3FFh equivalent circuit. BUF0190x VS AVDD RA 250kΩ VS R1 (1) VBIAS RB VCOM R2 VCOM RC NOTE: (1) Integrated into BUF01900 or external. Figure 21. Traditional VCOM Adjustment As Figure 22 shows, the 10-bit DAC acts as a Rail-to-Rail output voltage source with a nominal 250kΩ of output impedance. For example, at Code 000h, the lowest VCOM voltage is achieved since the 250kΩ impedance is now in parallel with R2, which lowers the impedance of the lower side of the voltage divider. Consequently, code 3FFh results in the highest adjustable VCOM voltage. Once the desired output level is obtained, the part can store the final setting using the non-volatile on-chip memory. See Programming section for detailed information. 14 Figure 22. Simplified Block Diagram for VCOM Adjustment using BUF0190x SELECTING THE ADJUSTMENT STEP SIZE A maximum of 1024 adjustment steps can be realized with the BUF0190x, leading to very high adjustment resolution and very small step sizes. This flexibility can be advantageous during the panel development phase. In a practical production setting, however, this capability might lead to adjustment times that can be too long. A simple solution is to increase the step size between settings to more practical values for mass production. Limiting the number of adjustment steps between code 000h and code 3FFh to between 16 and 128 has been shown to typically yield acceptable adjustment results in the smallest amount of adjustment time. "#$%&$$ "#$%&$% www.ti.com SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006 EXTERNAL VOLTAGE DIVIDER RESISTOR SELECTION The external resistive voltage-divider consisting of R1 and R2 (see Figure 16, Figure 17, and Figure 18) sets both the maximum value of the VCOM adjustment range and the initial VCOM voltage. Follow the steps below to calculate the correct values for R1 and R2 Step 1: Choose the supply voltage, (VS) Step 2: Set the nominal VCOM voltage. This voltage is the VCOM voltage at which the unadjusted panel should be at power-on. The default power-up DAC code is midscale. Step 3: Choose the VCOM adjustment range. The adjustment range is the difference between the lowest and the highest desired VCOM voltage. If the default power-up code is not overwritten by software at the beginning of the adjustment cycle, the adjustment range is symmetrical around the chosen nominal VCOM voltage. Step 4: Calculate the resistors based on the following formulas or simply download the Microsoft Excel calculator located in the product folder of BUF0190x available at www.ti.com. R1 + 250kW @ Adj_range VCOM * 0.5 @ (Adj_range) R2 + V V S COM ǒ ) 1 500kW Ǔ* 1 R 1 1 * 250kW The BUF01900 can be used to drive small motors directly because of the large output drive capability (> 100mA), as illustrated in Figure 23. VSD @ R 2 ) 250kW @ ǒR 1 ) R 2Ǔ 15V (2) @ R 2 @ V S ) R 1 @ R 2 @ V S (Codeń1023) R1 MOTOR DRIVE CIRCUIT 1 1 R 1 With R1 and R2 properly set, VBIAS or VCOM output voltage can be calculated for any digital code with the following formula: V COM + Step 1: Supply Voltage is 10V. Step 2: Nominal VCOM is determined to be 4V. Step 3: The desired total adjustment range is 1V. In the case of using the default power-up DAC code (midscale), the adjustment range for the VCOM voltage will be from 3.5V to 4.5V. Step 4: Calculation of R1 and R2 R1 = 71.4kΩ => choose closest 1% resistor (71.5kΩ) R2 = 45.5kΩ => choose closest 1% resistor (45.3kΩ) Step 5: Appropriate number of adjustment steps between code 00h and code 3FFh is determined to be 32. This value leads to a step size of 32 codes between adjustment points, which translates into approximately 31mV voltage difference between steps. (1) CALCULATING THE VCOM OUTPUT VOLTAGE 250kW DESIGN EXAMPLE 10kΩ 10kΩ VCOM µC BUF01900 M (3) CALCULATING THE ADJUSTMENT RESOLUTION Figure 23. Motor Drive Circuit The resolution of the adjustment is a function of the step size. The resolution can be calculated by simply dividing the chosen adjustment range by the number of steps: Resolution = Adj_range/steps (example: 32 steps between code 0h and code 3FFh) 15 "#$%&$$ "#$%&$% www.ti.com SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006 PROGRAMMABLE POWER SUPPLY The BUF0190x integrated buffer amplifier can drive large capacitive loads (see Typical Characteristics) and greater than 100mA of output current, making it well-suited for programmable power supplies. Note that the BUF01900 integrated buffer has an input range that only extends to about 0.8V above GND; therefore, the programmable power supply is not able to output voltages less than approximately 0.8V. 3.3V 10kΩ 15V 10kΩ (1) µC Load + 100µF BUF01900 NOTE: (1) Optional −see Typical Characteristic curves Figure 10 through Figure 14 for load regulation performance. Figure 24. Programmable Power Supply 16 QFN/DFN THERMALLY-ENHANCED PACKAGE The BUF0190x uses the 10-lead DFN package, a thin, thermally-enhanced package designed to eliminate the use of bulky heat sinks and slugs traditionally used in thermal packages. The DFN package can be easily mounted using standard printed circuit board (PCB) assembly techniques. See QFN/SON PCB Attachment Application Note (SLUA271) available at www.ti.com. The thermal resistance junction to ambient (Rq JA) of the DFN package depends on the PCB layout. Using thermal vias and wide PCB traces improves thermal resistance. The thermal pad must be soldered to the PCB. The thermal pad on the bottom of the package should be connected to GND. Soldering the exposed thermal pad significantly improves board-level reliability during temperature cycling, key push, package shear, and similar board-level tests. Even with applications that have low-power dissipation, the exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability. PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty BUF01900AIDRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BUF01900AIDRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BUF01900AIDRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BUF01900AIDRCTG4 ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BUF01900AIPW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BUF01900AIPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BUF01900AIPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BUF01900AIPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BUF01901AIDRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BUF01901AIDRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BUF01901AIDRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BUF01901AIDRCTG4 ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BUF01901AIPW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BUF01901AIPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BUF01901AIPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BUF01901AIPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2007 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant BUF01900AIDRCR DRC 10 SITE 41 330 12 3.3 3.3 1.1 8 12 Q2 BUF01900AIDRCT DRC 10 SITE 41 180 12 3.3 3.3 1.1 8 12 Q2 BUF01900AIPWR PW 8 SITE 41 330 12 7.0 3.6 1.6 8 12 Q1 BUF01901AIDRCR DRC 10 SITE 41 330 12 3.3 3.3 1.1 8 12 Q2 BUF01901AIDRCT DRC 10 SITE 41 180 12 3.3 3.3 1.1 8 12 Q2 BUF01901AIPWR PW 8 SITE 41 330 12 7.0 3.6 1.6 8 12 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) BUF01900AIDRCR DRC 10 SITE 41 346.0 346.0 29.0 BUF01900AIDRCT DRC 10 SITE 41 190.0 212.7 31.75 29.0 BUF01900AIPWR PW 8 SITE 41 346.0 346.0 BUF01901AIDRCR DRC 10 SITE 41 346.0 346.0 29.0 BUF01901AIDRCT DRC 10 SITE 41 190.0 212.7 31.75 BUF01901AIPWR PW 8 SITE 41 346.0 346.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. 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