www.ti.com TPS61030 TPS61031, TPS61032 SLUS534D – SEPTEMBER 2002 – REVISED APRIL 2004 96% EFFICIENT SYNCHRONOUS BOOST CONVERTER WITH 4A SWITCH FEATURES • • • • • • • • • • DESCRIPTION 96% Efficient Synchronous Boost Converter With 1000-mA Output Current From 1.8-V Input Device Quiescent Current: 20-µA (Typ) Input Voltage Range: 1.8-V to 5.5-V Fixed and Adjustable Output Voltage Options Up to 5.5-V Power Save Mode for Improved Efficiency at Low Output Power Low Battery Comparator Low EMI-Converter (Integrated Antiringing Switch) Load Disconnect During Shutdown Over-Temperature Protection Available in a Small 4 mm x 4 mm QFN-16 or in a TSSOP-16 Package The TPS6103x devices provide a power supply solution for products powered by either a one-cell Li-Ion or Li-polymer, or a two to three-cell alkaline, NiCd or NiMH battery. The converter generates a stable output voltage that is either adjusted by an external resistor divider or fixed internally on the chip. It provides high efficient power conversion and is capable of delivering output currents up to 1 A at 5 V at a supply voltage down to 1.8 V. The implemented boost converter is based on a fixed frequency, pulse-width- modulation (PWM) controller using a synchronous rectifier to obtain maximum efficiency. At low load currents the converter enters Power Save mode to maintain a high efficiency over a wide load current range. The Power Save mode can be disabled, forcing the converter to operate at a fixed switching frequency. It can also operate synchronized to an external clock signal that is applied to the SYNC pin. The maximum peak current in the boost switch is limited to a value of 4500 mA. APPLICATIONS • The converter can be disabled to minimize battery drain. During shutdown, the load is completely disconnected from the battery. A low-EMI mode is implemented to reduce ringing and, in effect, lower radiated electromagnetic energy when the converter enters the discontinuous conduction mode. All Single Cell Li or Dual Cell Battery Operated Products as MP-3 Player, PDAs, and Other Portable Equipment The device is packaged in a 16-pin QFN package measuring 4 mm x 4 mm (RSA) or in a 16-pin TSSOP PowerPAD™ package (PWP). L1 6.8 µH SW VOUT VBAT 1.8 V to 5 V Input C1 10 µF R1 R3 EN C2 2.2 µF C3 220 µF e.g. 5 V up to 1000 mA FB LBI R4 R6 R2 SYNC GND LBO PGND Low Battery Comparator Output TPS6103x Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2004, Texas Instruments Incorporated TPS61030 TPS61031, TPS61032 www.ti.com SLUS534D – SEPTEMBER 2002 – REVISED APRIL 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OUTPUT VOLTAGE OPTIONS (1) OUTPUT VOLTAGE DC/DC TA PACKAGE Adjustable 3.3 V 40°C to 85°C TPS61030PWP 16-Pin TSSOP PowerPAD™ 5V TPS61030RSA 16-Pin QFN 5V (1) (2) TPS61031PWP TPS61032PWP Adjustable 3.3 V PART NUMBER (2) TPS61031RSA TPS61032RSA Contact the factory to check availability of other fixed output voltage versions. The packages are available taped and reeled. Add R suffix to device type (e.g., TPS61030PWPR or TPS61030RSAR) to order quantities of 2000 devices per reel for the PWP packaged devices and 3000 units per reel for the RSA package. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) TPS6103x Input voltage range on LBI -0.3 V to 3.6 V Input voltage range on SW, VOUT, LBO, VBAT, SYNC, EN, FB -0.3 V to 7 V Maximum junction temperature TJ -40°C to 150°C Storage temperature range Tstg -65°C to 150°C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Supply voltage at VBAT, VI 1.8 5.5 V Operating ambient temperature range, TA -40 85 °C Operating virtual junction temperaturerange, TJ -40 125 °C 2 TPS61030 TPS61031, TPS61032 www.ti.com SLUS534D – SEPTEMBER 2002 – REVISED APRIL 2004 ELECTRICAL CHARACTERISTICS over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature range of 25°C) (unless otherwise noted) DC/DC STAGE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VI Input voltage range 1.8 5.5 V VO TPS61030 output voltage range 1.8 5.5 V VFB TPS61030 feedback voltage 490 500 510 mV f Oscillator frequency 500 600 700 kHz Frequency range for synchronization 500 700 kHz 4500 mA Switch current limit VOUT= 5 V 3600 Start-up current limit 4000 0.4 x ISW mA SWN switch on resistance VOUT= 5 V 55 mΩ SWP switch on resistance VOUT= 5 V 55 mΩ Total accuracy -3% 3% Line regulation 0.6% Load regulation 0.6% VBAT IO = 0 mA, VEN = VBAT = 1.8 V, VOUT =5 V 10 25 µA VOUT IO = 0 mA, VEN = VBAT = 1.8 V, VOUT = 5 V 10 20 µA VEN= 0 V, VBAT = 2.4 V 0.1 1 µA MIN TYP MAX UNIT 490 500 510 mV Quiescent current Shutdown current CONTROL STAGE PARAMETER TEST CONDITIONS VUVLO Under voltage lockout threshold VLBI voltage decreasing VIL LBI voltage threshold VLBI voltage decreasing 1.5 LBI input hysteresis V 10 mV LBI input current EN = VBAT or GND 0.01 0.1 LBO output low voltage VO = 3.3 V, IOI = 100 µA 0.04 0.4 LBO output low current LBO output leakage current VIL EN, SYNC input low voltage VIH EN, SYNC input high voltage EN, SYNC input current 100 VLBO= 7 V 0.01 V µA 0.1 µA 0.2 × VBAT V 0.1 µA 0.8 × VBAT Clamped on GND or VBAT µA V 0.01 Overtemperature protection 140 °C Overtemperature hysteresis 20 °C 3 TPS61030 TPS61031, TPS61032 www.ti.com SLUS534D – SEPTEMBER 2002 – REVISED APRIL 2004 PIN ASSIGNMENTS 1 2 3 4 5 6 7 8 PowerPAD 16 15 14 13 12 11 10 9 NC VOUT VOUT VOUT FB GND LBO EN VOUT NC SW LBO EN SYNC LBI SW PGND PGND PGND VBAT SW SW PGND PGND PGND VBAT LBI SYNC RSA PACKAGE (TOP VIEW) VOUT VOUT FB GND PWP PACKAGE (TOP VIEW) NC − No internal connection Terminal Functions TERMINAL NO. NAME I/O DESCRIPTION RSA EN 9 11 I Enable input. (1/VBAT enabled, 0/GND disabled) FB 12 14 I Voltage feedback of adjustable versions GND 11 13 I/O Control/logic ground LBI 7 9 I Low battery comparator input (comparator enabled with EN) LBO 10 12 O Low battery comparator output (open drain) NC 16 2 SYNC 8 10 SW 1, 2 PGND 3, 4, 5 VBAT 6 VOUT 13, 14, 15 PowerPAD™ 4 PWP Not connected I Enable/disable power save mode (1/VBAT disabled, 0/GND enabled, clock signal for synchronization) 3, 4 I Boost and rectifying switch input 5, 6, 7 I/O Power ground 8 I Supply voltage 1, 15, 16 O DC/DC output Must be soldered to achieve appropriate power dissipation. Should be connected to PGND. TPS61030 TPS61031, TPS61032 www.ti.com SLUS534D – SEPTEMBER 2002 – REVISED APRIL 2004 FUNCTIONAL BLOCK DIAGRAM SW VOUT AntiRinging VBAT PGND PGND Gate Control 100 k PGND 10 pF Error Amplifier _ FB Regulator + + _ VREF = 0.5 V Control Logic Oscillator GND Temperature Control EN SYNC GND + _ LBI + _ Low Battery Comparator LBO VREF = 0.5 V GND PARAMETER MEASUREMENT INFORMATION L1 6.8 µH SW VOUT VBAT Power Supply C1 10 µF R1 R3 EN C2 2.2 µF C3 220 µF VCC Boost Output FB LBI R4 R6 R2 SYNC GND List of Components: U1 = TPS6103xPWP L1 = Sumida CDRH124–6R8 C1, C2 = X7R/X5R Ceramic C3 = Low ESR Tantalum LBO Control Output PGND TPS6103x 5 TPS61030 TPS61031, TPS61032 www.ti.com SLUS534D – SEPTEMBER 2002 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS Table of Graphs DC/DC Converter Figure Maximum output current vs Input voltage Efficiency Output voltage 1, 2 vs Output current (TPS61030) (VO = 2.5 V, VI = 1.8 V, VSYNC = 0 V) 3 vs Output current (TPS61031) (VO = 3.3 V, VI = 1.8 V, 2.4 V, VSYNC = 0 V) 4 vs Output current (TPS61032) (VO = 5.0 V, VI = 2.4 V, 3.3 V, VSYNC = 0 V) 5 vs Input voltage (TPS61031) (IO = 10 mA, 100 mA, 1000 mA, VSYNC = 0 V) 6 vs Input voltage (TPS61032) (IO = 10 mA, 100 mA, 1000 mA, VSYNC = 0 V) 7 vs Output current (TPS61031) (VI = 2.4 V) 8 vs Output current (TPS61032) (VI = 3.3 V) 9 No-load supply current into VBAT vs Input voltage (TPS61032) 10 No-load supply current into VOUT vs Input voltage (TPS61032) 11 Minimum Load Resistance at Startup vs Input voltage (TPS61032) 12 Output voltage in continuous mode (TPS61032) 13 Output voltage in power save mode (TPS61032) 14 Load transient response (TPS61032) 15 Line transient response (TPS61032) 16 DC/DC converter start-up after enable (TPS61032) 17 Waveforms TPS61032 MAXIMUM OUTPUT CURRENT vs INPUT VOLTAGE 3.5 3.5 3 3 Maximum Output Current - A Maximum Output Current - A TPS61031 MAXIMUM OUTPUT CURRENT vs INPUT VOLTAGE 2.5 2 1.5 1 0.5 0 2 1.5 1 0.5 1.8 2.2 2.6 3 3.4 3.8 VI - Input Voltage - V Figure 1. 6 2.5 4.2 4.6 5 0 1.8 2.2 2.6 3 3.4 3.8 VI - Input Voltage - V Figure 2. 4.2 4.6 5 TPS61030 TPS61031, TPS61032 www.ti.com SLUS534D – SEPTEMBER 2002 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) TPS61030 EFFICIENCY vs OUTPUT CURRENT TPS61031 EFFICIENCY vs OUTPUT CURRENT 100 100 90 90 80 80 70 70 Efficiency - % Efficiency - % VBAT = 1.8 V 60 50 40 60 50 40 30 30 20 20 VO = 2.5 V VI = 1.8 V 10 VBAT = 2.4 V 10 VO = 3.3 V 0 0 1 10 100 1000 IO - Output Current - mA 1 10000 10 100 Figure 3. Figure 4. TPS61032 EFFICIENCY vs OUTPUT CURRENT TPS61031 EFFICIENCY vs INPUT VOLTAGE 100 10000 100 IO = 100 mA 90 VBAT = 2.4 V 80 IO = 1000 mA 90 VBAT = 3.3 V IO = 10 mA Efficiency - % 70 Efficiency - % 1000 IO - Output Current - mA 60 50 40 80 70 30 20 60 VO = 5 V 10 0 1 10 100 1000 IO - Output Current - mA Figure 5. 10000 50 1.8 2 2.2 2.4 2.6 2.8 VI - Input Voltage - V 3 3.2 Figure 6. 7 TPS61030 TPS61031, TPS61032 www.ti.com SLUS534D – SEPTEMBER 2002 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) TPS61032 EFFICIENCY vs INPUT VOLTAGE TPS61031 OUTPUT VOLTAGE vs OUTPUT CURRENT 3.4 100 IO = 100 mA 95 90 80 VO - Output Voltage - V Efficiency - % 3.35 IO = 10 mA 85 IO = 1000 mA 75 70 65 3.3 VBAT = 2.4 V 3.25 60 55 3.2 50 1.8 2.2 2.6 3 3.4 3.8 VI - Input Voltage - V 4.2 4.6 5 1 Figure 7. Figure 8. TPS61032 OUTPUT VOLTAGE vs OUTPUT CURRENT TPS61032 NO-LOAD SUPPLY CURRENT INTO VBAT vs INPUT VOLTAGE 5.15 5.1 VO - Output Voltage - V 10000 16 No-Load Supply Current Into VBAT - µ A 5.2 5.05 VBAT = 3.3 V 5 4.95 4.9 4.85 1 10 100 1000 IO - Output Current - mA Figure 9. 10000 85°C 14 25°C 12 -40°C 10 8 6 4 2 0 4.8 8 10 100 1000 IO - Output Current - mA 2 3 4 VI - Input Voltage - V Figure 10. 5 TPS61030 TPS61031, TPS61032 www.ti.com SLUS534D – SEPTEMBER 2002 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) TPS61032 NO-LOAD SUPPLY CURRENT INTO VOUT vs INPUT VOLTAGE MINIMUM LOAD RESISTANCE AT START-UP vs INPUT VOLTAGE 14 14 Ω 12 Minimum Load Resistance at Startup - No-Load Supply Current Into VOUT - µ A 85°C 25°C -40°C 10 8 6 4 2 0 2 3 4 VI - Input Voltage - V 5 12 10 8 6 4 2 0 1.8 2.2 2.6 3 3.4 3.8 4.2 VI - Input Voltage - V 4.6 Figure 11. Figure 12. TPS61032 OUTPUT VOLTAGE IN CONTINUOUS MODE TPS61032 OUTPUT VOLTAGE IN POWER SAVE MODE Output Voltage 20 mV/Div VI = 3.3 V, RL = 5 5 VI = 3.3 V, RL = 100 Output Voltage 50 mV/Div, AC Inductor Current 200 mA/Div Timebase - 1 µs/Div Figure 13. Inductor Current 200 mA/Div, DC Timebase - 200 µs/Div Figure 14. 9 TPS61030 TPS61031, TPS61032 www.ti.com SLUS534D – SEPTEMBER 2002 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) TPS61032 LOAD TRANSIENT RESPONSE VI = 2.5 V, IL = 80 mA to 800 mA TPS61032 LINE TRANSIENT RESPONSE Output Current 500 mA/Div, DC VI = 2.2 V to 2.7 V, RL = 50 Input Voltage 500 mV/Div, DC Output Voltage 20 mV/Div, AC Output Voltage 50 mV/Div, AC Timebase - 2 ms/Div Timebase - 2 ms/Div Figure 15. Figure 16. TPS61032 DC/DC CONVERTER START-UP AFTER ENABLE Enable 5 V/Div, DC Output Voltage 2 V/Div, DC Input Current 500 mA/Div, DC Voltage at SW 2 V/Div, DC VI = 2.4 V, RL = 20 Timebase - 400 µs/Div Figure 17. 10 TPS61030 TPS61031, TPS61032 www.ti.com SLUS534D – SEPTEMBER 2002 – REVISED APRIL 2004 DETAILED DESCRIPTION Controller Circuit The controller circuit of the device is based on a fixed frequency multiple feedforward controller topology. Input voltage, output voltage, and voltage drop on the NMOS switch are monitored and forwarded to the regulator. So changes in the operating conditions of the converter directly affect the duty cycle and must not take the indirect and slow way through the control loop and the error amplifier. The control loop, determined by the error amplifier, only has to handle small signal errors. The input for it is the feedback voltage on the FB pin or, at fixed output voltage versions, the voltage on the internal resistor divider. It is compared with the internal reference voltage to generate an accurate and stable output voltage. The peak current of the NMOS switch is also sensed to limit the maximum current flowing through the switch and the inductor. The typical peak current limit is set to 4000 mA. An internal temperature sensor prevents the device from getting overheated in case of excessive power dissipation. Synchronous Rectifier The device integrates an N-channel and a P-channel MOSFET transistor to realize a synchronous rectifier. Because the commonly used discrete Schottky rectifier is replaced with a low RDS(ON) PMOS switch, the power conversion efficiency reaches 96%. To avoid ground shift due to the high currents in the NMOS switch, two separate ground pins are used. The reference for all control functions is the GND pin. The source of the NMOS switch is connected to PGND. Both grounds must be connected on the PCB at only one point close to the GND pin. A special circuit is applied to disconnect the load from the input during shutdown of the converter. In conventional synchronous rectifier circuits, the backgate diode of the high-side PMOS is forward biased in shutdown and allows current flowing from the battery to the output. This device however uses a special circuit which takes the cathode of the backgate diode of the high-side PMOS and disconnects it from the source when the regulator is not enabled (EN = low). The benefit of this feature for the system design engineer is that the battery is not depleted during shutdown of the converter. No additional components have to be added to the design to make sure that the battery is disconnected from the output of the converter. Device Enable The device is put into operation when EN is set high. It is put into a shutdown mode when EN is set to GND. In shutdown mode, the regulator stops switching, all internal control circuitry including the low-battery comparator is switched off, and the load is isolated from the input (as described in the Synchronous Rectifier Section). This also means that the output voltage can drop below the input voltage during shutdown. During start-up of the converter, the duty cycle and the peak current are limited in order to avoid high peak currents drawn from the battery. Undervoltage Lockout An undervoltage lockout function prevents device start-up if the supply voltage on VBAT is lower than approximately 1.6 V. When in operation and the battery is being discharged, the device automatically enters the shutdown mode if the voltage on VBAT drops below approximately 1.6 V. This undervoltage lockout function is implemented in order to prevent the malfunctioning of the converter. Softstart When the device enables the internal start-up cycle starts with the first step, the precharge phase. During precharge, the rectifying switch is turned on until the output capacitor is charged to a value close to the input voltage. The rectifying switch current is limited in that phase. This also limits the output current under short-circuit conditions at the output. After charging the output capacitor to the input voltage the device starts switching. Until the output voltage is reached, the boost switch current limit is set to 40% of its nominal value to avoid high peak currents at the battery during startup. When the output voltage is reached, the regulator takes control and the switch current limit is set back to 100%. 11 TPS61030 TPS61031, TPS61032 SLUS534D – SEPTEMBER 2002 – REVISED APRIL 2004 www.ti.com Detailed Description (continued) Power Save Mode and Synchronization The SYNC pin can be used to select different operation modes. To enable power save, SYNC must be set low. Power save mode is used to improve efficiency at light load. In power save mode the converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output voltage with one or several pulses and goes again into power save mode once the output voltage exceeds the set threshold voltage. This power save mode can be disabled by setting the SYNC to VBAT. Applying an external clock with a duty cycle between 30% and 70% at the SYNC pin forces the converter to operate at the applied clock frequency. The external frequency has to be in the range of about ±20% of the nominal internal frequency. Detailed values are shown in the electrical characteristic section of the data sheet. Low Battery Detector Circuit—LBI/LBO The low-battery detector circuit is typically used to supervise the battery voltage and to generate an error flag when the battery voltage drops below a user-set threshold voltage. The function is active only when the device is enabled. When the device is disabled, the LBO pin is high-impedance. The switching threshold is 500 mV at LBI. During normal operation, LBO stays at high impedance when the voltage, applied at LBI, is above the threshold. It is active low when the voltage at LBI goes below 500 mV. The battery voltage, at which the detection circuit switches, can be programmed with a resistive divider connected to the LBI pin. The resistive divider scales down the battery voltage to a voltage level of 500 mV, which is then compared to the LBI threshold voltage. The LBI pin has a built-in hysteresis of 10 mV. See the application section for more details about the programming of the LBI threshold. If the low-battery detection circuit is not used, the LBI pin should be connected to GND (or to VBAT) and the LBO pin can be left unconnected. Do not let the LBI pin float. Low-EMI Switch The device integrates a circuit that removes the ringing that typically appears on the SW node when the converter enters discontinuous current mode. In this case, the current through the inductor ramps to zero and the rectifying PMOS switch is turned off to prevent a reverse current flowing from the output capacitors back to the battery. Due to the remaining energy that is stored in parasitic components of the semiconductor and the inductor, a ringing on the SW pin is induced. The integrated antiringing switch clamps this voltage to VBAT and therefore dampens ringing. 12 TPS61030 TPS61031, TPS61032 www.ti.com SLUS534D – SEPTEMBER 2002 – REVISED APRIL 2004 APPLICATION INFORMATION Design Procedure The TPS6103x dc/dc converters are intended for systems powered by a dual or triple cell NiCd or NiMH battery with a typical terminal voltage between 1.8 V and 5.5 V. They can also be used in systems powered by one-cell Li-Ion with a typical stack voltage between 2.5 V and 4.2 V. Additionally, two or three primary and secondary alkaline battery cells can be the power source in systems where the TPS6103x is used. Programming the Output Voltage The output voltage of the TPS61030 dc/dc converter section can be adjusted with an external resistor divider. The typical value of the voltage on the FB pin is 500 mV. The maximum allowed value for the output voltage is 5.5 V. The current through the resistive divider should be about 100 times greater than the current into the FB pin. The typical current into the FB pin is 0.01 µA, and the voltage across R6 is typically 500 mV. Based on those two values, the recommended value for R4 should be lower than 500 kΩ, in order to set the divider current at 1 µA or higher. Because of internal compensation circuitry the value for this resistor should be in the range of 200 kΩ. From that, the value of resistor R3, depending on the needed output voltage (VO), can be calculated using equation 1: V V O 1 180 k O 1 R3 R4 V 500 mV FB (1) If as an example, an output voltage of 3.3 V is needed, a 1-MΩ resistor should be chosen for R3. If for any reason the value for R4 is chosen significantly lower than 200 kΩ additional capacitance in parallel to R3 is recommended. The required capacitance value can be easily calculated using Equation 2: C parR3 10 pF 200 k –1 R4 (2) L1 VOUT SW C2 VBAT Power Supply C1 R1 C3 VCC Boost Output R3 EN FB LBI R4 R6 R2 SYNC LBO GND Control Output PGND TPS6103x Figure 18. Typical Application Circuit for Adjustable Output Voltage Option Programming the LBI/LBO Threshold Voltage The current through the resistive divider should be about 100 times greater than the current into the LBI pin. The typical current into the LBI pin is 0.01 µA, and the voltage across R2 is equal to the LBI voltage threshold that is generated on-chip, which has a value of 500 mV. The recommended value for R2 is therefore in the range of 500 kΩ. From that, the value of resistor R1, depending on the desired minimum battery voltage VBAT, can be calculated using Equation 3. 13 TPS61030 TPS61031, TPS61032 www.ti.com SLUS534D – SEPTEMBER 2002 – REVISED APRIL 2004 APPLICATION INFORMATION (continued) R1 R2 V V BAT LBIthreshold 1 390 k V BAT 1 500 mV (3) The output of the low battery supervisor is a simple open-drain output that goes active low if the dedicated battery voltage drops below the programmed threshold voltage on LBI. The output requires a pullup resistor with a recommended value of 1 MΩ. The maximum voltage which is used to pull up the LBO outputs should not exceed the output voltage of the dc/dc converter. If not used, the LBO pin can be left floating or tied to GND. Inductor Selection A boost converter normally requires two main passive components for storing energy during the conversion. A boost inductor and a storage capacitor at the output are required. To select the boost inductor, it is recommended to keep the possible peak inductor current below the current limit threshold of the power switch in the chosen configuration. For example, the current limit threshold of the TPS6103x's switch is 4500 mA at an output voltage of 5 V. The highest peak current through the inductor and the switch depends on the output load, the input (VBAT), and the output voltage (VOUT). Estimation of the maximum average inductor current can be done using Equation 4: V OUT I I L OUT V 0.8 BAT (4) For example, for an output current of 1000 mA at 5 V, at least 3500 mA of average current flows through the inductor at a minimum input voltage of 1.8 V. The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it is advisable to work with a ripple of less than 20% of the average inductor current. A smaller ripple reduces the magnetic hysteresis losses in the inductor, as well as output voltage ripple and EMI. But in the same way, regulation time at load changes rises. In addition, a larger inductor increases the total system costs. With those parameters, it is possible to calculate the value for the inductor by using Equation 5: V L V –V BAT OUT BAT I ƒ V L OUT (5) Parameter f is the switching frequency and ∆IL is the ripple current in the inductor, i.e., 10% × IL. In this example, the desired inductor has the value of 5.5 µH. In typical applications a 6.8 µH inductance is recommended. The minimum possible inductance value is 2.2 µH. With the calculated inductance and current values, it is possible to choose a suitable inductor. Care has to be taken that load transients and losses in the circuit can lead to higher currents as estimated in equation 4. Also, the losses in the inductor caused by magnetic hysteresis losses and copper losses are a major parameter for total circuit efficiency. The following inductor series from different suppliers have been used with the TPS6103x converters: List of Inductors VENDOR INDUCTOR SERIES CDRH124 Sumida CDRH103R CDRH104R Wurth Electronik EPCOS 14 7447779___ 744771___ B82464G TPS61030 TPS61031, TPS61032 www.ti.com SLUS534D – SEPTEMBER 2002 – REVISED APRIL 2004 Capacitor Selection Input Capacitor At least a 10-µF input capacitor is recommended to improve transient behavior of the regulator and EMI behavior of the total power supply circuit. A ceramic capacitor or a tantalum capacitor with a 100-nF ceramic capacitor in parallel, placed close to the IC, is recommended. Output Capacitor The major parameter necessary to define the output capacitor is the maximum allowed output voltage ripple of the converter. This ripple is determined by two parameters of the capacitor, the capacitance and the ESR. It is possible to calculate the minimum capacitance needed for the defined ripple, supposing that the ESR is zero, by using Equation 6: I C min V V OUT OUT BAT ƒ V V OUT (6) Parameter f is the switching frequency and ∆V is the maximum allowed ripple. With a chosen ripple voltage of 10 mV, a minimum capacitance of 100 µF is needed. The total ripple is larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 7: V I R ESR OUT ESR (7) An additional ripple of 80 mV is the result of using a tantalum capacitor with a low ESR of 80 mΩ. The total ripple is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the capacitor. In this example, the total ripple is 90 mV. Additional ripple is caused by load transients. This means that the output capacitance needs to be larger than calculated above to meet the total ripple requirements. The output capacitor must completely supply the load during the charging phase of the inductor. A reasonable value of the output capacitance depends on the speed of the load transients and the load current during the load change. With the calculated minimum value of 100 µF and load transient considerations, a recommended output capacitance value is in around 220 µF. For economical reasons this usually is a tantalum capacitor. Because of this the control loop has been optimized for using output capacitors with an ESR of above 30 mΩ. The minimum value for the output capacitor is 22 µF. Small Signal Stability When using output capacitors with lower ESR, like ceramics, it is recommended to use the adjustable voltage version. The missing ESR can be easily compensated there in the feedback divider. Typically a capacitor in the range of 10 pF in parallel to R3 helps to obtain small signal stability with lowest ESR output capacitors. For more detailed analysis the small signal transfer function of the error amplifier and regulator, which is given in Equation 8, can be used. 5 (R3 R4) A d REG V R4 (1 i 2.3 s) FB (8) LAYOUT CONSIDERATIONS As for all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a common ground node for power ground and a different one for control ground to minimize the effects of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC. The feedback divider should be placed as close as possible to the control ground pin of the IC. To lay out the control ground, it is recommended to use short traces as well, separated from the power ground traces. This avoids ground shift problems, which can occur due to superimposition of power ground current and control ground current. 15 TPS61030 TPS61031, TPS61032 www.ti.com SLUS534D – SEPTEMBER 2002 – REVISED APRIL 2004 Layout Considerations (continued) L1 Battery Input C2 2.2 µF VBAT R1 C1 10 µF VCC 5 V Boost Output VOUT SW 6.8 µH EN C3 220 µF FB R6 LBI R2 SYNC LBO LBO GND PGND TPS61032 List of Components: U1 = TPS6103xPWP L1 = Sumida CDRH124–6R8 C1, C2 = X7R,X5R Ceramic C3 = Low ESR Tantalum Figure 19. Power Supply Solution for Maximum Output Power C5 VCC2 10 V Unregulated Auxiliary Output DS1 C6 1 µF 0.1 µF L1 6.8 µH Battery Input SW C2 2.2 µF VBAT C3 10 µF R1 VCC1 5 V Boost Main Output VOUT C3 220 µF EN FB LBI R6 R2 SYNC GND List of Components: U1 = TPS6103xPWP L1 = Sumida CDRH124–6R8 C3, C5, C6, = X7R,X5R Ceramic C3 = Low ESR Tantalum DS1 = BAT54S LBO LBO PGND TPS61032 Figure 20. Power Supply Solution With Auxiliary Positive Output Voltage 16 TPS61030 TPS61031, TPS61032 www.ti.com SLUS534D – SEPTEMBER 2002 – REVISED APRIL 2004 Layout Considerations (continued) C5 DS1 VCC2 –5 V Unregulated Auxiliary Output C6 1 µF 0.1 µF L1 6.8 µH Battery Input SW C2 2.2 µF VBAT C1 10 µF R1 VCC1 5 V Boost Main Output VOUT C3 220 µF EN FB LBI R6 R2 SYNC GND List of Components: U1 = TPS6103xPWP L1 = Sumida CDRH124–6R8 C1, C2, C5, C6 = X7R,X5R Ceramic C3 = Low ESR Tantalum DS1 = BAT54S LBO LBO PGND TPS61032 Figure 21. Power Supply Solution With Auxiliary Negative Output Voltage THERMAL INFORMATION Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component. Three basic approaches for enhancing thermal performance are listed below: • Improving the power dissipation capability of the PCB design • Improving the thermal coupling of the component to the PCB • Introducing airflow in the system The maximum junction temperature (TJ) of the TPS6103x devices is 125°C. The thermal resistance of the 16-pin TSSOP PowerPAD package (PWP) is RΘJA = 36.5 °C/W (QFN package, RSA, 38.1 °C/W), if the PowerPAD is soldered. Specified regulator operation is assured to a maximum ambient temperature TA of 85°C. Therefore, the maximum power dissipation for the PWP package is about 1096 mW, for the RSA package it is about 1050 mW. More power can be dissipated if the maximum ambient temperature of the application is lower. T T J(MAX) A P 125°C 85°C 1096 mW D(MAX) R 36.5°CW JA 17 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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