Industrial Temperature K4F661612D, K4F641612D CMOS DRAM 4M x 16bit CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 4,194,304 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low pow er) are optional features of this family. All of this family have CAS -before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 Fast Page Mode DRAM family is fabricated using Samsung ′s advanced CMOS process to realize high band-width, low power consumption and high reliability. FEATURES • Fast Page Mode operation • Part Identification • 2CAS Byte/Word Read/Write operation - K4F661612D-TI/P(3.3V, 8K Ref.) - K4F641612D-TI/P(3.3V, 4K Ref.) • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability • Self-refresh capability (L-ver only) • Fast parallel test mode capability • LVTTL(3.3V) compatible inputs and outputs • Active Power Dissipation Unit : mW • Early Write or output enable controlled write Speed 8K 4K • JEDEC Standard pinout -45 324 468 • Available in Plastic TSOP(II) packages -50 288 432 -60 252 396 • +3.3V ±0.3V power supply • Industrial Temperature operating ( -40~85°C ) • Refresh Cycles Refresh cycle Normal L-ver K4F661612D* 8K 64ms 128ms K4F641612D 4K FUNCTIONAL BLOCK DIAGRAM Refresh time * Access mode & RAS only refresh mode : 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.) CAS -before-RAS & Hidden refresh mode : 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.) RAS UCAS LCAS W Control Clocks Refresh Timer • Performance Range Speed t RAC t CAC t RC t PC -45 45ns 12ns 80ns 31ns -50 50ns 13ns 90ns 35ns -60 60ns 15ns 110ns 40ns A0~A12 (A0~A11)*1 Row Address Buffer A0~A8 (A0~A9)*1 Col. Address Buffer Lower Data in Buffer Row Decoder Refresh Control Refresh Counter Vcc Vss VBB Generator Memory Array 4,194,304 x 16 Cells Column Decoder Note) *1 : 4K Refresh SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. Sens e Am ps & I/O Part NO. Lower Data out Buffer Upper Data in Buffer Upper Data out Buffer DQ0 to DQ7 OE D Q8 to DQ15 Industrial Temperature K4F661612D, K4F641612D CMOS DRAM PIN CONFIGURATION (Top Views) • K4F661612D-T • K4F641612D-T VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C VCC W RAS N.C N.C N.C N.C A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 V SS DQ15 DQ14 DQ13 DQ12 V SS DQ11 DQ10 DQ9 DQ8 N.C V SS LCAS UCAS OE N.C N.C A12(N.C)* A11 A10 A9 A8 A7 A6 V SS (400mil TSOP(II)) *(N.C) : N.C for 4K Refresh Product Pin Name Pin function A0 - A12 Address Inputs(8K Product) A0 - A11 Address Inputs(4K Product) DQ0 - 15 Data In/Out VSS Ground RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe W Read/Write Input OE Data Output Enable VCC Power(+3.3V) N.C No Connection Industrial Temperature K4F661612D, K4F641612D CMOS DRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Units VIN, VO U T -0.5 to +4.6 V Voltage on VC C supply relative to VSS V CC -0.5 to +4.6 V Storage Temperature Tstg -55 to +150 °C PD 1 W IOS Address 50 mA Voltage on any pin relative to VSS Power Dissipation Short Circuit Output Current * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter (Voltage referenced to Vss, T A= -40 to 85°C) Symbol Min Typ Max Units Supply Voltage VC C 3.0 3.3 3.6 V Ground VSS 0 0 0 V *1 Input High Voltage VI H 2.0 - Vcc+0.3 V Input Low Voltage V IL -0.3 *2 - 0.8 V *1 : Vcc+1.3V at pulse width ≤15ns which is measured at VCC *2 : -1.3 at pulse width ≤15ns which is measured at VSS DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter Symbol Min Max Units Input Leakage Current (Any input 0≤V I N≤V CC+0.3V, all other pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V≤V OUT ≤VCC ) IO(L) -5 5 uA Output High Voltage Level(IO H=-2mA) VO H 2.4 - V Output Low Voltage Level(I OL =2mA) VOL - 0.4 V Industrial Temperature K4F661612D, K4F641612D CMOS DRAM DC AND OPERATING CHARACTERISTICS Symbol Power Speed IC C 1 Don′t care IC C 2 (Continued) Max Units K4F661612D K4F641612D -45 -50 -60 90 80 70 130 120 110 mA mA mA Normal L Don′t care 1 1 1 1 mA mA IC C 3 Don′t care -45 -50 -60 90 80 70 130 120 110 mA mA mA IC C 4 Don′t care -45 -50 -60 70 60 50 70 60 50 mA mA mA IC C 5 Normal L Don′t care 0.5 200 0.5 200 mA uA IC C 6 Don′t care -45 -50 -60 130 120 110 130 120 110 mA mA mA IC C 7 L Don′t care 350 350 uA ICCS L Don′t care 350 350 uA IC C 1* : Operating Current (RAS and UCAS, LCAS, Address cycling @t R C=min.) IC C 2 : Standby Current (RAS=UCAS=LCAS=W=VIH ) IC C 3* : RAS-only Refresh Current (UCAS=LCAS=V IH , RAS, Address cycling @tRC =min.) IC C 4* : Fast Page Mode Current (RAS=VIL , UCAS or LCAS, Address cycling @ tPC =min.) IC C 5 : Standby Current (RAS=UCAS=LCAS=W=VCC -0.2V) IC C 6* : CAS-Before- RAS Refresh Current (RAS and UCAS or LCAS cycling @t R C=min) IC C 7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH )=VC C-0.2V, Input low voltage(VIL )=0.2V, UCAS , LCAS=CAS -before-RAS cycling or 0.2V, W, OE=V IH , Address=Don′t care, DQ=Open, TRC=31.25us IC C S : Self Refresh Current RAS=UCAS =LCAS=0.2V, W=OE=A0 ~ A12(A11)=VC C-0.2V or 0.2V, DQ0 ~ DQ15=V CC-0.2V, 0.2V or Open *Note : ICC1 , I CC3, I CC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In IC C 1, I CC3 and ICC6, address can be changed maximum once while RAS =VIL. In I CC4 , address can be changed maximum once within one fast page mode cycle time, t PC . Industrial Temperature K4F661612D, K4F641612D CAPACITANCE CMOS DRAM (TA=25°C, VCC=3.3V, f=1MHz) Parameter Symbol Min Max Units Input capacitance [A0 ~ A12] CI N 1 - 5 pF Input capacitance [RAS, UCAS, LCAS, W, OE ] CI N 2 - 7 pF Output capacitance [DQ0 - DQ15] C DQ - 7 pF AC CHARACTERISTICS (-40°C≤T A≤85°C, See note 2) Test condition : V CC =3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V Parameter -45 Symbol Min -50 Max Min -60 Max Min Units Note Max Random read or write cycle time tR C 80 90 110 ns Read-modify-write cycle time tRWC 115 133 153 ns Access time from RAS tRAC 45 50 60 ns 3,4,10 Access time from CAS tCAC 12 13 15 ns 3,4,5 Access time from column address tAA 23 25 30 ns 3,10 CAS to output in Low-Z tCLZ 0 ns 3 Output buffer turn-off delay tO F F 0 13 0 13 0 13 ns 6 Transition time (rise and fall) tT 1 50 1 50 1 50 ns 2 RAS precharge time tR P 25 RAS pulse width 0 0 30 10K 50 40 10K 60 ns tR A S 45 RAS hold time tRSH 12 13 15 10K ns ns CAS hold time tCSH 45 50 60 ns CAS pulse width tC A S 12 10K 13 10K 15 10K ns RAS to CAS delay time tRCD 18 33 20 37 20 45 ns 4 RAS to column address delay time tRAD 13 22 15 25 15 30 ns 10 CAS to RAS precharge time tCRP 5 5 5 ns Row address set-up time tASR 0 0 0 ns Row address hold time tRAH 8 10 10 ns Column address set-up time tASC 0 0 0 ns 13 Column address hold time 13 tCAH 8 10 10 ns Column address to RAS lead time tR A L 23 25 30 ns Read command set-up time tRCS 0 0 0 ns Read command hold time referenced to CAS tRCH 0 0 0 ns 8 Read command hold time referenced to RAS tRRH 0 0 0 ns 8 Write command hold time tWCH 8 10 10 ns Write command pulse width tW P 8 10 10 ns Write command to RAS lead time tRWL 13 15 15 ns Write command to CAS lead time tCWL 12 13 15 ns 16 Data set-up time tD S 0 0 0 ns 9,19 Data hold time tD H 10 10 10 ns 9,19 Industrial Temperature K4F661612D, K4F641612D AC CHARACTERISTICS CMOS DRAM (Continued) Parameter -45 Symbol Min Refresh period (Normal) -50 Max Min -60 Max Min Units Note Max t REF 64 64 64 ms Refresh period (L-ver) t REF 128 128 128 ms Write command set-up time t WCS 0 0 0 ns 7 CAS to W delay time t CWD 32 36 38 ns 7,15 RAS to W delay time t RWD 67 73 83 ns 7 Column address to W delay time t AWD 43 48 53 ns 7 CAS precharge W delay time tC P W D 48 53 60 ns CAS set-up time (CAS -before-RAS refresh) t CSR 5 5 5 ns 17 CAS hold time (CAS -before-RAS refresh) t CHR 10 10 10 ns 18 RAS to CAS precharge time t RPC 5 Access time from CAS precharge t CPA Fast Page mode cycle time 5 26 5 30 ns 35 ns t PC 31 35 40 ns Fast Page mode read-modify-write cycle time tP R W C 70 76 85 ns CAS precharge time (Fast page cycle) tC P 9 10 10 ns RAS pulse width (Fast page cycle) 3 14 t RASP 45 RAS hold time from CAS precharge t RHCP 28 OE access time t OEA OE to data delay t OED 12 Output buffer turn off delay time from OE tOEZ 0 OE command hold time t OEH 12 13 15 ns Write command set-up time (Test mode in) t WTS 10 10 10 ns 11 Write command hold time (Test mode in) t WTH 15 15 15 ns 11 W to RAS precharge time (C-B-R refresh) 200K 50 200 30 12 13 0 200 35 13 13 60 ns 15 13 13 0 ns ns 3 ns 13 ns 6 t WRP 10 10 10 ns W to RAS hold time (C-B-R refresh) t WRH 10 10 10 ns RAS pulse width (C-B-R self refresh) t RASS 100 100 100 us 20,21,22 RAS precharge time (C-B-R self refresh) t RPS 80 90 110 ns 20,21,22 CAS hold time (C-B-R self refresh) t CHS -50 -50 -50 ns 20,21,22 Industrial Temperature K4F661612D, K4F641612D CMOS DRAM TEST MODE CYCLE Parameter ( Note 11 ) -45 Symbol Min -50 Max Min -60 Max Min Units Note Max Random read or write cycle time tR C 85 95 115 ns Read-modify-write cycle time t RWC 120 138 160 ns Access time from RAS t RAC 50 55 65 ns 3,4,10,12 Access time from CAS t CAC 17 18 20 ns 3,4,5,12 Access time from column address t AA 28 30 35 ns 3,10,12 RAS pulse width tRAS 50 10K 55 10K 65 10K ns CAS pulse width tCAS 17 10K 18 10K 20 10K ns RAS hold time t RSH 17 18 20 ns CAS hold time t CSH 50 55 65 ns Column Address to RAS lead time tRAL 28 30 35 ns CAS to W delay time t CWD 37 41 43 ns 7 RAS to W delay time t RWD 72 78 88 ns 7 Column Address to W delay time t AWD 48 53 58 ns 7 Fast Page mode cycle time t PC 36 40 45 ns Fast Page mode read-modify-write cycle time t PRWC 75 81 90 ns RAS pulse width (Fast page cycle) t RASP 50 Access time from CAS precharge tCPA 31 OE access time t OEA 17 OE to data delay t OED 17 18 18 ns OE command hold time t OEH 17 18 20 ns 200K 55 200K 65 200K ns 35 40 ns 18 20 ns 3 Industrial Temperature K4F661612D, K4F641612D CMOS DRAM NOTES 1. An initial pause of 200§Á is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is achieved. 2. V IH(min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between V IH(min) and V IL (max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 1 TTL load and 100pF. 4. Operation within the t RCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If t RCD is greater than the specified t RCD (max) limit, then access time is controlled exclusively by tCAC . 5. Assumes that t R C D≥t R C D(max). 6. t OFF (min)and tOEZ (max) define the time at which the output achieves the open circuit condition and are not referenced Voh or Vol . 7. t W C S, tRWD , tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric characteristics only. If t W C S≥ tWCS (min), the cycles is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD ≥ tCWD (min), t RWD ≥t RWD (min) and tAWD ≥t AWD (min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or t RRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS leading edge in early write cycles and to the W falling edge in read-modifywrite cycles. 10. Operation within the t RAD (max) limit insures that t RAC (max) can be met. t RAD (max) is specified as a reference point only. If t RAD is greater than the specified t RAD (max) limit, then access time is controlled by t AA. 11. These specifications are applied in the test mode. 12. In test mode read cycle, the value of tRAC , t AA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. K4F64(6)1612D Truth Table RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE H X X X X Hi-Z Hi-Z Standby L H H X X Hi-Z Hi-Z Refresh L L H H L DQ-OUT Hi-Z Byte Read L H L H L Hi-Z DQ-OUT Byte Read L L L H L DQ-OUT DQ-OUT Word Read L L H L H DQ-IN - Byte Write L H L L H - DQ-IN Byte Write L L L L H DQ-IN DQ-IN Word Write L L L H H Hi-Z Hi-Z - Industrial Temperature K4F661612D, K4F641612D CMOS DRAM 13. tASC , tCAH are referenced to the earlier CAS falling edge. 14. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle. 15. tC W D is referenced to the later CAS falling edge at word read-modify-write cycle. 16. tC W L is specified from W falling edge to the earlier CAS rising edge. 17. tCSR is referenced to earlier CAS falling before RAS transition low. 18. tC H R is referenced to the later CAS rising high after RAS transition low. RAS LCAS UCAS t CSR tC H R 19. tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge. LCAS UCAS tD S DQ0 ~ DQ15 tDH Din 20. If t RASS ≥100us, then RAS precharge time must use tRPS instead of t R P. 21. For RAS -only-Refresh and Burst CAS -before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. 22. For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. Industrial Temperature K4F661612D, K4F641612D CMOS DRAM WORD READ CYCLE tR C tR A S tR P V IH RAS V IL - tC S H tCRP tRCD tCRP tR S H V IH - tCAS UCAS V IL - tC S H tCRP tR C D tC R P tR S H V IH - tC A S LCAS V IL - tR A D tASR V IH A V IL - tRAH tR A L tA S C tCAH COLUMN ADDRESS ROW ADDRESS tRCH tR C S tRRH V IH W V IL - tA A V IH OE tOEA V IL - DQ0 ~ DQ7 tR A C t CAC tC L Z tOFF tOEZ V OH - OPEN DATA-OUT V OL - tO F F t CAC DQ8 ~ DQ15 tR A C tC L Z tO E Z V OH - OPEN DATA-OUT V OL - D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM LOWER BYTE READ CYCLE N O T E : D IN = O P E N tR C tRAS t RP V IH RAS V IL - tC R P t RPC V IH UCAS V IL - t CSH tCRP tRCD tR S H V IH - tCAS LCAS V IL - tR A D tASR V IH A V IL - tRAH tASC ROW ADDRESS tR A L tC A H COLUMN ADDRESS tRCH tRCS tR R H V IH W V IL - t OFF tA A tOEZ V IH - tOEA OE V IL - t CAC tC L Z DQ0 ~ DQ7 tR A C V OH - OPEN DATA-OUT V OL - DQ8 ~ DQ15 V OH V OL - OPEN D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM UPPER BYTE READ CYCLE N O T E : D IN = O P E N tR C tR A S tR P V IH RAS V IL - tC S H tC R P tR C D tC R P tR S H V IH - tC A S UCAS V IL - tR P C tC R P V IH LCAS V IL - tR A D tRAL tA S R t RAH tA S C tCAH V IH A V IL - ROW ADDRESS COLUMN ADDRESS tRCH tRCS tRRH V IH W V IL - t OFF tAA tO E Z V IH - tO E A OE V IL - DQ0 ~ DQ7 V OH - OPEN V OL - tC A C tC L Z DQ8 ~ DQ15 tR A C V OH - OPEN DATA-OUT V OL - D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM WORD WRITE CYCLE ( EARLY WRITE ) N O T E : D OUT = O P E N tRC tR A S t RP V IH RAS V IL - t CSH tCRP tR C D tR S H V IH - tCRP tCAS UCAS V IL - tC S H tCRP tR C D tR S H V IH - tC R P tC A S LCAS V IL - tR A D tASR tRAH tR A L tA S C tCAH V IH A V IL - ROW ADDRESS COLUMN ADDRESS tWCS tWCH V IH W tW P V IL - V IH OE V IL - DQ0 ~ DQ7 tD S tDH V IH DATA-IN V IL - tD S DQ8 ~ DQ15 tDH V IH DATA-IN V IL - D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM LOWER BYTE WRITE CYCLE ( EARLY WRITE ) N O T E : D OUT = O P E N tR C t RAS t RP V IH RAS V IL - tCRP t RPC V IH UCAS V IL - tC S H tCRP tR C D tR S H V IH - tC R P tC A S LCAS V IL - t RAD tASR tRAH tR A L tASC tCAH V IH A V IL - COLUMN ADDRESS ROW ADDRESS tWCS tWCH V IH - tW P W V IL - V IH OE V IL - tD S DQ0 ~ DQ7 tDH V IH DATA-IN V IL - DQ8 ~ DQ15 V IH V IL - D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM UPPER BYTE WRITE CYCLE ( EARLY WRITE ) N O T E : D OUT = O P E N t RC tRAS tR P V IH RAS V IL - tC S H tCRP tRCD tCRP t RSH V IH - tC A S UCAS V IL - tCRP t RPC V IH LCAS V IL - tRAD t ASR tR A H t RAL t ASC t CAH V IH A V IL - ROW ADDRESS COLUMN ADDRESS tWCS tW C H V IH W tW P V IL - V IH OE V IL - DQ0 ~ DQ7 V IH V IL - tD S tD H DQ8 ~ DQ15 V IH DATA-IN V IL - D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM WORD WRITE CYCLE ( OE CONTROLLED WRITE ) N O T E : D OUT = O P E N tR C tRAS t RP V IH RAS V IL - t CSH tCRP tR C D t RSH V IH - tCRP tCAS UCAS V IL - tC S H tCRP tR C D t RSH V IH - tC R P tC A S LCAS V IL - tR A D tASR tRAH tR A L tA S C tC A H V IH A V IL - ROW ADDRESS COLUMN ADDRESS tC W L tRWL V IH - tW P W V IL - V IH OE V IL - tOEH tOED tD S DQ0 ~ DQ7 t DH V IH DATA-IN V IL - tD S DQ8 ~ DQ15 t DH V IH DATA-IN V IL - D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM LOWER BYTE WRITE CYCLE ( O E CONTROLLED WRITE ) N O T E : D OUT = O P E N tRC tR A S tR P V IH RAS V IL - tCRP t RPC V IH UCAS V IL - t CSH tCRP tRCD t RSH V IH - tCRP tCAS LCAS V IL - tRAD tA S R tR A H t RAL tA S C tC A H V IH A V IL - ROW ADDRESS COLUMN ADDRESS tCWL tRWL V IH - tWP W V IL - V IH OE V IL - DQ0 ~ DQ7 tO E H tOED tD S tD H V IH DATA-IN V IL - DQ8 ~ DQ15 V IH V IL - D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM UPPER BYTE WRITE CYCLE ( O E CONTROLLED WRITE ) N O T E : D OUT = O P E N t RC tR A S tR P V IH RAS V IL - tC S H tCRP tR C D tCRP tRSH V IH - tC A S UCAS V IL - tCRP t RPC V IH LCAS V IL - tRAD t ASR tR A H t RAL tA S C t CAH V IH A V IL - ROW ADDRESS COLUMN ADDRESS tCWL tRWL V IH W tW P V IL - V IH OE V IL - tOEH tOED DQ0 ~ DQ7 V IH V IL - DQ8 ~ DQ15 tD S tD H V IH DATA-IN V IL - D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM WORD READ - MODIFY - WRITE CYCLE tR W C tR A S tR P V IH RAS V IL - tC R P tRCD tR S H V IH - tCAS UCAS V IL - tC R P tRCD tR S H V IH - tCAS LCAS V IL - tRAD t CSH tA S R V IH A V IL - t RAH ROW ADDR tASC tC A H COLUMN ADDRESS tR W L tA W D tCWL tC W D V IH - tW P W V IL - tR W D tO E A V IH OE V IL - tCLZ tC A C tO E D tAA DQ0 ~ DQ7 t DS t DH tO E Z t RAC V I/OH - VALID DATA-OUT V I/OL - VALID DATA-IN t CLZ tC A C tAA DQ8 ~ DQ15 V I/OH V I/OL - tO E D tD S t DH tO E Z t RAC VALID DATA-OUT VALID DATA-IN D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM LOWER-BYTE READ - MODIFY - WRITE CYCLE tR W C tR A S tR P V IH RAS V IL - t RPC tCRP V IH UCAS V IL - tC R P tRCD tR S H V IH - t CAS LCAS V IL - tR A D t CSH tA S R V IH A V IL - ROW ADDR t RAH tASC t CAH COLUMN ADDRESS tRWL tAWD tCWD tC W L V IH - tW P W V IL - tR W D tO E A V IH OE V IL - tCLZ tC A C tAA DQ0 ~ DQ7 V I/OH V I/OL - tO E D tD S tDH tO E Z t RAC VALID DATA-OUT VALID DATA-IN DQ8 ~ DQ15 V I/OH - OPEN V I/OL - D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM UPPER-BYTE READ - MODIFY - WRITE CYCLE tR W C tR P tRAS V IH RAS V IL - tCRP tRCD tR S H V IH - tC A S UCAS V IL - tCRP tR P C V IH LCAS V IL - t RAD tC S H tASR V IH A V IL - tRAH ROW ADDR tASC tCAH COLUMN ADDRESS tR W L tA W D tC W L tCWD V IH - tW P W V IL - tR W D tO E A V IH OE V IL - DQ0 ~ DQ7 V I/OH - OPEN V I/OL - t CLZ t CAC tAA DQ8 ~ DQ15 V I/OH V I/OL - tOED t DS tR A C tDH tOEZ VALID DATA-OUT VALID DATA-IN D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM FAST PAGE MODE WORD READ CYCLE tR P tRASP V IH RAS V IL - ¡ó tR H C P tC S H tP C tC R P tP C t PC tC P tRCD tC P tC A S V IH - tCAS tC P t RPC tC A S tC A S UCAS V IL - t RAL tC R P tC P tRCD t CP tC A S V IH - t CAS tC P tR P C tC A S tC A S LCAS V IL - tA S R t RAD t RAH tASC t CAH t ASC tC A H tASC tC A H tASC tC A H V IH - ROW COLUMN COLUMN COLUMN COLUMN V IL - ADDR ADDRESS ADDRESS ADDR ADDRESS A tRCS tRCS tRCH tR C S tR C H tRCS tR R H tRCH tRCH V IH W V IL - t CAC tA A tAA tCPA tOEA V IH - t CAC tC A C t AA tCPA tO E A tAA t CPA tOEA tO E A OE V IL - tCAC DQ0 ~ DQ7 tOFF tR A C tOFF tOEZ tO F F tOEZ tO F F tO E Z tO E Z V OH VALID V OL - VALID DATA-OUT DATA-OUT VALID DATA-OUT VALID DATA-OUT tCLZ tC A C DQ8 ~ DQ15 tOFF tR A C tOFF tOEZ tO F F tOEZ tO F F tO E Z tO E Z V OH VALID DATA-OUT VOL - VALID DATA-OUT VALID DATA-OUT VALID DATA-OUT t CLZ D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM FAST PAGE MODE LOWER BYTE READ CYCLE tR A S P tR P V IH RAS V IL - ¡ó tR H C P tCRP t RPC V IH UCAS V IL - t RAL t CSH t PC tC R P t PC t PC tC P tR C D tC P tC A S V IH - tC A S tC P tRPC tC A S tC A S LCAS V IL - tR A D tASR V IH A V IL - t RAH tASC t CAH tASC t CAH tA S C tC A H tA S C tC A H ROW COLUMN COLUMN COLUMN COLUMN ADDR ADDRESS ADDRESS ADDR ADDRESS tR C S tR C S tRCH tRCS tRCH tRCS tRRH tRCH tR C H V IH W V IL - tC A C t AA tAA V IH - tCAC tA A tC P A tO E A tC A C tC P A tOEA tA A tC P A tO E A tO E A OE V IL - t CAC DQ0 ~ DQ7 t RAC VOH - VALID DATA-OUT VOL - tO F F tO F F t OFF tO E Z tO E Z tOEZ VALID DATA-OUT VALID DATA-OUT t OFF tOEZ VALID DATA-OUT tC L Z DQ8 ~ DQ15 V OH - OPEN V OL - D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM FAST PAGE MODE UPPER BYTE READ CYCLE tR P tR A S P V IH RAS V IL - ¡ó t CSH tR H C P t PC tCRP t PC t PC tC P tR C D tC P tC A S V IH - tC A S tC P t RPC tC A S tC A S UCAS V IL - tC R P t RPC V IH LCAS t RAL V IL - tRAD tASR V IH A V IL - tR A H tASC tC A H tASC t CAH tASC tCAH tASC tC A H ROW COLUMN COLUMN COLUMN COLUMN ADDR ADDRESS ADDRESS ADDR ADDRESS tRCS tRCS tR C H tRCS tR C H tRCS tRRH tR C H tR C H V IH W V IL - tC A C tAA tAA tC P A tO E A V IH - tC A C tCAC tA A tCPA tOEA tA A tC P A tO E A tO E A OE V IL - DQ0 ~ DQ7 V OH - OPEN V OL - tC A C DQ8 ~ DQ15 t RAC V OH - VALID DATA-OUT VOL - tO F F tO F F t OFF tO F F tO E Z tO E Z tOEZ tO E Z VALID DATA-OUT VALID DATA-OUT VALID DATA-OUT tCLZ D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM FAST PAGE MODE WORD WRITE CYCLE ( EARLY WRITE ) N O T E : D OUT = O P E N tRASP tR P V IH - tRHCP RAS V IL - ¡ó tP C tC R P tRCD t PC tC P V IH - tCAS UCAS t RSH t CP tC R P tC A S V IL - tCAS ¡ó tP C tCRP V IH - tC P tCAS LCAS tRSH t PC tC P tRCD tC A S V IL - tC A S ¡ó t RAD t RAL tCSH tA S R V IH A V IL - tR A H tASC t CAH tASC t CAH tA S C t CAH ¡ó ROW COLUMN COLUMN COLUMN ADDR ADDRESS ADDRESS ADDRESS ¡ó tW C S tWCH tWCS tW P V IH - tWCH tW P tWCS ¡ó tWCH tWP W V IL - ¡ó V IH OE V IL - DQ0 ~ DQ7 ¡ó tD S t DH tD S tD H tD S tD H ¡ó V IH - VALID DATA-IN V IL - VALID DATA-IN VALID DATA-IN ¡ó tD S t DH tD S tD H tD S tD H DQ8 ~ DQ15 V IH V IL - ¡ó VALID DATA-IN VALID VALID DATA-IN DATA-IN ¡ó D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM FAST PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE ) N O T E : D OUT = O P E N tRASP t RP V IH - tR H C P RAS V IL - ¡ó t RPC tC R P ¡ó V IH UCAS V IL - t PC tC R P tRCD t PC t CP V IH - tC A S LCAS t RSH tC P tC A S V IL - tCAS ¡ó t RAD tR A L tC S H tASR V IH A V IL - tR A H tASC tC A H tA S C tCAH tA S C t CAH ¡ó ROW COLUMN COLUMN COLUMN ADDR ADDRESS ADDRESS ADDRESS ¡ó tWCS tWCH tWCS tWP V IH - tW C H tW C S ¡ó tW P tW C H tW P W V IL - ¡ó V IH OE V IL - DQ0 ~ DQ7 V IH V IL - ¡ó t DS tD H t DS t DH t DS tDH ¡ó VALID DATA-IN VALID DATA-IN VALID DATA-IN ¡ó DQ8 ~ DQ15 V IH V IL - D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM FAST PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE ) N O T E : D OUT = O P E N t RASP t RP V IH - tRHCP RAS V IL - ¡ó tP C tCRP tR C D tP C t CP V IH - tC A S UCAS t RSH t CP tCAS V IL - t CAS ¡ó tR P C tC R P V IH LCAS V IL - tR A D t RAL tC S H tA S R V IH A V IL - t RAH tASC t CAH tASC tCAH tA S C tCAH ¡ó ROW COLUMN COLUMN COLUMN ADDR. ADDRESS ADDRESS ADDRESS ¡ó tWCS tWCH tWCS tW P V IH - tW C H tW P tWCS ¡ó tW C H tW P W V IL - ¡ó V IH OE V IL - ¡ó DQ0 ~ DQ7 ¡ó V IH V IL - DQ8 ~ DQ15 V IH V IL - ¡ó tD S t DH t DS tDH t DS tD H ¡ó VALID DATA-IN VALID DATA-IN VALID DATA-IN ¡ó D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM FAST PAGE MODE WORD READ-MODIFY-WRITE CYCLE tR P tR A S P V IH - tC S H RAS V IL - tP R W C tC R P tR S H tR C D tCRP tC P V IH - tCAS UCAS tC A S V IL - tC R P tR C D tCRP tC P V IH - tC A S tC A S LCAS V IL - t RAD t RAH t RAL t CAH tASR t CAH tA S C tASC V IH - ROW COL. COL. V IL - ADDR ADDR ADDR A tR W L tC W L tRCS tC W L tRCS V IH - tWP tW P W V IL - tCWD tAWD tRWD V IH - tCWD tAWD tCPWD tOEA tO E A OE V IL - t OED tCAC tC A C tAA DQ0 ~ DQ7 tD S t RAC t DH tAA tDH tO E Z tOED tD S tOEZ V I/OH V I/OL - tC L Z t CLZ VALID DATA-OUT VALID DATA-IN tOED VALID DATA-OUT t CAC VALID DATA-IN tOED tC A C tA A DQ8 ~ DQ15 tR A C tOEZ tD H tDH tA A tD S t DS tO E Z V I/OH V I/OL - tCLZ t CLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM FAST PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE tR P tRASP t CSH V IH RAS V IL - tCRP tR P C V IH UCAS V IL - tPRWC tCRP t RSH tRCD tC R P t CP V IH - tC A S LCAS tC A S V IL - tR A D tR A H tASR V IH A V IL - tR A L tC A H t ASC t CAH tASC ROW COL. COL. ADDR ADDR ADDR tR W L tRCS tCWL tC W L tRCS V IH - tW P tW P W V IL - tCWD tAWD tRWD V IH - tC W D tA W D tC P W D tO E A tOEA OE V IL - tO E D tC A C tC A C tAA DQ0 ~ DQ7 tD H tOEZ tDH tA A tD S tRAC tOED t DS tOEZ V I/OH V I/OL - tCLZ t CLZ VALID VALID VALID VALID DATA-OUT DATA-IN DATA-OUT DATA-IN DQ8 ~ DQ15 V I/OH - OPEN V I/OL - D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM FAST PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE t RP tR A S P tC S H V IH RAS V IL - tC R P tP R W C tRSH tR C D tCRP tC P V IH - t CAS UCAS t CAS V IL - tRPC tC R P V IH LCAS V IL - t RAD t RAH t RAL tC A H tASR tASC V IH A V IL - t CAH tASC ROW COL. COL. ADDR ADDR ADDR tR W L tRCS tCWL tC W L tRCS tWP V IH - tWP W V IL - tCWD tAWD tRWD V IH - tCWD tAWD tCPWD tO E A tO E A OE V IL - DQ0 ~ DQ7 V I/OH - OPEN V I/OL - tOED tOED tCAC tA A DQ8 ~ DQ15 t CAC t DH tOEZ tA A tD S tD H tO E Z tD S t RAC V I/OH V I/OL - t CLZ t CLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM RAS - ONLY REFRESH CYCLE N O T E : W , O E , D I N = D o n ′t c a r e D OUT = O P E N t RC V IH - tR P tRAS RAS V IL - t RPC tCRP V IH UCAS V IL - tCRP V IH LCAS V IL - tA S R tRAH V IH - ROW V IL - ADDR A CAS - BEFORE - RAS REFRESH CYCLE N O T E : O E , A = D o n ′t c a r e tR C tR P tR P tRAS V IH RAS V IL - tC R P tR P C tC P t CSR V IH - tC H R UCAS V IL - tC P t CSR V IH - tC H R LCAS V IL - DQ0 ~ DQ7 t OFF V OH - OPEN V OL DQ8 ~ DQ15 V OH - OPEN V OL - tW R P tWRH V IH W V IL - D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM HIDDEN REFRESH CYCLE ( READ ) t RC t RC tR P t RP tRAS V IH - tRAS RAS V IL - tC R P tRCD t RSH tCHR tRCD t RSH tC H R V IH UCAS V IL - tCRP V IH LCAS V IL - tR A D tR A L t ASR V IH A V IL - tRAH tA S C tC A H ROW ADDRESS COLUMN ADDRESS tW R H tR C S V IH W V IL - tA A V IH - tO E A OE V IL - tO F F t CAC tC L Z DQ0 ~ DQ7 tR A C tOEZ V OH - OPEN DATA-OUT OPEN D A T AD - IA NT A - O U T V OL - DQ8 ~ DQ15 V OH V OL - D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM HIDDEN REFRESH CYCLE ( WRITE ) N O T E : D OUT = O P E N t RC tRC tR P tR P tRAS tRAS V IH RAS V IL - tC R P tR C D t RSH tCHR tR C D tR S H tCHR V IH UCAS V IL - tC R P V IH LCAS V IL - tR A D tR A L tASR V IH A V IL - t RAH t ASC ROW ADDRESS tC A H COLUMN ADDRESS tW R H tW R P tWCS tWCH V IH W tW P V IL - V IH OE V IL - t DS t DH DQ0 ~ DQ7 V IH DATA-IN V IL - tD S tD H DQ8 ~ DQ15 V IH DATA-IN V IL - D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM CAS - BEFORE - RAS SELF REFRESH CYCLE N O T E : O E , A = D o n ′t c a r e tR P tRASS tR P S V IH RAS V IL - t RPC tR P C tC P V IH - t CSR tC H S t CSR tC H S UCAS V IL - tC P V IH LCAS V IL - DQ0 ~ DQ7 tO F F VOH - OPEN VOL DQ8 ~ DQ15 V OH - OPEN VOL - tW R P tWRH V IH W V IL - TEST MODE IN CYCLE N O T E : O E , A = D o n ′t c a r e tRC tR P tR P tRAS V IH RAS V IL - tCRP t RPC tC P tC S R V IH - tCHR UCAS V IL - tC P tC S R V IH - tCHR LCAS V IL - tW T S V IH W tWTH V IL DQ0 ~ DQ15 t OFF V OH - OPEN VOL D o n ′t c a r e Undefined Industrial Temperature K4F661612D, K4F641612D CMOS DRAM PACKAGE DIMENSION 50 TSOP(II) 400mil 0 .4 0 0 (1 0 . 1 6) 0 . 47 1 (1 1 .9 6 ) 0 . 45 5 (1 1 .5 6 ) Units : Inches (millimeters) 0.004 (0.10) 0.010 (0.25) 0.841 (21.35) MAX 0.821 (20.85) 0.829 (21.05) 0.047 (1.20) MAX 0.010 (0.25) TYP 0~8 0.034 (0.875) 0.0315 (0.80) 0.002 (0.05) MIN 0.010 (0.25) 0.018 (0.45) 0.018 (0.45) 0.030 (0.75) O