SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR SCLS401B – APRIL 1998 – REVISED JULY 1998 D D D D D EPIC (Enhanced-Performance Implanted CMOS) Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC, TA = 25°C Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J) SN54LV174A . . . J OR W PACKAGE SN74LV174A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) CLR 1Q 1D 2D 2Q 3D 3Q GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 6Q 6D 5D 5Q 4D 4Q CLK SN54LV174A . . . FK PACKAGE (TOP VIEW) 1Q CLR NC VCC 6Q D 3 1D 2D NC 2Q 3D description The ’LV174A devices are hex D-type flip-flops designed for 2-V to 5.5-V VCC operation. 4 2 1 20 19 18 5 17 6 16 7 15 8 14 6D 5D NC 5Q 4D 3Q GND NC CLK 4Q These devices are monolithic positive-edge9 10 11 12 13 triggered flip-flops with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the NC – No internal connection outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of the clock pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. The SN54LV174A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LV174A is characterized for operation from –40°C to 85°C. FUNCTION TABLE INPUTS CLR CLK D OUTPUT Q L X X L H ↑ H H H ↑ L L H L X Q0 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR SCLS401B – APRIL 1998 – REVISED JULY 1998 logic symbol† CLR CLK 1D 2D 3D 4D 5D 6D 1 9 3 R C1 2 1D 4 5 6 7 11 10 13 12 14 15 1Q 2Q 3Q 4Q 5Q 6Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. logic diagram (positive logic) 1 CLR CLK 1D 9 3 1D C1 2 1Q R To Five Other Channels Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR SCLS401B – APRIL 1998 – REVISED JULY 1998 recommended operating conditions (see Note 4) SN54LV174A VCC VIH MIN MAX 2 5.5 Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V High level input voltage High-level VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 0.5 VI VO Input voltage 0 Output voltage 0 ∆t/∆v Input transition rise or fall rate 0 VCC –50 V VCC × 0.3 5.5 0 VCC –50 –2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V V VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 VCC = 2 V VCC = 2.3 V to 2.7 V UNIT 0.5 VCC × 0.3 VCC × 0.3 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Low level output current Low-level 5.5 VCC × 0.7 VCC × 0.7 Low level input voltage Low-level IOL 2 1.5 VCC = 2 V VCC = 2.3 V to 2.7 V High level output current High-level MAX 1.5 VIL IOH SN74LV174A MIN V V V µA –2 –6 –6 –12 –12 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 6 6 12 12 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 200 0 200 0 100 0 100 VCC = 4.5 V to 5.5 V 0 20 0 20 mA µA mA ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS IOH = –50 µA IOH = –2 mA 2 V to 5.5 V IOL = 50 µA IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = VCC or GND VI = VCC or GND, Ioff Ci VI or VO = 0 to 5.5 V VI = VCC or GND IO = 0 MIN TYP SN74LV174A MAX MIN VCC–0.1 2 VCC–0.1 2 3V 2.48 2.48 4.5 V 3.8 3.8 2.3 V IOH = –6 mA IOH = –12 mA II ICC SN54LV174A VCC TYP MAX UNIT V 2 V to 5.5 V 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V 0.55 0.55 5.5 V ±1 ±1 µA 5.5 V 20 20 µA 0V 5 5 µA 3.3 V 1.7 1.7 V pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR SCLS401B – APRIL 1998 – REVISED JULY 1998 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) MIN tw Pulse duration tsu Set p time before CLK↑ Setup th Hold time, data after CLK↑ TA = 25°C TYP MAX SN54LV174A MIN MAX SN74LV174A MIN CLR low 6 6.5 6.5 CLK high or low 7 7 7 8.5 9.5 9.5 4 4 4 –0.5 0 0 Data CLR inactive MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) MIN tw Pulse duration tsu Set p time before CLK↑ Setup th Hold time, data after CLK↑ TA = 25°C TYP MAX SN54LV174A MIN MAX SN74LV174A MIN CLR low 5 5 5 CLK high or low 5 5 5 Data 5 6 6 CLR inactive 3 3 3 0 0 0 MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) MIN tw Pulse duration tsu Set p time before CLK↑ Setup th Hold time, data after CLK↑ TA = 25°C TYP MAX SN54LV174A MIN MAX SN74LV174A MIN CLR low 5 5 5 CLK high or low 5 5 5 Data 4.5 4.5 4.5 CLR inactive 2.5 2.5 2.5 0.5 0.5 0.5 MAX UNIT ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd* tpd LOAD CAPACITANCE CLK MIN MAX SN74LV174A MIN 55 115 50 50 45 90 40 40 CL = 15 pF Q CL = 50 pF 1 19.5 1 19.5 8.4 17.1 1 19 1 19 8.2 21.9 1 23.5 1 23.5 10.8 20.6 1 23 1 23 2 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. • DALLAS, TEXAS 75265 UNIT MHz 17.3 * On products compliant to MIL-PRF-38535, this parameter is not production tested. † Skew between any two outputs of the same package switching in the same direction POST OFFICE BOX 655303 MAX 6.3 tsk(o)† 4 SN54LV174A CL = 50 pF CLR CLK TA = 25°C TYP MAX CL = 15 pF* CLR Q MIN 2 ns ns SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR SCLS401B – APRIL 1998 – REVISED JULY 1998 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax LOAD CAPACITANCE MIN Q CLK MAX SN74LV174A MIN 170 80 80 CL = 50 pF 55 130 50 50 CL = 15 pF Q CLK MIN 95 CL = 50 pF MAX 11.4 1 13.5 1 13.5 5.8 11 1 13 1 13 6 14.9 1 17 1 17 7.5 14.5 1 16.5 1 16.5 tsk(o)† UNIT MHz 4.5 CLR tpd SN54LV174A CL = 15 pF* CLR tpd* TA = 25°C TYP MAX 1.5 ns ns 1.5 * On products compliant to MIL-PRF-38535, this parameter is not production tested. † Skew between any two outputs of the same package switching in the same direction switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax TA = 25°C TYP MAX Q CLK CL = 15 pF* 130 240 110 110 CL = 50 pF 90 180 80 80 CL = 15 pF CLR tpd Q CLK SN74LV174A MIN CLR tpd* SN54LV174A LOAD CAPACITANCE CL = 50 pF MIN MAX MIN MAX MHz 3 7.6 1 9 1 9 4.1 7.2 1 8.5 1 8.5 4.2 9.6 1 11 1 11 5.5 9.2 1 10.5 1 10.5 tsk(o)† UNIT 1 ns ns 1 * On products compliant to MIL-PRF-38535, this parameter is not production tested. † Skew between any two outputs of the same package switching in the same direction noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) SN74LV174A PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.34 0.8 V Quiet output, minimum dynamic VOL –0.3 –0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 3.02 High-level dynamic input voltage V 2.31 V VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only. 0.99 V VCC 3.3 V TYP UNIT 5V 15.1 operating characteristics, TA = 25°C PARAMETER Cpd Power dissi dissipation ation ca capacitance acitance TEST CONDITIONS CL = 50 pF F, f = 10 MHz 14 pF F PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR SCLS401B – APRIL 1998 – REVISED JULY 1998 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH In-Phase Output 50% VCC VOH 50% VCC VOL 50% VCC Output Waveform 2 S1 at GND (see Note B) 50% VCC 0V Output Waveform 1 S1 at VCC (see Note B) tPLH VOH 50% VCC VOL 50% VCC tPZL tPHL tPHL Out-of-Phase Output 0V VCC Output Control tPLZ 50% VCC tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS ≈ VCC VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. Figure 1. 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