TI CD74HCT164M96E4

[ /Title
(CD74
HC164
,
CD74
HCT16
4)
/Subject
(High
Speed
CMOS
Logic
8-Bit
SerialIn/Parallel-
CD54HC164, CD74HC164,
CD54HCT164, CD74HCT164
Data sheet acquired from Harris Semiconductor
SCHS155C
High-Speed CMOS Logic
8-Bit Serial-In/Parallel-Out Shift Register
October 1997 - Revised August 2003
Features
Description
• Buffered Inputs
The ’HC164 and ’HCT164 are 8-bit serial-in parallel-out shift
registers with asynchronous reset. Data is shifted on the
positive edge of Clock (CP). A LOW on the Master Reset
(MR) pin resets the shift register and all outputs go to the
LOW state regardless of the input conditions. Two Serial
Data inputs (DS1 and DS2) are provided, either one can be
used as a Data Enable control.
• Asynchronous Master Reset
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,
TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Ordering Information
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
PART NUMBER
• Significant Power Reduction Compared to LSTTL
Logic ICs
TEMP. RANGE
(oC)
PACKAGE
CD54HC164F3A
-55 to 125
14 Ld CERDIP
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
CD54HCT164F3A
-55 to 125
14 Ld CERDIP
CD74HC164E
-55 to 125
14 Ld PDIP
CD74HC164M
-55 to 125
14 Ld SOIC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
CD74HC164MT
-55 to 125
14 Ld SOIC
CD74HC164M96
-55 to 125
14 Ld SOIC
CD74HCT164E
-55 to 125
14 Ld PDIP
CD74HCT164M
-55 to 125
14 Ld SOIC
CD74HCT164MT
-55 to 125
14 Ld SOIC
CD74HCT164M96
-55 to 125
14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
Pinout
CD54HC164, CD54HCT164
(CERDIP)
CD74HC164, CD74HCT164
(PDIP, SOIC)
TOP VIEW
DS1 1
14 VCC
DS2 2
13 Q7
Q0 3
12 Q6
Q1 4
11 Q5
Q2 5
10 Q4
Q3 6
9 MR
GND 7
8 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
1
CD54HC164, CD74HC164, CD54HCT164, CD74HCT164
Functional Diagram
3
1
DS1
Q0
4
2
Q1
5
DS2
Q2
6
Q3
10
Q4
11
Q5
12
Q6
13
9
Q7
8
MR
GND = 7
VCC = 14
CP
TRUTH TABLE
INPUTS
OUTPUTS
OPERATING MODE
MR
CP
DS1
DS2
Q0
Q1 - Q7
RESET (CLEAR)
L
X
X
X
L
L-L
Shift
H
↑
l
l
L
q0 - q6
H
↑
l
h
L
q0 - q6
H
↑
h
l
L
q0 - q6
H
↑
h
h
H
q0 - q6
H= High Voltage Level.
h= High Voltage Level One Set-up Time Prior To The Low-to-high Clock Transition.
l= Low Voltage Level One Set-up Time Prior To The Low-to-high Clock Transition.
L= Low Voltage Level.
X= Don’t Care.
↑= Transition from Low to High Level.
qn= Lower Case Letters Indicate The State Of the Reference Input Clock Transition.
2
CD54HC164, CD74HC164, CD54HCT164, CD74HCT164
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
80
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
86
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
High Level Input
Voltage
VIH
-
Low Level Input
Voltage
VIL
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
HC TYPES
High Level Output
Voltage
CMOS Loads
VOH
-
VIH or
VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
-
-
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
3
CD54HC164, CD74HC164, CD54HCT164, CD74HCT164
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
SYMBOL
VI (V)
High Level Input
Voltage
VIH
-
-
Low Level Input
Voltage
VIL
-
High Level Output
Voltage
CMOS Loads
VOH
VIH or
VIL
PARAMETER
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
4.5 to
5.5
2
-
-
2
-
2
-
V
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
II
VCC to
GND
0
5.5
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
-
8
-
80
-
160
µA
∆ICC
(Note 2)
VCC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
Date Shift-In (1, 2)
0.3
MR
0.9
Clock
0.7
NOTE: Unit Load is ∆ICC limit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.
Prerequisite For Switching Function
25oC
PARAMETER
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
fMAX
2
6
-
5
-
4
-
MHz
4.5
30
-
24
-
20
-
MHz
6
35
-
28
-
24
-
MHz
2
60
-
75
-
90
-
ns
4.5
12
-
15
-
18
-
ns
6
10
-
13
-
15
-
ns
HC TYPES
Maximum Clock Frequency
MR Pulse Width
tw
4
CD54HC164, CD74HC164, CD54HCT164, CD74HCT164
Prerequisite For Switching Function
(Continued)
25oC
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
tW
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
2
60
-
75
-
90
-
ns
4.5
12
-
15
-
18
-
ns
6
10
-
13
-
15
-
ns
2
4
-
4
-
4
-
ns
4.5
4
-
4
-
4
-
ns
6
4
-
4
-
4
-
ns
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
fMAX
4.5
27
-
22
-
18
-
MHz
tw
6
18
-
23
-
27
-
ns
CP Pulse Width
tw
4.5
18
-
23
-
27
-
ns
Set-up Time
tSU
6
12
-
15
-
18
-
ns
Hold Time
tH
4.5
4
-
4
-
4
-
ns
tREM
6
16
-
20
-
24
-
ns
PARAMETER
CP Pulse Width
Set-up Time
tSU
Hold Time
tH
MR to Clock,
Removal Time
tREM
HCT TYPES
Maximum Clock Frequency
MR Pulse Width
MR to Clock,
Removal Time
Switching Specifications
PARAMETER
Input tr, tf = 6ns
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
25oC
-40oC TO 85oC -55oC TO 125oC
VCC (V)
TYP
MAX
MAX
MAX
UNITS
2
-
170
212
255
ns
4.5
-
34
43
51
ns
CL = 15pF
5
14
-
-
-
ns
CL = 50pF
6
-
29
36
43
ns
CL = 50pF
2
-
140
175
210
ns
4.5
-
28
35
42
ns
CL = 15pF
5
11
-
-
-
ns
CL = 50pF
6
-
24
30
36
ns
CL = 50pF
2
-
75
-
110
ns
4.5
-
15
-
22
ns
6
-
13
-
19
ns
HC TYPES
Propagation Delay,
CP to Qn
MR to Qn
Output Transition Times
Maximum Clock Frequency
Input Capacitance
tPLH, tPHL
tTLH, tTHL
fMAX
CL = 15pF
5
60
-
-
-
MHz
CIN
-
-
-
10
10
10
pF
5
CD54HC164, CD74HC164, CD54HCT164, CD74HCT164
Switching Specifications
PARAMETER
Input tr, tf = 6ns (Continued)
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
TEST
CONDITIONS
VCC (V)
TYP
MAX
MAX
MAX
UNITS
CPD
-
5
47
-
-
-
pF
CL = 50pF
4.5
-
36
45
54
ns
CL = 15pF
5
15
-
-
-
ns
CL = 50pF
4.5
-
38
46
57
ns
CL = 15pF
5
16
-
-
-
ns
CL = 50pF
4.5
-
15
19
22
ns
Power Dissipation
Capacitance
(Notes 3, 4)
HCT TYPES
Propagation Delay,
CP to Qn
tPLH, tPHL
MR to Qn
tPLH, tPHL
Output Transition Times
tTLH, tTHL
Input Capacitance
CIN
-
-
-
-
-
-
pF
Maximum Clock Frequency
fMAX
CL = 15pF
-
54
-
-
-
MHz
Power Dissipation
Capacitance
(Notes 3, 4)
CPD
-
5
49
10
10
10
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per device.
4. PD = VCC2 fi + ∑ (CL VCC2 + fO) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply
Voltage.
Test Circuits and Waveforms
CLOCK
INPUT
trCL
tfCL
trCL
VCC
90%
GND
tH(H)
GND
tH(H)
VCC
DATA
INPUT
50%
tH(L)
3V
1.3V
1.3V
1.3V
GND
tSU(H)
tSU(H)
tSU(L)
tTLH
90%
OUTPUT
tTHL
90%
50%
10%
tTLH
90%
1.3V
OUTPUT
tREM
3V
SET, RESET
OR PRESET
GND
tTHL
1.3V
10%
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
tPHL
1.3V
GND
IC
CL
50pF
GND
90%
tPLH
50%
IC
tSU(L)
tPHL
tPLH
tREM
VCC
SET, RESET
OR PRESET
1.3V
0.3V
tH(L)
DATA
INPUT
3V
2.7V
CLOCK
INPUT
50%
10%
tfCL
CL
50pF
FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
6
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
5962-8970401CA
ACTIVE
CDIP
J
14
1
TBD
A42 SNPB
N / A for Pkg Type
CD54HC164F
ACTIVE
CDIP
J
14
1
TBD
A42 SNPB
N / A for Pkg Type
Lead/Ball Finish
MSL Peak Temp (3)
CD54HC164F3A
ACTIVE
CDIP
J
14
1
TBD
A42 SNPB
N / A for Pkg Type
CD54HCT164F3A
ACTIVE
CDIP
J
14
1
TBD
A42 SNPB
N / A for Pkg Type
CD74HC164E
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HC164EE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HC164M
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC164M96
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC164M96E4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC164M96G4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC164ME4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC164MG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC164MT
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC164MTE4
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC164MTG4
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT164E
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HCT164EE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HCT164M
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT164M96
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT164M96E4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT164M96G4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT164ME4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT164MG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT164MT
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT164MTE4
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT164MTG4
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2007
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
30-Apr-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CD74HC164M96
D
14
MLA
330
16
6.5
9.0
2.1
8
16
Q1
CD74HCT164M96
D
14
MLA
330
16
6.5
9.0
2.1
8
16
Q1
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
CD74HC164M96
D
14
MLA
333.2
333.2
28.58
CD74HCT164M96
D
14
MLA
333.2
333.2
28.58
Pack Materials-Page 2
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amplifier.ti.com
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logic.ti.com
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