CHERRY CS3706

CS3706
CS3706
Dual Output Driver
Description
Features
The CS3706 integrated circuit provides an interface between lowlevel TTL inputs and high-power
switching devices such as power
MOSFETs. A typical application is
single-ended PWM control to pushpull power control conversion.
source or sink up to 1.5A. An internal flip-flop, driven by doublepulse suppression logic, can be
enabled to provide single-ended to
push-pull conversion. With the flipflop disabled, the outputs work in
parallel for 3.0A capability.
The primary function of this device
is to convert a bipolar single-ended
low current digital input to a pair of
totem pole outputs which can
Protection functions are also included for pulse-by-pulse current limiting, automatic deadband control
and thermal shutdown.
Block Diagram
+5V
Toggle Q
Flip
T Flop Q
F/F Enable
INHIBIT A
-A
16 Lead PDIP
+5V
+5V
V OUTA
A
Ou tp ut
L o g ic
Inh
Am p
+B
+5V
Inh
Am p
-
INHIBIT B
INV
+5V
+5V
+5V
B
Ou tp ut
L o g ic
Digital
Input
Logic
NONINV
(Internally Fused Leads)
INHIBIT B
1
16
INHIBIT A
INV
2
15
INHIBIT REF
NONINV
3
14
VIN
Gnd
4
13
Gnd
Gnd
5
12
Gnd
6
11
VOUTB
F/F ENABLE
7
10
STOP +
VCC
8
9
STOP -
VOUT
+5V
V IN
Package Options
V CC
+
INHIBIT REF
■ Dual 1.5A Totem Pole
Outputs
■ 40nsec Rise and Fall into
1000pF
■ Parallel or Push-Pull
Operation
■ Single-Ended to Push-Pull
Conversion
■ High-Speed Power
MOSFET Compatible
■ Low Cross-Conduction
Current Spike
■ Analog Latched
Shutdown
■ Internal Deadband Inhibit
Circuit
■ Low Quiescent Current
■ 5V to 40V Operation
■ Thermal Shutdown
Protection
A
V OUT B
Logic
Thermal
Voltage
Regulator Shutdown
+5V
130mV
STOP +
+V IN
S to p
Amp
R
S
Note: All Four Ground
Pins must be Connected
to Common Ground.
Analog
Stop
Latch
Gnd
STOP -
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
Rev. 4/29/99
1
A
¨
Company
CS3706
Absolute Maximum Ratings
Logic Supply Voltage (VIN) ...................................................................................................................................................40.0V
Output Supply Voltage (VCC) ...............................................................................................................................................40.0V
Output Current (each output, source, or sink)
Steady State ...............................................................................................................................................................±500mA
Peak Transient for Less Than 100µs ...........................................................................................................................±1.5A
Capacitive Discharge Energy ......................................................................................................................................20.0µJ
Digital Inputs (INV, NONINV) ..............................................................................................................................................5.5V
Analog Inputs (STOP +, STOP -) ............................................................................................................................................VIN
Inhibit Inputs (INHIBIT A, INHIBIT B, INHIBIT REF)......................................................................................................5.5V
Operating Temperature Range .......................................................................................................................................0 to 70ûC
Storage Temperature Range.......................................................................................................................................-65 to 150ûC
Lead Temperature Soldering
Wave Solder (through hole styles only).....................................................................................10 sec. max, 260¡C peak
Notes: All voltages are with respect to the four ground pins which must be connected together. All currents are positive into, negative out of the specified terminal.
Electrical Characteristics: These specifications apply over the operating temperature range of the IC.
(VIN = VCC = 20V, Pins 4, 5, 12 &13 = 0V; unless otherwise stated.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN Supply Current
VIN = 40V, VCC = 20V, INV = 0V,
Unused pins = open.
8
12
mA
VCC Supply Current
VIN = 20V, VCC = 40V, Outputs low
3
5
mA
VCC Leakage Current
VIN = 0V, VCC = 40V
0.05
Digital Input Low Level
Digital Input High Level
0.10
mA
0.8
V
2.2
V
Digital Input Current
VI = 0V
-0.6
-1.0
mA
Digital Input Leakage
VI = 5V
0.05
0.10
mA
Output High Sat., VC-VOUT
IOUT = -50mA
2.0
V
Output High Sat., VC-VOUT
IOUT = -500mA
2.5
V
Output Low Sat., VOUT
IOUT = 50mA
0.4
V
Output Low Sat., VOUT
IOUT = 500mA
Inhibit Threshold
VREF = 0.5V
0.4
Inhibit Threshold
VREF = 3.5V
3.3
Inhibit Input Current
VREF = 0V
Analog Threshold
VCM = 0V to 15 V
100
2.5
V
0.6
V
3.7
V
-10
-20
µA
130
150
mV
-20
µA
Analog Input Bias Current
VI = 0V, VCM = 15V
-10
Thermal Shutdown
Turn on
155
ûC
Thermal Shutdown
Turn off
125
ûC
2
PARAMETER
TEST CONDITIONS
OUTPUT CL =
UNIT
From Inv. Input to Output:
Rise Time Delay
10% to 90% Rise
Fall Time Delay
90% to 10% Fall
open
110
20
80
25
1.0
130
40
90
30
2.2
140
60
110
50
nF
ns
ns
ns
ns
From N.I. Input to Output:
Rise Time Delay
10% to 90% Rise
Fall Time Delay
90% to 10% Fall
120
20
100
25
130
40
120
30
140
60
130
50
ns
ns
ns
ns
VC Cross-Conduction
Current Spike Duration
Output Rise
Output Fall
25
0
ns
ns
Inhibit Delay
Inhibit Ref. = 1V
Inhibit = 0.5 to 1.5V
250
ns
Analog Shutdown Delay
Stop (+) Ref. = 0
Stop (-) Input = 0 to 0.5V
180
ns
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
16L PDIP
(Internally Fused Leads)
1
INHIBIT B
Control pin for deadband control on Channel B.
2
INV
3
NONINV
4
5
6
Gnd
Gnd
VOUT(A)
7
F/F ENABLE
8
VCC
9
STOP -
Inverting input for stop latch comparator.
10
STOP +
Noninverting input for stop latch comparator.
11
VOUT(B)
Channel B output.
12
Gnd
Ground.
13
Gnd
Ground.
14
VIN
Supply voltage (5V to 40V) for IC (except output driver).
15
INHIBIT REF
16
INHIBIT A
Inverting input for output drivers.
Noninverting input for output drivers.
Ground.
Ground.
Channel A output.
Controls the phase of the two outputs.
F/F ENABLE = Gnd
Out of phase.
F/F ENABLE = floating In phase.
Supply voltage (5V to 40V) for output drivers.
Reference input for deadband control.
Control pin for deadband control on channel A.
3
CS3706
Typical Switching Characteristics: (VIN = VCC = 20V, TA = 25ûC. Delays measured 50% in to 50% out.)
CS3706
Circuit Description
Outputs
The totem-pole outputs have been designed to minimize
cross-conduction current spikes while maximizing fast,
high-current rise and fall times. Current limiting can be
done externally either at the outputs or at the common
VCC pin. The output diodes included have slow recovery
and should be shunted with high-speed external diodes
when driving high-frequency inductive loads.
Analog Shutdown
This circuit is included to get a latched shutdown as close
to the outputs as possible, from a time standpoint. With an
internal 130mV threshold, this comparator has a commonmode range from ground to (VIN - 3V). When not used,
both inputs should be grounded. The time required for
this circuit to latch is inversely proportional to the amount
of overdrive but reaches a minimum of 180nsec. As with
the flip-flop, an input off-time of at least 200nsec is
required to reset the latch between pulses.
Flip/Flop
Grounding F/F Enable activates the internal flip-flop to
alternate the two outputs. With pin open, the two outputs
operate simultaneously and can be paralleled for higher
current operation. Since the flip-flop is triggered by the
digital input, an off-time of at least 200nsec. must be provided to allow the flip/flop to change states. Note that the
circuit logic is configured such that the ÒOFFÓ state is
defined as the outputs low.
Supply Voltage
With an internal 5V regulator, this circuit is optimized for
use with a 7 to 40V supply, however, with some slight
response time degradation, it can also be driven from 5V.
When VIN is low, the entire circuit is disabled and no current is drawn from VCC. When combined with a CS384X
PWM, the Driver Bias switch can be used to supply VIN to
the CS3706. VIN switching should be fast as undefined
operation of the outputs may occur with VIN less than 5V.
Digital Inputs
With both an inverting and non-inverting input available,
either active-high or active-low signals may be accepted.
These are true TTL compatible inputsÐthe threshold is
approximately 1.2V with no hysteresis; and external pullup resistors are not required.
Thermal Considerations
Should the chip temperature reach approximately 155ûC, a
parallel, non-inverting input is activated driving both outputs to the low state.
Inhibit Circuit
Although it may have other uses, this circuit is included to
eliminate the need for deadband control when driving relatively slow bipolar power transistors. A diode from each
inhibit input to the opposite power switch collector will
keep one output from turning on until the other has
turned-off. The threshold is determined by the voltage on
INHIBIT REF which can be set from 0.5 to 3.5 V. When this
circuit is not used, ground INHIBIT REF and leave INHIBIT A&B open.
Truth Table
INV.
N.I.
OUT
H
L
H
L
H
H
L
L
L
H
L
L
OUT = INV and N.I.
OUT = INV or N.I.
4
CS3706
Application Diagram
14V
10W
5V
VIN
VCC
INHIBIT B
.047mF
3k
VOUTA
REF
CS3706
2k
100W
10k
NONINV
Input
100W
INV
VOUTB
F/F ENABLE
.047mF
INHIBIT A
Gnd
5
10k
100mF
RL
CS3706
Package Specification
PACKAGE THERMAL DATA
PACKAGE DIMENSIONS IN mm (INCHES)
D
Lead Count
16L PDIP
(Internally Fused Leads)
Metric
Max
Min
19.69
18.67
16 Lead PDIP
Thermal Data
RQJC
typ
RQJA
typ
English
Max Min
.775
.735
(Internally Fused Leads)
15
50
ûC/W
ûC/W
Plastic DIP (N); 300 mil wide
7.11 (.280)
6.10 (.240)
8.26 (.325)
7.62 (.300)
1.77 (.070)
1.14 (.045)
2.54 (.100) BSC
3.68 (.145)
2.92 (.115)
.356 (.014)
.203 (.008)
0.39 (.015)
MIN.
.558 (.022)
.356 (.014)
REF: JEDEC MS-001
D
Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
All specs are the same.
Ordering Information
Part Number
CS3706GNF16
Rev. 4/29/99
Description
16 Lead PDIP
(Internally Fused Leads)
Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.
6
© 1999 Cherry Semiconductor Corporation