CS8120 CS8120 5V, 300mA Linear Regulator with RESET and ENABLE Description The CS8120 is a 5V, 300mA precision linear regulator with two microprocessor compatible control functions and protection circuitry included on chip. The composite NPN-PNP output pass transistor assures a lower dropout voltage (1V @ 200mA) without requiring excessive supply current (2.5mA). The CS8120Õs two logic control functions make this regulator well suited to applications requiring microprocessorbased control at the board or module level. ENABLE controls the output stage. A high voltage (>2.9V) on the ENABLE lead turns off the regulatorÕs pass transistor and sends the IC into Sleep mode where it draws only 250µA. The RESET function sends a Features RESET signal when the IC is powering up or whenever the output voltage moves out of regulation. The RESET signal is valid down to VOUT = 1V. The CS8120 design optimizes supply rejection by switching the internal bandgap reference from the supply input to the regulator output as soon as the nominal output voltage is achieved. Additional on chip filtering enhances rejection of high frequency transients on all external leads. The CS8120 is fault protected against short circuit, over voltage and thermal runaway conditions. ■ 5V ± 4% Output Voltage 300mA ■ Low Dropout Voltage (1V @ 150mA) ■ Low Quiescent Current (2.5mA @ IOUT = 150mA) ■ µP Compatible Control Functions RESET ENABLE ■ Low Current Sleep Mode IQ=250µA ■ Fault Protection Thermal Shutdown Short Circuit 60V Load Dump Block Diagram * Package Options 14 Lead SOIC Narrow 5 Lead TO-220 Tab (Gnd) V OUT VIN V IN Over Voltage Shutdown - ENABLE Output Current Limit ENABLE Comparator Bandgap Supply - + Gnd NC SENSE NC NC Error Amplifier + Thermal Shutdown TO VOUT RESET RESET ENABLE NC NC NC NC 8 Lead PDIP 1 VREF VOUT 1 NC VOUT Gnd 1 VIN NC Bandgap Reference SENSE RESET NC ENABLE 5 Lead D2 PAK RESET Comparator + 1 2 3 Gnd 4 5 1 * TO-220 Block Diagram VIN ENABLE Gnd RESET VOUT Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: [email protected] Web Site: www.cherry-semi.com Rev. 2/3/98 1 A ¨ Company CS8120 Absolute Maximum Ratings DC Input Voltage ...........................................................................................................................................................-0.7 to 26V Load Dump .................................................................................................................................................................................60V Output Current .................................................................................................................................................Internally Limited Electrostatic Discharge (Human Body Model) ......................................................................................................................2kV Operating Temperature .......................................................................................................................................-40¡C to +125¡C Junction Temperature...........................................................................................................................................-40¡C to +150¡C Storage Temperature ............................................................................................................................................-55¡C to +150¡C Lead Temperature Soldering Wave Solder (through hole styles only) .....................................................................................10 sec. max, 260¡C peak Reflow (SMD styles only) ......................................................................................60 sec. max above 183¡C, 230¡C peak Electrical Characteristics: VIN = 14V, IOUT =5 mA, -40ûC ² TJ ² 150ûC, -40ûC ² TC ² 125ûC unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP 4.8 5.0 MAX UNIT ■ Output Stage Output Voltage, VOUT 7V ² VIN ² 26V, 1mA ² IOUT ² 300mA 5.2 V Line Regulation 7V ² VIN ² 26V, IOUT = 200mA 50 mV Load Regulation 1mA ² IOUT ² 300mA 50 mV Supply Voltage Rejection VIN = 14VDC + 1VRMS @120Hz, ILOAD = 25½ Dropout Voltage IOUT = 200mA 1.0 1.5 V Quiescent Current ENABLE = High, VIN = 12V ENABLE = Low, IOUT = 200mA 0.25 2.5 0.65 15.0 mA mA 40 70 dB ■ Protection Circuits Short Circuit Current 300 600 mA Thermal Shutdown 150 190 ûC Overvoltage Shutdown 26 40 V ■ RESET RESET Saturation Voltage 1V < VOUT < VRT(OFF), 3.1k½ pull-up to VOUT RESET Output Leakage ENABLE = Low Current Power ON/OFF RESET Peak Output Voltage 0.1 0.4 V 0 25 µA 0.7 1.0 V VOUT - 0.10 VOUT - 0.04 V VOUT > VRT(ON), V RESET = VOUT 3.1k½ pull-up to VOUT RESET Threshold ON (VOUT Increasing) RESET Threshold OFF (VOUT Decreasing) 4.75 RESET Threshold Hysteresis 10 VOUT - 0.14 V 40 mV ■ ENABLE Input High Voltage 7V < VIN < 26V Input Low Voltage 7V < VIN < 26V 2.9 1.1 2.1 3.9 V V Input Hysteresis 7V < VIN < 26V 0.4 0.8 2.8 V Input Current Gnd < VIN(HI) < VOUT -10 0 +10 µA * To have safe operating junction temperatures, low duty cycle pulse testing is used on tests where applicable. 2 CS8120 Package Lead Description PACKAGE LEAD # 5 Lead TO-220 LEAD SYMBOL FUNCTION 8 Lead 14 Lead SO 5 Lead D2 PDIP Narrow PAK 1 2 1 1 Supply voltage to IC, usually direct from the battery. 2 VIN ENABLE 2 4 5 3 8 13 3 Gnd Ground connection. 4 6 10 4 RESET CMOS compatible output lead. RESET goes low whenever VOUT falls out of regulation. The RESET delay is externally programmed. 5 1 14 5 VOUT Regulated output voltage, 5V (typ). N/A 7 12 SENSE Kelvin Connection which allows remote sensing of output voltage for improved regulation. If remote sensing is not desired, connect to VOUT. NC No connection 3, 5 2,3,4, CMOS compatible logical input. VOUT is disabled i.e. placed in a high impedance state when ENABLE is high. 6,7,8,9,11 Typical Performance Characteristics Load Regulation vs. Output Current Over Temperature Output Voltage vs. Temperature 5.02 0 IOUT = 100mA 5.01 5.00V @25°C -10 Load Reg. (mV) 5 VOUT (V) -40°C -5 4.99 4.98 4.97 VIN =14V -15 125°C 25°C -20 -25 -30 -35 -40 4.96 -45 -50 4.95 -40 -20 0 0 20 40 60 80 100 120 140 150 100 200 300 IOUT (mA) Junction Temperature (°C) Line Regulation vs. Output Current Over Temperature 400 500 Dropout Voltage vs. Output Current Over Temperature 50 1.4 VIN = 7 to 25V 1.2 30 Dropout Voltage (V) Line Reg. (mV) 40 25°C 20 125°C 10 -40°C 0 1.0 -40°C 0.8 25°C 125°C 0.6 0.4 0.2 -10 0 50 0.0 100 150 200 250 300 350 400 450 500 IOUT (mA) 0 50 100 150 200 Output Current (mA) 3 250 300 350 CS8120 Typical Performance Characteristics: continued Quiescent Current vs. Output Current Over Temperature Output Voltage and Supply Current vs. Input Voltage VIN = 14V 3.0 5.5 22.0 5.0 20.0 VOUT 4.0 25°C VOUT (V) Quiescent Current (mA) -40°C 2.5 2.0 125°C 1.5 16.0 3.0 12.0 IQ 2.0 8.0 1.0 4.0 1.0 Supply Current (mA) 3.5 0.5 0.0 0.0 0 50 100 150 200 250 300 0.0 0.0 350 2.0 4.0 6.0 Supply Voltage (V) Output Current (mA) 8.0 10.0 RESET Output Voltage vs. Output Current 2000 Reset Output Voltage (mV) 1800 VIN = 5V 1600 1400 1200 1000 800 600 400 200 0 1 5 10 15 20 25 30 35 40 Reset Output Current (mA) Circuit Description The NPN pass device prevents deep saturation of the output stage which in turn improves the ICÕs efficiency by preventing excess current from being used and dissipated by the IC. Voltage Reference and Output Circuitry Precision Voltage Reference The regulated output voltage depends on the precision band gap voltage reference in the IC. By adding an error amplifier into the feedback loop , the output voltage is maintained within ±4% over temperature and supply variation. Output Stage Protection The output stage is protected against overvoltage, short circuit and thermal runaway conditions (Figure 2). > 30V Output Stage VIN The composite PNPNPN output structure (Figure 1) provides 300mA (typ) of output current while maintaining a low drop out voltage (1.00V, typ) and drawing little quiescent current (2.5mA). VIN VOUT IOUT VOUT Load Dump Figure 1: Composite Output Stage of the CS8120 Short Circuit Thermal Shutdown Figure 2: Typical Circuit Waveforms for Output Stage Protection. 4 CS8120 Circuit Description: continued If the input voltage rises above 26V (e.g. load dump), the output shuts down. This response protects the internal circuitry and enables the IC to survive unexpected voltage transients. Using an emitter sense scheme, the amount of current through the NPN pass transistor is monitored. Feedback circuitry insures that the output current never exceeds a preset limit. provide good noise immunity. RESET Function A RESET signal (low voltage) is generated as the IC powers up (VOUT > VOUT - 100mV) or when VOUT drops out of regulation (VOUT < VOUT - 140mV, typ). 40mV of hysteresis is included in the function to minimize oscillations. The RESET output is an open collector NPN transistor, controlled by a low voltage detection circuit. The circuit is functionally independent of the rest of the IC, thereby Should the junction temperature of the power device exceed 180ûC (typ) the power transistor is turned off. Thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the IC. VOUT Regulator Control Functions CS–8120 The CS8120 contains two microprocessor compatible control functions: ENABLE and RESET (Figure 3). ENABLE Function ENABLE switches the output transistor. When the voltage on the ENABLE lead exceeds 2.9V typ, the output pass transistor turns off, leaving a high impedance facing the load. The IC will remain in Sleep mode, drawing only 250µA, until the voltage on the lead drops below 2.1V typ. Hysteresis (800mV) is built into the ENABLE function to CRST Figure 4: RC Network for RESET Delay circuitry guaranteeing that the RESET signal is valid for VOUT as low as 1V. An external RC network on the RESET lead (Figure 4) provides a sufficiently long delay for most microprocessor based applications. RC values can be chosen using the following formula: VIN RTOT ´ CRST ENABLE HI VIN(HI) LO VRT(ON) where: VRT(OFF) VOUT RESET (2) VR VR [ ÐtDelay ln ( VT Ð VOUT VRST Ð VOUT )] RTOT = RRST in parallel with RIN, RIN = µP port impedance, CRST = RESET delay capacitor, (1) PEAK to mP RESET Port RESET FOR 7V < VIN < 26V VR H C2 22mF RRST 5V to mP and System Power PEAK tDelay = desired delay time, VRST = VSAT of RESET lead (0.7V @ turn - on), and VT = µP logic threshold voltage. SAT (1) = NO RESET DELAY CAPACITOR (2) = WITH RESET DELAY CAPACITOR Figure 3: Circuit Waveforms for CS8120 Applications Notes The circuit depicted in Figure 5 lets the microprocessor control its power source, the CS8120 regulator. An I/O port on the µP and the SWITCH port are used to drive the base of Q1. When Q1 is driven into saturation, the voltage on the ENABLE lead falls below its lower threshold. The regulatorÕs output is switched out. When the drive current is removed, the voltage on the ENABLE lead rises, the output is switched off and the IC moves into Sleep mode where it draws 250µA. By coupling these two controls with ENABLE , the system has added flexibility. Once the system is running, the state of the SWITCH is irrelevant as long as the I/O port continues to drive Q1. The µP can turn off its own power by withdrawing drive current, once the SWITCH is open. This software control at the I/O port allows the µP to finish key housekeeping functions before power is removed. The logic options are summarized in Table 1 below Table 1: Logic Control of CS8120 Output SWITCH ENABLE Output µP I/O drive ON OFF 5 Closed Open Closed Open LOW LOW LOW HIGH ON ON ON OFF CS8120 Application Notes VIN VBAT C1 0.1mF VOUT CS–8120 500kW ENABLE Gnd VCC mP C2 22mF RRST RESET RESET I/O Port CRST Q1 100kW 100kW 500kW SWITCH Figure 5: Microprocessor Control of CS8120 using an external switching transistor (Q1). The I/O port of the microprocessor typically provides 50µA to Q1. In automotive applications the SWITCH is connected to the ignition switch. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Remove the unit from the environmental chamber and heat the IC with a heat gun. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ± 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. Stability Considerations The output or compensation capacitor, C2, helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25¡C to -40¡C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor C2 shown in Figure 6 should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for C2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. 6 CS8120 Application Notes: continued VIN 5V to mP and System Power VOUT C 1* 0.1mF CS-8120 C2** 10mF RRST to mP RESET Port RESET ENABLE CRST *C1 is required if regulator is far from power source filter. **C2 is required for stability. Figure 6. Circuit showing output compensation capacitor. will keep the die temperature below 150¡C. Calculating Power Dissipation in a Single Output Linear Regulator In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. The maximum power dissipation for a single output regulator (Figure 7) is: PD(max)={VIN(max) Ð VOUT(min)}IOUT(max) + VIN(max)IQ Heat Sinks (1) A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RQJA: RQJA = RQJC + RQCS + RQSA where: RQJC = the junctionÐtoÐcase thermal resistance, Once the value of PD(max) is known, the maximum permissible value of RQJA can be calculated: RQCS = the caseÐtoÐheatsink thermal resistance, and 150¡C - TA RQJA = PD (2) RQSA = the heatsinkÐtoÐambient thermal resistance. The value of RQJA can then be compared with those in the package section of the data sheet. Those packages with RQJA's less than the calculated value in equation 2 IIN VIN Smart Regulator } (3) RQJC appears in the package section of the data sheet. Like RQJA, it too is a function of package type. RQCS and RQSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers. IOUT VOUT Control Features IQ Figure 7. Single output regulator with key performance parameters labeled. 7 CS8120 Package Specification PACKAGE THERMAL DATA PACKAGE DIMENSIONS IN mm (INCHES) D Lead Count Metric Max Min 8.75 8.55 10.16 9.02 14 Lead SOIC Narrow 8 Lead PDIP Thermal Data 5 Lead 5 Lead 8 Lead 14 Lead SOIC TO-220 D2Pak PDIP Narrow RQJC typ 3.1 3.1 52 30 ûC/W RQJA typ 50 10-50* 100 125 ûC/W English Max Min .344 .337 .400 .355 *Depending on thermal properties of substrate. RQJA = RQJC + RQCA 5 Lead TO-220 (T) Straight Plastic DIP (N); 300 mil wide 7.11 (.280) 6.10 (.240) 10.54 (.415) 9.78 (.385) 8.26 (.325) 7.62 (.300) 1.77 (.070) 1.14 (.045) 2.87 (.113) 6.55 (.258) 2.62 (.103) 5.94 (.234) 2.54 (.100) BSC 3.68 (.145) 2.92 (.115) 1.40 (.055) 1.14 (.045) 4.83 (.190) 4.06 (.160) 3.96 (.156) 3.71 (.146) 14.99 (.590) 14.22 (.560) .356 (.014) .203 (.008) 0.39 (.015) MIN. .558 (.022) .356 (.014) REF: JEDEC MS-001 14.22 (.560) 13.72 (.540) Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same. D 1.02 (.040) 0.76 (.030) Surface Mount Narrow Body (D); 150 mil wide 1.83(.072) 1.57(.062) 1.02(.040) 0.63(.025) 4.00 (.157) 3.80 (.150) 6.20 (.244) 5.80 (.228) 0.51 (.020) 0.33 (.013) 1.27 (.050) BSC 6.93(.273) 6.68(.263) 2.92 (.115) 2.29 (.090) 5 Lead D2PAK (DP) 10.31 (.406) 10.05 (.396) 1.75 (.069) MAX 1.40 (.055) 1.14 (.045) 1.68 (.066) 1.40 (.055) 1.57 (.062) 1.37 (.054) 1.27 (.050) 0.40 (.016) 0.56 (.022) 0.36 (.014) 8.53 (.336) 8.28 (.326) 0.25 (.010) 0.19 (.008) D 0.25 (0.10) 0.10 (.004) 15.75 (.620) 14.73 (.580) 2.74(.108) 2.49(.098) REF: JEDEC MS-012 0.91 (.036) 0.66 (.026) Ordering Information Part Number CS8120YT5 CS8120YTVA5 CS8120YTHA5 CS8120YN8 CS8120YDP5 CS8120YDPR5 CS8120YD14 CS8120YDR14 Rev. 2/3/98 2.79 (.110) 2.29 (.090) Description 5 Lead TO-220 Straight 5 Lead TO-220 Vertical 5 Lead TO-220 Horizontal 8 Lead PDIP 5 Lead D2 PAK 5 Lead D2 PAK (tape & reel) 14 Lead SOIC Narrow 14 Lead SOIC Narrow (tape & reel) 1.70 (.067) REF 4.57 (.180) 4.31 (.170) .254 (.010) REF 0.10 (.004) 0.00 (.000) Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. 8 © 1999 Cherry Semiconductor Corporation