CHERRY CS8151YNF16

CS8151
CS8151
5V, 100mA Low Dropout Linear Regulator
with WATCHDOG, RESET, & WAKE UP
Description
Features
is received, a falling edge is issued on
the wake-up signal line.
The CS8151 is a precision 5V, 100mA
micro-power voltage regulator with
very low quiescent current (400µA
typical at 200µA load). The 5V output
is accurate within ±2% and supplies
100 mA of load current with a typical
dropout voltage of 400mV.
Microprocessor control logic includes
Watchdog, Wake Up and RESET . This
unique combination of low quiescent
current and full microprocessor control makes the CS8151 ideal for use in
battery operated, microprocessor controlled equipment.
RESET is independent of VIN and
operates correctly to an output voltage
as low as 1V. A RESET signal is issued
in any of three situations. During
power up the RESET is held low until
the output voltage is in regulation.
During operation if the output voltage
shifts below the regulation limits, the
RESET toggles low and remains low
until proper output voltage regulation
is restored. And finally, a RESET signal
is issued if the regulator does not
receive a WATCHDOG signal within
the WAKE UP period.
The CS8151 WAKE UP function brings
the microprocessor out of Sleep mode.
The microprocessor in turn, signals its
WAKE UP status back to the CS8151
by issuing a WATCHDOG signal.
The RESET pulse width, WAKE UP
signal frequency, and WAKE UP delay
time are all set by one external capacitor CDelay.
The WATCHDOG logic function monitors an input signal (WDI) from the
microprocessor. The CS8151 responds
to the falling edge of the WATCHDOG signal which it expects at least
once during each wake-up period.
When the correct WATCHDOG signal
VOUT
VIN
VOUT
Over
Voltage
Shutdown
Current Limit
Sense
internally
connected on
TO-220 and
D2PAK
WAKE UP
Delay
WAKE UP
Circuit
Timing
Circuit
+
WATCHDOG
Circuit
WDI
Thermal
Shutdown
Package Options
The regulator is protected against
short circuit, over voltage, and thermal
runaway conditions. The device can
withstand 74 volt load dump transients, making it suitable for use in
automotive environments.
Block Diagram
Current Source
(Circuit Bias)
■ 5V ±2% / 100 mA Output
Voltage
■ Micropower Compatible
Control Functions:
WAKE UP
WATCHDOG
RESET
■ Low Dropout Voltage:
400mV @ 100mA
■ Low Sleep Mode Quiescent
Current (400µA typ)
■ Protection Features:
Thermal Shutdown
Short Circuit
74V Load Dump
Reverse Transient (-50V)
Sense
16 Lead PDIP
16 Lead SOIC Wide*
(Internally Fused)
N/C
N/C
WAKE UP
Gnd
Gnd
Gnd
Gnd
*N/C
WDI
Sense
N/C
VOUT
VIN
* For SO Wide package, pin # 6 is Gnd
7 Lead TO-220
Tab (Gnd)
7 Lead D2PAK
Tab (Gnd)
- Error
Amplifier
1. VOUT
2. VIN
3. WDI
1
4. Gnd
5. WAKE UP
6. RESET
7. Delay
Falling Edge
Detector
Bandgap
Reference
VOUT
Delay
______
RESET
1
N/C
RESET
RESET
Circuit
Gnd
1
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
Rev. 5/4/99
1
A
¨
Company
CS8151
Absolute Maximum Ratings
Power Dissipation.............................................................................................................................................Internally Limited
Output Current (VOUT, RESET , WAKE UP) .................................................................................................Internally Limited
Reverse Battery..........................................................................................................................................................................-15V
Maximum Load Dump Transient .........................................................................................................................................+74V
Maximum Negative Transient (t<2ms) .................................................................................................................................-50V
ESD Susceptibility (Human Body Model)..............................................................................................................................2kV
ESD Susceptibility (Machine Model).....................................................................................................................................200V
Logic Inputs/Outputs ................................................................................................................................................-0.3V to +6V
Storage Temperature Range ................................................................................................................................-55¡C to +150¡C
Lead Temperature Soldering
Wave Solder (through hole styles only) .....................................................................................10 sec. max, 260¡C peak
Reflow (SMD styles only) ......................................................................................60 sec. max above 183¡C, 230¡C peak
Electrical Characteristics: TA = -40¡C to +125¡C, -40¡C ² TJ ² 150¡C, 6V ² VIN ² 26V, IOUT = 100µA to 100mA, C2 = 47µF
(ESR < 8½), CDelay = 0.1µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5.00
5.00
5.10
5.15
V
V
■ Output Section
Output Voltage, VOUT
9V < VIN < 16V
6V < VIN < 26V, 0 < IOUT < 100mA
4.90
4.85
Dropout Voltage (VIN - VOUT)
IOUT = 100mA
IOUT = 100µA
400
100
600
150
mV
mV
Load Regulation
VIN = 14V, 100µA < IOUT < 100mA
10
50
mV
10
50
mV
Line Regulation
IOUT = 1mA, 6V < VIN < 26V
Ripple Rejection
7V < VIN < 17V @ f = 120Hz,
IOUT = 100mA
60
75
dB
Current Limit
VOUT = 4.5V
100
250
mA
150
180
210
¡C
50
56
62
V
Thermal Shutdown
Overvoltage Shutdown
VOUT < 1V
Quiescent Current
IOUT = 200µA (Sleep)
IOUT = 50mA
IOUT = 100mA (WAKE UP)
0.40
4
12
0.75
20
mA
mA
mA
VOUT = 5V, VIN = 0V
1.0
1.5
mA
VOUT - 0.3
4.50
4.70
VOUT - 0.04
4.91
V
V
Reverse Current
■ RESET
Threshold High (RTH)
Threshold Low (RTL)
RTH VOUT Increasing
RTL VOUT Decreasing
Hysteresis
RTH Ð RTL
150
200
250
mV
1V < VOUT < RTL, IOUT = 25µA
IOUT = 25µA, VOUT > RTH
3.8
0.2
4.2
0.8
5.1
V
V
0.025
0.1
0.50
12
1.30
80
mA
mA
3
5
7
ms
Output
LOW
HIGH
Current Limit
RESET = 0V, VOUT > VRTH (sourcing)
RESET = 5V, VOUT > 1V (sinking)
Delay Time
POR Mode
2
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Threshold
HIGH
LOW
1.4
1.3
2.0
0.8
V
V
Hysteresis
25
100
-10
0
■ WATCHDOG Input
mV
Input Current
0 < WDI < 6V
+10
µA
Pulse Width
50% WDI falling edge to
50% WDI rising edge and
50% WDI rising edge to 50%
WDI falling edge (see Figure 1)
5
WAKE UP Period
see Figure 1a
30
40
50
ms
WAKE UP Duty Cycle nominal
see Figure 1c
40
50
60
%
RESET HIGH to WAKE UP
Rising Delay Time
50% RESET rising edge to
50% WAKE UP edge
(see Figure 1)
15
20
25
ms
WAKE UP Response
to Watchdog Input
50% WDI falling edge to
50% WAKE UP falling edge
2
10
µs
WAKE UP Response
to RESET
50% RESET falling edge to
50% WAKE UP falling edge
VOUT = 5V®4.5V
2
10
µs
0.2
4.2
0.8
5.1
V
V
1.00
7.00
3.50
mA
mA
µs
■ WAKE UP Output
Output
LOW
HIGH
IOUT = 25µA(sinking)
IOUT = 25µA(sourcing)
Current Limit
3.8
WAKE UP = 5V
WAKE UP = 0V
0.025
.05
Package Lead Description
Package Lead #
7L TO-220 &
7L D2PAK
2
16 L PDIP
Lead Symbol
Function
16L SOIC
(internally fused) (internally fused)
9
9
VIN
Supply voltage to the IC.
3
11
11
WDI
CMOS/TTL compatible input lead. The watchdog function
monitors the falling edge of the incoming signal.
4
4,5,12,13
4,5,6,12,13
Gnd
Ground Connection
7
16
16
Delay
Input lead from timing capacitor for RESET and WAKE UP
signal.
6
15
15
RESET
CMOS/TTL compatible output lead RESET goes low whenever VOUT drops by more than 6% from nominal, or during
the absence of a correct watchdog signal.
5
14
14
WAKE UP
CMOS/TTL compatible output consisting of a continuously
generated signal used to WAKE UP the microprocessor from
sleep mode.
1
8
8
VOUT
Regulated output voltage 5V ± 2%.
7
7
Sense
Kelvin connection which allows remote sensing of the output
voltage for improved regulation. If remote sensing is not
required, connect to VOUT.
3
CS8151
Electrical Characteristics: continued
CS8151
Timing Diagrams
Figure 1a. Power Up, Sleep Mode and Normal Operation
VIN
______
RESET
WAKE UP Duty Cycle = 50%
WAKE UP
WDI
VOUT-
POR
______
RESET High
to Wakeup
Delay Time
Power Up
Normal Operation with varying WATCHDOG Signal
Sleep Mode
Figure 1b. Error Condition: Watchdog remains LOW and a RESET is issued
______
RESET delay time
VIN
______
RESET
WAKE UP
WDI
VOUT
POR
______
RESET HIGH
to WAKE UP
DELAY TIME
WAKE UP
period
______
RESET HIGH
to WAKEUP
DELAY TIME
Figure 1c. Power Down and Restart Sequence
______
RESET
WAKE UP period
WAKE UP
WDI
RTL
VOUT
POR
POWER DOWN
POR
WATCHDOG Pulse Width
4
Dropout Voltage:
The input-output voltage differential at which the circuit ceases to regulate against further reduction in
input voltage. Measured when the output voltage has
dropped 100mV from the nominal value obtained at
14V input, dropout voltage is dependent upon load
current and junction temperature.
Input Voltage:
The DC voltage applied to the input terminals with
respect to ground.
Line Regulation:
The change in output voltage for a change in the
input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not
significantly affected.
Load Regulation:
The change in output voltage for a change in load
current at constant chip temperature.
Quiescent Current:
The part of the positive input current that does not
contribute to the positive load current. The regulator
ground lead current.
Ripple Rejection:
The ratio of the peak-to-peak input ripple voltage to
the peak-to-peak output ripple voltage.
Current Limit:
Peak current that can be delivered to the output.
Circuit Description
Capacitor temperature coefficient and tolerance as well as the
tolerance of the CS8151 must be taken into account in order
to get the correct system tolerance for each parameter.
Functional Description
To reduce the drain on the battery a system can go into a
low current consumption mode when ever its not performing a main routine. The WAKE UP signal is generated
continuously and is used to interrupt a microcontroller
that is in sleep mode. The nominal output is a 5 volt
square wave with a duty cycle of 50% at a frequency that
is determined by a timing capacitor, CDelay.
WAKE UP
When the microprocessor receives a rising edge from the
WAKE UP output, it must issue a watchdog pulse and
check its inputs to decide if it should resume normal operations or remain in the sleep mode.
WDI
The first falling edge of the watchdog signal causes the
WAKE UP to go low within 2µs (typ) and remain low until
the next WAKE UP cycle (see Figure 2). Other watchdog
pulses received within the same cycle are ignored (Figure
1).
WAKE UP
Response to
WDI
During power up, RESET is held low until the output voltage is in regulation. During operation, if the output voltage shifts below the regulation limits, the RESET toggles
low and remains low until proper output voltage regulation is restored. After the RESET delay, RESET returns
high.
Figure 2. WAKE UP response to WDI
______
RESET
The WATCHDOG circuitry continuously monitors the
input watchdog signal (WDI) from the microprocessor.
The absence of a falling edge on the WATCHDOG input
during one WAKE UP cycle will cause a RESET pulse to
occur at the end of the WAKE UP cycle. (see Figure 1b).
WAKE UP
The WAKE UP output is pulled low during a RESET
regardless of the cause of the RESET . After the RESET
returns high, the WAKE UP cycle begins again (see
Figures 1b).
The RESET pulse width, WAKE UP signal frequency and
RESET high to WAKE UP delay time are all set by one
external capacitor CDelay.
WAKE UP
Response to
______
RESET
WAKE UP period=(4x10 5)CDelay
Figure 3. WAKE UP response to RESET (Low Voltage)
RESET Delay Time=(5x10 4)CDelay
RESET HIGH to WAKE UP Delay Time =(2x10 5)CDelay
5
CS8151
Definition of Terms
CS8151
Application Notes
To determine an acceptable value for C2 for a particular
application, start with a tantalum capacitor of the recommended value and work towards a less expensive
alternative part.
Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade
box outside the chamber, the small resistance added by the
longer leads is negligible.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load
while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to
ensure a stable design under steady state conditions.
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that
cause the greatest oscillation. This represents the worst
case load conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in step
3 and vary the input voltage until the oscillations increase.
This point represents the worst case input voltage conditions.
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor
will usually cost less and occupy less board space. If the
output oscillates within the range of expected operating
conditions, repeat steps 3 and 4 with the next larger standard capacitor value.
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7: Remove the unit from the environmental chamber
and heat the IC with a heat gun. Vary the load current as
instructed in step 5 to test for any oscillations.
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for
the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic
capacitors have a tolerance of ±20% so the minimum value
found should be increased by at least 50% to allow for this
tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than
50% of the maximum allowable ESR found in step 3 above.
Output Stage Protection
The output stage is protected against overvoltage, short
circuit and thermal runaway conditions (see Figure 4).
> 30V
VIN
VOUT
IOUT
Load
Dump
Thermal
Shutdown
Short
Circuit
Figure 4: Typical Circuit Waveforms for Output Stage Protection.
If the input voltage rises above 56V (e.g. load dump), the
output shuts down. This response protects the internal circuitry and enables the IC to survive unexpected voltage
transients.
Should the junction temperature of the power device
exceed 180ûC (typ) the power transistor is turned off.
Thermal shutdown is an effective means to prevent die
overheating since the power transistor is the principle heat
source in the IC.
Stability Considerations
The output or compensation capacitor C2 (see Figure 5)
helps determine three main characteristics of a linear regulator: start-up delay, load transient response and loop stability.
VIN
VOUT
C 1*
0.1mF
RRST
CS8151
C2**
10mF
RESET
*C1 required if regulator is located
far from the power supply filter.
**C2 required for stability.
Calculating Power Dissipation
in a Single Output Linear Regulator
Figure 5. Test and application circuit showing output compensation.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum
or aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25¡C to -40¡C), both the value and ESR of the
capacitor will vary considerably. The capacitor manufacturers data sheet usually provide this information.
The value for the output capacitor C2 shown in the test
and applications circuit should work for most applications, however it is not necessarily the optimized solution.
The maximum power dissipation for a single output regulator (Figure 6) is:
PD(max) = {VIN(max) Ð VOUT(min)}IOUT(max) + VIN(max)IQ
(1)
where:
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
IOUT(max) is the maximum output current for the application, and
IQ is the quiescent current the regulator consumes at
IOUT(max).
6
CS8151
Application Diagram
Once the value of PD(max) is known, the maximum permissible value of RQJA can be calculated:
RQJA =
150¡C - TA
PD
Heat Sinks
Each material in the heat flow path between the IC and
the outside environment will have a thermal resistance.
Like series electrical resistances, these resistances are
summed to determine the value of RQJA:
(2)
The value of RQJA can then be compared with those in
the package section of the data sheet. Those packages with
RQJA's less than the calculated value in equation 2 will
keep the die temperature below 150¡C.
RQJA = RQJC + RQCS + RQSA
where:
RQJC = the junctionÐtoÐcase thermal resistance,
RQCS = the caseÐtoÐheatsink thermal resistance, and
RQSA = the heatsinkÐtoÐambient thermal resistance.
RQJC appears in the package section of the data sheet. Like
RQJA, it too is a function of package type. RQCS and RQSA
are functions of the package type, heatsink and the interface between them. These values appear in heat sink data
sheets of heat sink manufacturers.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
IIN
VIN
IOUT
Smart
Regulator
}
VOUT
Control
Features
IQ
Figure 6. Single output regulator with key performance parameters
labeled.
into the surrounding air.
Application Diagram
BATTERY
VOUT
V
VCC
IN
C1
C2
CS8151
Microprocessor
WDI
CDelay
Gnd
(3)
I/O
______
RESET
______
RESET
WAKE UP
CDelay
I/O
7
CS8151
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES)
PACKAGE THERMAL DATA
D
Metric
English
Max Min Max Min
16L PDIP (Internally Fused Leads) 19.69 18.67 .775 .735
16L SOIC Wide
10.50 10.10 .413 .398
(Internally Fused Leads)
Thermal Data 7 Lead 7 Lead 16 Lead 16 Lead
TO-220 D2PAK PDIP SOIC Wide
RQJC typ
1.8
1.8
15
18 ûC/W
Lead Count
RQJA
typ
50
10-50*
50
75
ûC/W
*Depending on thermal properties of substrate. RQJA = RQJC + RQCA
7 Lead D2PAK (DPS)* Short-Leaded
Plastic DIP (N); 300 mil wide
1.68 (.066)
1.40 (.055)
1.40 (.055)
1.14 (.045)
10.31 (.406)
10.05 (.396)
7.11 (.280)
6.10 (.240)
8.53 (.336)
8.28 (.326)
1.77 (.070)
1.14 (.045)
8.26 (.325)
7.62 (.300)
2.79 (.110)
2.54 (.100)
14.71 (.579)
13.69 (.539)
2.54 (.100) BSC
3.68 (.145)
2.92 (.115)
1.98 (.078)
1.47 (.058)
0.91 (.036)
0.66 (.026)
TERMINAL 8
1.27 (.050)
REF
.254 (.010)
REF
6.50 (.256) REF
0.39 (.015)
MIN.
.356 (.014)
.203 (.008)
.558 (.022)
.356 (.014)
REF: JEDEC MS-001
D
4.57 (.180)
4.31 (.170)
7.75 (.305)
REF
Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
All specs are the same.
0.10 (.004)
0.00 (.000)
Surface Mount Wide Body (DW); 300 mil wide
*CHERRY SEMICONDUCTOR SHORT-LEADED FOOTPRINT
7.60 (.299)
7.40 (.291)
0.51 (.020)
0.33 (.013)
1.27 (.050) BSC
2.49 (.098)
2.24 (.088)
1.27 (.050)
0.40 (.016)
7 Lead TO-220 (T) Straight
10.65 (.419)
10.00 (.394)
6.55 (.258)
5.94 (.234)
D
14.99 (.590)
14.22 (.560)
3.96 (.156)
3.71 (.146)
0.30 (.012)
0.10 (.004)
14.22 (.560)
13.72 (.540)
Ordering Information
Part Number
CS8151YT7
CS8151YTVA7
CS8151YDPS7
CS8151YDPSR7
Description
7 lead TO-220 Straight
7 lead TO-220 Vertical
7 lead D2PAK Short-Leaded
7 lead D2PAK Short-Leaded
(tape & reel)
CS8151YNF16
16 lead PDIP (Internally Fused Leads)
CS8151YDWF16 16 lead SOIC Wide
(Internally Fused Leads)
CS8151YDWFR16 16 lead SOIC Wide
(Internally Fused Leads) (tape & reel)
Rev. 5/4/99
1.40 (.055)
1.14 (.045)
2.87 (.113)
2.62 (.103)
2.65 (.104)
2.35 (.093)
0.32 (.013)
0.23 (.009)
REF: JEDEC MS-013
4.83 (.190)
4.06 (.160)
10.54 (.415)
9.78 (.385)
0.94 (.037)
0.58 (.023)
1.40 (.055)
1.14 (.045)
0.64 (.025)
0.38 (.015)
7.75 (.305)
7.49 (.295)
0.56 (.022)
0.36 (.014)
2.92 (.115)
2.29 (.090)
Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.
8
© 1999 Cherry Semiconductor Corporation