CS8421 32-bit, 192 kHz Asynchronous Sample Rate Converter z Flexible 3-Wire Serial Digital Audio Input and Features z 175 dB Dynamic Range z –140 dB THD+N z No Programming Required z No External Master Clock Required z Supports Sample Rates up to 211 kHz z Input/Output Sample Rate Ratios from 7.5:1 to 1:8 z Master Clock Support for 128 x fs, 256 x fs, 384 x fs, and 512 x fs (Master Mode) z 16, 20, 24, or 32-bit Data I/O z 32-bit Internal Signal Processing z Dither Automatically Applied and Scaled to Output Resolution Output Ports z Master and Slave Modes for Both Input and Output z Bypass Mode z Time Division Multiplexing (TDM) Mode z Attenuates Clock Jitter z Multiple Part Outputs are Phase Matched z Linear Phase FIR Filter z Automatic Soft Mute/Unmute z +2.5 V Digital Supply (VD) z +3.3 V or 5.0 V Digital Interface (VL) z Space Saving 20-pin TSSOP and QFN Packages I RST BYPASS ISCLK ILRCK Level Translators SDIN MS_SEL Serial Audio Input Data Sync Info Time Varying Digital Filters Data Sync Info Digital PLL SAOF 3.3 V or 5.0 V (VL) Clock Generator Preliminary Product Information http://www.cirrus.com 2.5 V (VD) TDM_IN SDOUT OSCLK OLRCK SRC_UNLOCK Serial Port Mode Decoder SAIF Serial Data Audio Output Level Translators Level Translators GND XTI MCLK_OUT XTO This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) JAN ‘05 DS641PP1 1 CS8421 General Description The CS8421 is a 32-bit, high performance, monolithic CMOS stereo asynchronous sample rate converter. Digital audio inputs and outputs can be 32, 24, 20, or 16-bits. Input and output data can be completely asynchronous, synchronous to an external data clock, or the part can operate without any external clock by using an integrated oscillator. Audio data is input and output through configurable 3-wire input/output ports. The CS8421 does not require any software control via a control port. Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR), digital mixing consoles, high quality D/A, effects processors, computer audio systems, and automotive audio systems. The part is available in space saving 20-pin TSSOP and QFN packages and supports sample rates up to 211 kHz. ORDERING INFORMATION Product Description Container Order# Rail CS8421-CZZ TSSOP YES -10° to +70°C CS8421 32-bit Asynchronous Sample Rate Converter TSSOP YES -10° to +70°C Tape and Reel CS8421-CZZR CS8421 32-bit Asynchronous Sample Rate Converter QFN YES -10° to +70°C Rail CS8421-CNZ CS8421 32-bit Asynchronous Sample Rate Converter QFN YES -10° to +70°C Tape and Reel CS8421-CNZR CS8421 32-bit Asynchronous Sample Rate Converter TSSOP YES -40° to +85°C CS8421 32-bit Asynchronous Sample Rate Converter TSSOP YES -40° to +85°C Tape and Reel CS8421-DZZR - - CDB8421 Evaluation Board for CS8421 2 Package Pb-Free Temp Range CS8421 32-bit Asynchronous Sample Rate Converter - Rail - CS8421-DZZ CDB8421 DS641PP1 CS8421 TABLE OF CONTENTS 1. 2. 3. 4. 5. 6. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5 TYPICAL CONNECTION DIAGRAMS ................................................................................. 10 GENERAL DESCRIPTION ..................................................................................................... 12 THREE-WIRE SERIAL INPUT/OUTPUT AUDIO PORT ........................................................ 12 MODE SELECTION ................................................................................................................ 12 SAMPLE RATE CONVERTER (SRC) .................................................................................... 15 6.1 Clocking ........................................................................................................................... 15 6.2 Data Resolution and Dither ............................................................................................. 15 6.3 SRC Locking and Varispeed ........................................................................................... 15 6.4 Bypass Mode ................................................................................................................... 16 6.5 Muting .............................................................................................................................. 16 6.6 Group Delay and Phase Matching Between Multiple CS8421 Parts ............................... 16 6.7 Master Clock .................................................................................................................... 17 6.8 Time Division Multiplexing (TDM) Mode .......................................................................... 18 7. PIN DESCRIPTIONS ........................................................................................................ 20 7.1 TSSOP Pin Descriptions .............................................................................................. 21 7.2 QFN Pin Descriptions ..................................................................................................... 22 8. PERFORMANCE PLOTS .............................................................................................. 23 9. APPLICATIONS .................................................................................................................... 32 9.1 Reset, Power Down, and Start-up ................................................................................... 32 9.2 Power Supply, Grounding, and PCB layout ..................................................................... 32 10. PACKAGE DIMENSIONS ................................................................................................... 33 11. REVISION HISTORY ........................................................................................................... 35 LIST OF FIGURES Figure 1. Non-TDM Slave Mode Timing.......................................................................................... 8 Figure 2. TDM Slave Mode Timing ................................................................................................. 8 Figure 3. Non-TDM Master Mode Timing........................................................................................ 9 Figure 4. TDM Master Mode Timing ............................................................................................... 9 Figure 5. Typical Connection Diagram, Master and Slave Modes ................................................ 10 Figure 6. Typical Connection Diagram, No External Master Clock ............................................... 11 Figure 7. Serial Audio Interface Format - I²S ................................................................................ 14 Figure 8. Serial Audio Interface Format - Left Justified................................................................. 14 Figure 9. Serial Audio Interface Format - Right Justified .............................................................. 14 Figure 10. Typical Connection Diagram for Crystal Circuit ........................................................... 17 Figure 11. TDM Slave Mode Timing Diagram............................................................................... 18 Figure 12. TDM Master Mode Timing Diagram............................................................................. 18 Figure 13. TDM Mode Configuration (All CS8421 outputs are slave) ........................................... 19 Figure 14. TDM Mode Configuration (First CS8421 output is master, all others are slave).......... 19 Figure 15a. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:48 kHz ...................... 23 Figure 15b. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 44.1 kHz:192 kHz ................. 23 Figure 16a. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 44.1 kHz:48 kHz ................... 23 Figure 16b. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:44.1 kHz ................... 23 Figure 17a. Wideband FFT Plot (1Fsi6k Points) 0 dBFS 1 kHz Tone, 48 kHz:96 kHz ................. 23 Figure 17b. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 96 kHz:48 kHz ...................... 23 Figure 18a. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 192 kHz:48 kHz .................... 24 Figure 18b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:96 kHz................... 24 Figure 19a. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:48 kHz................... 24 Figure 19b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 44.1 kHz:192 kHz.............. 24 Figure 20a. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 44.1 kHz:48 kHz................ 24 Figure 20b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:44.1 kHz................ 24 DS641PP1 3 CS8421 Figure 21b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 96 kHz:48 kHz ................... 25 Figure 21b. IMD, 10 kHz and 11 kHz -7 dBFS, 96 kHz:48 kHz..................................................... 25 Figure 22a. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 192 kHz:48 kHz ................. 25 Figure 22b. IMD, 10 kHz and 11 kHz -7 dBFS, 48 kHz:44.1 kHz.................................................. 25 Figure 23a. IMD, 10 kHz and 11 kHz -7 dBFS, 44.1 kHz:48 kHz.................................................. 25 Figure 23b. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 44.1 kHz:48 kHz ................. 25 Figure 24a. Wideband FFT Plot (16k Points) 0 dBFS 80 kHz Tone, 192 kHz:192 kHz ................ 26 Figure 24b. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:96 kHz .................... 26 Figure 25a. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:48 kHz .................... 26 Figure 25b. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 96 kHz:48 kHz .................... 26 Figure 26a. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:44.1 kHz ................. 26 Figure 26b. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 192 kHz ...................... 26 Figure 27a. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 48 kHz ........................ 27 Figure 27b. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 96 kHz ........................ 27 Figure 28a. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 44.1 kHz ..................... 27 Figure 28b. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 192 kHz...... 27 Figure 29a. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 32 kHz ........................ 27 Figure 29b. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 32 kHz........ 27 Figure 30a. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 96 kHz........ 28 Figure 30b. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 44.1 kHz..... 28 Figure 31a. Frequency Response with 0 dBFS Input.................................................................... 28 Figure 31b. Passband Ripple, 192 kHz:48 kHz............................................................................. 28 Figure 32a. Dynamic Range........ vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 48 kHz28 Figure 32b. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:48 kHz ........................ 28 Figure 33a. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:44.1 kHz ..................... 29 Figure 33b. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:96 kHz ........................ 29 Figure 34a. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 96 kHz:48 kHz ........................ 29 Figure 34b. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:192 kHz ................... 29 Figure 35a. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:48 kHz ..................... 29 Figure 35b. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 192 kHz:44.1 kHz ................... 29 Figure 36a. THD+N vs. Input Amplitude, 1 kHz Tone, 48 kHz:44.1 kHz....................................... 30 Figure 36b. THD+N vs. Input Amplitude, 1 kHz Tone, 48 kHz:96 kHz.......................................... 30 Figure 37a. THD+N vs. Input Amplitude, 1 kHz Tone, 96 kHz:48 kHz.......................................... 30 Figure 37b. THD+N vs. Input Amplitude, 1 kHz Tone, 44.1 kHz:192 kHz..................................... 30 Figure 38a. THD+N vs. Input Amplitude, 1 kHz Tone, 44.1 kHz:48 kHz....................................... 30 Figure 38b. THD+N vs. Input Amplitude, 1 kHz Tone, 192 kHz:48 kHz........................................ 30 Figure 39a. THD+N vs. Frequency Input, 0 dBFS, 48 kHz:44.1 kHz ............................................ 31 Figure 39b. THD+N vs. Frequency Input, 0 dBFS, 48 kHz:96 kHz ............................................... 31 Figure 40a. THD+N vs. Frequency Input, 0 dBFS, 44.1 kHz:48 kHz ............................................ 31 Figure 40b. THD+N vs. Frequency Input, 0 dBFS, 96 kHz:48 kHz ............................................... 31 LIST OF TABLES Table 1. Serial Audio Port Master/Slave and Clock Ratio Select Startup Options (MS_SEL) ...... 13 Table 2. Serial Audio Input Port Startup Options (SAIF) ............................................................... 13 Table 3. Serial Audio Output Port Startup Options (SAOF) .......................................................... 13 Table 4. TSSOP Pin Descriptions ................................................................................................. 21 Table 5. QFN Pin Descriptions...................................................................................................... 22 Table 6. Revision History .............................................................................................................. 35 4 DS641PP1 CS8421 1. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C.) SPECIFIED OPERATING CONDITIONS (GND = 0 V, all voltages with respect to 0 V) Parameter Power Supply Voltage Ambient Operating Temperature: ‘-CZ’ ‘-CNZ’ ‘-DZ’ Symbol Min Nominal Max Units VD VL 2.38 3.14 2.5 3.3 or 5.0 2.62 5.25 V V TA -10 -10 -40 - +70 +70 +85 °C °C °C ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.) Parameter Symbol Min Max Units VD VL -0.3 -0.3 3.5 6.0 V V Iin - ±10 mA Vin -0.3 VL+0.4 V Ambient Operating Temperature (power applied) TA -55 +125 °C Storage Temperature Tstg -65 +150 °C Power Supply Voltage Input Current, Any Pin Except Supplies Input Voltage (Note 1) Notes: 1. Transient currents of up to 100 mA will not cause SCR latch-up. 2. Numbers separated by a colon indicate input and output sample rates. For example, 48 kHz:96 kHz indicates that Fsi = 48 khz and Fso = 96 kHz. DS641PP1 5 CS8421 PERFORMANCE SPECIFICATIONS (XTI/XTO = 27 MHz; Input signal = 1.000 kHz, 0 dBFS, Measurement Bandwidth = 20 to Fso/2 Hz, and Word Width = 32-Bits, unless otherwise stated.) Parameter Resolution Sample Rate with XTI = 27.000 MHz Sample Rate with other XTI clocks Slave Master Slave Master Sample Rate with ring oscillator (XTI to GND or VL, XTO floating) Sample Rate Ratio - Upsampling Sample Rate Ratio - Downsampling Interchannel Gain Mismatch Interchannel Phase Deviation Peak Idle Channel Noise Component (32-bit operation) Dynamic Range (20 Hz to Fso/2, 1 kHz, -60 dBFS Input) 44.1 kHz:48 kHz A-Weighted Unweighted 44.1 kHz:192 kHz A-Weighted Unweighted 48 kHz:44.1 kHz A-Weighted Unweighted 48 kHz:96 kHz A-Weighted Unweighted 96 kHz:48 kHz A-Weighted Unweighted 192 kHz:32 kHz A-Weighted Unweighted Total Harmonic Distortion + Noise (20 Hz to Fso/2, 1 kHz, 0 dBFS Input) 32 kHz:48 kHz 44.1 kHz:48 kHz 44.1 kHz:192 kHz 48 kHz:44.1 kHz 48 kHz:96 kHz 96 kHz:48 kHz 192 kHz:32 kHz Min 16 7.2 53 XTI/3750 XTI/512 12 - Typ 0.0 0.0 - Max Units 32 bits 207 kHz 211 kHz XTI/130 kHz XTI/128 kHz 96 kHz 1:8 7.5:1 dB Degrees -192 dBFS - 180 177 175 172 180 177 179 176 176 173 175 172 - dB dB dB dB dB dB dB dB dB dB dB dB - -161 -171 -130 -160 -148 -168 -173 - dB dB dB dB dB dB dB DIGITAL FILTER CHARACTERISTICS Parameter Passband (Upsampling or Downsampling) Passband Ripple Stopband Stopband Attenuation Group Delay Min Typ Max Units 0.4535*Fso Hz ±0.007 dB Hz 0.5465*Fso 125 dB (Note 3) ms Notes: 3. The equation for the group delay through the sample rate converter is (56.581 / Fsi) + (55.658 / Fso). For example, if the input sample rate is 192 kHz and the output sample rate is 96 kHz, the group delay through the sample rate converter is (56.581/192,000) + (55.658/96,000) =.875 milliseconds. 6 DS641PP1 CS8421 DC ELECTRICAL CHARACTERISTICS (GND = 0 V; all voltages with respect to 0 V.) Parameters Symbol Min Typ Max Units Power-down Mode (Note 4) Supply Current in power down (Oscillator attached to XTI-XTO) VD VL = 3.3 V VL = 5.0 V - 50 100 200 - µA µA µA Supply Current in power down (Crystal attached to XTI-XTO) VD VL = 3.3 V VL = 5.0 V - 99.9 1.34 3.54 - µA mA mA Supply Current at 48 kHz Fsi and Fso (Oscillator attached to XTI-XTO) VD VL = 3.3 V VL = 5.0 V - 23.1 2.17 3.42 - mA mA mA Supply Current at 192 kHz Fsi and Fso (Oscillator attached to XTI-XTO) VD VL = 3.3 V VL = 5.0 V - 78.7 7.7 12.49 - mA mA mA Supply Current at 48 kHz Fsi and Fso (Crystal attached to XTI-XTO) VD VL = 3.3 V VL = 5.0 V - 23.1 2.92 6.02 - mA mA mA Supply Current at 192 kHz Fsi and Fso (Crystal attached to XTI-XTO) VD VL = 3.3 V VL = 5.0 V - 78.7 3.037 6.25 - mA mA mA Normal Operation (Note 5) Notes: 4. Power Down Mode is defined as RST = LOW with all clocks and data lines held static, except when a crystal is attached across XTI-XTO, in which case the crystal will begin oscillating. 5. Normal operation is defined as RST = HI. DIGITAL INPUT CHARACTERISTICS Symbol Min Typ Max Units Input Leakage Current Parameters Iin - - ±10 µA Input Capacitance Iin - 8 - pF - 250 - mV Input Hysteresis DIGITAL INTERFACE SPECIFICATIONS (GND = 0 V; all voltages with respect to 0 V.) Parameters Symbol Min Max Units High-Level Output Voltage, except MCLK_OUT and SDOUT (IOH=-4 mA) VOH 0.77xVL - V Low-Level Output Voltage, except MCLK_OUT and SDOUT (IOL=4 mA) VOL - .6 V High-Level Output Voltage, MCLK_OUT (IOH=-6 mA) VOH 0.77xVL - V Low-Level Output Voltage, MCLK_OUT (IOL=6 mA) VOL - .6 V High-Level Output Voltage, SDOUT (IOH=-8 mA) VOH 0.77xVL - V Low-Level Output Voltage, SDOUT (IOL=8 mA) VOL - .6 V High-Level Input Voltage VIH 0.55xVL VL+0.3 V Low-Level Input Voltage VIL -0.3 0.8 V DS641PP1 7 CS8421 SWITCHING SPECIFICATIONS (Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF) Parameters Symbol Min Max Units 1 - ms 16.384 1.024 27.000 27.000 MHz MHz 14.8 - ns 45 55 % - 24.576 MHz tlrckh 326 - ns tsckh 9 - ns I/OSCLK Low Time tsckl 9 - ns I/OLRCK Edge to I/OSCLK Rising tlcks 6 - ns OLRCK Rising Edge to OSCLK Rising Edge (TDM) tfss 5 - ns I/OSCLK Rising Edge to I/OLRCK Edge tlckd 5 - ns OSCLK Rising Edge to OLRCK Falling Edge (TDM) tfsh 5 - ns OSCLK Falling Edge/OLRCK Edge to SDOUT Output Valid tdpd - 18 ns SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge tds 3 - ns SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge tdh 5 - ns RST pin Low Pulse Width (Note 6) XTI Frequency (Note 7) Crystal Digital Clock Source XTI Pulse Width High/Low MCLK_OUT Duty Cycle Slave Mode I/OSCLK Frequency OLRCK High Time (Note 8) I/OSCLK High Time tlrckh I/OLRCK (input) tlckd tlcks tsckh OLRCK tsckl (input) tfss tfsh tsckh tsckl I/OSCLK (input) OSCLK tds SDIN (input) tdh tds MSB (input) TDM_IN (input) tdpd SDOUT (output) MSB MSB-1 MSB MSB-1 tdpd MSB MSB-1 SDOUT (output) Figure 1. Non-TDM Slave Mode Timing 8 tdh MSB-1 Figure 2. TDM Slave Mode Timing DS641PP1 CS8421 Parameters Symbol Min Max Units Master Mode (Note 9) I/OSCLK Frequency (non-TDM) 64*Fsi/o MHz OSCLK Frequency (TDM) 256*Fso MHz I/OLRCK Duty Cycle 45 55 % I/OSCLK Duty Cycle 45 55 % I/OSCLK Falling Edge to I/OLRCK Edge tlcks - 5 ns OSCLK Falling Edge to OLRCK Edge (TDM) tfss - 5 ns OSCLK Falling Edge to SDOUT Output Valid tdpd - 7 ns SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge tds 3 - ns SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge tdh 5 - ns Notes: 6. After powering up the CS8421, RST should be held low until the power supplies and clocks are settled. 7. The maximum possible sample rate is XTI/128. 8. OLRCK must remain high for at least 8 OSCLK periods in TDM mode. 9. Only the input or the output serial port can be set as master at a given time. I/OLRCK (output) tlcks OLRCK (output) tfss I/OSCLK (output) OSCLK tds SDIN (output) tdh tds MSB MSB-1 (input) TDM_IN (output) MSB Figure 3. Non-TDM Master Mode Timing DS641PP1 MSB-1 MSB MSB-1 tdpd SDOUT (output) MSB (input) tdpd SDOUT tdh MSB-1 Figure 4. TDM Master Mode Timing 9 CS8421 2. TYPICAL CONNECTION DIAGRAMS +2.5 V +3.3 V or +5.0 V 0.1 µF 0.1 µF VD Serial Audio Source VL ILRCK OLRCK ISCLK OSCLK SDIN SDOUT Serial Audio Input Device TDM_IN MS_SEL CS8421 SAIF XTI Crystal /Clock Source SAOF XTO SRC_UNLOCK BYPASS MCLK_OUT RST * 47 kΩ GND GND ** To external hardware Hardware Control Settings Figure 5. Typical Connection Diagram, Master and Slave Modes * The connection (VL or GND) and value of these three resistors determines the mode of operation for the input and output serial ports as described in Table 1, “Serial Audio Port Master/Slave and Clock Ratio Select Startup Options (MS_SEL)", Table 2, “Serial Audio Input Port Startup Options (SAIF)", and Table 3, “Serial Audio Output Port Startup Options (SAOF)", all on page 13. ** MCLK_OUT pin should be pulled high through a 47 kΩ resistor if an MCLK output is not needed. 10 DS641PP1 CS8421 +2.5 V +3.3 V or +5.0 V 0.1 µF 0.1 µF VD Serial Audio Source VL ILRCK OLRCK ISCLK OSCLK SDIN SDOUT Serial Audio Input Device TDM_IN MS_SEL CS8421 SAIF XTI 1 kΩ * SAOF SRC_UNLOCK BYPASS ** RST GND GND Hardware Control Settings Figure 6. Typical Connection Diagram, No External Master Clock * When no external master clock is supplied to the part, both input and output must be set to salve mode for the part to operate properly. This is done by connecting the MS_SEL pin to ground through a resistance of 0Ω to 1 kΩ ± 1% as stated in Table 1, “Serial Audio Port Master/Slave and Clock Ratio Select Startup Options (MS_SEL),” on page 13 ** The connection (VL or GND) and value of these two resistors determines the mode of operation for the input and output serial ports as described in Table 1, “Serial Audio Port Master/Slave and Clock Ratio Select Startup Options (MS_SEL)", Table 2, “Serial Audio Input Port Startup Options (SAIF)", and Table 3, “Serial Audio Output Port Startup Options (SAOF)", all on page 13. DS641PP1 11 CS8421 3. GENERAL DESCRIPTION The CS8421 is a 32-bit, high performance, monolithic CMOS stereo asynchronous sample rate converter. The digital audio data is input and output through configurable 3-wire serial ports. The digital audio input/output ports offer Left Justified, Right Justified, and I²S serial audio formats. The CS8421 also supports a TDM mode which allows multiple channels of digital audio data on one serial line. A bypass mode allows the data to be passed directly to the output port without sample rate conversion. The CS8421 does not require a control port interface, helping to speed design time by not requiring the user to develop software to configure the part. Pins that are sensed after reset allow the part to be configured. See “Reset, Power Down, and Start-up” on page 32. Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR), digital mixing consoles, high quality D/A, effects processors and computer audio systems. Figure 5 and Figure 6 show the supply and external connections to the CS8421. 4. THREE-WIRE SERIAL INPUT/OUTPUT AUDIO PORT A 3-wire serial audio input/output port is provided. The interface format should be chosen to suit the attached device through the MS_SEL, SAIF, and SAOF pins. Table 1, Table 2, and Table 3 show the pin functions and their corresponding settings. The following parameters are adjustable: • Master or slave. • Master clock (MCLK) ratios of 128*Fsi/o, 256*Fsi/o, 384*Fsi/o, and 512*Fsi/o (Master mode). • Audio data resolution of 16, 20, 24, or 32-bits. • Left or right justification of the data relative to left/right clock (LRCK) as well as I²S. Figure 7, Figure 8, and Figure 9 show the input/output formats available. In master mode, the left/right clock and the serial bit clock are outputs, derived from the XTI input pin master clock. In slave mode, the left/right clock and the serial bit clock are inputs and may be asynchronous to the XTI master clock. The left/right clock should be continuous, but the duty cycle can be less than 50% if enough serial clocks are present in each phase to clock all of the data bits. ISCLK is always set to 64*Fsi when the input is set to master. In normal operation, OSCLK is set to 64*Fso. In TDM slave mode, OSCLK must operate at N*64*Fso, where N is the number of CS8421’s connected together. In TDM master mode, OSCLK is set to 256*Fso 5. MODE SELECTION The CS8421 uses the resistors attached to the MS_SEL, SAIF, and SAOF pins to determine the modes of operation. After reset the resistor value and condition (VL or GND) are sensed. This operation will take approximately 4 µs to complete. The SRC_UNLOCK pin will remain high and the SDOUT pin will be muted until the mode detection sequence has completed. After this, if all clocks are stable, SRC_UNLOCK will be brought low when audio output is valid and normal operation will occur. Table 1, Table 2, and Table 3 show the pin functions and their corresponding settings. If the 1.0 kΩ option is selected for MS_SEL, SAIF, or SAOF, the resistor connected to that pin may be replaced by a direct connection to VL or GND as appropriate. The resistor attached to each mode selection pin should be placed physically close to the CS8421. The end of the resistor not connected to the mode selection pins should be connected as close as possible to VL and GND to minimize noise. Table 1, Table 2, and Table 3 show the pin functions and their corresponding settings. 12 DS641PP1 CS8421 MS_SEL pin 1.0 kΩ ± 1% to GND 1.96 kΩ ± 1% to GND 4.02 kΩ ± 1% to GND 8.06 kΩ ± 1% to GND 16.2 kΩ ± 1% to GND 1.0 kΩ ± 1% to VL 1.96 kΩ ± 1% to VL 4.02 kΩ ± 1% to VL 8.06 kΩ ± 1% to VL Input M/S Slave Slave Slave Slave Slave Master (128 x Fsi) Master (256 x Fsi) Master (384 x Fsi) Master (512 x Fsi) Output M/S Slave Master (128 x Fso) Master (256 x Fso) Master (384 x Fso) Master (512 x Fso) Slave Slave Slave Slave Table 1. Serial Audio Port Master/Slave and Clock Ratio Select Startup Options (MS_SEL) SAIF pin 1.0 kΩ ± 1% to GND 1.96 kΩ ± 1% to GND 4.02 kΩ ± 1% to GND 1.0 kΩ ± 1% to VL 1.96 kΩ ± 1% to VL 4.02 kΩ ± 1% to VL Input Port Configuration I²S up to 32-bit data Left Justified up to 32-bit data Right Justified 16-bit data Right Justified 20-bit data Right Justified 24-bit data Right Justified 32-bit data Table 2. Serial Audio Input Port Startup Options (SAIF) SAOF pin 1.0 kΩ ± 1% to GND 1.96 kΩ ± 1% to GND 4.02 kΩ ± 1% to GND 8.06 kΩ ± 1% to GND 16.2 kΩ ± 1% to GND 32.4 kΩ ± 1% to GND 63.4 kΩ ± 1% to GND 127.0 kΩ ± 1% to GND 1.0 kΩ ± 1% to VL 1.96 kΩ ± 1% to VL 4.02 kΩ ± 1% to VL 8.06 kΩ ± 1% to VL 16.2 kΩ ± 1% to VL 32.4 kΩ ± 1% to VL 63.4 kΩ ± 1% to VL 127.0 kΩ ± 1% to VL Output Port Configuration I²S 16-bit data I²S 20-bit data I²S 24-bit data I²S 32-bit data Left Justified 16-bit data Left Justified 20-bit data Left Justified 24-bit data Left Justified 32-bit data Right Justified 16-bit data Right Justified 20-bit data Right Justified 24-bit data Right Justified 32-bit data TDM Mode 16-bit data TDM Mode 20-bit data TDM Mode 24-bit data TDM Mode 32-bit data Table 3. Serial Audio Output Port Startup Options (SAOF) DS641PP1 13 CS8421 I/OLRCK Channel A Channel B I/OSCLK SDIN SDOUT M SB MSB LSB MSB LSB Figure 7. Serial Audio Interface Format - I²S I/OLRCK Channel A Channel B I/OSCLK SDIN SDOUT M SB LSB MSB LSB MSB Figure 8. Serial Audio Interface Format - Left Justified I/OLRCK Channel A Channel B I/OSCLK SDIN SDOUT MSB Extended MSB LSB MSB LSB MSB Extended MSB LSB MSB LSB Figure 9. Serial Audio Interface Format - Right Justified 14 DS641PP1 CS8421 6. SAMPLE RATE CONVERTER (SRC) Multirate digital signal processing techniques are used to conceptually upsample the incoming data to a very high rate and then downsample to the outgoing rate. The internal data path is 32-bits wide even if a lower bit depth is selected at the output. The filtering is designed so that a full input audio bandwidth of 20 kHz is preserved if the input sample and output sample rates are greater than or equal to 44.1 kHz. When the output sample rate becomes less than the input sample rate, the input is automatically band limited to avoid aliasing products in the output. Careful design ensures minimum ripple and distortion products are added to the incoming signal. The SRC also determines the ratio between the incoming and outgoing sample rates, and sets the filter corner frequencies appropriately. Any jitter in the incoming signal has little impact on the dynamic performance of the rate converter and has no influence on the output clock. 6.1 Clocking In order to ensure proper operation of the CS8421, the clock or crystal attached to XTI must simultaneously satisfy the requirements of LRCK for both the input and output as follows: • If the input is set to master, Fsi ≤ XTI/128 and Fso ≤ XTI/130. • If the output is set to master, Fso ≤ XTI/128 and Fsi ≤ XTI/130. • If both input and output are set to slave, XTI ≥ 130*[minimum(Fsi,Fso)], XTI/Fsi < 3750, and XTI/Fso < 3750. 6.2 Data Resolution and Dither When using the serial audio input port in left justified and I²S modes all input data is treated as 32-bits wide. Any truncation that has been done prior to the CS8421 to less than 32-bits should have been done using an appropriate dithering process. If the serial audio input port is in right justified mode, the input data will be truncated to the bit depth set by SAIF pin setting. If the SAIF bit depth is set to 16, 20, or 24-bits, and the input data is 32-bits wide, then truncation distortion will occur. Similarly, in any serial audio input port mode, if an inadequate number of bit clocks are entered (i.e. 16 clocks instead of 20 clocks), then the input words will be truncated, causing truncation distortion at low levels. In summary, there is no dithering mechanism on the input side of the CS8421, and care must be taken to ensure that no truncation occurs. Dithering is used internally where appropriate inside the SRC block. The output side of the SRC can be set to 16, 20, 24, or 32-bits. Dithering is applied and is automatically scaled to the selected output word length. This dither is not correlated between left and right channels. 6.3 SRC Locking and Varispeed The SRC calculates the ratio between the input sample rate and the output sample rate, and uses this information to set up various parameters inside the SRC block. The SRC takes some time to make this calculation, approximately 4200/Fso (8.75 ms at Fso of 48 kHz). If Fsi is changing, as in a varispeed application, the SRC will track the incoming sample rate. During this tracking mode, the SRC will still rate convert the audio data, but at increased distortion levels. Once the incoming sample rate is stable the SRC will return to normal levels of audio quality. The data buffer in the SRC can overflow if the input sample rate changes at greater than 10%/sec. The SRC_UNLOCK pin is used to indicate when the SRC is not locked. When RST is asserted, or if there is a change in Fsi or Fso, SRC_UNLOCK will be set high. The SRC_UNLOCK pin will continue to be high until the SRC has reacquired lock and settled, at which point it will transition low. When the SRC_UNLOCK pin is set low, SDOUT is outputting valid audio data. This can be used to signal a DAC to unmute its output. DS641PP1 15 CS8421 6.4 Bypass Mode When the BYPASS pin is set high, the input data bypasses the sample rate converter and is sent directly to the serial audio output port. No dithering is performed on the output data. This mode is ideal for passing non-audio data through without a sample rate conversion. ILRCK and OLRCK should be the same sample rate and synchronous in this mode. 6.5 Muting The SDOUT pin is set to all zero output (full mute) immediately after the RST pin is set high. When the output from the SRC becomes valid, though the SRC may not have reached full performance, SDOUT is unmuted over a period of approximately 4096 OLRCK cycles (soft unmuted). When the output becomes invalid, depending on the condition, SDOUT is either immediately set to all zero output (hard muted) or SDOUT is muted over a period of approximately 4096 OLRCK cycles until it reaches full mute (soft muted). The SRC will soft mute SDOUT if there is an illegal ratio between ILRCK and the XTI master clock. Conditions that will cause the SRC to hard mute SDOUT include removing OLRCK, the RST pin being set low, or illegal ratios between OLRCK and the XTI master clock. After all invalid states have been cleared, the SRC will soft unmute SDOUT. 6.6 Group Delay and Phase Matching Between Multiple CS8421 Parts The equation for the group delay through the sample rate converter is shown in “Digital Filter Characteristics” on page 6. This phase delay is equal across multiple parts. Therefore, when multiple parts operate at the same Fsi and Fso and use a common XTI/XTO clock, their output data is phase matched. 16 DS641PP1 CS8421 6.7 Master Clock The CS8421 uses the clock signal supplied through XTI as its master clock (MCLK). MCLK can be supplied from a digital clock source, a crystal oscillator, or a fundamental mode crystal. Figure 10 shows the typical connection diagram for using a fundamental mode crystal. Please refer to the crystal manufacturer’s specifications for the external capacitor recommendations. If XTO is not used, such as with a digital clock source or crystal oscillator, XTO should be left unconnected or pulled low through a 47 kΩ resistor to GND. If either serial audio port is set as master, MCLK will be used to supply the sub-clocks to the master SCLK and LRCK. In this case MCLK will be synchronous to the master serial audio port. If both serial audio ports are set as slave, MCLK can be asynchronous to either or both ports. If the user needs to change the clock source to XTI while the CS8421 is still powered on and running, a RESET must be issued once the XTI clock source is present and valid to ensure proper operation. When both serial ports are configured as slave and operating at sample rates less than 96 kHz, the CS8421 has the ability to operate without a master clock input through XTI. This benefits the design by not requiring extra external clock components (lowering production cost) and not requiring a master clock to be routed to the CS8421, resulting in lowered noise contribution in the system. In this mode, an internal oscillator provides the clock to run all of the internal logic. To enable the internal oscillator simply tie XTI to GND or VL. In this mode, XTO should be left unconnected. The CS8421 can also provide a buffered MCLK output through the MCLK_OUT pin. This pin can be used to supply MCLK to other system components that operate synchronously to MCLK. If MCLK_OUT is not needed, the output of the pin can be disabled by pulling the pin high through a 47 kΩ resistor to VL. MCLK_OUT is also disabled when using the internal oscillator mode. The MCLK_OUT pin will be set low when disabled by using the internal oscillator mode. XTI XTO R C C Figure 10. Typical Connection Diagram for Crystal Circuit DS641PP1 17 CS8421 6.8 Time Division Multiplexing (TDM) Mode TDM mode allows several CS8421 to be serially connected together allowing their corresponding SDOUT data to be multiplexed onto one line for input into a DSP or other TDM capable multichannel device. The CS8421 can operate in two TDM modes. The first mode consists of all of the CS8421’s output ports set to slave as shown in Figure 13. The second mode consists of one CS8421 output port set to master and the remaining CS8421’s output ports set to slave as shown in Figure 14. The TDM_IN pin is used to input the data while the SDOUT pin is used to output the data. The first CS8421 in the chain should have its TDM_IN set to GND. Data is transmitted from SDOUT most significant bit first on the first OSCLK after an OLRCK transition and is valid on the rising edge of OSCLK. In TDM slave mode, the number of channels that can by multiplexed to one serial data line depends on the output sampling rate. For slave mode, OSCLK must operate at N*64*Fso, where N is the number of CS8421’s connected together. The maximum allowable OSCLK frequency is 24.576 MHz, so for Fso = 48 kHz, N = 8 (16 channels of serial audio data). In TDM master mode, OSCLK operates at 256*Fso, which is equivalent to N = 4, so a maximum of 8 channels of digital audio can be multiplexed together. Note that for TDM master mode, MCLK must be at least 256*Fso, where Fso ≤ 96 kHz. OLRCK identifies the start of a new frame. Each time slot is 32-bits wide, with the valid data sample left justified within the time slot. Valid data lengths are 16, 20, 24 or 32-bits. Figure 11 and Figure 12 show the interface format for master and slave TDM modes. OLRCK OSCLK SDOUT/ TDM_IN MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB Channel1 Channel2 Channel3 Channel4 Channel5 Channel6 Channel7 Channel8 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks Figure 11. TDM Slave Mode Timing Diagram 256 clks OLRCK OSCLK SDOUT/ TDM_IN MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB Channel1 Channel2 Channel3 Channel4 Channel5 Channel6 Channel7 Channel8 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks Figure 12. TDM Master Mode Timing Diagram 18 DS641PP1 CS8421 Output Clock Source LRCK SCLK CS8421 TDM_IN CS8421 SDIN OLRCK OSCLK DSP OLRCK OLRCK OLRCK LRCK OSCLK OSCLK OSCLK SCLK SDOUT SDIN TDM_IN SDOUT ILRCK ISCLK CS8421 TDM_IN SDOUT ILRCK ILRCK Phase Master / Slave 0 SDOUT Slave 1 Slave n OSCLK Slave SDIN SDIN OLRCK PCM Source 0 ISCLK ISCLK SDOUT OLRCK PCM Source 1 OSCLK SDOUT PCM Source n Figure 13. TDM Mode Configuration (All CS8421 outputs are slave) CS8421 TDM_IN CS8421 SDIN OLRCK OSCLK SDOUT PCM Source 0 DSP OLRCK OLRCK OLRCK LRCK OSCLK OSCLK OSCLK SCLK SDOUT SDIN SDOUT TDM_IN ILRCK ISCLK CS8421 TDM_IN SDOUT ILRCK ILRCK Clock and Phase Master ISCLK ISCLK Slave 0 Slave n OLRCK OSCLK SDOUT PCM Source 1 Slave SDIN SDIN OLRCK OSCLK SDOUT PCM Source n Figure 14. TDM Mode Configuration (First CS8421 output is master, all others are slave) DS641PP1 19 CS8421 7. PIN DESCRIPTIONS XTO 1 20 SRC_UNLOCK XTI 2 19 SAIF VD 3 18 SAOF GND 4 17 VL RST 5 16 GND BYPASS 6 15 MS_SEL ILRCK 7 14 OLRCK ISCLK 8 13 OSCLK 12 SDOUT 11 TDM_IN 9 SDIN XTI XTO SRC_UNLOCK SAIF SAOF 10 MCLK_OUT 20 Top-Down View 20-pin TSSOP Package 20 19 18 17 16 2 14 GND RST 3 Thermal Pad 13 MS_SEL BYPASS 4 Top-Down View 20-pin QFN Package 12 OLRCK ILRCK 5 11 OSCLK 6 7 8 9 10 SDOUT GND TDM_IN VL MCLK_OUT 15 SDIN 1 ISCLK VD DS641PP1 CS8421 7.1 TSSOP PIN DESCRIPTIONS PIN XTO 1 Crystal Out (Output) - Crystal output for Master clock. See “Master Clock” on page 17. XTI 2 Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “Master Clock” on page 17. VD 3 Digital Power (Input) - Digital core power supply. Typically +2.5 V. GND 4 Ground (Input) - Ground for I/O and core logic. RST 5 Reset (Input) - When RST is low the CS8421 enters a low power mode and all internal states are reset. On initial power up RST must be held low until the power supply is stable and all input clocks are stable in frequency and phase. BYPASS 6 Sample Rate Converter Bypass (Input) - When BYPASS is high, the sample rate converter will be bypassed and any data input through the serial audio input port will be directly output on the serial audio output port. When Bypass is low the sample rate converter will operate normally. ILRCK 7 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin. ISCLK 8 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin. SDIN 9 Serial Audio Input Data Port (Input) - Audio data serial input pin. MCLK_OUT 10 Master Clock Output (Output) - Buffered and level shifted output for Master clock. If MCLK_OUT is not required, this pin should be pulled high through a 47 kΩ resistor to turn the output off. See “Master Clock” on page 17. TDM_IN 11 Serial Audio TDM Input (Input) - Time Division Multiplexing serial audio data input. Grounded when not used. See “Time Division Multiplexing (TDM) Mode” on page 18 SDOUT 12 Serial Audio Output Data Port (Output) - Audio data serial output pin. Optionally this pin may be pulled low through a 47 kΩ resistor, but should not be pulled high. OSCLK 13 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin. OLRCK 14 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT pin. MS_SEL 15 Master/Slave Select (Input) - Used to select Master or Slave for the input and output serial audio ports at startup and reset. See Table 1 on page 13 for format settings. GND 16 Ground (Input) - Ground for I/O and core logic. VL 17 Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V. SAOF 18 Serial Audio Output Format Select (Input) - Used to select the serial audio output format at startup and reset. See Table 3 on page 13 for format settings. SAIF 19 Serial Audio Input Format Select (Input) - Used to select the serial audio input format at startup and reset. See Table 2 on page 13 for format settings. SRC_UNLOCK 20 SRC Unlock Indicator (Output) - Indicates when the SRC is unlocked. See “SRC Locking and Varispeed” on page 15. Table 4. TSSOP Pin Descriptions DS641PP1 21 CS8421 7.2 QFN PIN DESCRIPTIONS PIN VD 1 Digital Power (Input) - Digital core power supply. Typically +2.5 V. GND 2 Ground (Input) - Ground for I/O and core logic. RST 3 Reset (Input) - When RST is low the CS8421 enters a low power mode and all internal states are reset. On initial power up RST must be held low until the power supply is stable and all input clocks are stable in frequency and phase. BYPASS 4 Sample Rate Converter Bypass (Input) - When BYPASS is high, the sample rate converter will be bypassed and any data input through the serial audio input port will be directly output on the serial audio output port. When Bypass is low the sample rate converter will operate normally. ILRCK 5 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin. ISCLK 6 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin. SDIN 7 Serial Audio Input Data Port (Input) - Audio data serial input pin. MCLK_OUT 8 Master Clock Output (Output) - Buffered and level shifted output for Master clock. If MCLK_OUT is not required, this pin should be pulled high through a 47 kΩ resistor to turn the output off. See “Master Clock” on page 17. TDM_IN 9 Serial Audio TDM Input (Input) - Time Division Multiplexing serial audio data input. Grounded when not used. See “Time Division Multiplexing (TDM) Mode” on page 18 SDOUT 10 Serial Audio Output Data Port (Output) - Audio data serial output pin. Optionally this pin may be pulled low through a 47 kΩ resistor, but should not be pulled high. OSCLK 11 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin. OLRCK 12 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT pin. MS_SEL 13 Master/Slave Select (Input) - Used to select Master or Slave for the input and output serial audio ports at startup and reset. See Table 1 on page 13 for format settings. GND 14 Ground (Input) - Ground for I/O and core logic. VL 15 Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V. SAOF 16 Serial Audio Output Format Select (Input) - Used to select the serial audio output format at startup and reset. See Table 3 on page 13 for format settings. SAIF 17 Serial Audio Input Format Select (Input) - Used to select the serial audio input format at startup and reset. See Table 2 on page 13 for format settings. SRC_UNLOCK 18 SRC Unlock Indicator (Output) - Indicates when the SRC is unlocked. See “SRC Locking and Varispeed” on page 15. XTO 19 Crystal Out (Output) - Crystal output for Master clock. See “Master Clock” on page 17. XTI 20 Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “Master Clock” on page 17. THERMAL PAD - Thermal Pad - Thermal relief pad for optimized heat dissipation. Table 5. QFN Pin Descriptions 22 DS641PP1 CS8421 8. PERFORMANCE PLOTS d B F S +0 +0 -20 -20 -40 -40 -60 -60 -80 d B F S -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 -200 5k 10k 15k -200 20k 20k 40k Figure 15a. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:48 kHz d B F S +0 -20 -20 -40 -40 -60 -60 -80 d B F S -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 5k 10k 15k -200 20k 2.5k 5k 7.5k 10k Hz +0 -20 -20 -40 -40 -60 -60 -80 d B F S -100 -120 -120 -140 -160 -180 -180 -200 30k 40k Hz Figure 17a. Wideband FFT Plot (1Fsi6k Points) 0 dBFS 1 kHz Tone, 48 kHz:96 kHz DS641PP1 20k -100 -160 20k 17.5k -80 -140 10k 15k Figure 16b. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:44.1 kHz +0 -200 12.5k Hz Figure 16a. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 44.1 kHz:48 kHz d B F S 80k Figure 15b. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 44.1 kHz:192 kHz +0 -200 60k Hz Hz 5k 10k 15k 20k Hz Figure 17b. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 96 kHz:48 kHz 23 CS8421 +0 -60 -20 -40 -80 -60 d B F S -100 -80 d B F S -100 -120 -140 -120 -140 -160 -160 -180 -180 -200 5k 10k 15k -200 20k 10k 20k Figure 18a. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 192 kHz:48 kHz -60 -60 -80 -80 -100 d B F S -120 -140 -120 -140 -160 -160 -180 -180 -200 5k 10k 15k -200 20k 20k 40k Hz -60 -80 -80 -100 -100 d B F S -120 -140 -120 -140 -160 -160 -180 -180 5k 10k 15k 20k Hz Figure 20a. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 44.1 kHz:48 kHz 24 80k Figure 19b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 44.1 kHz:192 kHz -60 -200 60k Hz Figure 19a. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:48 kHz d B F S 40k Figure 18b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:96 kHz -100 d B F S 30k Hz Hz -200 2.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k Hz Figure 20b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:44.1 kHz DS641PP1 CS8421 +0 -60 -20 -80 -40 -60 -100 d B F S d B F S -120 -140 -80 -100 -120 -140 -160 -160 -180 -200 -180 5k 10k 15k -200 20k 5k 10k Hz 15k 20k Hz Figure 21b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 96 kHz:48 kHz Figure 21b. IMD, 10 kHz and 11 kHz -7 dBFS, 96 kHz:48 kHz +0 -60 -20 -40 -80 -60 -100 d B F S d B F S -120 -140 -80 -100 -120 -140 -160 -160 -180 -200 -180 5k 10k 15k -200 20k 2.5k 5k 7.5k 10k Figure 22a. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 192 kHz:48 kHz d B F S +0 +0 -20 -40 -40 -60 -60 -80 d B F S -100 -120 -120 -160 -160 -180 -180 15k 20k Hz Figure 23a. IMD, 10 kHz and 11 kHz -7 dBFS, 44.1 kHz:48 kHz DS641PP1 20k -80 -140 10k 17.5k -100 -140 5k 15k Figure 22b. IMD, 10 kHz and 11 kHz -7 dBFS, 48 kHz:44.1 kHz -20 -200 12.5k Hz Hz -200 5k 10k 15k 20k Hz Figure 23b. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 44.1 kHz:48 kHz 25 CS8421 d B F S +0 +0 -20 -20 -40 -40 -60 -60 -80 d B F S -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 -200 20k 40k 60k -200 80k 10k 20k Figure 24a. Wideband FFT Plot (16k Points) 0 dBFS 80 kHz Tone, 192 kHz:192 kHz d B F S +0 -20 -20 -40 -40 -60 -60 -80 d B F S -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 5k 10k 40k Figure 24b. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:96 kHz +0 -200 30k Hz Hz 15k -200 20k 5k 10k Hz 15k 20k Hz Figure 25a. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:48 kHz Figure 25b. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 96 kHz:48 kHz -120 +0 -122.5 -20 -125 -40 -127.5 -60 d B F S -130 -80 d B F S -100 -120 -132.5 -135 -137.5 -140 -140 -142.5 -160 -145 -180 -200 -147.5 2.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k Hz Figure 26a. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:44.1 kHz 26 -150 50k 75k 100k 125k 150k 175k Hz Figure 26b. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 192 kHz DS641PP1 CS8421 -120 -120 -122.5 -122.5 -125 -125 -127.5 -127.5 -130 d B F S -130 -132.5 d B F S -135 -137.5 -132.5 -135 -137.5 -140 -140 -142.5 -142.5 -145 -145 -147.5 -147.5 -150 50k 75k 100k 125k 150k -150 175k 50k 75k 100k 125k 150k 175k Hz Hz Figure 27a. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 48 kHz Figure 27b. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 96 kHz -120 -135 -122.5 -136 -125 -137 -127.5 -138 -130 d B F S -132.5 d B F S -135 -137.5 -140 -139 -140 -141 -142 -142.5 -143 -145 -144 -147.5 -150 50k 75k 100k 125k 150k -145 175k 50k 75k 100k Hz Figure 28a. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 44.1 kHz -120 -120 -122.5 -122.5 -125 -125 -127.5 -127.5 d B F S -135 -137.5 -132.5 -135 -137.5 -140 -140 -142.5 -142.5 -145 -145 -147.5 -147.5 -150 50k 75k 100k 125k 150k 175k Hz Figure 29a. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 32 kHz DS641PP1 175k -130 -132.5 -150 150k Figure 28b. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 192 kHz -130 d B F S 125k Hz 50k 75k 100k 125k 150k 175k Hz Figure 29b. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 32 kHz 27 CS8421 d B F S -120 -120 -122.5 -122.5 -125 -125 -127.5 -127.5 -130 -130 -132.5 -132.5 d B F S -135 -137.5 -135 -137.5 -140 -140 -142.5 -142.5 -145 -145 -147.5 -147.5 -150 50k 75k 100k 125k 150k -150 175k 50k 75k 100k Hz 125k 150k 175k Hz Figure 30a. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 96 kHz Figure 30b. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 44.1 kHz +0 +0 -0.02 -20 -0.04 -40 d B F S -0.06 192 kHz:48 kHz -60 d B F S 192 kHz:96 kHz -80 -100 -0.08 -0.1 -0.12 -0.14 192 kHz:32 kHz -0.16 -120 -0.18 -140 0 10k 20k 30k 40k 50k -0.2 0 60k 5k 10k 15k 20k 25k Hz Hz Figure 31b. Passband Ripple, 192 kHz:48 kHz Figure 31a. Frequency Response with 0 dBFS Input -120 +0 -122.5 d B F S -10 -125 -20 -127.5 -30 -130 -40 -50 -132.5 d B F S -135 -137.5 -60 -70 -80 -90 -140 -100 -142.5 -110 -145 -120 -147.5 -150 -130 50k 75k 100k 125k 150k 175k Hz Figure 32a. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 48 kHz 28 -140 -140 -120 -100 -80 -60 -40 -20 +0 dBFS Figure 32b. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:48 kHz DS641PP1 CS8421 +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 d B F S d B F S -60 -70 -80 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 -120 -100 -80 -60 -40 -20 -140 -140 +0 -120 -100 -80 Figure 33a. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:44.1 kHz +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -70 -80 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -120 -100 -80 -60 -40 -20 -140 -140 +0 -120 -100 -80 -40 -20 +0 Figure 34b. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:192 kHz +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 d B F S -60 -70 -80 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -120 -100 -80 -60 -40 -20 +0 dBFS Figure 35a. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:48 kHz DS641PP1 -60 dBFS Figure 34a. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 96 kHz:48 kHz -140 -140 +0 -60 dBFS d B F S -20 -50 d B F S -60 -140 -140 -40 Figure 33b. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:96 kHz -50 d B F S -60 dBFS dBFS -140 -140 -120 -100 -80 -60 -40 -20 +0 dBFS Figure 35b. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 192 kHz:44.1 kHz 29 CS8421 -110 -110 -115 -115 -120 -120 -125 -125 -130 -130 -135 -135 d B F S -140 d B F S -145 -150 -140 -145 -150 -155 -155 -160 -160 -165 -165 -170 -170 -175 -175 -180 -140 -120 -100 -80 -60 -40 -20 -180 -140 +0 -120 -100 -80 dBFS -110 -110 -115 -115 -120 -120 -125 -125 -130 -130 -140 d B F S -145 -150 -145 -150 -155 -155 -160 -160 -165 -165 -170 -170 -175 -175 -120 -100 -80 -60 -40 -20 -180 -140 +0 -120 -100 -80 -40 -20 +0 Figure 37b. THD+N vs. Input Amplitude, 1 kHz Tone, 44.1 kHz:192 kHz -110 -110 -115 -115 -120 -120 -125 -125 -130 -130 -135 -135 -140 d B F S -145 -150 -140 -145 -150 -155 -155 -160 -160 -165 -165 -170 -170 -175 -175 -120 -100 -80 -60 -40 -20 dBFS Figure 38a. THD+N vs. Input Amplitude, 1 kHz Tone, 44.1 kHz:48 kHz 30 -60 dBFS Figure 37a. THD+N vs. Input Amplitude, 1 kHz Tone, 96 kHz:48 kHz -180 -140 +0 -140 dBFS d B F S -20 -135 -135 -180 -140 -40 Figure 36b. THD+N vs. Input Amplitude, 1 kHz Tone, 48 kHz:96 kHz Figure 36a. THD+N vs. Input Amplitude, 1 kHz Tone, 48 kHz:44.1 kHz d B F S -60 dBFS +0 -180 -140 -120 -100 -80 -60 -40 -20 +0 dBFS Figure 38b. THD+N vs. Input Amplitude, 1 kHz Tone, 192 kHz:48 kHz DS641PP1 CS8421 -110 -110 -115 -115 -120 -120 -125 -125 -130 -130 -135 -135 d B F S -140 d B F S -145 -150 -140 -145 -150 -155 -155 -160 -160 -165 -165 -170 -170 -175 -175 -180 0 -180 2.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k -140 -120 -100 Figure 39a. THD+N vs. Frequency Input, 0 dBFS, 48 kHz:44.1 kHz -110 -110 -115 -115 -120 -120 -125 -125 -130 -130 -40 -20 +0 -135 -140 d B F S -145 -150 -140 -145 -150 -155 -155 -160 -160 -165 -165 -170 -170 -175 -175 -180 0 -60 Figure 39b. THD+N vs. Frequency Input, 0 dBFS, 48 kHz:96 kHz -135 d B F S -80 dBFS Hz 2.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k Hz Figure 40a. THD+N vs. Frequency Input, 0 dBFS, 44.1 kHz:48 kHz -180 0 2.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k Hz Figure 40b. THD+N vs. Frequency Input, 0 dBFS, 96 kHz:48 kHz All performance plots represent typical performance. Measurements for all performance plots were taken under the following conditions, unless otherwise stated: • VD = 2.5 V, VL = 3.3 V • Serial Audio Input port set to slave • Serial Audio Output port set to slave • Input and output clocks and data are asynchronous • XTI/XTO = 27 MHz • Input signal = 1.000 kHz, 0 dBFS • Measurement Bandwidth = 20 to (Fso/2) Hz • Word Width = 24 Bits DS641PP1 31 CS8421 9. APPLICATIONS 9.1 Reset, Power Down, and Start-up When RST is low the CS8421 enters a low power mode, all internal states are reset, and the outputs are disabled. After RST transitions from low to high the part senses the resistor value on the configuration pins (MS_SEL, SAIF, and SAOF) and sets the appropriate mode of operation. After the mode has been set (approximately 4 µs) the part is set to normal operation and all outputs are functional. 9.2 Power Supply, Grounding, and PCB layout The CS8421 operates from a VD = +2.5 V and VL = +3.3 V or +5.0 V supply. These supplies may be set independently. Follow normal supply decoupling practices, see Figure 5. Extensive use of power and ground planes, ground plane fill in unused areas, and surface mount decoupling capacitors are recommended. Decoupling capacitors should be mounted on the same side of the board as the CS8421 to minimize inductance effects and all decoupling capacitors should be as close to the CS8421 as possible. The pin of the configuration resistors not connected to MS_SEL, SAIF, and SAOF should be connected as close as possible to VL or GND. 32 DS641PP1 CS8421 10. PACKAGE DIMENSIONS 20L TSSOP (4.4 mm BODY) PACKAGE DRAWING N D E11 A2 E A ∝ A1 b2 e END VIEW L SIDE VIEW SEATING PLANE 1 2 3 TOP VIEW INCHES DIM A A1 A2 b D E E1 e L ∝ MIN -0.002 0.03346 0.00748 0.252 0.248 0.169 -0.020 0° NOM -0.004 0.0354 0.0096 0.256 0.2519 0.1732 -0.024 4° MILLIMETERS MAX 0.043 0.006 0.037 0.012 0.259 0.256 0.177 0.026 0.028 8° MIN -0.05 0.85 0.19 6.40 6.30 4.30 -0.50 0° NOM --0.90 0.245 6.50 6.40 4.40 -0.60 4° NOTE MAX 1.10 0.15 0.95 0.30 6.60 6.50 4.50 0.65 0.70 8° 2,3 1 1 JEDEC #: MO-153 Controlling Dimension is Millimeters. Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. THERMAL CHARACTERISTICS Parameter Junction to Ambient Thermal Impedance DS641PP1 2 Layer Board 4 Layer Board Symbol Min Typ Max Units θJA - 48 38 - °C/Watt °C/Watt 33 CS8421 20-PIN QFN (5 × 5 MM BODY) PACKAGE DRAWING b D Pin #1 Corner e Pin #1 Corner E2 E A1 D2 L A Top View Side View Bottom View INCHES DIM A A1 b D D2 E E2 e L MIN -0.0000 0.0091 0.1201 0.1202 0.0197 NOM --0.0110 0.1969 BSC 0.1220 0.1969 BSC 0.1221 0.0256 BSC 0.0236 MILLIMETERS MAX 0.0394 0.0020 0.0130 MIN -0.00 0.23 0.1240 3.05 0.1241 3.05 0.0276 0.50 NOM --0.28 5.00 BSC 3.10 5.00 BSC 3.10 0.65 BSC 0.60 NOTE MAX 1.00 0.05 0.33 3.15 3.15 0.70 1 1 1,2 1 1 1 1 1 1 JEDEC #: MO-220 Controlling Dimension is Millimeters. Notes: 1. Dimensioning and tolerance per ASME Y 14.5M-1995. 2. Dimensioning lead width applies to the plated terminal and is measured between 0.23mm and 0.33mm from the terminal tip. THERMAL CHARACTERISTICS Parameter Junction to Ambient Thermal Impedance 34 2 Layer Board 4 Layer Board Symbol Min Typ Max Units θJA - 131 38 - °C/Watt °C/Watt DS641PP1 CS8421 11. REVISION HISTORY Release A1 PP1 Date July 2004 January 2005 Changes Initial Advance Release -Updated “Features” on page 1. -Updated “Sample Rate with other XTI clocks” on page 6. -Updated “DC Electrical Characteristics” on page 7. -Updated “Digital Input Characteristics” on page 7. -Updated “Digital Interface Specifications” on page 7 -Updated Figure 5. “Typical Connection Diagram, Master and Slave Modes” on page 10. -Added Figure 6. “Typical Connection Diagram, No External Master Clock” on page 11. -Corrected reference to bypass mode to output only data on page 12. -Added section 6.1, “Clocking” on page 15. -Updated “Master Clock” on page 17. -Updated “Time Division Multiplexing (TDM) Mode” on page 18. -Added Thermal Pad label “Pin Descriptions” on page 20. -Added Thermal Pad pin description to “QFN Pin Descriptions” on page 22. -Updated “Performance Plots” beginning on page 23. Table 6. Revision History DS641PP1 35 CS8421 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IIMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. 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