CMLMICRO FX619M1

CML Semiconductor Products
PRODUCT INFORMATION
FX619 'Eurocom' Delta Codec
Publication D/619/6 September 1997
Features/Applications
On-Chip Input and Output Filters
Designed to Meet Eurocom D1-IA8f
Meets Stanag 4209 and
Stanag 4380
Military Communications
Delta MUX, Switch and Phone
Applications
Programmable Sampling Clocks
3 or 4-bit Compand Algorithm
Forced Idle Facility
Powersave Facility
Single 5V CMOS Process
Single Chip Full Duplex Codec
Full Duplex CVSD* Codec
DATA ENABLE
ENCODER FORCE IDLE
ENCODER INPUT
MOD
VDD
ENCODER OUTPUT
V SS
f1
XTAL/CLOCK
f2
f0
XTAL
CLOCK RATE
ENCODER DATA CLOCK
DECODER DATA CLOCK
VBIAS
MODE 1
CLOCK MODE
MODE 2
LOGIC
ALGORITHM
POWERSAVE
FX619
GENERATORS
SAMPLING RATE
CONTROL
3 or 4-BIT
f3
f1
DECODER INPUT
DEMOD
DECODER OUTPUT
DECODER FORCE IDLE
Fig.1 Internal Block Diagram
Brief Description
The FX619 is an LSI circuit designed as a
*Continuously Variable Slope Delta Codec and
is intended for use in military communications
systems.
Designed to meet Eurocom D1-IA8 with
external components, the device is suitable for
applications in military Delta Multiplexers,
switches and phones.
Encoder input and decoder output filters are
incorporated on-chip. Sampling clock rates can
be programmed to 16, 32 or 64 k bits/second
from an internal clock generator or may be
externally applied in the range 8 to 64 k bits/
second. Sampling clock frequencies are output
for the synchronization of external circuits.
6.1
The encoder has an enable function for use in
multiplexer applications. Encoder and Decoder
forced idle facilities are provided forcing a
10101010..... pattern in encode and a VDD/2
bias in decode. The companding circuits may
be operated with a 3 or 4-bit algorithm which is
externally selected. The device may be put in
the standby mode by selection of the
powersave facility. A reference 1.024MHz
oscillator uses an external clock or Xtal.
The FX619 is a low-power, 5 volt CMOS
device and is available in 22-pin cerdip DIL,
24-lead/pin plastic and 28-lead ceramic
leadless SMT packages.
Pin Number
Function
FX619 FX619 FX619
J
L1/L2 M1
1
1
1
Xtal/Clock : Input to the clock oscillator inverter. A 1.024MHz Xtal input or externally
derived clock is injected here. See Clock Mode pins and Figure 3.
2
2
No connection
2
3
3
Xtal : Output of clock oscillator inverter. Xtal circuitry shown is in accordance with CML
application note D/XT/1 April 1986.
3
4
4
No connection
4
5
5
Encoder Data Clock : A logic I/O port. External encode clock input or internal data clock
output. Clock frequency is dependant upon clock mode 1, 2 inputs and Xtal frequency (see
Clock Mode pins).
5
6
6
Encoder Output : The encoder digital output, this is a three state output whose condition is
set by Data Enable and Powersave inputs as shown :
Data Enable
1
0
1
7, 8
Powersave
1
1
0
Encoder Output
Enabled
High Z (o/c)
Vss
No connection
6
7
9
Encoder Force Idle : When this pin is a logical '0' the encoder is forced to an idle state and
the encoder digital output is 0101..., a perfect idle pattern. When this pin is a logical '1' the
encoder encodes as normal. Internal 1MΩ Pullup.
7
8
10
Data Enable : Data is made available at the encoder output pin by control of this input. See
Encoder Output pin. Internal 1MΩ Pullup.
8
9
11
No connection
9
10
12
Bias : Normally at VDD /2 bias, this pin requires to be externally decoupled by a capacitor,
C4. Internally pulled to VSS when "Powersave" is a logical '0'.
10
11
13
Encoder Input : The analogue signal input. Internally biased at VDD /2, external
components are required on this input. The source impedance should be less than 100Ω,
output idle channel noise levels will improve with an even lower source impedance. See
Fig. 3.
11
12
14
VSS : Negative Supply.
2
Pin Number
Function
FX619 FX619 FX619
J
L1/L2 M1
12
13
15,16
13
14
17
14
15
18,19
15
16
20
Powersave : A logical '0' at this pin puts most parts of the codec into a quiescent nonoperational state. When at a logical '1' the codec operates normally. Internal 1MΩ Pullup.
17
21
No connection
16
18
22
Decoder Force Idle : A logical '0' at this pin gates a 0101...pattern internally to the
decoder so that the decoder output goes to VDD/2. When this pin is at a logical '1' the
decoder operates as normal. Internal 1MΩ Pullup.
17
19
23
Decoder Input : The received digital signal input. Internal 1MΩ Pullup.
18
20
24
Decoder Data Clock : A Logic I/O port. External decode clock input or internal data clock
output, dependant upon clock mode 1, 2 inputs, see Clock Mode pins.
19
21
25
Algorithm : A logical '1' at this pin sets this device for a 3-bit companding algorithm. A
logical '0' sets a 4-bit companding algorithm. Internal 1MΩ Pullup.
20
22
26
Clock Mode 2 :
21
23
27
Clock Mode 1 :
Internal 1MΩ
Pullups.
No connection
Decoder Output : The recovered analogue signal is output at this pin, it is the buffered
output of a bandpass filter and requires external components. During "Powersave" this
output is o/c.
No connection
Clock Mode 1
0
0
1
1
Clock Mode 2
0
1
0
1
Facility
External clocks
Internal, 64kb/s = f ÷ 16
Internal, 32kb/s = f ÷ 32
Internal, 16kb/s = f ÷ 64
Clock rates refer to f = 1.024 MHz Xtal/clock input. During internal operation the data
clock frequencies are available at the ports for external circuit synchronization.
Independant or common data rate inputs to Encode and Decode data clock ports may be
employed in the External Clocks mode.
22
24
28
VDD : Positive Supply. A single + 5 volt power supply is required.
3
Codec Integration
FX619 PARAMETERS
MEASURED HERE
EUROCOM
ANALOGUE
INPUT
INTERFACE
(BALUN
&
BUFFER)
EUROCOM
INPUT
FX619
ENCODER
DATA
FX619
DECODER
CLOCK MODE
CLOCKS
1.024 MHz
FX619 PARAMETERS
MEASURED HERE
REGULATED POWER
SUPPLY
16/32/64kb/s
EUROCOM
ANALOGUE
OUTPUT
INTERFACE
(BALUN
&
BUFFER)
EUROCOM
OUTPUT
DATA
CLOCKS
SYNCHRONOUS CLOCK
AND
DATA SYSTEM
1.024 MHz
Fig.2 Eurocom System Configuration – showing the FX619, which with the indicated interfacing, will conform to
the Eurocom Basic Parameters Specification D1 – IA8.
Component
Unit Value
R1
R2
C1
C2
C3
Note – with reference to Figure 3 (below)
1M
Selectable
33p
33p
1.0µ
C4
C5
X1
Oscillator Inverter bias resistor.
Xtal Drive limiting resistor.
Xtal Circuit drain capacitor.
Xtal Circuit gate capacitor.
Encoder Input coupling capacitor – The drive source impedance to this
input should be less than 100Ω. Output Idle channel noise levels will
improve with an even lower source impedance.
Bias decoupling capacitor.
VDD decoupling capacitor.
A 1.024 MHz Xtal/clock input will yield exactly 16/32/64 kb/s data clock
rates. Xtal circuitry shown is in accordance with CML application note
D/XT/1 April 1986.
Tolerance :– Resistors ± 10% Capacitors ± 20%
1.0µ
1.0µ
1.024 MHz
VDD
XTAL/CLOCK
X1
C2
C1
22
XTAL
2
21
N/C
3
20
4
19
ENCODER OUTPUT
5
18
ENCODER FORCE IDLE
6
R2
ENCODER DATA CLOCK
DATA ENABLE
N/C
BIAS
ENCODER INPUT
C3
C4
VDD
1
R1
CLOCK MODE 2
ALGORITHM
FX619J
DECODER DATA CLOCK
DECODER INPUT
17
DECODER FORCE IDLE
7
16
8
15
9
14
10
13
11
12
POWERSAVE
N/C
DECODER OUTPUT
VSS
Fig.3 Recommended External Components
CLOCK MODE 1
V SS
4
N/C
C5
Codec Timing Information
ENCODER TIMING
TIMING
ENCODER
CLOCK
t
CH
t
t CL
t IF
DATA CLOCKED
tCH Clock '1' Pulse
Width
1.0µs Min.
CH
t IR
tCL Clock '0' Pulse
Width
1.0µs Min.
ENCODER DATA
OUTPUT
t PCO
tIR Clock Rise Time
100ns Typ.
DECODER TIMING
tIF Clock Fall Time
100ns Typ.
DECODER
CLOCK
tSU Data Set-up Time
450ns Min.
DATA CLOCKED
tH Data Hold Time
600ns Min.
DECODER DATA
INPUT
t SU
tSU + tH Data True
Time.
tH
tPCO Clock to Output
Delay time
750ns Max.
DATA TRUE TIME
MULTIPLEXING FUNCTION
ENCODER
OUTPUT
tDR Data Rise Time
100ns Typ.
HIGH Z
HIGH Z
t DR
tDF Data Fall Time
100ns Typ.
t DF
Xtal Input Frequency
1.024MHz.
DATA ENABLE
Fig.4 Codec Timing Diagrams
Codec Performance ...... Using the Bit Sequence Tests (a to g) at the Decoder Input pin in accordance with
the Eurocom Specification D1 – IA8, the decoder output is as shown in Table 1.
MLA
Duty cycle
Typical
Output
Level
10110100100100101101
1011011010101001001001001001010101101101
0
0
- 41.5dBm0
- 42.0dBm0
16kbit/s
32kbits
11011001001001001101
1011011010101001001000100100101011011011
0.05
0.05
- 25.0dBm0
- 25.0dBm0
c.
16kbits
32kbit/s
10110101000100101011
1101101101010010001000100100101011011101
0.1
0.1
- 19.0dBm0
- 18.5dBm0
d.
16kbit/s
32kbit/s
11011001000010011011
1101110110010100010000100010011010111011
0.2
0.2
- 11.0dBm0
- 11.5dBm0
e.
16kbit/s
32kbit/s
11011010000010010111
1110111011001000100000010001001101110111
0.3
0.3
- 6.5dBm0
- 6.5dBm0
f.
16kbit/s
32kbit/s
11011010000001001111
1111011101010001000000001000101011101111
0.4
0.4
- 3.0dBm0
- 3.0dBm0
g.
16kbit/s
32kbit/s
11101010000000101111
1111101110100010000000000100010111011111
0.5
0.5
0dBm0
0dBm0
Test
Sample Rate
a.
16kbit/s
32kbit/s
b.
Bit Sequence at Decoder Input
Table 1 Bit Sequence Test Table
5
3
3
2
2
Attenuation (dB)
Attenuation (dB)
Codec Performance ...... relative to the Eurocom Specification D1 - IA8
1
0
-1
Ref: 0dBm0 Input Level = 489mVrms
Input Frequency = 820Hz
-2
-3
- 40
- 30
- 20
- 10
0
Ref: 0dBm0 Input Level = 489mVrms
Input Frequency = 820Hz
-1
-2
-3
ref.
- 50
1
0
10
ref.
- 50
- 40
Input Level (dBm0)
- 20
- 10
0
10
Input Level (dBm0)
Fig.6 Gain vs Input Level (32kbit/s)
Fig.5 Gain vs Input Level (16kbit/s)
20
- 30
Ref: 0dBm0 Input Level = 489mVrms
Input Frequency = 820Hz
Ref: 0dBm0 Input Level = 489mVrms
Input Frequency = 820Hz
S/N Ratio (dB)
S/N Ratio (dB)
25
15
20
10
8
15
- 40
- 30
- 20
- 10
- 40
0
- 30
- 20
- 10
0
Input Level (dBm0)
Input Level (dBm0)
Fig.8 S/N vs Input Level (32kbit/s)
Fig.7 S/N vs Input Level (16kbit/s)
+ 10
1.5
0
1.5
- 10
Gain (dB)
Input Level = -20dBm0
- 20
- 30
- 40
- 50
- 60
0
0.3
1
2
2.6
3
4
5
6
Frequency (kHz)
Fig.9 Attenuation Distortion vs Frequency (16kbit/s)
6
Codec Performance ...... relative to the Eurocom Specification D1 - IA8
30
Input Level = -20dBm0
Input Level = -20dBm0
20
15
S/N Ratio (dB)
S/N Ratio (dB)
25
10
20
15
10
5
5
0
1
2
3
0
1
Input Frequency (kHz)
2
3
Input Frequency (kHz)
Fig.11 S/N vs Input Frequency (32kbit/s)
Fig.10 S/N vs Input Frequency (16kbit/s)
Amplitude of test
signal (g) - Table 1.
1.0
0
Amplitude
0.9
Amplitude (dB)
-6
- 12
- 6dB/octave
- 18
0.397
- 24
0.1
- 30
0.00794
10
100
1k
Beginning of
discharge
Amplitude of
test signal (a)
8.76
10k
5.76
Frequency (Hz)
Time (ms)
Fig.12 Principal Integrator Response
Fig.13 Compand Envelope
+ 10
2
0
3
- 10
Gain (dB)
Input Level = -20dBm0
- 20
- 30
- 40
- 50
- 60
0
0.3
1
2
1.4
2.6
3
3.4
4
5
6
Frequency (kHz)
Fig.14 Attenuation Distortion vs Frequency (32kbit/s)
7
Specifications
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is
not implied.
Supply voltage
-0.3 to 7.0V
Input voltage at any pin (ref VSS = 0V)
-0.3 to (VDD + 0.3V)
Source/sink current (supply pins)
± 30mA
(other pins)
± 20mA
Total device dissipation @ 25°C
800mW Max.
Derating (J and M1 packages)
10mW/°C
Derating (L1 and L2 packages)
13mW/°C
Operating temperature range: FX619J
-40°C to +85°C (cerdip)
FX619L1/L2
-40°C to +85°C (plastic)
FX619M1
-40°C to +85°C (cerquad)
Storage temperature range:
FX619J
-55°C to +125°C (cerdip)
FX619L1/L2
-40°C to +85°C (plastic)
FX619M1
-55°C to +125°C (cerquad)
Operating Limits
All characteristics are measured using the following parameters unless otherwise specified:
VDD = 5.0V, TAMB = 25°C, Xtal/Clock f0 = 1.024MHz, Audio Level 0dB ref (0dBm0) = 489 mV rms.
Audio Test Frequency = 820 Hz. Sample Clock Rate = 32kb/s. Compand Algorithm = 3-bit.
Characteristics
See Note
Min.
Typ.
Max.
Static Values
Supply Voltage
1
4.5
5.0
5.5
Supply Current (Enabled)
–
4.5
–
Supply Current (Powersave)
–
1.0
–
Inputs Logic '1'
8
3.5
–
–
Inputs Logic '0'
8
–
–
1.5
Outputs Logic '1'
8
4.0
–
–
Outputs Logic '0'
8
–
–
1.0
Digital Input Impedance
(Logic I/O pins)
1.0
10
–
Digital Input Impedance
(Logic input pins, pullup resistor)
2
300
–
–
Digital Output Impedance
–
–
4
Analogue Input Impedance
4
1
–
Analogue Output Impedance
7
–
–
800
Three State Output Leakage
Current (output disabled)
-4
–
+4
Insertion Loss
3
-2
–
+2
Dynamic Values
1
Encoder:
Analogue Signal Input Levels
5,9
-35
–
+6
Principle Integrator Frequency
–
275
–
Encoder Passband
3400
Compand Time Constant
–
4
–
Decoder:
Analogue Signal Output Levels
5,9
-35
–
+6
Decoder Passband
300
–
3400
Encoder Decoder (Full codec):
Compression Ratio (Cd = 0.5 to Cd = 0.0)
–
50
–
Passband
300
–
3400
Stopband
6
–
10
Stopband Attenuation
–
60
–
Passband Gain
–
0
–
Passband Ripple (300Hz –1400Hz)
-1
–
+1
(1400Hz – 2600Hz)
-1
–
+3
(2600Hz – 3400Hz)
-2
–
+3
Output Noise (Input short circuit)
9
–
–
-62
Perfect Idle Channel Noise (Encoder forced) 9
–
-63
–
Group Delay Distortion
6
(1000Hz to 2600Hz)
–
–
450
(600Hz to 2800Hz)
–
–
750
(500Hz to 3000Hz)
–
–
1.5
Xtal/Clock Frequency
500
1024
1500
– Notes to be used with these specifications are detailed on page 9 (overleaf)
8
Unit
V
mA
mA
V
V
V
V
MΩ
kΩ
kΩ
kΩ
Ω
µA
dB
dBm0
Hz
Hz
ms
dBm0
Hz
Hz
kHz
dB
dB
dB
dB
dB
dBm0p
dBm0p
µs
µs
ms
kHz
››››
Specifications ......
Notes: 1. Dynamic characteristics are specified at 5V unless otherwise specified.
2. All logic inputs except, Encoder and Decoder Data Clocks.
3. For an Encoder/Decoder combination, Insertion Loss contributed by a single component is half this
figure.
4. Driven with a source impedance of <100Ω.
5. Recommended values – See Figures 5, 6, 7 and 8.
6 Group Delay Distortion for the full codec is relative to the delay with 820Hz, -20dB at the encoder input.
7. An Emitter Follower output stage.
8. 4V = 80% VDD, 3.5V = 70% VDD, 1.5V = 30% VDD, 1V = 20% VDD.
9. Analogue Voltage Levels used in this Data Sheet: 0dBm0 = 489mVrms = - 4dBm = 0dB.
- 20dBm0 = 49mVrms = - 24dBm.
Process Information
The following Table gives details of the process and test controls employed in the manufacture of the FX619
Eurocom Delta Codec in J and M1 packages only. L1 and L2 products are supplied without the process and test
controls detailed below.
Function
Reference
Remarks
Hermeticity
Fine Leak Test –
Coarse Leak Test –
Mil Std 883C
Mil Std 883C
using Method 1014 – test condition A1.
using Method 1014 – test condition C.
Burnin
Mil Std 883C
using Method 1015 – test condition E.
168 Hours @ 85°C with 5v power, and clocks applied.
Temperature Cycling
Mil Std 883C
using Method 1010 – test condition B.
10 cycles -55°C to +125°C.
The following mechanical assembly tests are Qualified to BS9450
Vibration
BS9450
Shock
BS9450
Low Pressure
Transport and Storage –
Operation –
Humidity
BS9450
BS9450
Section 1.2.6.8.1
55Hz to 500Hz at 98 m/sec acceleration.
Section 1.2.6.6
981 m/sec for 6 msec.
Section 1.2.6.12
225mmHg (altitude 9000m).
600mmHg (altitude 2400m).
Section 1.2.6.4
96 Hours @ 45°C, 95% relative humidity plus condensed
water.
Application Recommendations
Due to the very low levels of signal and idle channel noise specified in the Eurocom Basic Parameters Specification
D1 – IA8 – a noisy or badly regulated power supply could cause instability putting the overall system performance
out of specification. Adherence to the points noted below will assist in minimizing this problem.
(a)
Care should be taken on the design and layout of
the printed circuit board.
(e)
Inputs and outputs should be screened wherever
possible.
(b)
All external components (as recommended in
Figure 3) should be kept close to the package.
(f)
A "ground plane" connected to VSS will assist in
eliminating external pick-up on the input and output
pins.
(c)
Tracks should be kept short, particularly the
Encoder Input capacitor and the VBIAS capacitor.
(g)
It is recommended that the power supply rails
have less than 1mVrms of noise allowed.
(d)
Xtal/clock tracks should be kept well away from
analogue inputs and outputs.
(h)
The source impedance to the Encoder Input pin
must be less than 100Ω, Output Idle channel noise
levels will improve with even lower source impedances.
9
Package Outlines
Handling Precautions
The FX619 is available in the package styles outlined
below. Mechanical package diagrams and specifications
are detailed in Section 10 of this document.
Pin 1 identification marking is shown on the relevant
diagram and pins on all package styles number
anti-clockwise when viewed from the top.
The FX619 is a CMOS LSI circuit which includes input
protection. However precautions should be taken to
prevent static discharges which may cause damage.
FX619J
FX619L1
22-pin cerdip DIL
(J3)
NOT TO SCALE
NOT TO SCALE
Max. Body Length
Max. Body Width
FX619L2
24-pin quad plastic encapsulated
bent and cropped
(LG)
24-pin plastic leaded chip
carrier
Max. Body Length
Max. Body Width
27.38mm
9.75mm
10.25mm
10.25mm
FX619M1 28-lead ceramic leaded chip
carrier
(M1)
(LS)
NOT TO SCALE
NOT TO SCALE
Max. Body Length
Max. Body Width
Max. Body Length
Max. Body Width
10.40mm
10.40mm
11.60mm
11.60mm
Ordering Information
FX619J 22-pin cerdip DIL
(J3)
FX619L1 24-pin quad plastic encapsulated
bent and cropped
(LG)
FX619L2 24-pin plastic leaded chip carrier
(LS)
FX619M1 28-lead ceramic leaded chip
carrier
(M1)
CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied
and CML reserves the right at any time without notice to change the said circuitry.
10
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor
companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc
(USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst
maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA)
Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits.
These companies are all 100% owned operating companies of the CML Microsystems Plc
Group and these changes are purely changes of name and do not change any underlying legal
entities and hence will have no effect on any agreements or contacts currently in force.
CML Microcircuits Product Prefix Codes
Until the latter part of 1996, the differentiator between products manufactured and sold from
MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX
respectively. These products use the same silicon etc. and today still carry the same prefixes.
In the latter part of 1996, both companies adopted the common prefix: CMX.
This notification is relevant product information to which it is attached.
Company contact information is as below:
CML Microcircuits
(UK)Ltd
CML Microcircuits
(USA) Inc.
CML Microcircuits
(Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon,
Essex, CM9 6WG, England
Tel: +44 (0)1621 875500
Fax: +44 (0)1621 875600
uk.sales@cmlmicro.com
www.cmlmicro.com
4800 Bethania Station Road,
Winston-Salem, NC 27105, USA
Tel: +1 336 744 5050,
0800 638 5577
Fax: +1 336 744 5054
us.sales@cmlmicro.com
www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/
06 Mactech Industrial Building,
Singapore 349307
Tel: +65 7450426
Fax: +65 7452917
sg.sales@cmlmicro.com
www.cmlmicro.com
D/CML (D)/1 February 2002