CMLMICRO MX805AJ

MX805A
COMMUNICATION SEMICONDUCTORS
Sub-Audio Signaling
Processor
DATA BULLETIN
Features
•
•
•
•
•
•
•
Non-predictive CTCSS Tone Decoder
DCS Sub-Audio Signal demodulator
CTCSS /NRZ Encoder with TX level
adjustment and lowpass filter output
stage with optional NRZ pre-emphasis
RX LPF
RX SUB-AUDIO
OUT
COMPARATOR
OUT
IN
RX SUB-AUDIO
IN
+
DIGITAL
NOISE
FILTER
_
180Hz/260Hz
Selectable Sub-Audio bandstop filter
NoTone (CTCSS RX) period timer
Low Power Operation
Member of DBS800 Family (C-BUS
Compatible)
FREQUENCY
ASSESMENT
NOTONE
NOTONE
TIMER
COMPARATOR
AMP
AMP OUT
COMMAND DATA
RAW NRZ DATA
REPLY DATA
NRZ RX
DATA AND
BAUD RATE
EXTRACTOR
+
AMP IN
_
RX AMP
NRZ RX
BAUD RATE
NRZ
RX DATA
VDD
FREQUENCY
MEASUREMENT
CLOCK
GENERATOR
DATA BUFFER
AND
SHIFT REGISTER
SERIAL CLOCK
WAKE
ADDRESS SELECT
NRZ
TX DATA
VARIABLE
BANDWIDTH
CTCSS SUBAUDIO FREQUENCY
XTAL
VSS
INTERRUPT
AND
TX
XTAL/
CLOCK
CHIP SELECT
CONTROL
LOGIC
RX
VBIAS
C-BUS
INTERFACE
TX SUB-AUDIO
OUT
TX LEVEL
ADJUST
SUB-AUDIO BANDSTOP
TX SUB-AUDIO LPF
AUDIO IN
AUDIO OUT
AUDIO SIGNAL PATH
AUDIO BYPASS
The MX805A is a sub-audio frequency signaling processor that provides outband audio and digital signaling
capability for LMR systems. Designed for the transmission and non-predictive reception of Continuous Tone
Controlled Squelch (CTCSS) tones and other non-standard frequencies, the MX805A also handles NonTM
Return-to Zero (NRZ) data reception and transmission to provide Digitally Coded Squelch (DCS/DPL ) and
TM
LTR signaling.
Setting the MX805A functions and modes is accomplished by data loaded from the microcontroller to the
controlling registers within the device. Reply Data and Interrupt protocol keep the microcontroller up to date
on the operational status of the circuitry. CTCSS tone data for transmission is generated in the
microcontroller, loaded to the CTCSS TX Frequency Register, encoded and output as a tone via the TX Subaudio LPF. Received non-predicted CTCSS tone frequencies are measured and the resulting data, in the
form of a 2-byte data word, is presented to the microcontroller for matching against a lookup table. Noise
filtering is provided to improve the signal quality prior to measurement. NRZ coded data streams for
transmission, when generated within a microcontroller, are loaded to the NRZ TX Data Buffer and output, in
8-bit bytes, through the lowpass filter circuitry as subaudible signals. DCS turnoff tones can be added to the
data signals by switching the MX805A to the CTCSS transmit mode at the appropriate time. NRZ coding is
produced by the microcontroller and translated to subaudio signals by the MX805A. Received NRZ data is
filtered, detected, and placed into the NRZ Data Register, which is then available for transfer (one byte at a
time) to the microcontroller for decoding by software. Clock extraction circuitry is provided on-chip. TX ad RX
baud rates are selectable.
Hardware and software are designed to allow consecutive addressing of two MX805A Sub-Audio Signaling
Processors to achieve multi-mode duplex operation. Powersaving may be controlled by software or by an
input dedicated to the purpose.
The MX805A may be used with a 5.0V power supply and is available in the following packages:
24-pin SOIC (MX805ADW), 24-pin PLCC (MX805ALH), and 24-pin PDIP (MX805AP).
ã2001 MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Doc. # 20480116.005
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Sub-Audio Signaling Processor
Page 2 of 24
MX805A
Contents
Section
Page
1 Block Diagram ............................................................................................................... 4
2 Signal List ...................................................................................................................... 5
3 External Components ................................................................................................... 7
3.1
Input configurations............................................................................................................ 8
3.1.1
Using and External Op-Amp...................................................................................................... 8
4 General Description ...................................................................................................... 9
4.1
4.2
Glossary ............................................................................................................................ 9
Operating Modes ............................................................................................................... 9
4.2.1
NRZ Encoding ........................................................................................................................... 9
4.2.2
CTCSS Encoding ...................................................................................................................... 9
4.2.3
NRZ Decoding ......................................................................................................................... 10
4.2.4
CTCSS Decoding .................................................................................................................... 10
5 Controlling Protocol ................................................................................................... 10
5.1
5.2
MX805A Internal Registers .............................................................................................. 10
5.1.1
Control Register (70H/78H)..................................................................................................... 10
5.1.2
Status Register (71H/79H) ...................................................................................................... 10
5.1.3
CTCSS Rx Frequency Register (72H/7AH) ............................................................................ 10
5.1.4
CTCSS Tx Frequency/NRZ Tx or Rx Baud Rate Register (73H/7BH) ................................... 10
5.1.5
NRZ Rx Data Register (74H/7CH) .......................................................................................... 10
5.1.6
NRZ Tx Data Register (75H/7DH)........................................................................................... 10
5.1.7
Gain Set Register (76H/7EH) .................................................................................................. 10
Address/Commands ........................................................................................................ 11
5.2.1
Write to Control Register - A/C 70H (78H) followed by 1 byte of Command Data.................. 12
5.2.2
General Reset ......................................................................................................................... 12
5.2.3
Read Status Register –A/C 71H (79H) followed by 1 byte of Rely Data. ............................... 13
5.2.4
Read CTCSS RX Frequency Register –A/C 72H (7AH) followed by 2 bytes of Reply Data .. 13
5.2.5
Write to CTCSS TX Frequency/NRZ Baud Data Rate Register –A/C 73H (7BH) followed
by 2 bytes of Command Data.................................................................................................. 15
5.2.6
Read NRZ RX Data Register – A/C 74H (7CH) followed by 1 byte Reply Data ..................... 17
5.2.7
Write to NRZ TX Data Register – A/C 75H (7DH) followed by 1 byte of Command Data. ..... 17
5.2.8
Write to Gain Set Register – A/C 76H (7EH) followed by 1 byte of Command Data .............. 17
ã2001 MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
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Doc. # 20480116.005
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Sub-Audio Signaling Processor
Page 3 of 24
MX805A
6 Performance Specifications ....................................................................................... 18
6.1
Electrical Specifications ................................................................................................... 18
6.1.1
Absolute Maximum Limits .............................................................................................................. 18
6.1.2
Operating Limits............................................................................................................................. 18
6.1.3
Operating Characteristics .............................................................................................................. 19
6.1.4
Timing ............................................................................................................................................ 22
6.2
Packages......................................................................................................................... 23
MXCOM, Inc. reserves the right to change specifications at any time without notice.
ã2001 MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Doc. # 20480116.005
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Sub-Audio Signaling Processor
Page 4 of 24
MX805A
1 Block Diagram
RX LPF
RX SUB-AUDIO
OUT
COMPARATOR
OUT
IN
RX SUB-AUDIO
IN
+
DIGITAL
NOISE
FILTER
_
180Hz/260Hz
FREQUENCY
ASSESMENT
NOTONE
NOTONE
TIMER
COMPARATOR
AMP
AMP OUT
COMMAND DATA
RAW NRZ DATA
REPLY DATA
NRZ RX
DATA AND
BAUD RATE
EXTRACTOR
+
AMP IN
_
RX AMP
NRZ RX
BAUD RATE
NRZ
RX DATA
VDD
FREQUENCY
MEASUREMENT
CHIP SELECT
INTERRUPT
AND
SERIAL CLOCK
CONTROL
LOGIC
RX
VBIAS
C-BUS
INTERFACE
WAKE
TX
XTAL/
CLOCK
DATA BUFFER
AND
SHIFT REGISTER
CLOCK
GENERATOR
ADDRESS SELECT
NRZ
TX DATA
VARIABLE
BANDWIDTH
CTCSS SUBAUDIO FREQUENCY
XTAL
VSS
TX SUB-AUDIO
OUT
TX LEVEL
ADJUST
SUB-AUDIO BANDSTOP
TX SUB-AUDIO LPF
AUDIO IN
AUDIO OUT
AUDIO SIGNAL PATH
AUDIO BYPASS
Figure 1: Block Diagram
ã2001 MX-COM, Inc.
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Sub-Audio Signaling Processor
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MX805A
2 Signal List
Pin
Signal
Description
The output from the on-chip clock oscillator inverter. External components are
required at this input when a Xtal input is used. See Figure 2.
The input to the clock oscillator inverter. A Xtal or externally derived clock should
be connected here.
This input enables two MX805A’s to be used on the same C-BUS to provide dullduplex operation. See Table 4 and Table 5.
1
Xtal
2
Xtal/Clock
3
Address Select
4
IRQ
5
Serial Clock
6
Command Data
7
CS
Chip Select . This is the ‘C-BUS’ data loading control function. This input is
provided by the microcontroller. Data transfer sequences are initiated, completed
or aborted by the CS signal. See Timing diagrams.
8
Reply Data
9
TX Sub-Audio Out
10
Audio In
11
Audio Out
12
VSS
13
RX Amp In (-)
14
RX Amp In (+)
15
RX Amp Out
16
RX Sub-Audio In
17
RX Sub-Audio Out
18
VBIAS
19
Comparator In (-)
20
Comparator In (+)
This is the ‘C-BUS’ serial data output to the microcontroller. The transmission of
Reply Data bytes is synchronized to the Serial Clock under the control of the CS
input. This 3-state output is held at high impedance when not sending data to the
microcontroller. See Timing Diagrams
This is the subaudio output (pure or NRZ derived). Signals are band limited. The
TX Output Filter had a variable bandwidth (See Table 9). This output is at VBIAS
(a) when the NRZ Encoder is enabled but no data is being transmitted, (b) when
the MX805A is placed in the Powersave All condition.
This is the input to the switched sub-audio bandstop (highpass) filter. It is
internally biased, and should be AC coupled by capacitor C7.
This is the output of the audio signal path (filter or bandpass). It is controlled by
the Control Register. When disabled, the pin is held at VBIAS.
Negative Supply (GND)
This is the inverting input to the on-chip RX Input Amp. (See Figure 2, Figure 3,
and Figure 4).
This is the non-inverting input to the on-chip RX Input Amp.
This is the output of the on-chip RX Input Op-Amp. This circuit may be used, with
external components, as a signal amplifier and anti-aliasing filter prior to the RX
Lowpass Filter, or for other purposes. See Figure 2 for Component details.
This is the received Sub-Audio (CTCSS/NRZ) input. It is internally referenced to
VBIAS. This signal to this pin should be AC coupled or biased. See Figure 2.
This is the output of the RX lowpass filter. It may be coupled into the on-chip
amplifier or comparator as required.
The internal circuitry bias line, held at VDD/2. This pin must be decoupled to VSS
by capacitor C8. See Figure 2.
This is the inverting input to the on-chip ‘comparator’ amplifier. See Figure 2,
Figure 3, and Figure 4.
This is the non-inverting input to the on-chip ‘comparator’ amplifier. See Figure 2,
Figure 3, and Figure 4.
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Interrupt Request . The output of this pin indicates an interrupt condition to the
microcontroller by going to a logic ‘0”. This ‘wire-or-able’ output allows the
connection of up to 8 peripherals to 1 interrupt port on the microcontroller. This
pin has a low impedance pulldown to logic ‘0’ when active, and a high impedance
when inactive. The system IRQ line requires 1 pull-up resistor to VDD. The
conditions that cause interrupts are indicated in the Table 5 and Table 7.
This is the ‘C-BUS’ serial Clock input. This clock, produced by the
microcontroller, is used for transfer timing of commands and data to and from the
MX805A. See timing diagrams.
This is the ‘C-BUS’ serial data input from the microcontroller. Data is loaded to
this device in 8-bit bytes, MSB (bit 7) first and LSB (bit 0) last, synchronized to the
Serial Clock. See Timing diagrams.
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Sub-Audio Signaling Processor
Pin
Page 6 of 24
Signal
21
Comparator Out
22
Notone Timing
23
Wake
MX805A
Description
This is the output of the ‘comparator’ amplifier. This node is also connected
internally to the input of the /digital Noise Filter (See Figure 1). When both
decoders (CTCSS or NRZ) are powersaved, this output is at a logic ‘0’.
External RC components connected to this pin form the timing mechanism of a
Notone period timer. The external network determines the “charge rate” of the
timer to VBIAS. The expiration of the timer will cause an interrupt. This function is
only used in the CTCSS RX mode. See page 9.
This ‘real time’ input can be used to reactivate the MX805A from the ‘Powersave
All’ condition using an externally derived signal. The MX805A will be in
‘Powersave All’ condition when both this pin and bit 0 of the Control Register are
set to a logic ‘1’. Recovery from ‘Powersave All’ is achieved by putting either the
Wake pin or the ‘Powersave All” bit at logic ‘0’. This allows MX805A activation by
the microcontroller or an external signal, such as RSSI or Carrier Detect.
24 VDD
Positive Supply. A single 5.0V regulated supply is required.
Note: More information on external components and the DBS800 system integration of the MX805A are
contained in the DBS800 System Support Documentation. Guidance on the generation and
manipulation of NRZ and RX and TX data is given in the DBS800 Application support documentation.
C-BUS: This is MX-COM’s proprietary standard for the transmission of commands and data between a
microcontroller and DBS8000 microcircuits. It may be used with any microcontroller, and can, if
desired, take advantage of the hardware and serial I/O functions embodied into many types of
microcontroller. The C-BUS data rate is determined by the microcontroller.
Table 1: Signal List
RX CTCSS Tone Measurement Completed
CTCSS NOTONE Timer Expired
1 NRZ RX Data Byte Received
New NRZ Data Received Before Last Byte Read
NRZ TX Buffer Ready
NRZ Data Transmission Complete
Table 2: Interrupt Conditions
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Sub-Audio Signaling Processor
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MX805A
3 External Components
VDD
+
R7
SEE INSET
XTAL
XTAL/CLOCK
ADDRESS SELECT
IRQ
SERIAL CLOCK
COMMAND DATA
CS
REPLY DATA
R8
TX SUB-AUDIO OUT
C7
AUDIO IN
AUDIO OUT
VSS
1
2
3
4
5
6
7
8
9
10
11
12
MX805AJ
24
23
22
21
20
19
18
17
16
15
14
13
C5
R6
V DD
WAKE
C6
NOTONE
+
COMPARATOR OUT
R4
C8
COMPARATOR IN (+)
COMPARATOR IN (-)
VBIAS
RX SUB-AUDIO OUT
C3
RX SUB-AUDIO IN
R3
D1
D2
RX AMP OUT
RX AMP IN (+)
RX AMP IN (-)
R2
+
R5
C4
INSET
XTAL
1
X1
MX805AJ
R1
XTAL/CLOCK
C2
2
C1
Figure 2: Recommended External Components
Component
Notes
Value
Tolerance
Component
Value
Tolerance
R1
5
1.0MΩ
±5%
C3
1.5µF
±20%
R2
4
360kΩ
±5%
C4
15.0µF,
6V Tant.
±20%
R3
1
10.0kΩ
±5%
C5
1.0µF,
10V Tant.
±20%
R4
4
150kΩ
±5%
C6
1.0µF,
10V Tant.
±20%
R5
4
100kΩ
±5%
C7
0.1µF,
25V x 7R
±20%
150kΩ
±5%
C8
1.0µF
R6
R7
6
22.0kΩ
±5%
R8
2
360kΩ
±5%
C1
C2
5
5
Notes
D1
8
D2
X1
8
4.00MHz
Table 3: Recommended External Components
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MX805A
Recommended External Component Notes:
1. Xtal/Clock circuitry shown in inset are recommended in accordance with the MX-COM’s “Standard and
DBS 800 Crystal Oscillators” application note.
2. Resistor R8 is a System Component. Its value is chosen together with the MX806A Modulation Summing
Amplifier to provide a subaudio signal level of –11.0dB to the system modulator.
3. Figure 3 and Figure 4 illustrate alternative input component configurations.
4. The values for R2 and R5 are dependent on the input signal level. Values given are for the specified
composite signal (reference page 14). R4 add hysteresis to the comparator and is not always required.
5. The values used for C1 and C2 are determined by the frequency of X1.
C1 = C2 = 33pF for X1 < 5.0MHz
As a guide:
C1 = C2 = 18pF for X1 > 5.0MHz
If the on-chip Xtal oscillator is to be used, then the external components X1, C1, C2, and R1 are required
as shown in Figure 2 (inset). If an external clock source is used these components are not required; the
input should be connected to the Xtal/Clock pin and the Xtal pin unconnected.
6. Resistor R7 is used as the DBS800 system common pull-up for the C-BUS Interrupt Request ( IRQ ) line.
The optimum value of this component will depend upon the circuitry connected to the IRQ line.
7. The level at this point should be approximately 900mVP-P.
8. Silicon small signal
3.1
Input Configurations
Figure 3 shows an input configuration that is generally for use for CTCSS signal and NRZ data reception.
Input coupling capacitor C3 is required because the RX Sub-Audio Input is held at VBIAS during all powered
conditions of the MX805A. Diodes D1 and D2 can be any silicon small signal diode.
The output resistance (open loop) of the on-chip Rx Amp is = 6kΩ. In the configuration shown in Figure 3, the
(Rx Amp) RC time constant is therefore 90ms. If this period is too long for some systems, i.e. those using half
duplex, short data burst, and external amplifier should be considered in place of the on-chip Rx Amp.
MX805A
RX AMP
MX805A
RX LPF
17
D.C. RESTORATION
+
14
MX805A
COMPARATOR
RX AMP IN
13
16
C3
HYSTERESIS (OPTIONAL)
NOTE 7
15
_
R4
R3
D1
D2
R2
20
+
COMPARATOR IN
RX SUB-AUDIO
INPUT
19
R5
21
_
C4
COMPARATOR
OUT
Figure 3: MX805A Input Components
3.1.1
Using and External Op-Amp
For DC coupling the MX805A to the receiver’s discriminator output when using burst mode NRZ
communication, it is recommended that an additional, external Op-Amp is employed as configured in
Figure 4. This configuration will quickly compensate for sudden shift of DC input bas.
Components R9, R10, and R11, should be calculated to provide an accurate potential of 2.5VDC (equal to
VBIAS) at pin junction 15/16when using a discriminator input and 900mVP-P at the output of the external opamp. Note that the MX805A LPF has a 6dB gain. If additional filtering is required, C9 should be used, it
should be calculated with R9 to provide a lowpass cutoff frequency (fCO) of 500Hz.
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Sub-Audio Signaling Processor
Page 9 of 24
MX805A RX LPF
Gain = 6dB
FROM RX
DISCRIMINATOR
MX805A
RX AMP
+
14
MX805A
16
RX AMP IN
15
17
+
EXTERNAL
OP-AMP
NOTE 6
(see p.4)
_
13
_
MX805A
COMPARATOR
R3
C9
D2
270k
D1
20
R9
19
100k
VDD
+
COMPARATOR IN
21
_
15 mF
COMPARATOR
OUT
R11
R10
D.C. RESTORATION
LEVEL SHIFT AND AMPLIFY
Figure 4: MX805A Input Components using and External Op-Amp
4 General Description
4.1
Glossary
DCS
CTCSS
TM
DPL
TM
LTR
NRZ
fCO
fCTCSS IN
fCTCSS OUT
fTONE
fXTAL
RNRZRX
RNRZTX
sINPUT
4.2
4.2.1
Continuous Digitally Coded Squelch
Continuous Tone Controlled Sub-Audio Squelch
Digital Private Line
Logic Trunked Radio
Non-Return-to-Zero
Filter Cutoff frequency
Sub-Audio Rx frequency
Sub-Audio Tx frequency
Tone frequency
Xtal/Clock frequency
NRZ RX baud rate
NRZ TX baud rate
Audio input signal.
Operating Modes
NRZ Encoding
The NRZ Encoder is formed by a shift register and the TX Sub-Audio Lowpass Filter. Data loaded from the
Command Data line is output one 8-bit byte at a time from the NRZ Tx Data Register. The output data level
may be adjusted and filtered. Data may be pre-emphasized via a C-BUS command. The expected Rx baud
rate is programmed as the NRZ Tx Baud Rate (RNRZTX). See Table 8
4.2.2
CTCSS Encoding
The CTCSS Tone Encoder is comprised of a clock divider programmed by an 11-bit binary number (Q)
loaded to the CTCSS Tx Frequency Register (See Table 8) via the C-BUS Command Data line.
The square-wave output of the encoder is fed through the Tx Level Adjust variable gain block to the Tx
Sub-Audio lowpass filter, a variable gain bandwidth circuit controlled by 4-bits (P) if the CTCSS Tx Frequency
Register. The Tx Sub-Audio output is a sine-wave. Standard and nonstandard sub-audio tones are available.
A CDCS turnoff tone may also be generated.
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4.2.3
Page 10 of 24
MX805A
NRZ Decoding
Input (NRZ type) sub-audio signals are filtered and the data clock extracted. Decoded data is serially loaded
into a shift register buffer. This data is output on 8-bit byte at a time as Reply Data from the NRZ Rx Data
Register to the microcontroller. The expected Rx baud rate is programmed as the NRZ Rx Baud Rate
(RNRZRX). See Table 8. Any codeword recognition can be carried out by software.
4.2.4
CTCSS Decoding
Received CTCSS signals are filtered, and coherence is increased by the digital noise filter. The quality of the
signal is assessed by measurement of the cycle–to-cycle period variance and, provided it is sufficiently good,
the frequency is measured over a period of 122.64ms (4.0MHz crystal).
If the average signal quality is consistently too low, NoTone is indicated; if not the input frequency is precisely
indicated in the CTCSS Rx Frequency Register in a binary form.
Any single sub-audio tone within the specified range may be selected, enabling a DCS turnoff tone of 134Hz)
to be decoded while in the NRZ Rx mode.
5 Controlling Protocol
Control of the MX805A Sub-Audio Signaling Processor’s operation is by communications between the
microcontroller and the MX805A internal registers on the C-BUS, using Address/Commands (A/Cs) and
appended instructions or data (See Figure 10). The use and content of these instructions is detailed in the
following paragraphs and tables. The Address Select Input enables the addressing of 2 separate MX805As
on the C-BUS to provide full-duplex signaling.
5.1
5.1.1
MX805A Internal Registers
Control Register (70H/78H)
Write only, control and configuration of the MX805A.
5.1.2
Status Register (71H/79H)
Read only, reporting of device functions.
5.1.3
CTCSS Rx Frequency Register (72H/7AH)
Read only, a 2-byte binary word indicating the frequency of the received sub-audio input.
5.1.4
CTCSS Tx Frequency/NRZ Tx or Rx Baud Rate Register (73H/7BH)
Write only, a 2-byte command to set the relevant parameters.
5.1.5
NRZ Rx Data Register (74H/7CH)
Read only, a single byte f received NRZ data.
5.1.6
NRZ Tx Data Register (75H/7DH)
Write only, to load a single byte of NRZ data for transmission.
5.1.7
Gain Set Register (76H/7EH)
Write only, a single byte to set the gain of the Tx Lowpass Filter.
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Sub-Audio Signaling Processor
5.2
Page 11 of 24
MX805A
Address/Commands
The first byte of a loaded data sequence is always recognized by the C-BUS as an Address/Command (A/C)
byte. Instruction and data transactions to and from this device consist of an Address/Command byte followed
by either:
(i) further instructions or data
(ii) a Status or data Reply
Instructions and data are loaded and transferred, via C-BUS, in accordance with the timing information in
Figure 9 and Figure 11.
Placing the Address Select input at a logic “0” will address MX805A #1, a logic “1” will address MX805A #2.
Table 4 and Table 5 show the list of A/C bytes relevant to the MX805A
Command Assignment
Address/Command (A/C) byte
Hex
Data Bytes
Binary
MSB
LSB
General Reset
01
00000001
Write to Control Register
70
01110000
+1 byte instruction to Control
Register
Read Status Register
71
01110001
+1 byte reply from Status Register
Read CTCSS Rx Freq. Reg.
72
01110010
+2 byte reply of CTCSS Rx Data
Write to CTCSS Tx Freq./NRZ
Baud Rate Reg.
73
01110011
+2 byte instruction for Tx Frequency
and NRZ Tx/Rx baud rates
Read NRZ Rx Data Reg.
74
01110100
+1 byte binary data Reply
Write to NRZ Tx Data Reg.
75
01110101
+1 byte binary data Command
Write to Gain Set Reg.
76
01110110
+1 byte instruction for Tx Output
Table 4: MX805A #1 C-BUS Address/Commands – (Address Select input at a logic “0”)
Command Assignment
Address/Command (A/C) byte
Hex
Data Bytes
Binary
MSB
LSB
General Reset
01
00000001
Write to Control Register
78
01111000
+1 byte instruction to Control
Register
Read Status Register
79
01111001
+1 byte reply from Status Register
Read CTCSS Rx Freq. Reg.
7A
01111010
+2 byte reply of CTCSS Rx Data
Write to CTCSS Tx Freq./NRZ
Baud Rate Reg.
7B
01111011
+2 byte instruction for Tx Frequency
and NRZ Tx/Rx baud rates
Read NRZ Rx Data Reg.
7C
01111100
+1 byte binary data Reply
Write to NRZ Tx Data Reg.
7D
01111101
+1 byte binary data Command
Write to Gain Set Reg.
7E
01111110
+1 byte instruction for Tx Output
Table 5: MX805A #2 C-BUS Address/Commands – (Address Select input at a logic “1”)
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5.2.1
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MX805A
Write to Control Register - A/C 70H (78H) followed by 1 byte of Command Data
Table 6 shows the configurations available to the MX805A. Bits 5, 6, and 7 are used together to Enable and
Powersave circuits sections as required.
Setting
Control Bits
Transmitted First
MSB
7
6
5
Enabled
Powersaved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CTCSS Decoder
NRZ Decoder
CTCSS Encoder
NRZ Encoder
CTCSS Encoder and Decoder
NRZ Encoder and CTCSS Decoder
NRZ Decoder and CTCSS Decoder
NRZ Decoder
NRZ Decoder and Both Encoders
CTCSS Decoder and Both Encoders
All Decoders
All Decoders
NRZ Encoder and Decoder
No circuits
All Encoders
All Encodes except Tx Sub-Audio LPF
and CTCSS Decoder
4
1
0
Enable Audio Output – Used with Bit 3
Disable Audio Output – output to VBIAS
3
1
0
Enable Sub-Audio Bandstop Filter (Audio Signal Path)
Bypass Sub-Audio Bandstop Filter
2
1
0
Enable All MX805A Interrupts
Disable All MX805A Interrupts
1
1
0
Set Rx Lowpass Filter Bandwidth to 180Hz – for low CTCSS tones or NRZ Data
Set Rx Lowpass Filter Bandwidth to 260Hz
0
1
0
All encoders and Decoders Powersaved
All Encoders and Decoders Enabled unless individually Powersaved
Table 6: Control Register
5.2.2
General Reset
Upon power-up the bits in the MX805A registers will be random (either 0 or 1). A General Reset Command
(01H) will be required to reset all devices on the C-BUS. It has the following effect on the MX805A:
Control Register
Set to 00H
Status Register
Set to 00H
NoTone Timer
Discharged
Warning: The following MX805A register configurations are not affected by a General Rest Command:
CTCSS Rx Frequency
CTCSS Tx Frequency/NRZ Baud Rate Register
NRZ Rx Data Register
NRZ Tx Data Register
Gain Set Register
Note: Setting the Control Register in this way will set the MX805A to the CTCSS decode mode and overwrite
a “Powersave All” instruction. It should also be considered that a General Reset command will reset All
DBS800 ICs operating on the C-BUS.
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5.2.3
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MX805A
Read Status Register –A/C 71H (79H) followed by 1 byte of Rely Data.
The Status Register indicates the operational condition of the MX805A. Bits 0 to 5 are set individually to
indicate specific actions within the device. When a Status bit is set to a logic “1”, and Interrupt Request (IRQ)
output is generated. A read of the Status Register will reset the Interrupt and ascertain the state of this
register. Table 7 shows the conditions indicated by the Status bits.
Setting
MSB
7, 6
Set By
Logic
Received First
Not Used
Cleared By
Logic
0
Not Used
0
5
NRZ data transmission complete.
No new data is loaded.
1
1. Write to NRZ Data Reg., or
2. General Reset, or
3. NRZ Encoder Powersave
0
4
NRZ TX Data Buffer ready for next
data byte.
1
1. Write to NRZ TX Data Reg., or
2. General Rest, or
3. NRZ TX Powersave
0
3
New NRZ RX data received before
last byte was read.
1
1. Read NRZ RX Data Reg., or
2. General Reset, or
3. NRZ Decoder powersave
0
2
1 byte of NRZ data received
1
1. Read NRZ RX Data Reg., or
2. General Reset, or
3. NRZ Decoder powersave
0
1
NoTone timer period expired
1
1. Read Status Register, or
2. General Rest, or
3. CTCSS Decoder Powersave
0
0
RX Tone Measurement Complete
1
1. Read Status Register, or
2. General Reset, or
3. CTCSS Decoder Powersave
0
Table 7: Status Register
5.2.4
5.2.4.1
Read CTCSS RX Frequency Register –A/C 72H (7AH) followed by 2 bytes of Reply Data
Measurement of CTCSS RX Frequency (fCTCSS IN)
The input sub-audio signal (fCTCSS IN) is filtered, doubled and measured in the Frequency Counter over the
“measurement period” (122.64ms) (4.0MHz Xtal).
The measuring function counts the number of complete input cycles occurring within the measurement period
and the number of measuring-clock cycles necessary to make up one period.
When the measurement period of a successful decode is complete, the RX Tone Measurement bit in the
Status Register and the Interrupt bit are set.
The CTCSS RX Frequency Register will now indicated the sub-audio signal frequency (fCTCSS IN) in the form
of 2 data bytes (1 and 0) as illustrated in Figure 6.
Measurement Period
Complete
Input
Cycle
Complete
Input
Cycle
Complete
Input
Cycle
Complete
Input
Cycle
FILTERED AND DOUBLED SUB-AUDIO INPUT SIGNAL
Complete
Input
Cycle
2 x f
Measuring
Clock
Cycles
CTCSS IN
N
R
Figure 5: Measurement of a CTCSS RX Frequency
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5.2.4.1.1
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MX805A
The Integer (N) –Byte 1
The binary number representing twice the number of complete input sub-audio cycle periods counted during
the measurement period of 122.64ms (4.0MHz crystal)
5.2.4.1.2
The Remainder (R) –Byte 0
A binary number representing the remainder part, R, of 2x the Sub-Audio Input Frequency. R = number of
specified measuring-clock cycles required to complete the specified measurement period (See N). The clock
cycle frequency is 4166.6Hz (4.0MHz crystal)
Byte 1
(Reply Data)
(MSB) - Transmitted First
15
14
"0"
"0"
13
12
11
Byte 0
10
9
8
Integer (N)
7
6
"0"
"0"
5
4
3
(Reply Data)
(LSB) - Transmitted Last
2
1
0
Remainder (R)
CTCSS RX Frequency Register
Figure 6: Format of the CTCSS RX Frequency Register
5.2.4.2
CTCSS RX Frequency Register
The format of the CTCSS RX Frequency Register is shown in Figure 6.
Bits 8 (LSB) to 13 (MSB) are used to represent the Integer (N). From Byte 1, valid values of
N = 16 ≤ N ≤ 61 i.e. values of N less than 16 and greater than 61 are not within the specified frequency band.
Bits 0 (LSB) to 5 (MSB) are used to represent the Remainder (R). From Byte 0, valid values of R ≤ 31 . This
register is not affected by the General Reset command (01H) and may adopt any random configuration at
Power-UP.
5.2.4.3
CTCSS RX Frequency Measurement Formulas
To assist in the production of “lookup” tables and limit-values in the microcontroller, and to provide guidance
upon the determination of N and R from a measured CTCSS frequency, the following formulas show the
derivation of the CTCSS RX Frequency (fCTCSS IN) from the measured data bytes (N and R).
5.2.4.3.1
fCTCSS IN
In the measurement period of 122.64ms there are N cycles at 2 x fCTCSS IN and R clcok cycles at 4166.6Hz,
for any input frequency.
f CTCSS IN =
N × f XTAL
1920 × (511 - R)
é 1920 x 511 xfCTCSS IN ù
N = INT ê
ú
f XTAL
ë
û
é
æ
N x f XTAL
R = INT ê511 - çç
êë
è 1920 x f CTCSS IN
ù
ö
÷ + .5 ú
÷
úû
ø
Calculate N first
Example: (fXTAL = 4.00Mhz): fCTCSS IN = 100Hz N = 24 R = 11; fCTCSS IN = 250Hz N = 61 R = 3
5.2.4.4
NoTone Timing
The input sub-audio signal is monitored by the Frequency Assessment Circuitry. Before any NoTone action is
enabled, the MX805A must have achieved at least one successful “Tone Measurement Complete” action.
If there is no signal or the signal is of a consistently poor quality, the NoTone timer will start to charge via the
timing components. When the timing period has expired (at VDD/2), an Interrupt and a Status bit (NoTone
Timer Expired) are generated. This is a one-shot function which is rest by a “Tone Measurement Complete”
interrupt.
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5.2.5
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MX805A
Write to CTCSS TX Frequency/NRZ Baud Data Rate Register –A/C 73H (7BH) followed by 2
bytes of Command Data.
The information loaded to this register will set either the:
(a) CTCSS TX Tone Frequency
fCTCSS OUT
(b) NRZ TX Baud Rate
RNRZ TX
(c) NRZ RX Baud Rate
RNRZ RX
The chosen mode for this register (a, b, or c) is determined by the MX805A modes enabled by the Control
Register, as shown in Table 8.
Control Register Bits
7
6
5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
MX805A Mode
Enabled
CTCSS TX/NRZ Baud Rate
Register Function
CTCSS Decode
NRZ Decode
CTCSS Decode
NRZ Encode
CTCSS Encode and Decode
NRZ Encode & CTCSS Decode
NRZ & CTCSS Decode
NRZ Decode
NRZ RX Baud Rate
CTCSS TX Frequency
NRZ TX Baud Rate
CTCSS TX Frequency
NRZ TX Baud Rate
NRZ RX Baud Rate
NRZ RX Baud Rate
Table 8 CTCSS Frequency/NRZ Baud Rate Register Configurations
5.2.5.1
Data Format
Data is transmitted to this register as 2 bytes of Command Data in the form illustrated in the diagram below.
This register is not affected by the General Rest Command (01H) and may adopt any random configuration at
power-up.
Byte 1
(Command Data)
(MSB) - Loaded First
15
13
14
P
12
11
Byte 0
10
9
8
7
6
"0"
5
4
3
(Command Data)
(LSB) - Loaded Last
2
1
0
Q
CTCSS TX Frequency/NRZ Baud Rate Register
Figure 7: Format of the CTCSS TX Frequency/NRZ Baud Rate Register
5.2.5.2
Command Words P and Q
The two words, P and Q, loaded to this register are interpreted as:
P=
a binary number to set the TX Sub-Audio Lowpass filter bandwidth (applicable to NRX and CTCSS
modes).
Q=
A binary number to set the frequency r baud rate of the selected functon.
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5.2.5.2.1
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MX805A
Command Word P
Bits
LSB
15
14
13
12
P
LPF Bandwidth
0
0
0
0
0
0
1
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
2
3
4
5
6
7
8
300Hz
200Hz
150Hz
120Hz
100Hz
85.7Hz
75Hz
Table 9: Valid Values of P
Bits 12 to 15 are used to produce the data word “P” as shown in Table 9. The cutoff frequency fC/O (0.5dB
point) of the TX Sub-Audio Lowpass filter is calculated as:
f C/O =
P=
f XTAL
32 x 208.33 x P
f XTAL
32 × 208.33 × f C/O
Table 9 is provided as and example and calculated using a Xtal/Clock (fXTAL) frequency of 4.00MHz. As
illustrated, only values of “P” of 2 to 8 are usable
5.2.5.2.2
Command Word Q
Bits 0 to 10 (See Figure 7) are used to produce the data word “Q” which sets one of the parameters described
below. As you can see, Command Word “Q” could be used to produce a parameter outside that specified in
the “Characteristics” section of this data bulletin. Care should be taken not to do this. Examples for limits of
“Q” in each operational configuration are included. “Q” = 0 is not valid in the following calculations. Bit 11 is
not used and must be set to logic “0”.
(a) CTCSS TX Tone Frequency (fCTCSS OUT)
f CTCSS
OUT
f XTAL
Hz
32 x " Q"
fCTCSS OUT
=
67Hz
So “Q”
=
1866
f XTAL
Hz
32 x fCTCSS OUT
fCTCSS OUT
=
250Hz
So “Q”
=
500
f XTAL
bits/sec
32 x " Q"
RNRZ TX
=
67bps
So “Q”
=
1866
f XTAL
32 x R NRZ TZ
RNRZ TX
=
300bits/sec
So “Q”
=
417
=
so " Q" =
“11101001010”
“00111110100”
(b) NRZ TX Baud Rate (RNRZ TX)
R NRZ TZ =
so " Q" =
“11101001010”
“00110100001”
(c) NRZ RX Baud Rate (RNRZ RX)
R NRZ RX =
so " Q" =
f XTAL
bits/sec
32 x 11 x " Q"
RNRZ RX
=
100bps
So “Q”
=
114
f XTAL
352 x R NRZ RX
RNRZ RX
=
300bits/sec
So “Q”
=
38
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5.2.6
Page 17 of 24
MX805A
Read NRZ RX Data Register – A/C 74H (7CH) followed by 1 byte Reply Data
Received NRZ data bits are organized into bytes and made available to the microcontroller via the Reply Data
line. As 8 bits are received into this register and interrupt is generated to indicate that a complete byte has
th
been received. This byte must be read before the arrival of the last (8 ) bit of the next incoming byte. If this
in not done, an interrupt to indicate this condition will be generated and the previous RX data is discarded.
See Table 7.
Word synchronization is not provided. Byte synchronization and any codeword recognition will be performed
by the host microcontroller. The RX baud rate is set by writing to the CTCSS TX Frequency/NRZ Baud Rate
Register (73H/7BH). The first bit received is the first bit sent to the microcontroller.
This register is not affected by the General Reset Command (01H), and may adopt random configuration at
Power-Up.
5.2.7
Write to NRZ TX Data Register – A/C 75H (7DH) followed by 1 byte of Command Data.
A byte for transmission is loaded from the C-BUS Command Data line with the A/C. The first data bit
received via the C-BUS is transmitted first. The transmitter operation is non-inverting.
The first data byte loaded after the NRZ Encoder is enabled (Control Register) initiates the transmission
sequence and an interrupt will be generated when the NRZ TX Data Buffer is ready for the next data byte.
Subsequently, interrupts occur for every 8 bits transmitted.
Transmission is terminated, the TX Sub-Audio Output is placed at VBIAS, and a interrupt is generated if the
next byte is not loaded within 7 bit periods. See Table 7.
This register is not affected by the General Reset Command (01H), and may adopt any random configuration
at Power-Up.
5.2.8
5.2.8.1
Write to Gain Set Register – A/C 76H (7EH) followed by 1 byte of Command Data
Gain Set Register Settings:
The settings of this register control the CTCSS and NRZ signal level that is presented at the TX Sub-Audio
Output.
Bit 3, when enabled, is used to produce a pre-emphasis effect on the NRZ TX Data by increasing the gain of
the data bit before a level change (See Figure 8), by 1.72dB to make that data pulse level slightly more
positive (or negative). The signal level will be 1.72dB greater that that set by Bits 0 to 2. If the TX Sub-Audio
Output level is set to +2.58dB, the pre-emphasis level will be +4.3dB.
The pre-emphasis function will remain enabled until disabled by setting Bit 3 to a logic “0”. If this function
remains enabled when using the CTCSS Encoder, the output signal may be adversely affected. Therefore
this function should be enabled when in the NRZ Encode mode.
This register is not affected by the General Reset Command (01H), and may adopt any random configuration
at Power-Up.
Setting
Gain Setting
7
6
5
4
0
0
0
0
Transmitted Bit 7 First
3
Pre-Emphasis Setting
1
0
1.72dB Gain Enabled
1.72dB Gain Disabled
2
1
0
Tx Level Adjust Gain Setting
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-2.58dB
–1.72dB
–0.86dB
0dB
+0.86dB
+1.72dB
+2.58dB
Not Used
Table 10: Gain Set Register Settings
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Sub-Audio Signaling Processor
13
14
MX805A
Byte 1
(Command Data)
(MSB) - Loaded First
15
Page 18 of 24
12
Byte 0
9
10
11
8
7
6
"0"
P
5
4
(Command Data)
(LSB) - Loaded Last
1
2
3
0
Q
CTCSS TX Frequency/NRZ Baud Rate Register
Figure 8: Gain Set with Pre-Emphasisi
6 Performance Specifications
6.1
Electrical Specifications
6.1.1
Absolute Maximum Limits
Exceeding these maximum ratings can result in damage to the device.
General
Notes
Supply (VDD-VSS)
Voltage on any pin to VSS
Current
VDD
VSS
Any other pin
P / DW / LH Packages
Total allowable Power dissipation
at TAMB = 25°C
Min.
Typ.
Max.
Units
-0.3
-0.3
7.0
VDD + 0.3
V
V
-30
-30
30
30
mA
mA
-20
20
mA
800
mW
10
Derating above 25°C
Operating Temperature
mW/°C above 25°C
-40
85
°C
Storage Temperature
-55
125
°C
Table 11: Absolute Maximum Ratings
6.1.2
Operating Limits
Correct Operation of the device outside these limits is not implied.
Notes
Supply (VDD-VSS)
Operating Temperature
Xtal Frequency
Min.
Typ.
Max.
Units
4.5
-40
5.0
5.5
85
V
4.0
°C
MHz
Table 12: Operating Limits
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MX805A
Operating Characteristics
For the following conditions unless otherwise specified.
VDD = 5.0V @ TAMB = 25°C
Xtal/Clock Frequency = 4.0MHz, Audio Level 0dB ref. = 308mVRMS @ 1kHz
Composite Signal = 308mVRMS @ 1kHz + 75mVRMS Noise + 31mVRMS Sub-Audio signal
Noise Bandwidth = 5kHz Band Limited Gaussian
Notes
Min.
Typ.
Max.
Units
5.0
2.0
7.0
3.0
mA
mA
0.9
1.5
mA
Static Values
Supply Current
All Functions Enabled
All Functions Disabled
Powersave All
Analog Impedances
RX Sub-Audio Input
350.0
Audio Input
350.0
Audio Bypass Switch On
5
Audio Bypass Switch OFF
5
1500.0
kΩ
kΩ
2.0
kΩ
1.0
6.5
MΩ
RX Amp Input (+ and -)
1.0
6.5
MΩ
Comparator Input (+ and -)
1.0
6.5
MΩ
2.0
kΩ
RX Sub-Audio Output
TX Sub-Audio Output
Encoder Enabled
5
2.0
kΩ
Encoder Disabled
5
500.0
kΩ
Audio Output
Encoder Enabled
5
2.0
kΩ
Encoder Disabled
5
500.0
kΩ
6.0
kΩ
600.0
kΩ
RX Amp and Comparator Outputs
Large Signal
Small Signal
Dynamic Values
Digital Interface
Input Logic 1
1
Input Logic 0
Output Logic 1 (IOH = -120mA)
1
2
Output Logic 1 (IOL = -360mA)
IOUT Tristate (Logic 1 or 0)
3.5
V
1.5
V
V
3
3
0.4
4.0
V
Input Capacitance
1
7.5
µA
pF
Logic Input Current (VIN = 0 to 5.0V)
1
1.0
µA
IOX (VOUT = 5.0V)
4
4.0
µA
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Notes
MX805A
Min.
Typ.
Max.
Overall Performance
Units
dB
kHz
CTCSS - Decode
Sensitivity (Composite Signal)
Response Time (Composite Signal)
100Hz to 257Hz Tone
6
65Hz Tone
Tone Measurement Resolution
Tone Measurement Accuracy
9
NoTone Response Time (Composite Signal)
False tone Interrupts (Noise Input Only)
CTCSS Encode
Frequency Range
Tone Frequency Resolution
Tone Amplitude Tolerance
-20.0
-26.0
210.0
250.0
ms
210.0
0.2
384.0
ms
%
%
175.0
20.0
250.0
ms
/Hr
257.0
0.2
1.0
Hz
%
dB
30.0
50.0
5.0
ms
ms
%
-0.5
7
10
0.5
65.0
12
-1.0
Rise Time (to 90%)
Fall Time (to 10%)
Total Harmonic Distortion
NRX – Decode
RX Bit Rate Sync Time
RX Bit Error Rate
2
-3
1 x 10
11
NRZ – TX
TX Bit Rate
TX LPF (3dB) Bandwidth
dB
67.0
75.0
Sub-Audio TX Output Level
CTCSS
edge
P(ERROR)
300.0
300.0
0
NRZ
Amplitude Adjustment Range
Adjustment Step Size (7 Steps)
Sub-Audio Bandstop Filter
Passband
Passband Gain (@ 1.0kHz)
dB
0.871
-2.58
8
2.58
0.86
297.0
Hz
dB
0.5
-45.7
dB
dB
dB
62.5
kHz
280.0
Hz
6.0
4.0
6.1
dB
MHz
-1.5
36.0
-50.0
Alias Frequency
Receive Lowpass Filter (See Figure 9)
Cutoff Frequency (-3dB)
Passband Gain
Xtal/Clock Frequency (fXTAL)
VP-P
dB
dB
3000.0
0
Passband Ripple (with respect to gain @ 1.0Hz)
Stopband Gain < 250Hz
Residual Hum and Noise
bits/sec
Hz
Table 13: Operating Characteristics
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Sub-Audio Signaling Processor
Page 21 of 24
MX805A
Operating Characteristics Notes:
1. Device control pins: Serial Clock, Command Data, Wake , and CS .
2. Reply Data Output
3. Reply Data and IRQ outputs
4. Leakage current into the “OFF” IRQ output.
5. See Control Register
6. With input gain components set as recommended in Figure 2.
7. Probability 97%
8. See Gain Set Register.
9. For fCTCSS IN of 65Hz to 100Hz, Response Time tR = (100/fTone) x 250ms.
10. Distributed across the RX Frequency band
11. With 10dB signal-to-noise ratio in a bit-rate bandwidth.
12. At any gain setting of Gain Register.
Signal
Level
(dB)
Xtal = 4.0 MHz
VDD = 5.0V
10dB/division
0
0
100
200
300
400
500
600
700
800
Frequency (Hz)
Figure 9: Typical Frequency Response of RX Lowpass Filter
ã2001 MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Doc. # 20480116.005
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Sub-Audio Signaling Processor
6.1.4
Page 22 of 24
MX805A
Timing
Timing Parameters for two-way communications between the µC and the MX805A on the C-BUS are shown
in Table 14.
C-BUS Timing
tCSE
Chip Select Low to First Serial Clock Rising Edge
Min.
2.0
Typ.
Max.
Units
µs
tCHS
Last Serial Clock Rising Edge to Chip Select High
4.0
µs
tCSOFF
Chip Select High
2.0
µs
tNXT
Command Data Inter-Byte Time
4.0
µs
tCK
Serial Clock Period
2.0
tCH
tCL
tCDS
tCDH
tRDS
tRDH
tHIZ
Decoder or Encoder Clock High
Decoder or Encoder Clock Low
Command Data Set-Up Time
Command Data Hold Time
Reply Data Set-Up Time
Reply Data Hold Time
Chip Select High to Reply Data High – Z
500
500
250
0
250
50.0
µs
ns
ns
ns
ns
ns
ns
2.0
µs
Table 14: Timing Information
Notes:
1. Command Data is transmitted to the peripheral MSB (bit 7) first, LSB (bit 0) last. Reply Data is read from
the MX805A MXB (bit 7) first, LSB (bit 0) last.
2. Data is clocked into the MX805A and into the microcontroller on the rising Serial Clock edge.
3. Loaded data instructions are acted upon at the end of each individual, loaded byte.
4. To allow for differing microcontroller serial interface formats, the MX805A will work with either polarity
Serial clock pulses.
t CSOFF
CHIP SELECT
t CSE
t NXT
t CSH
t NXT
SERIAL CLOCK
t CK
COMMAND DATA
7
6
5
4
3
2
1
MSB
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
LSB
FIRST DATA BYTE
ADDRESS/COMMAND
BYTE
LAST DATA BYTE
t HIZ
REPLY DATA
7
Logic level is not important
6
5
4
3
2
1
0
7
LSB
MSB
FIRST REPLY DATA BYTE
6
5
4
3
2
1
0
LAST REPLY DATA BYTE
Figure 10: C-BUS Timing Information
ã2001 MX-COM, Inc.
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Sub-Audio Signaling Processor
Page 23 of 24
MX805A
t CK
70% VDD
t CH
t CL
SERIAL CLOCK
(from C)
30% VDD
t CDH
t CDS
COMMAND DATA
(from µC)
t RDH
t RDS
REPLY DATA
(to µC)
Figure 11: Timing Relationships for C-BUS Information Transfer
6.2
Packages
A
Package Tolerances
B
DIM.
A
B
C
E
E1
H
J
J1
K
L
P
T
Y
E
E1
Y
T
PIN1
K
H
L
C
J1
J
MIN.
TYP.
MAX.
1.270 (32.26)
1.200 (30.48)
0.555 (14.04)
0.500 (12.70)
0.151 (3.84)
0.220 (5.59)
0.600 (15.24)
0.670 (17.02)
0.590 (14.99)
0.625 (15.88)
0.015 (0.38)
0.045 (1.14)
0.015 (0.38)
0.023 (0.58)
0.040 (1.02)
0.065 (1.65)
0.066 (1.67)
0.074 (1.88)
0.121 (3.07)
0.160 (4.05)
0.100 (2.54)
0.008 (0.20)
0.015 (0.38)
7°
NOTE : All dimensions in inches (mm.)
Angles are in degrees
P
Figure 12: 24-pin PDIP Mechanical Outline: Order as part no. MX805AP
Package Tolerances
A
Z
B
Alternative Pin
Location
Marking
E
W
L
T
PIN 1
X
Y
C K
H
J
P
DIM.
A
B
C
E
H
J
K
L
P
T
W
X
Y
Z
MIN.
TYP.
MAX.
0.613 (15.57)
0.299 (7.59)
0.105 (2.67)
0.419 (10.64)
0.020 (0.51)
0.020 (0.51)
0.046 (1.17)
0.597 (15.16)
0.286 (7.26)
0.093 (2.36)
0.390 (9.90)
0.003 (0.08)
0.013 (0.33)
0.036 (0.91)
0.050 (1.27)
0.016 (0.41)
0.050 (1.27)
0.0125 (0.32)
0.009 (0.23)
45°
10°
0°
5°
7°
5°
NOTE : All dimensions in inches (mm.)
Angles are in degrees
Figure 13: 24-pin SOIC Mechanical Outline: Order as part no. MX805ADW
ã2001 MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
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Doc. # 20480116.005
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Sub-Audio Signaling Processor
Page 24 of 24
E
B
C
Package Tolerances
K
Y
DA
W
J
W
T
PIN 1
MX805A
H
P
G
DIM.
A
B
C
D
E
F
G
H
J
K
P
T
W
Y
MIN.
TYP.
MAX.
0.409 (10.40)
0.380 (9.61)
0.409 (10.40)
0.380 (9.61)
0.146 (3.70)
0.128 (3.25)
0.417 (10.60)
0.435 (11.05)
0.435 (11.05)
0.417 (10.60)
0.250 (6.35)
0.250 (6.35)
0.023 (0.58)
0.018 (0.45)
0.022 (0.55)
0.047 (1.19)
0.048 (1.22)
0.051 (1.30)
0.049 (1.24)
0.009 (0.22)
0.006 (0.152)
30°
45°
6°
NOTE : All dimensions in inches (mm.)
Angles are in degrees
F
Figure 14: 24-pin PLCC Mechanical Outline: Order as part no. MX805ALH
ã2001 MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Doc. # 20480116.005
All trademarks and service marks are held by their respective companies.
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor
companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc
(USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst
maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA)
Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML
Microcircuits.
These companies are all 100% owned operating companies of the CML Microsystems Plc
Group and these changes are purely changes of name and do not change any underlying legal
entities and hence will have no effect on any agreements or contacts currently in force.
CML Microcircuits Product Prefix Codes
Until the latter part of 1996, the differentiator between products manufactured and sold from
MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX
respectively. These products use the same silicon etc. and today still carry the same prefixes.
In the latter part of 1996, both companies adopted the common prefix: CMX.
This notification is relevant product information to which it is attached.
CML Microcircuits (USA) [formerly MX-COM, Inc.] Product Textual Marking
On CML Microcircuits (USA) products, the ‘MX-COM’ textual logo is being replaced by a ‘CML’
textual logo.
Company contact information is as below:
CML Microcircuits
(UK)Ltd
CML Microcircuits
(USA) Inc.
CML Microcircuits
(Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon,
Essex, CM9 6WG, England
Tel: +44 (0)1621 875500
Fax: +44 (0)1621 875600
uk.sales@cmlmicro.com
www.cmlmicro.com
4800 Bethania Station Road,
Winston-Salem, NC 27105, USA
Tel: +1 336 744 5050,
0800 638 5577
Fax: +1 336 744 5054
us.sales@cmlmicro.com
www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/
06 Mactech Industrial Building,
Singapore 349307
Tel: +65 7450426
Fax: +65 7452917
sg.sales@cmlmicro.com
www.cmlmicro.com
D/CML (D)/2 May 2002