SCLS384G − SEPTEMBER 1997 − REVISED DECEMBER 2004
D 2-V to 5.5-V VCC Operation
D Max tpd of 6.5 ns at 5 V
D Typical VOLP (Output Ground Bounce)
D
D
D
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on
All Ports
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
SN54LV240A . . . FK PACKAGE
(TOP VIEW)
2Y4
1A1
1OE
VCC
description/ordering information
These octal buffers/drivers are designed for 2-V to
5.5-V VCC operation.
1A2
2Y3
1A3
2Y2
1A4
The ’LV240A devices are designed specifically to
improve both the performance and density of
3-state memory address drivers, clock drivers,
and bus-oriented receivers and transmitters.
2OE
D
SN54LV240A . . . J OR W PACKAGE
SN74LV240A . . . DB, DGV, DW, NS, OR PW PACKAGE
(TOP VIEW)
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2Y1
GND
2A1
1Y4
2A2
These devices are organized as two 4-bit
buffers/line drivers with separate output-enable
(OE) inputs. When OE is low, the device passes
data from the A inputs to the Y outputs. When OE
is high, the outputs are in the high-impedance
state.
1Y1
2A4
1Y2
2A3
1Y3
ORDERING INFORMATION
TOP-SIDE
MARKING
Tube of 25
SN74LV240ADW
Reel of 2000
SN74LV240ADWR
SOP − NS
Reel of 2000
SN74LV240ANSR
74LV240A
SSOP − DB
Reel of 2000
SN74LV240ADBR
LV240A
Tube of 70
SN74LV240APW
Reel of 2000
SN74LV240APWR
Reel of 250
SN74LV240APWT
TVSOP − DGV
Reel of 2000
SN74LV240ADGVR
LV240A
CDIP − J
Tube of 20
SNJ54LV240AJ
SNJ54LV240AJ
CFP − W
Tube of 85
SNJ54LV240AW
SNJ54LV240AW
LCCC − FK
Tube of 55
SNJ54LV240AFK
SOIC − DW
−40°C to 85°C
TSSOP − PW
−55°C
−55
C to 125
125°C
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
LV240A
LV240A
SNJ54LV240AFK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!"#$%&' #"'(' ')"*%("' #$**&' ( ") +$,-#("' !(&. *"!$# #"')"*% "
+&#)#("' +&* & &*% ") &/( '*$%&' ('!(*! 0(**('1.
*"!$#"' +*"#&'2 !"& '" '&#&(*-1 '#-$!& &'2 ") (-+(*(%&&*.
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1
SCLS384G − SEPTEMBER 1997 − REVISED DECEMBER 2004
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each buffer)
INPUTS
OE
A
OUTPUT
Y
L
H
L
L
L
H
H
X
Z
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
2
1
2OE
2
18
4
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
POST OFFICE BOX 655303
19
11
9
13
7
15
5
17
3
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2Y1
2Y2
2Y3
2Y4
SCLS384G − SEPTEMBER 1997 − REVISED DECEMBER 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range applied in the high or low state, VO (see Notes 1 and 2) . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
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3
SCLS384G − SEPTEMBER 1997 − REVISED DECEMBER 2004
recommended operating conditions (see Note 4)
VCC
VIH
VI
Input voltage
VO
Output voltage
∆t/∆v
VCC = 2 V
VCC = 2.3 V to 2.7 V
High-level input voltage
Low-level input voltage
IOL
SN74LV240A
MIN
MAX
MIN
MAX
2
5.5
2
5.5
Supply voltage
VIL
IOH
SN54LV240A
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.5
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
Low-level output current
Input transition rise or fall rate
0.5
0
0
VCC × 0.3
VCC × 0.3
VCC × 0.3
5.5
0
High-level output current
V
0.5
VCC × 0.3
VCC × 0.3
3-state
V
1.5
VCC × 0.7
VCC × 0.7
High or low state
UNIT
0
VCC
5.5
VCC × 0.3
5.5
0
0
V
V
VCC
5.5
V
µA
VCC = 2 V
VCC = 2.3 V to 2.7 V
−50
−50
−2
−2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
−8
−8
−16
−16
VCC = 2 V
VCC = 2.3 V to 2.7 V
50
50
2
2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
8
8
16
16
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
200
200
100
100
VCC = 4.5 V to 5.5 V
20
20
mA
µA
mA
ns/V
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV240A
PARAMETER
VOH
VOL
TEST CONDITIONS
IOH = −50 µA
IOH = −2 mA
VCC
MIN
2 V to 5.5 V
IOL = 50 µA
IOL = 2 mA
3V
2.48
2.48
4.5 V
3.8
TYP
MAX
UNIT
V
3.8
0.1
0.1
2.3 V
0.4
0.4
3V
0.44
0.44
4.5 V
0.55
0.55
0 to 5.5 V
±1
±1
µA
5.5 V
±5
±5
µA
V
II
IOZ
VI = 5.5 V or GND
VO = VCC or GND
ICC
Ioff
VI = VCC or GND, IO = 0
VI or VO = 0 to 5.5 V
5.5 V
20
20
µA
0
5
5
µA
Ci
VI = VCC or GND
3.3 V
2.3
')"*%("' #"'#&*' +*"!$# ' & )"*%(3& "*
!&2' +(& ") !&3&-"+%&'. (*(#&*# !(( ('! "&*
+&#)#("' (*& !&2' 2"(-. &/( '*$%&' *&&*3& & *2 "
#('2& "* !#"''$& && +*"!$# 0"$ '"#&.
4
MIN
VCC−0.1
2
2 V to 5.5 V
IOL = 8 mA
IOL = 16 mA
MAX
VCC−0.1
2
2.3 V
IOH = −8 mA
IOH = −16 mA
TYP
SN74LV240A
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2.3
pF
SCLS384G − SEPTEMBER 1997 − REVISED DECEMBER 2004
switching characteristics over recommended operating
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
tdis
OE
Y
tpd
A
ten
OE
tdis
OE
PARAMETER
LOAD
CAPACITANCE
MIN
free-air
TA = 25°C
TYP
MAX
∗
6.3
11.6∗
temperature
SN54LV240A
range,
SN74LV240A
MIN
1∗
MAX
14∗
MIN
MAX
1
14
8.5∗
14.6∗
1∗
17∗
1
17
9.7∗
14.1∗
1∗
16∗
1
16
Y
8.2
14.4
1
17
1
17
Y
10.3
17.8
1
21
1
21
14.2
19.2
1
21
1
21
CL = 15 pF
CL = 50 pF
Y
tsk(o)
2
UNIT
ns
ns
2
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
tpd
ten
free-air
FROM
(INPUT)
TO
(OUTPUT)
A
Y
TA = 25°C
MIN
TYP
MAX
4.6∗
7.5∗
Y
6.2∗
OE
LOAD
CAPACITANCE
CL = 15 pF
temperature
SN54LV240A
range,
SN74LV240A
MIN
1∗
MAX
9∗
MIN
MAX
1
9
10.6∗
1∗
12.5∗
1
12.5
12.5∗
1∗
13.5∗
tdis
OE
Y
8.3∗
1
13.5
tpd
A
Y
5.9
11
1
12.5
1
12.5
ten
OE
Y
7.5
14.1
1
16
1
16
tdis
OE
11.8
15
1
17
1
17
CL = 50 pF
Y
tsk(o)
1.5
UNIT
ns
ns
1.5
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
tdis
OE
tpd
ten
tdis
OE
Y
PARAMETER
LOAD
CAPACITANCE
MIN
free-air
TA = 25°C
TYP
MAX
∗
3.4
5.5∗
temperature
SN54LV240A
range,
SN74LV240A
MIN
1∗
MAX
6.5∗
MIN
MAX
1
6.5
4.6∗
7.3∗
1∗
8.5∗
1
8.5
Y
7.4∗
12.2∗
1∗
13.5∗
1
13.5
A
Y
4.4
7.5
1
8.5
1
8.5
OE
Y
5.6
9.3
1
10.5
1
10.5
9.7
14.2
1
15.5
1
15.5
CL = 15 pF
CL = 50 pF
tsk(o)
1
UNIT
ns
ns
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
')"*%("' #"'#&*' +*"!$# ' & )"*%(3& "*
!&2' +(& ") !&3&-"+%&'. (*(#&*# !(( ('! "&*
+&#)#("' (*& !&2' 2"(-. &/( '*$%&' *&&*3& & *2 "
#('2& "* !#"''$& && +*"!$# 0"$ '"#&.
POST OFFICE BOX 655303
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5
SCLS384G − SEPTEMBER 1997 − REVISED DECEMBER 2004
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
SN74LV240A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
VOL(V)
Quiet output, maximum dynamic VOL
0.56
V
Quiet output, minimum dynamic VOL
−0.49
V
VOH(V)
VIH(D)
Quiet output, minimum dynamic VOH
2.82
V
High-level dynamic input voltage
2.31
V
VIL(D)
Low-level dynamic input voltage
NOTE 5: Characteristics are for surface-mount packages only.
0.99
V
VCC
3.3 V
TYP
UNIT
5V
16.4
operating characteristics, TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
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f = 10 MHz
14
pF
SCLS384G − SEPTEMBER 1997 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
Input
50% VCC
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
0V
VOH
50% VCC
VOL
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPLZ
tPZL
Output
Waveform 1
S1 at VCC
(see Note B)
tPLH
VOH
50% VCC
VOL
VCC
Output
Control
≈VCC
50% VCC
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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7
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
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