TI SN74LVC1G66DCKTE4

SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323L – JUNE 2001 – REVISED JANUARY 2007
FEATURES
•
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoFree™ Package
1.65-V to 5.5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 0.8 ns at 3.3 V
High On-Off Output Voltage Ratio
High Degree of Linearity
High Speed, Typically 0.5 ns
(VCC = 3 V, CL = 50 pF)
•
•
DBV PACKAGE
(TOP VIEW)
A
1
B
2
GND
3
Low On-State Resistance, Typically ≈5.5 Ω
(VCC = 4.5 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCK PACKAGE
(TOP VIEW)
A
VCC
5
1
B
2
GND
3
5
4
DRL PACKAGE
(TOP VIEW)
VCC
A
1
B
2
GND
3
5
4
YZP PACKAGE
(BOTTOM VIEW)
VCC
GND
C
3 4
B
2
A
1 5
C
VCC
C
C
4
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single analog switch is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G66 can handle both analog and digital signals. The device permits signals with amplitudes of
up to 5.5 V (peak) to be transmitted in either direction.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
ORDERING INFORMATION
TA
PACKAGE (1)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
–40°C to 85°C
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
SOT (SOT-553) – DRL
(1)
(2)
ORDERABLE PART NUMBER
Reel of 3000
SN74LVC1G66YZPR
Reel of 3000
SN74LVC1G66DBVR
Reel of 250
SN74LVC1G66DBVT
Reel of 3000
SN74LVC1G66DCKR
Reel of 250
SN74LVC1G66DCKT
Reel of 4000
SN74LVC1G66DRLR
TOP-SIDE MARKING (2)
_ _ _C6_
C66_
C6_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2007, Texas Instruments Incorporated
SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323L – JUNE 2001 – REVISED JANUARY 2007
FUNCTION TABLE
CONTROL
INPUT
(C)
SWITCH
L
OFF
H
ON
LOGIC DIAGRAM (POSITIVE LOGIC)
1
2
A
B
4
C
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage
range (2)
–0.5
6.5
V
VI
Input voltage range (2) (3)
–0.5
6.5
V
VI/O
Switch I/O voltage range (2) (3) (4)
–0.5
VCC + 0.5
V
IIK
Control input clamp current
VI < 0
–50
mA
IIOK
I/O port diode current
VI/O < 0 or VI/O > VCC
±50
mA
IT
On-state switch current
VI/O < 0 to VCC
±50
mA
±100
mA
Continuous current through VCC or GND
θJA
Package thermal impedance (5)
Tstg
Storage temperature range
DBV package
206
DCK package
252
DRL package
142
YZP package
(1)
(2)
(3)
(4)
(5)
2
UNIT
°C/W
132
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 5.5 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
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SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323L – JUNE 2001 – REVISED JANUARY 2007
Recommended Operating Conditions
(1)
MIN
MAX
UNIT
VCC
Supply voltage
1.65
5.5
V
VI/O
I/O port voltage
0
VCC
V
VCC × 0.65
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage, control input
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
V
VCC × 0.35
VCC = 1.65 V to 1.95 V
VIL
Low-level input voltage, control input
VI
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC = 4.5 V to 5.5 V
VCC × 0.3
Control input voltage
∆t/∆v
Input transition rise/fall time
TA
Operating free-air temperature
0
5.5
VCC = 1.65 V to 1.95 V
20
VCC = 2.3 V to 2.7 V
20
VCC = 3 V to 3.6 V
10
VCC = 4.5 V to 5.5 V
(1)
V
V
ns/V
10
–40
°C
85
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
ron
On-state switch resistance
TEST CONDITIONS
VI = VCC or GND,
VC = VIH
(see Figure 1 and
Figure 2)
VCC
MIN TYP (1)
MAX
IS = 4 mA
1.65 V
12
30
IS = 8 mA
2.3 V
9
20
IS = 24 mA
3V
7.5
15
IS = 32 mA
4.5 V
5.5
10
IS = 4 mA
1.65 V
74.5
120
IS = 8 mA
2.3 V
20
30
IS = 24 mA
3V
11.5
20
IS = 32 mA
4.5 V
7.5
15
UNIT
Ω
Peak on resistance
VI = VCC or GND,
VC = VIH
(see Figure 1 and
Figure 2)
IS(off)
Off-state switch leakage
current
VI = VCC and VO = GND or
VI = GND and VO = VCC,
VC = VIL (see Figure 3)
5.5 V
IS(on)
On-state switch leakage
current
VI = VCC or GND, VC = VIH, VO = Open
(see Figure 4)
5.5 V
II
Control input current
VC = VCC or GND
5.5 V
ICC
Supply current
VC = VCC or GND
5.5 V
∆ICC
Supply current change
VC = VCC – 0.6 V
5.5 V
Cic
Control input capacitance
5V
2
pF
Cio(off)
Switch input/output
capacitance
5V
6
pF
Cio(on)
Switch input/output
capacitance
13
pF
ron(p)
(1)
±1
5V
±0.1 (1)
±1
±0.1 (1)
±1
±0.1 (1)
10
1 (1)
500
Ω
µA
µA
µA
µA
µA
TA = 25°C
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3
SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323L – JUNE 2001 – REVISED JANUARY 2007
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)
(1)
(2)
(3)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
MIN
MAX
MIN
MIN
0.6
ns
A or B
2.5
12
1.9
6.5
1.8
5
1.5
4.2
ns
A or B
2.2
10
1.4
6.9
2
6.5
1.4
5
ns
FROM
(INPUT)
TO
(OUTPUT)
tpd (1)
A or B
B or A
ten (2)
C
tdis (3)
C
PARAMETER
2
MAX
1.2
MAX
VCC = 5 V
± 0.5 V
UNIT
MIN MAX
0.8
tPLH and tPHL are the same as tpd. The propagation delay is the calculated RC time constant of the typical on-state resistance of the
switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
tPZL and tPZH are the same as ten.
tPLZ and tPHZ are the same as tdis.
Analog Switch Characteristics
TA = 25°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
CL = 50 pF, RL = 600 Ω,
fin = sine wave
(see Figure 6)
response (1)
Frequency
(switch ON)
A or B
B or A
CL = 5 pF, RL = 50 Ω,
fin = sine wave
(see Figure 6)
Crosstalk
(control input to signal output)
C
A or B
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (square wave)
(see Figure 7)
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 8)
Feedthrough attenuation (2)
(switch OFF)
A or B
B or A
CL = 5 pF, RL = 50 Ω,
fin = 1 MHz (sine wave)
(see Figure 8)
CL = 50 pF, RL = 10 kΩ,
fin = 1 kHz (sine wave)
(see Figure 9)
Sine-wave distortion
A or B
B or A
CL = 50 pF, RL = 10 kΩ,
fin = 10 kHz (sine wave)
(see Figure 9)
(1)
(2)
4
Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads –3 dB.
Adjust fin voltage to obtain 0 dBm at input.
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VCC
TYP
1.65 V
35
2.3 V
120
3V
175
4.5 V
195
1.65 V
>300
2.3 V
>300
3V
>300
4.5 V
>300
1.65 V
35
2.3 V
50
3V
70
4.5 V
100
1.65 V
–58
2.3 V
–58
3V
–58
4.5 V
–58
1.65 V
–42
2.3 V
–42
3V
–42
4.5 V
–42
1.65 V
0.1
2.3 V
0.025
3V
0.015
4.5 V
0.01
1.65 V
0.15
2.3 V
0.025
3V
0.015
4.5 V
0.01
UNIT
MHz
mV
dB
%
SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323L – JUNE 2001 – REVISED JANUARY 2007
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST
CONDITIONS
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
f = 10 MHz
8
9
9
11
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UNIT
pF
5
SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323L – JUNE 2001 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
B or A
A or B
VI = VCC or GND
VO
C
VC
VIH
(ON)
GND
IS
r on +
V
VI − VO
Figure 1. On-State Resistance Test Circuit
100
VCC = 1.65 V
r on − Ω
VCC = 2.3 V
VCC = 3.0 V
10
1
0.0
VCC = 4.5 V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN − V
Figure 2. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC
6
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VI * VO
W
IS
SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323L – JUNE 2001 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
VI
B or A
A or B
A
VIL
VO
C
VC
(OFF)
GND
Condition 1: VI = GND, VO = VCC
Condition 2: VI = VCC, VO = GND
Figure 3. Off-State Switch Leakage-Current Test Circuit
VCC
VCC
VI = VCC or GND
A
B or A
A or B
VO
VO = Open
VIH
C
VC
(ON)
GND
Figure 4. On-State Switch Leakage-Current Test Circuit
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7
SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323L – JUNE 2001 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
VCC
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
VCC/2
VCC/2
2 × VCC
2 × VCC
2 × VCC
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VM
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VOH
Output
VI
Output
Control
VM
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
8
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SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323L – JUNE 2001 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
0.1 µF
fin
50 Ω
B or A
A or B
VIH
C
VC
VO
RL
(ON)
GND
CL
VCC/2
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
Figure 6. Frequency Response (Switch ON)
VCC
VCC
Rin
600 Ω
VCC/2
B or A
A or B
VO
RL
600 Ω
C
VC
GND
50 Ω
CL
50 pF
VCC/2
Figure 7. Crosstalk (Control Input – Switch Output)
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9
SN74LVC1G66
SINGLE BILATERAL ANALOG SWITCH
www.ti.com
SCES323L – JUNE 2001 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
0.1 µF
50 Ω
fin
B or A
A or B
RL
VO
C
VC
VIL
CL
RL
(OFF)
GND
VCC/2
VCC/2
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
Figure 8. Feedthrough (Switch OFF)
VCC
VCC
10 µF
fin
600 Ω
VIH
VO
RL
10 kΩ
C
VC
(ON)
GND
VCC = 1.65 V, VI = 1.4 VP-P
VCC = 2.3 V, VI = 2 VP-P
VCC = 3 V, VI = 2.5 VP-P
VCC = 4.5 V, VI = 4 VP-P
Figure 9. Sine-Wave Distortion
10
10 µF
B or A
A or B
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VCC/2
CL
50 pF
PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVC1G66DBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G66DBVRE4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G66DBVRG4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G66DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G66DBVTE4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G66DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G66DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G66DCKRE4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G66DCKRG4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G66DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G66DCKTE4
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G66DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G66DRLR
ACTIVE
SOT
DRL
5
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G66DRLRG4
ACTIVE
SOT
DRL
5
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G66YZPR
ACTIVE
DSBGA
YZP
5
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2008
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G66 :
• Automotive: SN74LVC1G66-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
SN74LVC1G66DBVR
SOT-23
3000
180.0
9.2
DBV
5
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
SN74LVC1G66DBVT
SOT-23
DBV
5
250
180.0
9.2
3.23
3.17
1.37
4.0
8.0
Q3
SN74LVC1G66DCKR
SC70
DCK
5
3000
180.0
9.2
2.24
2.34
1.22
4.0
8.0
Q3
SN74LVC1G66DCKR
SC70
DCK
5
3000
180.0
9.2
2.24
2.34
1.22
4.0
8.0
Q3
SN74LVC1G66DCKT
SC70
DCK
5
250
180.0
9.2
2.24
2.34
1.22
4.0
8.0
Q3
SN74LVC1G66DRLR
SOT
DRL
5
4000
180.0
9.2
1.78
1.78
0.69
4.0
8.0
Q3
SN74LVC1G66YZPR
DSBGA
YZP
5
3000
180.0
8.4
1.02
1.52
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC1G66DBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
SN74LVC1G66DBVT
SOT-23
DBV
5
250
202.0
201.0
28.0
SN74LVC1G66DCKR
SC70
DCK
5
3000
205.0
200.0
33.0
SN74LVC1G66DCKR
SC70
DCK
5
3000
202.0
201.0
28.0
SN74LVC1G66DCKT
SC70
DCK
5
250
202.0
201.0
28.0
SN74LVC1G66DRLR
SOT
DRL
5
4000
202.0
201.0
28.0
SN74LVC1G66YZPR
DSBGA
YZP
5
3000
220.0
220.0
34.0
Pack Materials-Page 2
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