CONEXANT CX28332-3X

Advance Information
This document contains information on a product under development. The parametric information
contains target parameters that are subject to change.
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
The CX28333 is a three-channel, E3/DS3/STS-1 fully-integrated Line Interface Unit
(LIU). It is configured via external pins and does not need a microprocessor interface.
Each channel has an independent equalizer on the receive side requiring no user
configuration. Also, each channel has a programmable transmit pulse shaper that can
be set to ensure that the cross-connect pulse mask requirement is met for transmit
cable length up to 450 feet. The CX28332 is a dual-channel, and the CX28331 is a
single-channel LIU with performance identical to the CX28333.
The CX28333 gives the user new economies of scale in concentrator applications
where three DS3 or STS-1 channels are concentrated into a single STS-3 channel. By
including three independent transceivers on a chip, significant external components are
eliminated, with the exception of 1:1 coupling transformers, termination resistors, and
supply bypass capacitors.
NOTE:
In this document, "i" is used to represent the number of channels:
i = 1 (CX28331), i = 2 (CX28332), and i = 3 (CX28333).
Distinguishing Features
•
•
•
•
•
•
•
•
•
Functional Block Diagram
•
XOE
LBO
E3MODE
•
•
PDB
•
TPOS
TNEG
TCLK
PDATA/
NDATA
ENCODER
Pulse
Shaper
LINE
DRIVER
TLINEP
TLINEM/N
TCLK
TAIS
DATA
MUX
ENDECDIS
RLOOP
LLOOP
TX
Monitor
Can be used as a data transceiver
over a maximum of 900 feet of Type
734/728 coaxial cable or equivalent
in an on-premise environment
Programmable pulse filtering to meet
cross-connect pulse masks (ANSI
T1.102-1993)
Meets jitter specifications of Bellcore
GR499, GR253, and TBR24 (with
external JAT).
Large input dynamic range
Alarms for coding violation and loss
of signal
Full diagnostic loopback capability
Uses a minimum of external
components
Compatible with ITU-T G.703, G.823
Independent power down mode per
channel
Easily interfaced to the DS3/E3
Framer IC (CX28342/3/4/6/8 and
CN8330)
Selectable B3ZS/HDB3
encoding/decoding
Superior input receiver sensitivity
(< 25 mV)
Transmit monitor inputs (CX2833i-3x
series only)
TMONP
TMONM
TXMON
TMONTST
REFCLK
Physical Characteristics
•
•
•
•
•
•
80- and 100-pin ETQFP package
Single 3.3 V power supply
1 W maximum power dissipation
(CX28333)
–40 °C to +85 °C temperature range
5 V-tolerant pins
TTL digital pins
Applications
RPOS
RNEG
RCLK
RLOS
DECODER
PDATA
Clock/
NDATA
Data
DATCLK Recovery
P
N
Receiver
ALOS
RLINEP
RLINEM/N
REQH
LIU #1
LIU #2
LIU #3
•
•
•
•
•
•
•
Digital Cross-Connect Systems
Routers
ATM Switches
Channelized Line Aggregation Units
Test Equipment
Channel Service Units
Multiplexers
NOTE(S): The TX Monitor is only used with the 100-pin CX2833i-3X.
Data Sheet
100985A
June 2, 2000
CX28333EVM
TX B3ZS/HDB3 analog out
NRZTX DATA and CLK in
CH1
CH1
NRZRX DATA and CLK out
F
R
A
M
E
R
S
I
D
E
RX B3ZS/HDB3 analog in
TX B3ZS/HDB3 analog out
NRZTX DATA and CLK in
CH2
CX28333
NRZRX DATA and CLK out
CH2
RX B3ZS/HDB3 analog in
TX B3ZS/HDB3 analog out
NRZTX DATA and CLK in
CH3
CH3
NRZRX DATA and CLK out
L
I
N
E
S
I
D
E
RX B3ZS/HDB3 analog in
Loss of Signal
Clock Input
Code Violation
Control
100985_002
© 2000, Conexant Systems, Inc.
All Rights Reserved.
Information in this document is provided in connection with Conexant Systems, Inc. (“Conexant”) products. These materials are
provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no
responsibility for errors or omissions in these materials. Conexant may make changes to specifications and product descriptions at
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conflicts or incompatibilities arising from future changes to its specifications and product descriptions.
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engineer.
100985A
Conexant
Ordering Information
Operating
Temperature
Model Number
Package
Description
CX28331-1x
CX28332-1x
CX28333-1x
CX28331-3x
CX28332-3x
CX28333-3x
80-Pin ETQFP
80-Pin ETQFP
80-Pin ETQFP
100-Pin ETQFP
100-Pin ETQFP
100-Pin ETQFP
Single-channel LIU
Dual-channel LIU
Triple-channel LIU
Single channel with Transmit Monitoring
Dual channel with Transmit Monitoring
Triple channel with Transmit Monitoring
Revision History
Revision
Level
Date
A
—
May 5, 2000
100985A
Description
Initial Release
Conexant
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
100985A
Conexant
Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
1.0
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
2.0
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.3
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.4
Receive Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AGC/VGA Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The PLL Clock Recovery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loss Of Signal (LOS) Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B3ZS/HDB3 Decoder With Bipolar Violation Detector . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Squelching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-10
2-10
2-10
2-11
2-11
2-11
2-12
Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.4.1
2.5
AMI B3ZS/HDB3 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Pulse Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.3.1
Transmit Pulse Mask Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Alarm Indication Signal (AIS) Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Transmit Monitor Block (CX2833i-3x Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Jitter Generation (Intrinsic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Jitter Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Additional CX28331/CX28332/CX28333 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.5.1
2.5.2
2.5.3
Bias Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Loopback Multiplexers (MUXes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.6
Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
100985A
Conexant
v
CX28331/CX28332/CX28333
Table of Contents
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.7.1
2.7.2
3.0
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.8
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.9
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1
PCB Design Considerations for CX28331/CX28332/CX28333 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
Power Supply and Ground Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Other Passive Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
IBIS Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Recommended Vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.1
Applicable Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Appendix B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.1
vi
Evaluation Module Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Conexant
100985A
CX28331/CX28332/CX28333
List of Figures
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
List of Figures
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 1-4.
Figure 1-5.
Figure 1-6.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 2-9.
Figure 2-10.
Figure 2-11.
Figure 2-12.
Figure 3-1.
Figure B-1.
Figure B-2.
Figure B-3.
100985A
CX28331-1x Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
CX28332-1x Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
CX28333-1x Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
CX28331-3x Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
CX28332-3x Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
CX28333-3x Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Typical Application Of Single CX2833i Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Pulse Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Pulse Measurement Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Transmit Pulse Mask for DS3 Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Transmit Pulse Mask for STS-1 Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Transmit Pulse Mask for E3 Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
AIS Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Minimum Jitter Tolerance Requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Maximum Jitter Transfer Curve Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
CX2833i-1x Mechanical Drawing (80-Pin)—Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
CX2833i-3x Mechanical Drawing (100-Pin)—Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Typical CX28333 Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Recommended Schematic for the CX2833i-1x Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
Recommended Schematic for the CX2833i-3x Device (1 of 2) . . . . . . . . . . . . . . . . . . . . . . B-3
Recommended Schematic for the CX2833i-3x Device (2 of 2) . . . . . . . . . . . . . . . . . . . . . . B-4
Conexant
vii
CX28331/CX28332/CX28333
List of Figures
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
viii
Conexant
100985A
CX28331/CX28332/CX28333
List of Tables
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
List of Tables
Table 1-1.
Table 1-2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
100985A
CX28331/CX28332/CX28333 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
CX2833i-3x Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
DS3 Transmit Template Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
STS-1 Transmit Template Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
AC Characteristics (Logic Timing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Conexant
ix
CX28331/CX28332/CX28333
List of Tables
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
x
Conexant
100985A
1
1.0 Pin Description
1.1 Pin Assignments
Figures 1-1 (CX28331-1x), 1-2 (CX28332-1x), and 1-3 (CX28333-1x) illustrate
pin assignments for the 80-pin Exposed Thin Quad Flat Package (ETQFP). See
Table 1-1 for the CX2833i-1x pin descriptions.
Figures 1-4 (CX28331-3x), 1-5 (CX28332-3x), and 1-6 (CX28333-3x)
illustrate pin assignments for the 100-pin ETQFP. The 100-pin package adds
more functionality, supporting new features such as Transmit Monitoring and
Transmit Monitoring Status testing. See Table 1-2 for the CX2833i-3x pin
descriptions.
The input/output (I/O) column is coded as follows:
I = Input
O = Output
I/O = Bidirectional
P = Power
NOTE:
All digital inputs and outputs contain 75 kΩ pull-down resistors.
When a channel is disabled (i.e., the PDx pin is tied low or not connected), all
receive and transmit analog circuitry powers down. Analog inputs (RLINE) are
ignored and analog outputs (TLINE) are high impedance. Digital inputs of a
powered-down channel are still active, but ignored. Overall noise on the device
can be lowered by not driving the digital inputs of a powered-down channel.
NOTE:
100985A
When power is disconnected from the device, TLINE pins are low
impedance to ground if driven by more than one forward-bias diode
voltage (0.7 V) below ground. Additionally, driving TLINE, a
forward-bias diode voltage above the VGG pin, creates a low impedance
path from the TLINE pin to the VGG pin. Otherwise, the TLINE pins are
high impedance.
Conexant
1-1
1.0 Pin Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
RBIAS
VGG
RESET
GPD
NC
NC
NC
DVDDIO
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
Figure 1-1. CX28331-1x Pin Diagram
VSS
1
60
DVDDC
NC
2
59
ENDECDIS
NC
3
58
PD
VDD
4
57
RLOOP
VDD
5
56
LLOOP
NC
6
55
RNEG/RLCV
NC
7
54
RPOS/RNRZ
VSS
8
53
RCLK
TVSS
9
52
RLOS
TLINEP
10
51
TAIS
TLINEN
11
50
TCLK
TVDD
12
49
TPOS/TNRZ
RVDD
13
48
TNEG/NC
RLINEP
14
47
REFCLK
RLINEN
15
46
REQH
RVSS
16
45
XOE
VSS
17
44
LBO
NC
18
43
E3MODE
NC
19
42
NC
VDD
20
41
DVSSC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VDD
NC
NC
VSS
NC
NC
NC
DVSSIO
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
CX28331-1x
100985_003
1-2
Conexant
100985A
CX28331/CX28332/CX28333
1.0 Pin Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
RBIAS
VGG
RESET
GPD
PD1
RLOOP1
LLOOP1
DVDDIO
LBO1
XOE1
REQH1
RNEG1/RLCV1
RPOS1/RNRZ1
RCLK1
RLOS1
REFCLK1
TNEG1/NC1
TPOS1/TNRZ1
TCLK1
TAIS1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
Figure 1-2. CX28332-1x Pin Diagram
TVSS1
1
60
DVDDC
TLINE1P
2
59
ENDECDIS
TLINE1N
3
58
NC
TVDD1
4
57
NC
RVDD1
5
56
NC
RLINE1P
6
55
NC
RLINE1N
7
54
NC
RVSS1
8
53
NC
VSS
9
52
NC
NC
10
51
NC
NC
11
50
NC
VDD
12
49
NC
VDD
13
48
NC
NC
14
47
NC
NC
15
46
NC
VSS
16
45
NC
TVSS2
17
44
NC
TLINE2P
18
43
E3MODE
TLINE2N
19
42
NC
TVDD2
20
41
DVSSC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RVDD2
RLINE2P
RLINE2N
RVSS2
PD2
RLOOP2
LLOOP2
DVSSIO
LBO2
XOE2
REQH2
RNEG2/RLCV2
RPOS2/RNRZ2
RCLK2
RLOS2
REFCLK2
TNEG2/NC2
TPOS2/TNRZ2
TCLK2
TAIS2
CX28332-1x
100985_004
100985A
Conexant
1-3
1.0 Pin Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
RBIAS
VGG
RESET
GPD
PD1
RLOOP1
LLOOP1
DVDDIO
LBO1
XOE1
REQH1
RNEG1/RLCV1
RPOS1/RNRZ1
RCLK1
RLOS1
REFCLK1
TNEG1/NC1
TPOS1/TNRZ1
TCLK1
TAIS1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
Figure 1-3. CX28333-1x Pin Diagram
TVSS1
1
60
DVDDC
TLINE1P
2
59
ENDECDIS
TLINE1N
3
58
PD2
TVDD1
4
57
RLOOP2
RVDD1
5
56
LLOOP2
RLINE1P
6
55
RNEG2/RLCV2
RLINE1N
7
54
RPOS2/RNRZ2
RVSS1
8
53
RCLK2
TVSS2
9
52
RLOS2
51
TAIS2
TLINE2P
10
TLINE2N
11
50
TCLK2
TVDD2
12
49
TPOS2/TNRZ2
RVDD2
13
48
TNEG2/NC2
RLINE2P
14
47
REFCLK2
RLINE2N
15
46
REQH2
RVSS2
16
45
XOE2
TVSS3
17
44
LBO2
TLINE3P
18
43
E3MODE
TLINE3N
19
42
NC
TVDD3
20
41
DVSSC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RVDD3
RLINE3P
RLINE3N
RVSS3
PD3
RLOOP3
LLOOP3
DVSSIO
LBO3
XOE3
REQH3
RNEG3/RLCV3
RPOS3/RNRZ3
RCLK3
RLOS3
REFCLK3
TNEG3/NC3
TPOS3/TNRZ3
TCLK3
TAIS3
CX28333-1x
100985_005
1-4
Conexant
100985A
CX28331/CX28332/CX28333
1.0 Pin Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
Table 1-1. CX2833i-1x Pin Definitions (1 of 6)
Pin #
Signal Name
Description
I/O/P
Notes
Ch1 positive receive
data
I
Ch1 negative receive
data
I
Differential inputs for each channel
from its respective receive coax
line. The RX expects balanced
differential inputs, usually achieved
using a 1:1 transformer.
The inputs are internally DC biased
to 1.9 V.
CX28331-1x CX28332-1x CX28333-1x
Coaxial Line Pins
14
—
—
RLINEP
—
6
6
RLINE1P
15
—
—
RLINEN
—
7
7
RLINE1N
—
22
14
RLINE2P
Ch2 positive receive
data
I
—
23
15
RLINE2N
Ch2 negative receive
data
I
—
—
22
RLINE3P
Ch3 positive receive
data
I
—
—
23
RLINE3N
Ch3 negative receive
data
I
10
—
—
TLINEP
O
—
2
2
TLINE1P
Ch1 positive transmit
data
11
—
—
TLINEN
O
—
3
3
TLINE1N
Ch1 negative transmit
data
—
18
10
TLINE2P
Ch2 positive transmit
data
O
—
19
11
TLINE2N
Ch2 negative transmit
data
O
—
—
18
TLINE3P
Ch3 positive transmit
data
O
—
—
19
TLINE3N
Ch3 negative transmit
data
O
100985A
Conexant
Differential, coax-driver balanced
outputs for pulse-shaped AMI
B3ZS/HDB3 encoded waveforms
for each channel.
These pins should be connected to
the primary side of the 1:1
transformer through two
backmatch resistors (see Appendix
B).
1-5
1.0 Pin Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
Table 1-1. CX2833i-1x Pin Definitions (2 of 6)
Pin #
Signal Name
Description
I/O/P
Notes
CX28331-1x CX28332-1x CX28333-1x
Digital Data Pins
1-6
54
—
—
RPOS/
RNRZ
Ch1 receive Positive rail
or NRZ data
O
—
68
68
RPOS1/
RNRZ1
55
—
—
RNEG/
RLCV
—
69
69
RNEG1/
RLCV1
—
33
54
RPOS2/
RNRZ2
—
32
55
—
—
—
Ch1 receive Negative rail
or line code violation
O
When ENDECDIS = 1, these outputs
are positive and negative AMI data
(RPOS and RNEG).
Ch2 receive Positive rail
or NRZ data
O
RNEG2/
RLCV2
Ch2 receive Negative rail
or line code violation
O
When ENDECDIS = 0, these outputs
are decoded NRZ data (RNRZ) and
line code violation (RLCV). A line
code violation is indicated when
RLCV = 1.
33
RPOS3/
RNRZ3
Ch3 receive Positive rail
or NRZ data
O
—
32
RNEG3/
RLCV3
Ch3 receive Negative rail
or line code violation
O
53
—
—
RCLK
Receive clock Ch1
O
—
67
67
RCLK1
—
34
53
RCLK2
Receive clock Ch2
O
—
—
34
RCLK3
Receive clock Ch3
O
49
—
—
TPOS/
TNRZ
Ch1 transmit Positive
rail or NRZ data
I
—
63
63
TPOS1/
TNRZ1
Synchronized transmit data
intended to be strobed in by the
corresponding TCLK.
48
—
—
TNEG/
NC
Ch1 transmit Negative
rail or no connect data
I
—
64
64
TNEG1/
NC1
When ENDECDIS = 1, these inputs
are expected to be positive and
negative AMI data (TPOS and
TNEG).
—
38
49
TPOS2/
TNRZ2
Ch2 transmit Positive or
NRZ data
I
—
37
48
TNEG2/
NC2
Ch2 transmit Negative
rail or no connect data
I
When ENDECDIS = 0, these inputs
are expected to be uncoded NRZ
data (TNRZ) and no connects (NC).
—
—
38
TPOS3/
TNRZ3
Ch3 transmit Positive or
NRZ data
I
—
—
37
TNEG3/
NC3
Ch3 transmit Negative
rail or no connect data
I
Conexant
Resynchronized receive data
intended to be strobed out by the
corresponding RCLK.
See notes on the ENDECDIS pin in
the Control Signals section.
Recovered clock for each channel
receiver, intended for strobing the
corresponding RDAT into the
following framer or logic.
See notes on the ENDECDIS pin in
the Control Signals section.
100985A
CX28331/CX28332/CX28333
1.0 Pin Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
Table 1-1. CX2833i-1x Pin Definitions (3 of 6)
Pin #
Signal Name
Description
I/O/P
Notes
Transmit clock Ch1
I
Transmit bit clock input for strobing
with transmit data into the CX2833i.
CX28331-1x CX28332-1x CX28333-1x
50
—
—
TCLK
—
62
62
TCLK1
—
39
50
TCLK2
Transmit clock Ch2
I
—
—
39
TCLK3
Transmit clock Ch3
I
52
—
—
RLOS
Loss of signal Ch1
O
—
66
66
RLOS1
—
35
52
RLOS2
Loss of signal Ch2
O
—
—
35
RLOS3
Loss of signal Ch3
O
Loss Of Signal (LOS) indication for
each channel, as determined by
insufficient pulse density. Signal
loss detected when RLOS = 1. An
LOS will be asserted when 175 ±75
0s occur in a row and deasserted
when the pulse density is between
28% and 33% (DS3/STS-1) (i.e., a
1s density).
Control Signals
59
59
59
ENDECDIS
Encoder/decoder
disable (for all channels)
I
1 = Dual rail pulse coded data
format. Input transmit data pins
TPOS, TNRZ, TNEG and NC are
interpreted as TPOS and TNEG
(encoded positive and negative rail
data). Output receive data pins
RPOS and RNRZ, and RNEG and
RLCV are interpreted as RPOS and
RNEG, with RPOS having a positive
pulse in place of every positive AMI
pulse and RNEG having a negative
pulse in place of every negative AMI
pulse.
0 = NRZ format. Transmit data pins
TPOS and TNEG are interpreted as
TNRZ and NC (not connected).
Receive data pins RPOS and RNEG
are interpreted as RNRZ and RLCV.
In this mode, all line code violations
are reported as active high on
RLCV.
51
—
—
TAIS
I
—
61
61
TAIS1
Transmit Ch1 AIS mode
enable
—
40
51
TAIS2
Transmit Ch2 AIS mode
enable
I
—
—
40
TAIS3
Transmit Ch3 AIS mode
enable
I
Transmission of Alarm Indication
Signal (AIS) for a given channel.
Replace transmit data with AIS
signal. The AMI form of AIS
supported is alternating 1s.
(+1, -1, +1, -1, +1, ...)
Looping takes precedence over AIS.
1 = AIS mode enabled
0 = AIS mode disabled
100985A
Conexant
1-7
1.0 Pin Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
Table 1-1. CX2833i-1x Pin Definitions (4 of 6)
Pin #
Signal Name
Description
I/O/P
Notes
E3MODE
I
When the pin is set to high, it
enables the E3 mode on all
channels, instead of the DS3/STS-1
mode. This also changes the pulse
shaper to E3 mode and overrides all
LBO pins. It also changes the
encoder/decoder from B3ZS mode
to HDB3 mode.
1 = E3 mode
0 = DS3/STS-1 mode
Transmit line Ch1
build-out mode
I
Line build-out mode per channel,
based on the length of cable on the
transmit side of the cross-connect
block. This bit is overridden and the
pulse shaper is disabled (no pulse
shaping) if E3MODE = 1.
1 = Inserts line build-out into the
transmit channel. Usually used
when the transmit cable is less than
350 feet in length.
0 = Line build-out bypassed (not
inserted). Usually used when the
transmit cable is greater than 350
feet in length.
CX28331-1x CX28332-1x CX28333-1x
1-8
43
43
43
E3MODE
44
—
—
LBO
—
72
72
LBO1
—
29
44
LBO2
Transmit line Ch2
build-out mode
I
—
—
29
LBO3
Transmit line Ch3
build-out mode
I
56
—
—
LLOOP
I
—
74
74
LLOOP1
Local loopback enable
Ch1
—
27
56
LLOOP2
Local loopback enable
Ch2
I
—
—
27
LLOOP3
Local loopback enable
Ch3
I
57
—
—
RLOOP
I
—
75
75
RLOOP1
Remote loopback enable
Ch1
—
26
57
RLOOP2
Remote loopback enable
Ch2
I
—
—
26
RLOOP3
Remote loopback enable
Ch3
I
45
—
—
XOE
I
—
71
71
XOE1
Transmit output enable
Ch1
—
30
45
XOE2
Transmit output enable
Ch2
I
—
—
30
XOE3
Transmit output enable
Ch3
I
Conexant
Local loopback enable per channel.
The transmit data is looped back
immediately from the encoder to
the decoder in place of the received
data.
1 = local loopback enabled
0 = local loopback disabled
Remote loopback enable per
channel. The receive data, retimed
after clock recovery, is looped back
into the AMI generator in place of
the transmit data.
1 = remote loopback enabled
0 = remote loopback disabled
Transmit output enable per channel.
1 = transmit line output driver
enabled
0 = transmit output driver set to
high impedance state
100985A
CX28331/CX28332/CX28333
1.0 Pin Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
Table 1-1. CX2833i-1x Pin Definitions (5 of 6)
Pin #
Signal Name
Description
I/O/P
Notes
I
The equalizer in the CX2833i has
two gain settings. The higher gain
setting is designed to optimally
equalize a nominally-shaped (meets
the pulse template), pulse-driven
DS3 or STS-1 waveform that is
driven through 0–900 feet of cable.
Square-shaped pulses such as E3
or DS3-HIGH require less
high-frequency gain and should use
the low EQ gain setting.
CX28331-1x CX28332-1x CX28333-1x
46
—
—
REQH
Ch1 Receive High EQ
Gain Enable
—
70
70
REQH1
—
31
46
REQH2
Ch2 Receive High EQ
Gain Enable
—
—
31
REQH3
Ch3 Receive High EQ
Gain Enable
I
REQH = 1 high EQ gain
(DS3/STS-1 modes)
REQH = 0 low EQ gain (E3/DS3
Square Modes)
Power/Ground
12
—
—
TVDD
TX power Ch1
P
—
4
4
TVDD1
—
20
12
—
—
9
TVDD2
TX power Ch2
P
20
TVDD3
TX power Ch3
P
—
—
TVSS
TX ground Ch1
P
—
1
1
TVSS1
—
17
9
TVSS2
TX ground Ch2
P
—
—
17
TVSS3
TX ground Ch3
P
13
—
—
RVDD
RX power Ch1
P
—
5
5
RVDD1
—
21
13
RVDD2
RX power Ch2
P
—
—
21
RVDD3
RX power Ch3
P
16
—
—
RVSS
RX ground Ch1
P
—
8
8
RVSS1
—
24
16
RVSS2
RX ground Ch2
P
—
—
24
RVSS3
RX ground Ch3
P
60
60
60
DVDDC
Digital core power
P
Digital core power for all channels
(3.3 V).
41
41
41
DVSSC
Digital core ground
P
Digital core ground for all channels.
79
79
79
VGG
5 V/3.3 V ESD pin (1)
P
5 V supply for 5 V-tolerant, digital
pad ESD diodes. No static power is
drawn from pin.
73
73
73
DVDDIO
Digital I/O power
P
Connect to 3.3 V digital power.
28
28
28
DVSSIO
Digital ground
P
Digital ground.
100985A
Conexant
Power pins for transmit circuitry
per channel (3.3 V).
Ground pins for transmit circuitry
per channel.
Power pins for receive circuitry per
channel (3.3 V).
Connect to 3.3 V power.
Ground pins for receive circuitry
per channel.
Connect to ground.
1-9
1.0 Pin Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
Table 1-1. CX2833i-1x Pin Definitions (6 of 6)
Pin #
Signal Name
Description
I/O/P
Notes
CX28331-1x CX28332-1x CX28333-1x
4, 5, 20, 21
12, 13
—
VDD
Power
P
Connect to 3.3 V power.
1, 8, 17, 24
9, 16
—
VSS
Ground
P
Connect to ground.
Power down for Ch1
I
Power down transceiver channel
0 = Power down channel (off)
1 = Channel active (on)
Note: A special power-down mode
exists when all three PDBs are set
low. This special mode shuts off the
entire chip (including biasing). This
is useful for static Idd testing.
Miscellaneous
58
—
—
PD
—
76
76
PD1
—
25
58
PD2
Power down for Ch2
I
—
—
25
PD3
Power down for Ch3
I
47
—
—
REFCLK
Reference clock for Ch1
I
—
65
65
REFCLK1
—
36
47
REFCLK2
Reference clock for Ch2
I
—
—
36
REFCLK3
Reference clock for Ch3
I
80
80
80
RBIAS
Bias resistor
O
A 12.1 kΩ ± 1% resistor tied from
this pin to ground provides the
current reference to the entire
chip.(2)
78
78
78
Reset
Reset
I/O
Asynchronous reset (reset entire
device).
77
77
77
GPD
Global Power down
I/O
Power down (Static Idd testing).
0 = Power down disable
1 = Power down active
2, 3, 6, 7, 18,
19, 22, 23,
25, 26, 27,
29, 30, 31,
32, 33, 34,
35, 36, 37,
38, 39, 40,
42, 61, 62,
63, 64, 65,
66, 67, 68,
69, 70, 71,
72, 74, 75,
76
10, 11, 14,
15, 42,
44–58
42
NC
No connect
—
Not connected.
Reference clock from off-chip.
This clock should be set to one of
the following:
• E3 rate (34.368 MHz)
• DS3 rate (44.736 MHz)
• STS-1 rate (51.84 MHz)
The clock rate should correspond to
the mode of operation that has been
chosen for the channel.
NOTE(S):
(1)
This pin should be connected to 3.3 V in an all-3.3 V design.
Placing a capacitor from this pin to ground may result in instabilities.
3. All digital input pins contain a 75 kΩ pull-down resistor from input to DVSS.
(2)
1-10
Conexant
100985A
CX28331/CX28332/CX28333
1.0 Pin Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VSS
RBIAS
VGG
RESET
GPD
NC
NC
NC
DVDDIO
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Figure 1-4. CX28331-3x Pin Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CX28331-3x
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DVDDC
ENDECDIS
PD
RLOOP
LLOOP
RNEG/RLCV
RPOS/RNRZ
RCLK
RLOS
NC
NC
NC
TAIS
TCLK
TPOS/TNRZ
TNEG/NC
TLOS
REFCLK
REQH
XOE
LBO
TMONTST
E3MODE
NC
DVSSC
VDD
NC
NC
VSS
NC
NC
NC
DVSSIO
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
NC
NC
VDD
VDD
NC
NC
VSS
TVSS
TMONP
TLINEP
TLINEM
TMONM
TVDD
RVDD
RLINEP
RLINEM
RVSS
VSS
NC
NC
NC
NC
VDD
100985_015
100985A
Conexant
1-11
1.0 Pin Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
TVSS1
RBIAS
VGG
RESET
GPD
PD1
RLOOP1
LLOOP1
DVDDIO
LBO1
XOE1
REQH1
NC
NC
NC
RNEG1/RLCV1
RPOS1/RNRZ1
RCLK1
RLOS1
REFCLK1
TLOS1
TNEG1/NC1
TPOS1/TNRZ1
TCLK1
TAIS1
Figure 1-5. CX28332-3x Pin Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CX28332-3x
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DVDDC
ENDECDIS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TMONTST
E3MODE
NC
DVSSC
RVDD2
RLINE2P
RLINE2M
RVSS2
PD2
RLOOP2
LLOOP2
DVSSIO
LBO2
XOE2
REQH2
NC
NC
NC
RNEG2/RLCV2
RPOS2/RNRZ2
RCLK2
RLOS2
REFCLK2
TLOS2
TNEG2/NC2
TPOS2/TNRZ2
TCLK2
TAIS2
NC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
TMON1P
TLINE1P
TLINE1M
TMON1M
TVDD1
RVDD1
RLINE1P
RLINE1M
RVSS1
VSS
NC
NC
NC
NC
VDD
VDD
NC
NC
VSS
TVSS2
TMON2P
TLINE2P
TLINE2M
TMON2M
TVDD2
100985_016
1-12
Conexant
100985A
CX28331/CX28332/CX28333
1.0 Pin Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
TVSS1
RBIAS
VGG
RESET
GPD
PD1
RLOOP1
LLOOP1
DVDDIO
LBO1
XOE1
REQH1
NC
NC
NC
RNEG1/RLCV1
RPOS1/RNRZ1
RCLK1
RLOS1
REFCLK1
TLOS1
TNEG1/NC1
TPOS1/TNRZ1
TCLK1
TAIS1
Figure 1-6. CX28333-3x Pin Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CX28333-3x
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DVDDC
ENDECDIS
PD2
RLOOP2
LLOOP2
RNEG2 / RLCV2
RPOS2 / RNRZ2
RCLK2
RLOS2
NC
NC
NC
TAIS2
TCLK2
TPOS2/TNRZ2
TNEG2/NC2
TLOS2
REFCLK2
REQH2
XOE2
LBO2
TMONTST
E3MODE
NC
DVSSC
RVDD3
RLINE3P
RLINE3M
RVSS3
PD3
RLOOP3
LLOOP3
DVSSIO
LBO3
XOE3
REQH3
NC
NC
NC
RNEG3/RLCV3
RPOS3/RNRZ3
RCLK3
RLOS3
REFCLK3
TLOS3
TNEG3/NC3
TPOS3/TNRZ3
TCLK3
TAIS3
NC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
TMON1P
TLINE1P
TLINE1M
TMON1M
TVDD1
RVDD1
RLINE1P
RLINE1M
RVSS1
TVSS2
TMON2P
TLINE2P
TLINE2M
TMON2M
TVDD2
RVDD2
RLINE2P
RLINE2M
RVSS2
TVSS3
TMON3P
TLINE3P
TLINE3M
TMON3M
TVDD3
100985_006
100985A
Conexant
1-13
1.0 Pin Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
Table 1-2. CX2833i-3x Pin Definitions (1 of 8)
Pin #
Signal Name
Description
I/O/P
Notes
Ch1 positive
receive data
I
Ch1 negative
receive data
I
Differential inputs for each channel from its
respective receive coax line. The RX expects
balanced differential inputs, usually
achieved using a 1:1 transformer.
The inputs are internally DC biased to 1.9 V.
CX28331-3x CX28332-3x CX28333-3x
Coaxial Line Pins
1-14
17
—
—
RLINEP
—
7
7
RLINE1P
18
—
—
RLINEM
—
8
8
RLINE1M
—
27
17
RLINE2P
Ch2 positive
receive data
I
—
28
18
RLINE2M
Ch2 negative
receive data
I
—
—
27
RLINE3P
Ch3 positive
receive data
I
—
—
28
RLINE3M
Ch3 negative
receive data
I
12
—
—
TLINEP
O
—
2
2
TLINE1P
Ch1 positive
transmit data
13
—
—
TLINEM
O
—
3
3
TLINE1M
Ch1 negative
transmit data
—
22
12
TLINE2P
Ch2 positive
transmit data
O
—
23
13
TLINE2M
Ch2 negative
transmit data
O
—
—
22
TLINE3P
Ch3 positive
transmit data
O
—
—
23
TLINE3M
Ch3 negative
transmit data
O
Conexant
Differential, coax-driver balanced outputs
for pulse-shaped AMI B3ZS/HDB3 encoded
waveforms for each channel.
These pins should be connected to the
primary side of the 1:1 transformer through
two backmatch resistors (see Appendix B).
100985A
CX28331/CX28332/CX28333
1.0 Pin Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
Table 1-2. CX2833i-3x Pin Definitions (2 of 8)
Pin #
Signal Name
Description
I/O/P
Notes
O
Resynchronized receive data intended to be
strobed out by the corresponding RCLK.
CX28331-3x CX28332-3x CX28333-3x
Digital Data Pins
69
—
—
RPOS/
RNRZ
—
84
84
RPOS1/
RNRZ1
70
—
—
RNEG/
RLCV
—
85
85
RNEG1/
RLCV1
—
41
69
—
40
—
Ch1 receive
Positive rail or
NRZ data
Ch1 receive
Negative rail or
line code
violation
O
When ENDECDIS = 1, these outputs are
positive and negative AMI data (RPOS and
RNEG).
RPOS2/
RNRZ2
Ch2 receive
Positive rail or
NRZ data
O
When ENDECDIS = 0, these outputs are
decoded NRZ data (RNRZ) and line code
violation (RLCV). A line code violation is
indicated when RLCV = 1.
70
RNEG2/
RLCV2
Ch2 receive
Negative rail or
line code
violation
O
See notes on the ENDECDIS pin in the
Control Signals section.
—
41
RPOS3/
RNRZ3
Ch3 receive
Positive rail or
NRZ data
O
—
—
40
RNEG3/
RLCV3
Ch3 receive
Negative rail or
line code
violation
O
68
—
—
RCLK
O
—
83
83
RCLK1
Receive clock
Ch1
—
42
68
RCLK2
Receive clock
Ch2
O
—
—
42
RCLK3
Receive clock
Ch3
O
100985A
Conexant
Recovered clock for each channel receiver,
intended for strobing the corresponding
RDAT into the following framer or logic.
1-15
1.0 Pin Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
Table 1-2. CX2833i-3x Pin Definitions (3 of 8)
Pin #
Signal Name
Description
I/O/P
Notes
Ch1 transmit
Positive rail or
NRZ data
I
Synchronized transmit data intended to be
strobed in by the corresponding TCLK.
Ch1 transmit
Negative rail or
no connect data
I
CX28331-3x CX28332-3x CX28333-3x
1-16
61
—
—
TPOS/
TNRZ
—
78
78
TPOS1/
TNRZ1
60
—
—
TNEG/
NC
—
79
79
TNEG1/
NC1
—
47
61
TPOS2/
TNRZ2
Ch2 transmit
Positive or NRZ
data
I
—
46
60
TNEG2/
NC2
Ch2 transmit
Negative data or
no connect data
I
—
—
47
TPOS3/
TNRZ3
Ch3 transmit
Positive or NRZ
data
I
—
—
46
TNEG3/NC3
Ch3 transmit
Negative data or
no connect data
I
62
—
—
TCLK
I
—
77
77
TCLK1
Transmit clock
Ch1
—
48
62
TCLK2
Transmit clock
Ch2
I
—
—
48
TCLK3
Transmit clock
Ch3
I
67
—
—
RLOS
O
—
82
82
RLOS1
Loss of signal
Ch1
—
43
67
RLOS2
Loss of signal
Ch2
O
—
—
43
RLOS3
Loss of signal
Ch3
O
Conexant
When ENDECDIS = 1, these inputs are
expected to be positive and negative AMI
data (TPOS and TNEG).
When ENDECDIS = 0, these inputs are
expected to be uncoded NRZ data (TNRZ)
and no connects (NC).
See notes on the ENDECDIS pin in the
Control Signal section.
Transmit bit clock input for strobing with
transmit data into the CX2833i.
Loss Of Signal (LOS) indication for each
channel, as determined by insufficient pulse
density. Signal loss detected when RLOS =
1. An LOS will be asserted when 175 ±75 0s
occur in a row and deasserted when the
pulse density is between 28% and 33%
(DS3/STS-1) (i.e., a 1s density).
100985A
CX28331/CX28332/CX28333
1.0 Pin Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
Table 1-2. CX2833i-3x Pin Definitions (4 of 8)
Pin #
Signal Name
Description
I/O/P
Notes
I
1 = Dual rail pulse coded data format. Input
transmit data pins TPOS, TNRZ, TNEG and
NC are interpreted as TPOS and TNEG
(encoded positive and negative rail data).
Output receive data pins RPOS and RNRZ,
and RNEG and RLCV are interpreted as
RPOS and RNEG, with RPOS having a
positive pulse in place of every positive AMI
pulse and RNEG having a negative pulse in
place of every negative AMI pulse.
CX28331-3x CX28332-3x CX28333-3x
Control Signals
74
74
74
ENDECDIS
Encoder/decoder
disable (for all
channels)
0 = NRZ format. Transmit data pins TPOS
and TNEG are interpreted as TNRZ and NC
(not connected). Receive data pins RPOS
and RNEG are interpreted as RNRZ and
RLCV. In this mode, all line code violations
are reported as active high on RLCV.
63
—
—
TAIS
Transmit Ch1
AIS mode enable
I
—
76
76
TAIS1
—
49
63
TAIS2
Transmit Ch2
AIS mode enable
I
—
—
49
TAIS3
Transmit Ch3
AIS mode enable
—
53
53
53
E3MODE
55
—
—
LBO
—
91
91
LBO1
—
34
55
—
—
34
Transmission of Alarm Indication Signal
(AIS) for a given channel. Replace transmit
data with AIS signal. The AMI form of AIS
supported is alternating 1s.
(+1, -1, +1, -1, +1, ...)
Looping takes precedence over AIS.
1 = AIS mode enabled
0 = AIS mode disabled
E3MODE
I
When the pin is set to high, it enables the
E3 mode on all channels, instead of the
DS3/STS-1 mode. This also changes the
pulse shaper to E3 mode and overrides all
LBO pins. It also changes the
encoder/decoder from B3ZS mode to HDB3
mode.
1 = E3 mode
0 = DS3/STS-1 mode
Transmit line
Ch1 build-out
mode
I
LBO2
Transmit line
Ch2 build-out
mode
I
Line build-out mode per channel, based on
the length of cable on the transmit side of
the cross-connect block. This bit is
overridden and the pulse shaper is disabled
(no pulse shaping) if E3MODE = 1.
LBO3
Transmit line
Ch3 build-out
mode
I
1 = Inserts line build-out into the transmit
channel. Usually used when the transmit
cable is less than 350 feet in length.
0 = Line build-out bypassed (not inserted).
Usually used when the transmit cable is
greater than 350 feet in length.
100985A
Conexant
1-17
1.0 Pin Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
Table 1-2. CX2833i-3x Pin Definitions (5 of 8)
Pin #
Signal Name
Description
I/O/P
Notes
Local loopback
enable Ch1
I
CX28331-3x CX28332-3x CX28333-3x
71
—
—
LLOOP
—
93
93
LLOOP1
—
32
71
LLOOP2
Local loopback
enable Ch2
I
Local loopback enable per channel. The
transmit data is looped back immediately
from the encoder to the decoder in place of
the received data.
—
—
32
LLOOP3
Local loopback
enable Ch3
I
1 = local loopback enabled
0 = local loopback disabled
72
—
—
RLOOP
I
—
94
94
RLOOP1
Remote
loopback enable
Ch1
—
31
72
RLOOP2
Remote
loopback enable
Ch2
I
Remote loopback enable per channel. The
receive data, retimed after clock recovery, is
looped back into the AMI generator in place
of the transmit data.
1 = remote loopback enabled
0 = remote loopback disabled
—
—
31
RLOOP3
Remote
loopback enable
Ch3
I
56
—
—
XOE
I
Transmit output enable per channel.
—
90
90
XOE1
Transmit output
enable Ch1
—
35
56
XOE2
Transmit output
enable Ch2
I
1 = transmit line output driver enabled
0 = transmit output driver set to high
impedance state
—
—
35
XOE3
Transmit output
enable Ch3
I
57
—
—
REQH
I
—
89
89
REQH1
Ch1 Receive
High EQ Gain
Enable
—
36
57
REQH2
Ch2 Receive
High EQ Gain
Enable
I
—
—
36
REQH3
Ch3 Receive
High EQ Gain
Enable
I
The equalizer in the CX2833i has two gain
settings. The higher gain setting is designed
to optimally equalize a nominally-shaped
(meets the pulse template), pulse-driven
DS3 or STS-1 waveform that is driven
through 0–900 feet of cable.
Square-shaped pulses such as E3 or
DS3-HIGH require less high-frequency gain
and should use the low EQ gain setting.
REQH = 1 high EQ gain (DS3/STS-1 modes)
REQH = 0 low EQ gain (E3/DS3
Square Modes)
Power/Ground
15
1-18
—
—
TVDD
TX power Ch1
P
5
5
TVDD1
—
25
15
TVDD2
TX power Ch2
P
—
—
25
TVDD3
TX power Ch3
P
Conexant
Power pins for transmit circuitry per
channel (3.3 V).
100985A
CX28331/CX28332/CX28333
1.0 Pin Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
Table 1-2. CX2833i-3x Pin Definitions (6 of 8)
Pin #
Signal Name
Description
I/O/P
Notes
CX28331-3x CX28332-3x CX28333-3x
10
—
—
TVSS
TX ground Ch1
P
—
100
100
TVSS1
—
20
10
—
—
16
Ground pins for transmit circuitry per
channel.
TVSS2
TX ground Ch2
P
20
TVSS3
TX ground Ch3
P
—
—
RVDD
RX power Ch1
P
—
6
6
RVDD1
—
26
16
RVDD2
RX power Ch2
P
—
—
26
RVDD3
RX power Ch3
P
19
—
—
RVSS
RX ground Ch1
P
—
9
9
RVSS1
—
29
19
RVSS2
RX ground Ch2
P
—
—
29
RVSS3
RX ground Ch3
P
75
75
75
DVDDC
Digital core
power
P
Digital core power for all channels (3.3 V).
51
51
51
DVSSC
Digital core
ground
P
Digital core ground for all channels.
98
98
98
VGG
5 V/3.3 V ESD
pin (1)
P
5 V supply for 5 V-tolerant, digital pad ESD
diodes. No static power is drawn from pin.
92
92
92
DVDDIO
Digital I/O power
P
Connect to 3.3 V digital power.
33
33
33
DVSSIO
Digital ground
P
Digital ground.
5, 6, 25, 26
15, 16
—
VDD
Power
P
Connect to 3.3 V power.
9, 20, 29,
100
10, 19
—
VSS
Ground
P
Connect to ground.
Power down for
Ch1
I
Power down transceiver channel
0 = Power down channel (off)
1 = Channel active (on)
Power down for
Ch2
I
Power down for
Ch3
I
Power pins for receive circuitry per channel
(3.3 V).
Connect to 3.3 V power.
Ground pins for receive circuitry per
channel.
Connect to ground.
Miscellaneous
73
—
—
PD
—
95
95
PD1
—
30
73
PD2
—
100985A
—
30
PD3
Conexant
Note: A special power-down mode exists
when all three PDBs are set low. This
special mode shuts off the entire chip
(including biasing). This is useful for static
Idd testing.
1-19
1.0 Pin Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
Table 1-2. CX2833i-3x Pin Definitions (7 of 8)
Pin #
Signal Name
Description
I/O/P
Reference clock
for Ch1
I
Notes
CX28331-3x CX28332-3x CX28333-3x
1-20
58
—
—
REFCLK
—
81
81
REFCLK1
—
44
58
REFCLK2
Reference clock
for Ch2
I
—
—
44
REFCLK3
Reference clock
for Ch3
I
99
80
99
RBIAS
Bias resistor
O
A 12.1 kΩ ± 1% resistor tied from this pin
to ground provides the current reference to
the entire chip.(2)
97
97
97
Reset
Reset
I/O
Asynchronous reset (reset entire device).
96
96
96
GPD
Global Power
down
I/O
Power down (Static Idd testing).
0 = Power down disable
1 = Power down active
11
—
—
TMONP
I
—
1
1
TMON1P
Ch1 positive
input
14
—
—
TMONM
I
—
4
4
TMON1M
Ch1 negative
input
—
21
11
TMON2P
Ch2 positive
input
I
—
24
14
TMON2M
Ch2 negative
input
I
—
—
21
TMON3P
Ch3 positive
input
I
—
—
24
TMON3M
Ch3 negative
input
I
59
—
—
TLOS
O
—
80
80
TLOS1
TX loss of signal
Ch1 Output
—
45
59
TLOS2
TX loss of signal
Ch2 Output
O
—
—
45
TLOS3
TX loss of signal
Ch3 Output
O
54
54
54
TMONTST
TX monitor test
pin
I
Conexant
Reference clock from off-chip.
This clock should be set to one of the
following:
• E3 rate (34.368 MHz)
• DS3 rate (44.736 MHz)
• STS-1 rate (51.84 MHz)
The clock rate should correspond to the
mode of operation that has been chosen for
the channel.
Transmit monitor input pins are normally
tied to their respective transmit line
outputs, i.e., (TMON1P ⇒ TLINE1P and
TMON1M ⇒ TLINE1M).
Loss of signal outputs are active high
when the monitor inputs detect no signal.
The TX monitor test pin will assert all
TLOS outputs when TMONTST is high.
This is used to test board level functionality
downstream from the TLOS outputs.
100985A
CX28331/CX28332/CX28333
1.0 Pin Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
Table 1-2. CX2833i-3x Pin Definitions (8 of 8)
Pin #
Signal Name
Description
I/O/P
Notes
CX28331-3x CX28332-3x CX28333-3x
1–4, 7, 8,
21–24, 27,
28, 30–32,
34–50, 52,
64–66,
76–91,
93–95
11–14,
17–18,
37–39, 50,
52, 55–73,
86–88
37, 38, 39,
50, 64, 65,
66, 86, 87,
88
52
No connect
—
Not connected.
NOTE(S):
(1)
This pin should be connected to 3.3 V in an all-3.3 V design.
Placing a capacitor from this pin to ground may result in instabilities.
3. All digital input pins contain a 75 kΩ pull-down resistor from input to DVSS.
(2)
100985A
Conexant
1-21
1.0 Pin Description
1.1 Pin Assignments
1-22
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Conexant
100985A
2
2.0 Functional Description
2.1 Overview
CX28333 is a triple E3/DS3/STS-1 Line Interface Unit (LIU). It is the physical
layer interface between the data framer (or other terminal-side equipment) and the
electrical cable used for data transmission.
The CX28333 LIU consists of three independent data transceivers that can
operate over type 734/728 coaxial cable at the rates of 34.368 Mbps (E3), 44.736
Mbps (DS3), and 51.84 Mbps (STS-1). The transmit side takes an NRZ or
already-encoded dual rail input and encodes it into AMI B3ZS (for DS3/STS-1)
or HDB3 (for E3) analog waveforms to be transmitted over the coaxial cable. The
receiver side takes in the attenuated and distorted analog receive signal and
equalizes, slices, and resynchronizes the signal before decoding it to the NRZ
output or sending out a non-decoded dual rail.
CX28331 and CX28332 are single- and dual-E3/DS3/STS-1 LIUs,
respectively. In all respects, their performance and features are identical to the
CX28333.
The architecture of the CX2833i includes the following internal functions for
each channel:
Transmitter:
•
•
•
•
•
AMI B3ZS/HDB3 encoder
pulse shaper
line driver
Alarm Indication Signal (AIS) insertion
transmit monitor
Receiver:
•
•
•
•
•
•
•
100985A
receive sensitivity
Automatic Gain Control (AGC)
receive equalizer
Clock Recovery circuit
Loss Of Signal (LOS) detector
B3ZS/HDB3 decoder with bipolar violation detector
data squelching
Conexant
2-1
2.0 Functional Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.1 Overview
Additional Functions:
•
•
•
bias generator
power-on reset
loopback MUXes
In addition, each channel has the ability to perform remote and local
loopbacks. Figure 2-1 illustrates a typical application using the CX2833i in a
channel.
External pins are provided to configure the various line rates and formats for
each channel.
The CX2833i is used as a data transceiver over a coaxial cable that is up to
900 feet long (or up to 450 feet from the DSX) in an on-premise environment
within any public or private networks which use these data rates.
Figure 2-1. Typical Application Of Single CX2833i Channel
TX
RX
0–450 ft COAX
(type 734/728)
0–450 ft COAX
(type 734/728)
0–450 ft COAX
(type 734/728)
DSX
DSX
0–450 ft COAX
(type 734/728)
RX
TX
100604_012
2-2
Conexant
100985A
CX28331/CX28332/CX28333
2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.2 Transmitter
2.2 Transmitter
This section describes the detailed operation of the various blocks in the CX2833i
transmitter.
2.2.1 AMI B3ZS/HDB3 Encoder
ENDECDIS and the E3MODE pins configure the encoder mode.
When ENDECDIS = 0, the encoder is receiving non-encoded Nonreturn to
Zero (NRZ) data on the TNRZ (TPOS) pin alone, and the NC (no connect)
(TNEG) pin is ignored.
Data is encoded into a representation of a three-level B3ZS (E3MODE = 0) or
HDB3 (E3MODE = 1) signal (conforming to the coding rules as specified in
Appendix A) before going on to the pulse shaper in the form of two binary signals
representing the positive and negative three-level pulses.
When ENDECDIS = 1, the encoder is disabled. The encoder passes
already-encoded data over TPOS (TNRZ) and TNEG (NC) to the pulse shaper.
The transmit digital data is clocked into the chip via a rising TCLK edge,
which must be equal to the symbol rate (line rate). A small delay added to the data
provides a certain amount of negative data hold time.
2.2.2 Pulse Shaper
The pulse shaper converts the two digital (clocked) positive and negative pulses
into a single analog three-level Alternate Mark Inversion (AMI) pulse. The pulses
are in Return to Zero (RZ) format, meaning that all positive and negative pulses
have a duration of the first half of the symbol period.
For the E3 rate (E3MODE = 1), the AMI pulse is a full-amplitude,
square-shaped pulse with very little slope.
Figure 2-2. Pulse Shaper
E3
Mode
+ Pulse
– Pulse
LBO
LBO = 0
Pulse
Shaper
Line Driver
LBO = 1
100604_008
100985A
Conexant
2-3
2.0 Functional Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.2 Transmitter
For DS3/STS-1 rates, a pulse-shaper block is used to shape the transmit
waveform and reduce its high-frequency energy content. This ensures that the
transmit pulse template is met at the cross-connect block, which follows 0–450
feet of transmit-side coaxial cable.
2.2.3 Line Driver
The differential line driver takes the filtered transmit waveform, increases it to the
proper level, and drives it into the transmit magnetics. The two external discrete
back-matching resistors (36 Ω) aid in line matching. The driver is presented with
an approximately 150 Ω differential load. Driver gain accounts for the 6 dB gain
loss in the back-matching resistors.
Figure 2-3 illustrates the Pulse/Power template measurement points for the
various data rates.
Figure 2-3. Pulse Measurement Points
Pulse/Power Template for DS3/STS-1
TX
0–450 ft COAX
(type 734/728)
0–450 ft COAX
(type 734/728)
DSX
RX
Pulse/Power Template for E3
RX
0–450 ft COAX
(type 734/728)
DSX
0–450 ft COAX
(type 734/728)
TX
100604_013
2-4
Conexant
100985A
CX28331/CX28332/CX28333
2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.2 Transmitter
2.2.3.1 Transmit Pulse
Mask Templates
Figure 2-4. Transmit Pulse Mask for DS3 Rates
Transmit Pulse Mask for STS-1 Rates
1.2
1
Normalized Pulse Amplitude
0.8
0.6
0.4
0.2
0
0.2
1
0.5
0
0.5
Normalized Symbol Time
1
1.5
100985_014
Table 2-1. DS3 Transmit Template Specifications
Time Axis Range (UI)
Normalized Amplitude Equation
Upper Curve
–0.85 ≤ T ≤ –0.68
0.03
–0.68 ≤ T ≤ 0.36
0.03 + 0.5 {1 + sin [(pi / 2)(1 + T / 0.34)]}
0.36 ≤ T ≤ 1.4
0.08 + 0.407 e –1.84(T – 0.36)
Lower Curve
–0.85 ≤ T ≤ –0.36
–0.03
–0.36 ≤ T ≤ 0.36
–0.03 + 0.5{1 + sin[(pi / 2)(1 + T / 0.18)]}
0.36 ≤ T ≤ 1.4
0.03
100985A
Conexant
2-5
2.0 Functional Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.2 Transmitter
Figure 2-5. Transmit Pulse Mask for STS-1 Rates
Transmit Pulse Mask for STS-1 Rates
1.2
1
Normalized Pulse Amplitude
0.8
0.6
0.4
0.2
0
0.2
1
0.5
0
0.5
Normalized Symbol Time
1
1.5
100985_014
Table 2-2. STS-1 Transmit Template Specifications
Time Axis Range (T)
Normalized Amplitude Equation
Upper Curve
–0.85 ≤ T ≤ –0.68
0.03
–0.68 ≤ T ≤ 0.26
0.03 + 0.5{1 + sin[(pi / 2)(1 + T / 0.34)]}
0.26 ≤ T ≤ 1.4
0.1 + 0.61 e –2.4(T – 0.26)
Lower Curve
–0.85 ≤ T ≤ –0.38
–0.03
–0.38 ≤ T ≤ 0.36
–0.03 + 0.5{1 + sin[(pi / 2)(1 + T / 0.18)]}
0.36 ≤ T ≤ 1.4
0.03
2-6
Conexant
100985A
CX28331/CX28332/CX28333
2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.2 Transmitter
Figure 2-6. Transmit Pulse Mask for E3 Rate
17 ns
0.2
0.1
0.1
Volts
Normalized
14.55 ns
0.2
8.65 ns
0.1
12.1 ns
24.5 ns
0.1
0.1
29.1 ns
Time
100985_007
100985A
Conexant
2-7
2.0 Functional Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.2 Transmitter
2.2.4 Alarm Indication Signal (AIS) Generator
When TAIS is asserted, an AIS replaces the transmit data at TPOS and TNEG.
The E3 type of AIS signal (all 1s) is supported. In three-level signal form, this is a
continuously alternating positive and negative pulse stream, as if the transmit data
were a continuous string of logical 1s. Figure 2-7 illustrates the AIS signal.
The TAIS pin has the same data latency as the TX data pins and can be used to
replace single symbols within a data stream. When the encoder is disabled
(ENDECDIS = 1), the TAIS mode maintains the proper phase, based upon the
polarity of the last 1 received.
The AIS signal follows the same path as the TX data during remote or local
loopback.
Figure 2-7. AIS Signal
POSITIVE
PULSE
NEGATIVE
PULSE
TLINEP
(output voltage)
TLINEN
(output voltage)
8333_009
2.2.5 Transmit Monitor Block (CX2833i-3x Only)
The transmit monitor inputs (TMONP and TMONM) are designed to monitor the
line driver outputs (TLINEP and TLINEM/N) for pulses and to assert a Loss Of
Signal (TLOS) indicator when no output pulse has been detected for 32 TCLK
periods. After TLOS is asserted, it will not deassert until a pulse is again
detected. The transmit monitor is an independent function in which TMONP and
TMONM must be externally connected to TLINEP and TLINEM/N, respectively.
A special pin (TMONTST) is available for testing board-level functionality
downstream from the TLOS outputs. When TMONST is high it will assert all
TLOS channel outputs. TLOS outputs are active high when the monitor inputs do
not detect a signal.
2-8
Conexant
100985A
CX28331/CX28332/CX28333
2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.2 Transmitter
2.2.6 Jitter Generation (Intrinsic)
The CX2833i device meets the jitter generation requirements for various rates
with large margins, with the condition that the input transmit clock (TCLK) is
jitter-free. Data rates and jitter generation requirements are defined in the
following documents:
•
•
•
100985A
E3 rate—ETSI TBR24, ITU-T 9.823
DS3 rate—Bellcore Telecardia GR499, AT&T Accunet TR54014,
ITU-T 9.824
STS-1 rate—Bellcore Telecardia GR253
Conexant
2-9
2.0 Functional Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.3 Receiver
2.3 Receiver
This section describes the detailed operation of the various blocks in the CX2833i
receiver.
2.3.1 Receive Sensitivity
The receiver recovers data from the coaxial cable that is attenuated due to the
frequency-dependent characteristics of the cable. In addition, the receiver
compensates for the flat loss (across all frequencies) in the various electrical
components and the variation in transmitted signal power.
The CX2833i device is able to recover data that has been attenuated by a
maximum of 900 feet of coax having characteristics and attenuation consistent
with ANSI T1.102-1993, Annex C, Figure C.2. This approximates the
characteristics of AT&T type 734/728 cable; almost the same attenuation
characteristic is achieved by one-half the length of AT&T type 735 cable.
2.3.2 AGC/VGA Block
The Variable Gain Amplifier (VGA) receives the AMI input signal from the
coaxial cable. The VGA supplies flat gain (independent of frequency) to make up
for various flat losses in the transmission channel and for loss at one-half the
symbol rate that cannot be made up by the equalizer. The VGA gain is controlled
by a feedback loop which senses the amplitude of the equalizer output, acting to
servo this amplitude for optimal slicing.
2.3.3 Receive Equalizer
The receive equalizer receives the differential signal from a VGA and acts to
boost the high frequency content of the signal to reduce inter-symbol interference
(ISI) to the point that correct decisions can be made by the slicer with a minimum
of jitter in the recovered data.
The REQH pin is provided to allow lower amounts of equalization (shorter
equivalent cable lengths) for cases where a square-shaped pulse (that does not
meet the DS3/STS-1 standards) is transmitted to the receiver. A square-shaped
input has a much larger high-frequency content and could have overshoots at the
EQ output high enough to cause bit errors. Setting REQH = 0 will lower the gain
and reduce the amount of overshoot.
2-10
Conexant
100985A
CX28331/CX28332/CX28333
2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.3 Receiver
2.3.4 The PLL Clock Recovery Circuit
The clock recovery circuit (RX PLL) extracts the embedded clock from the sliced
data and provides this clock and the retimed data to the decoder (data mode).
Upon startup (after the internal reset is deasserted), the RX PLL uses a reference
clock (REFCLK, running at the symbol rate) and a phase-frequency detector to
lock to the correct data rate (reference mode). During reference mode, the data
outputs are squelched (set to 0). The RX PLL is kept in reference mode until a
valid input is detected.
2.3.5 Loss Of Signal (LOS) Detector
The Receive Loss Of Signal (RLOS) is a digital function which monitors the
retimed data from the clock recovery block. The AMI data is checked for a
continuous run of zeroes. When a continuous run of 128 ± 1 consecutive zeroes
occurs, the RLOS signal is asserted. After the RLOS signal is asserted, a 1s count
is made on every block of 128 AMI symbols. The RLOS signal is deasserted
when the 1s count within a block of 128 symbols is at least:
B3ZS: Minimum 1s density = 39 ± 1 count out of 128 (~30.5%)
HDB3: Minimum 1s density = 29 ± 1 count out of 128 (~22.7%)
The RLOS detector will always monitor the cable-side RX inputs. The
detector is not affected by the state of remote or local looping.
2.3.6 B3ZS/HDB3 Decoder With Bipolar Violation Detector
In the CX2833i device, when ENDECDIS = 0 (encoder/decoder enabled), the
decoder takes the output from the clock recovery circuit and decodes the data
(HDB3 or B3ZS) into a single retimed NRZ data signal. The data signal is then
sent out of the CX2833i over the RNRZ (RPOS) pin. Any detected Line Code
Violations (LCV) are sent out over the corresponding RLCV (RNEG) pin. The
RLCV pin is asserted for one symbol period at the time the violation appears on
the RX output pin (RNRZ).
The following shows data sequence criteria for LCV; violations are indicated
in bold text. A valid bipolar pulse is indicated by a B. A bipolar violation
(non-alternating positive or negative) pulse is indicated by a V.
•
•
•
Excessive zeros: 0, 0, 0, 0 (HDB3) or 0, 0, 0 (B3ZS). These violations are
passed on as 0 data on the RNRZ pin.
Bipolar violation: B, 0, V (i.e., +1, 0, +1 or -1, 0, -1 for HDB3) B, V
(B3ZS and HDB3). These violations are passed on as 1 data on the RNRZ
pin.
Coding violation: 0, 0, V (HDB3) or 0, V (B3ZS) with an even number of
Bs since the last valid 0 substitution V (follows coding rule). These
violations are passed on as 0 data on the RNRZ pin.
The even/odd counter (used to count the number of Bs between Vs) will count
a bipolar violation as a B. A coding violation or a valid 0 substitution resets the
counter.
100985A
Conexant
2-11
2.0 Functional Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.3 Receiver
When ENDECDIS = 1, the decoder is disabled, and the retimed slicer outputs
are sent out over RPOS (RNRZ) and RNEG (RLCV) pins. These outputs are then
decoded by the Framer or other downstream device. Line code violations are not
detected in this mode of operation. The decoder is configurable for either:
•
•
E3 mode using HDB3 coding (E3MODE = 1)
DS3/STS-1 mode using B3ZS coding (E3MODE = 0)
The receiver digital data outputs are centered on the rising edge of RCLK
(see Section 2.9).
2.3.7 Data Squelching
A counter in the receiver keeps track of the number of consecutive symbol
periods without a valid data pulse. When 128 or more 0s in a row are counted, the
receiver assumes that it has lost the signal and resets itself to try and regain the
signal. While the receiver is reacquiring the signal, the clock recovery block locks
to the reference clock and the data squelching is achieved by forcing the data bits
to zero. The data squelching is true in both NRZ and dual rail mode. When the
input signal has been properly amplified and equalized, the clock recovery PLL
will then switch to the incoming data.
2-12
Conexant
100985A
CX28331/CX28332/CX28333
2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.4 Jitter Tolerance
2.4 Jitter Tolerance
The CX2833i receiver is able to tolerate a specified amount of high-frequency
jitter in the received signal while providing error-free operation (generally
defined as a bit error rate of less than 10-9). The specifications (illustrated in
Figure 2-9) for jitter tolerance are discussed in the following documents:
•
NOTE:
100985A
E3 rate – ITU-T G.823 and ETSI TBR24 contain frequency masks for input
jitter tolerance.
To meet jitter transfer requirements for loop-timed operation, an external
jitter attenuator is required. The jitter attenuator lessens jitter from the
receive clock.
•
DS3 rate – ITU-T G.823 and Bellcore GR499 specify jitter tolerance
frequency masks for Category I and Category II interfaces.
•
STS-1 rate – Bellcore GR253 specifies a jitter tolerance. It is noted that the
STS-1 jitter tolerance differs from DS3 requirements only for Category II
interfaces.
Conexant
2-13
2.0 Functional Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.4 Jitter Tolerance
Figure 2-8. Minimum Jitter Tolerance Requirement
E3 Rate
Input Jitter Amplitude
1.0 UI
0.1 UI
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
Jitter Frequency
DS3 / STS-1 Rates
STS-1
DS3 Category I
DS3 Category II
Input Jitter Amplitude
10 UI
1.0 UI
0.1 UI
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Jitter Frequency
100604_014
2-14
Conexant
100985A
CX28331/CX28332/CX28333
2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.4 Jitter Tolerance
2.4.1 Jitter Transfer
The receiver must meet certain jitter transfer specifications between the input and
output jitter as a function of frequency. These specifications are only intended to
be met with the use of a jitter attenuator. Because the CX2833i does not contain a
jitter attenuator, one will have to be supplied externally. For reference purposes,
the specifications are discussed in the following documents and shown in
Figure 2-9.
E3 rate—Assume the same as DS3.
DS3 rate—Bellcore GR499, section 7.3.2 and figures 7-3, 7-4, and 7-5,
defines and describes DS3 jitter transfer.
STS-1 rate—Bellcore GR253, section 5.6.2.1, defines and describes jitter
transfer for the STS-1 rate.
Figure 2-9. Maximum Jitter Transfer Curve Requirement
Jitter Gain
0.1 dB
–19.9 dB
STS-1 Category II
(Note: All slopes are 20 dB/decade)
DS3 Category I
DS3 Category II
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Jitter Frequency
100985_012
100985A
Conexant
2-15
2.0 Functional Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.5 Additional CX2833i Functions
2.5 Additional CX2833i Functions
2.5.1 Bias Generator
To achieve good isolation between the channels, each channel utilizes an
independent power and ground to both transmit and receive. Additionally, each
channel has its own band gap voltage reference. Because only one external
resistor for current generation exists, only one band gap voltage can be used. The
band gap from Ch1 has been chosen for this task.
The 12.1 kΩ external resistor from pin RBIAS to ground, is specified to have
a tolerance of ±1%. This helps to keep tighter control on power dissipation and
circuit performance.
NOTE:
Capacitance should be kept to a minimum on the RBIAS pin.
2.5.2 Power-On Reset (POR)
A POR function is provided in the CX2833i device to ensure all of the resettable
digital logic and analog control lines are starting from a known state. This circuit
uses a fixed RC timer (~1µs); additionally, 128 clocks from REFCLK are counted
(after the RC timer has timed-out) before reset is deasserted, which begins timing
after a minimum supply voltage is reached (see Table 2-4).
2.5.3 Loopback Multiplexers (MUXes)
Two loopback MUXes per channel in the CX2833i allow for local loopback
(terminal or framer side), remote loopback (cable side), or both (the AIS signal
follows the same path as the transmit data during loopback). The RLOS signal
monitors the RX cable inputs irrespective of any loopback.
In remote loopback, set by asserting pin RLOOP high, the receive data
(retimed after clock recovery but not decoded) loops back into the pulse shaper in
place of the transmit data. Additionally, this data sent out the RPOS, RNEG, and
RCLK pins.
In local loopback, set by asserting pin LLOOP, the transmit data loops back
immediately from the encoder output to the decoder input in place of the received
data. Additionally, this data is sent out the TLINEP and TLINEM/N pins.
2-16
Conexant
100985A
CX28331/CX28332/CX28333
2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.6 Mechanical Specifications
2.6 Mechanical Specifications
Figure 2-10. CX2833i-1x Mechanical Drawing (80-Pin)—Dimensions
D
D1
Pin #1
Ref. Mark
D2
D
3
D1
D D1 D2
e
D3
b
TOP
BOTTOM
Millimeters
Dim.
See DETAIL B
A
A
A1
2
c
L
DETAIL B
L
1
Min.
A
A1
Max.
1.20 MAX.
0.05
0.15
0.95
1.05
15.75
16.25
A2
D
D1
D2
13.90
D3
L
L1
b
c
e
Coplanarity
14.10
Inches
Min.
Max.
0.047 MAX.
0.002
0.006
0.040
0.041
0.620
0.547
0.640
0.555
12.35 REF.
6.50 REF.
0.45
0.75
0.486 REF.
0.256 REF.
0.018
0.030
1.00 REF.
0.32 REF.
0.09
0.20
0.039 REF.
0.013 REF.
0.004
0.008
0.65 REF.
0.10 MAX.
0.026 REF.
0.004 MAX.
Ref. 80-Pin ETQFP (GP00-D537)
100985_008
100985A
Conexant
2-17
2.0 Functional Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.6 Mechanical Specifications
Figure 2-11. CX2833i-3x Mechanical Drawing (100-Pin)—Dimensions
D
D1
Pin #1
Ref. Mark
D
2
D3
D D1 D2
D1
e
D3
b
TOP
BOTTOM
Millimeters
Dim.
See DETAIL B
A
A
A2
c
1
A2
D
D1
D2
D3
L
L1
b
e
L
DETAIL B
Min.
A
A1
c
Coplanarity
L1
Max.
Inches
Min.
Max.
1.20 MAX.
0.05
0.15
0.95
1.05
15.75
16.25
0.047 MAX.
0.002
0.006
0.004
0.041
0.620
0.640
13.90
0.547
14.10
0.555
12.00 REF.
8.00 REF.
0.45
0.75
0.472 REF.
0.315 REF.
0.018
0.006
1.00 REF.
0.22 REF.
0.50 REF.
0.09
0.20
0.039 REF.
0.009 REF.
0.020 REF.
0.004
0.008
0.08 MAX.
0.004 MAX.
Ref. 100-Pin ETQFP (GP00-D543)mm
100985_008a
2-18
Conexant
100985A
CX28331/CX28332/CX28333
2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.7 Electrical Characteristics
2.7 Electrical Characteristics
2.7.1 Absolute Maximum Ratings
Table 2-3. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
DVDDC/
RVDD/
TVDD/
VDD
Power Supply Voltage
–0.3
6
V
VI
Voltage on Any Signal Pin
–1.0
VGG + 0.3 V
V
TST
Storage Temperature
–40
125
°C
TVSOL
Vapor Phase Soldering
Temperature (1 min.)
—
220
°C
θJA
Thermal Resistance (Still
air, socketed)
—
40
°C/W
θJA
Thermal Resistance (Still
air, soldered)
—
24
°C/W
—
7.40
°C/W
—
313
fits
θJc
FIT
—
Failures in time @ 89,000
device hours, temperature
of 55 °C, 0 failures.
NOTE(S):
1. Stresses above those listed as absolute maximum ratings may cause permanent damage
to the device. This is a stress rating only, and functional operation of the device at these or
any other conditions beyond those indicated in the other sections of this document is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
100985A
Conexant
2-19
2.0 Functional Description
CX28331/CX28332/CX28333
2.7 Electrical Characteristics
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.7.2 Recommended Operating Conditions
Table 2-4 specifies various operating conditions, power supplies, and the bias
resistor.
Table 2-4. Recommended Operating Conditions
Parameter
Conditions
Min
Nom
Max
Unit
Power supply voltage
DVDDC, RVDD, TVDD,
VDD
3.135
3.3
3.465
V
ESD voltage(1)
VGG
3.135
5
5.5
V
Power dissipation
(CX28333)
Total chip
—
0.83
1.0
W
Power dissipation
(CX28332)
Total chip
—
—
0.8
W
Power dissipation
(CX28331)
Total chip
—
—
.450
W
External bias resistor
Pin RBIAS to GND; ±1%
11.98
12.1
12.22
kΩ
NOTE(S):
(1)
2-20
With 5 V logic input, VGG should be tied to 5 V. With 3.3 V logic input, VGG should be tied
to 3.3 V.
Conexant
100985A
CX28331/CX28332/CX28333
2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.8 DC Characteristics
2.8 DC Characteristics
Table 2-5. DC Characteristics
Parameter
Conditions
Min
Nom
Max
Unit
Vih high threshold
Digital inputs
2.0
—
VGG + 0.3
V
Vil low threshold
Digital inputs
–0.3
—
0.8
V
Voh high threshold
Digital outputs, Ioh = –4 mA
2.4
—
—
V
Vol low threshold
Digital outputs, Iol = 4 mA
—
—
0.4
V
ILEAK
0 V ≤ digital Vin ≤ VGG
–10
—
200
µA
—
—
10
pF
—
—
15
pF
Input capacitance
Load capacitance
—
Digital outputs
NOTE(S):
1. The digital inputs of CX2833i are TTL 5 V compliant. These inputs are diode protected to DVDDIO and DVSSIO pins.
Additionally, all of the CX2833i digital inputs contain 75 kΩ pull-down resistors.
2. The digital outputs of CX2833i are also TTL 5 V compliant. However, these outputs will not drive to 5 V, nor will they accept
5 V external pull-ups. The output is DVDDC (3.3 V).
100985A
Conexant
2-21
2.0 Functional Description
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.9 AC Characteristics
2.9 AC Characteristics
Table 2-6. AC Characteristics (Logic Timing)
Parameter
Conditions
Min
Nom
Max
Unit
Tosym, Tisym
RCLK and TCLK
E3
DS-3
STS-1
—
29.10
22.35
19.29
—
ns
ns
ns
Clock Duty Cycle
Towidth/Tosym, RCLK
Tiwidth/Tisym, TCLK
Tiwidth/Tisym, REFCLK
45
40
40
—
55
60
60
%
%
%
—
—
—
3
ns
Todelay
Tisetup
TPOS/TNRZ, TNEG,
TAIS
4
—
—
ns
Tihold
TPOS/TNRZ, TNEG,
TAIS
0
—
—
ns
NOTE(S):
1. The description applies to the DS3, E3, and STS-1 clock rates and other parameters such
as pulse width, set-up time, hold time, and duty cycle.
2. The timing diagram, illustrated in Figure 2-12, describes the logical relationship between
various clock and data signals, and parameter values.
2-22
Conexant
100985A
CX28331/CX28332/CX28333
2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.9 AC Characteristics
Figure 2-12. Timing Diagram
Tosym
DATA OUTPUTS
RCLK
Towidth
Todelay
RPOS/RNRZ,
RNEG/RLCV
Tisym
DATA INPUTS
Tiwidth
TCLK
Tisetup
TPOS/TNRZ,
TNEG, TAIS,
Don't
Care
Tihold
Valid Data
Don't
Care
100604_016
100985A
Conexant
2-23
2.0 Functional Description
2.9 AC Characteristics
2-24
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Conexant
100985A
3
3.0 Applications
The CX28331/CX28332/CX28333 can be used in a variety of applications.
Figure 3-1 illustrates an example of three DS3 lines being terminated by the
CX28333. The data and clock are extracted and passed on to the framer chip for
further data manipulation and user interface.
It is important to employ high-frequency design techniques for the printed
board layout.
3.1 PCB Design Considerations for CX2833i
The CX28333 device is a triple LIU operating at frequencies up to 52.84 MHz.
The high-speed nature of the device calls for a careful design of the PCB using
this device. Some design considerations are outlined below.
3.1.1 Power Supply and Ground Plane
A unified power plane with properly placed capacitors of the correct size will
mitigate most power rail-related voltage transients. A properly placed bulk
capacitor, where the power enters the board, with noise-bypassing capacitors at
the power pins on the integrated circuits should be adequate. The noise-bypassing
capacitors must be able to supply all the switching current.
Ferrite beads are used with power rails to filter the high-frequency noise. For
every design, noise frequencies and levels are different. Therefore, whether beads
are necessary, and the effective frequency where they should operate, is difficult
to determine. It is a good idea to provision for ferrite beads on the boards.
The board trace from the CX28333 power supply pin to the noise-bypassing
capacitor should be minimized. Additionally, ground connections from the
ground plane to the CX28333 ground pins and the noise-bypassing capacitor
ground pins should be minimized.
A unified ground plane is the best way to minimize ground impedance. Most
of the ground noise is produced by the return currents and power supply transients
during switching. This effect is minimized by reducing the ground plane
impedance.
100985A
Conexant
3-1
3.0 Applications
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
3.1 PCB Design Considerations for CX2833i
3.1.2 Impedance Matching
It is critical that traces around the transformers and matching resistors be kept to a
minimum length and, in the following cases, the trace impedance be matched to
75 Ω with a ±10% tolerance:
•
•
The impedance from the BNC connector to the transformer
The impedance from the transformer to the matching resistors
3.1.3 Other Passive Parts
The reference design uses the Pulse T3001 extended temperature range 1:1
transformer for the coupling of the BNC connector to the device.
The ferrite beads used to decouple the receive- and transmit-VDD pins on all
analog input VDD pins are type 2508056017Y0 from Fair-Rite Products
Corporation. The bulk capacitor used for where the power enters the board
should be a tantulum–type capacitor, the recommended value and type is a 220 µf
tantulum capacitor.
3.1.4 IBIS Models
IBIS (Input/Output Buffer Interface Specification) models for the
CX28331/CX28332/CX28333-1x and -3x are available from Conexant’s web site
(www.conexant.com).
3.1.5 Recommended Vendors
America
Address:
Telo:
Fax:
Northern Asia
Telo:
Northern Europe
Telo:
Fax:
3-2
Product: Transformers
Product: Ferrite Beads
Pulse
Corporate Office
12220 World Trade Drive
San Diego, CA 92128
858-674-8100
858-674-8262
Telo:
Web site:
Fair-Rite Products Corp.
P.O. Box J
One Commercial Row
Wallkill, NY 12589
914-895-2055
www.Fair-Rite.com
Pulse
3F-4, No. 81, Sec. 1
Hsin Tai Wu Road
Hsi-Chih
Tapei Hsien, Taiwan
R.O.C.
886-2-26980228
886-2-26980948
Product: Crystals
Pulse
1S2 Huxley Road
The Surrey Research Park
Guildford, Surrey GU2 5RE
United Kingdom
44-1483-401700
44-1483-401701
Telo:
Fax:
E-mail:
Web site:
Crystek Corp.
12730 Commonwealth Drive
Fort Myers, FL 33913
800-237-3061
941-561-1025
[email protected]
www.crystek.com
Conexant
100985A
CX28331/CX28332/CX28333
3.0 Applications
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
3.1 PCB Design Considerations for CX2833i
Figure 3-1.
CX28333
TMONP
TPOS
TNEG
TCLK
TLINEP
TX
TLINEN
31.6 W
TMONM
Framer
Channel 1
RPOS
RNEG
RCLK
Type 728, 734, 735
75 W
31.6 W 1:1
37.4 W
RLINEP
RX
RLINEN
BIAS
RESET
0.01µF
1:1
Type 728, 734, 735
75 W
37.4 W
MODE
TMONP
TPOS
TNEG
TCLK
TX
TLINEN
31.6 W
TMONM
Framer
Channel 2
RPOS
RNEG
RCLK
Type 728, 734, 735
75 W
31.6 W 1:1
TLINEP
37.4 W
RLINEP
RX
RLINEN
BIAS
RESET
0.01µF
1:1
Type 728, 734, 735
75 W
37.4 W
MODE
TMONP
TLINEP
TPOS
TNEG
TCLK
TX
TLINEN
31.6 W
TMONM
Framer
Channel 2
RPOS
RNEG
RCLK
Type 728, 734, 735
75 W
31.6 W 1:1
37.4 W
RLINEP
RX
RLINEN
MODE
BIAS
RESET
MODE
BIAS
RESET
0.01µF
1:1
Type 728, 734, 735
75 W
37.4 W
12.1K W
RBIAS
Mode/Status Pins
100985_009
NOTE(S):
1. All transformers are part number T3001 from Pulse Technology. See Recommended Vendors, Section 3.1.5.
2. TMONP and TMONM are only available on the CX2833i-3x device and are denoted by dotted lines.
100985A
Conexant
3-3
3.0 Applications
3.1 PCB Design Considerations for CX2833i
3-4
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Conexant
100985A
A
Appendix A
A.1 Applicable Standards
The applicable standards documents are as follows:
• ANSI T1.102-1993 (DS3 and STS-1 standard)
• ANSI T1.404a-1996 (DS3 metallic interface)
• ITU Recommendation G.703 (DS3 and E3 standard)
• ITU Recommendation G.823 and G.824 (jitter and wander)
• Bellcore GR499, Issue 1, 12/89 (formerly TR-TSY-000499)
(DS3 and STS-1 requirements)
• Bellcore GR253, Issue 2, 12/91 (formerly TA-NWT-000253)
(STS-1 requirements and jitter)
• Bellcore TR-TSY-000191, Issue 1, 5/86 (AIS and LOS)
• ETSI TBR24 and TBR25 (E3 terminal equipment interface)
• ETSI ETS 300 686 and ETS 300 687 (E3 standard)
• AT&T Technical Reference TR54014, May 1992 (Accunet Interface
Specification for DS-3 jitter only)
100985A
Conexant
A-1
CX28331/CX28332/CX28333
Appendix A
A.1 Applicable Standards
A-2
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Conexant
100985A
B
Appendix B
B.1 Evaluation Module Schematic
100985A
Conexant
B-1
J6
J5
J4
J3
J2
BNC
BNC
BNC
BNC
5
4
2
3
PULSE
T3001
6
1
L6
4
3
PULSE
T3001
5
2
CHANNEL 3 RECEIVE
6
1
L5
4
3
CHANNEL 3 TRANSMIT
5
2
PULSE
T3001
6
1
L4
4
3
CHANNEL 2 RECEIVE
5
2
PULSE
T3001
6
1
L3
4
3
CHANNEL 2 TRANSMIT
5
2
PULSE
T3001
6
1
RLOS3
RLOS2
RLOS1
37.4
R12
37.4
R11
31.6
R10
31.6
R9
37.4
R8
37.4
R7
+3_3V
+3_3V
31.6
R6
31.6
R5
37.4
R4
37.4
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
C3
C2
C1
J10
J9
J8
L13
L12
C6
CC
0.01
CC
0.01
0.1
CC
C7
0.1
CC
0.01
402
R16
402
R15
402
R14
CC
CC 1
CC 1
CC
CR3
CR2
CR1
+3_3V
+3_3V
2
2
CH3_LOS
CH2_LOS
CH1_LOS
L15
L14
+3_3V
L11
0.1
C5
CC
L7
C8
CC
0.1
C4
CC
0.1
L10
+3_3V
SOCKET
0.1
C9
CC
+3_3V
20
19
18
17
16
14
15
13
12
11
10
9
8
7
6
5
4
3
2
1
1
3
Y1
NC VCC
14
2
0.1
0.1
C13
CC
+3_3V
1/4
R17
42.2
TVDD3
TLINE3M
TLINE3P
TVSS3
RVSS2
RLINE2P
RLINE2M
RVDD2
TVDD2
TLINE2M
TLINE2P
TVSS2
RVSS1
RLINE1M
RLINE1P
RVDD1
TVDD1
TLINE1M
TLINE1P
C12
CC
TVSS1
J7
ANALOG GND
N1
CC
7 GND OUT 8
1
12.1K
R13
+5V
U1
80 ETQFP
CX28333
SOCKET
CC
REFCLK
SW9
53
54
55
47
46
48
49
50
+3_3V
TMUXLAT
DVSS 41
E3MODE 43
TMUXLAT 42
XOE2 45
LBO2 44
REFCLK2
REQH2/TMUXA0
TNEG2/NC2
TPOS2/TNRZ2
TCLK2
RLOS2 52
51
TAIS2/TMUXA3
RCLK2
RPOS2/RNRZ2
RNEG2/RLCV2
RLOOP2 57
LLOOP2 56
DVDD 60
59
ENDECDIS
PDB2 58
TAIS1/TMUXA2
TCLK1
TPOS1/TNRZ1
TNEG1/NC1
REFCLK
RLOS1
RCLK1
RPOS1/RNRZ1
RNEG1/RLCV1
REQH1/TMUXDAT
XOE1
LBO1
LLOOP1
RLOOP1
PDB1
TMUXIO2
TMUXIO1
RVSS3
24
R3
25
L2
PDB3
CHANNEL 1 RECEIVE
RLOOP3
26
BNC
LLOOP3
27
CC
DVSS2
28
R2
LBO3
29
31.6
RVDD3
73
DVDD2
LBO1 72
XOE3
30
C11
TCLK3
TAIS3/TMUXA4
PDB1
TAIS1/TMUXA2
XOE1
LBO1
LLOOP1
RLOOP1
+3_3V
PDB3
+3_3V
3
2 Pin DIP Switch Setting
4
2
SW4
1
+3_3V
Position 5 XOE (1=Transmitter Enabled 0=Disabled)
Position 7 REQH(1=Enable Equalization 0=Disable)
Position 6 TAIS (1=Enable AIS operation 0=disable)
Position 4 LBO (1=TX CABLE less than 250ft 0=greater than 250ft)
PDB3
Position 2 RLOOP (1=Remote LPBK Enabled 0=Disabled)
Position 1 PDB POWERDOWN (0=Powerdown 1=Active)
Seven Position DIP Switch Settings for all Channels
DECODER AND E3 SELECTION
Pin 2 E3MODE 1=E3 mode is enabled 0=Disabled
Pin 1 ENDECDIS 1=Dual rail pulse coded data format
ENDECDIS
E3MODE
REQH3/TMUXA1
TAIS3/TMUXA4
XOE3
LBO3
LLOOP3
RLOOP3
LBO2
REQH2/TMUXA0
TAIS2/TMUXA3
XOE2
RLOOP3
+3_3V
PDB2
LLOOP2
RLOOP2
Position 3 LLOOP (1=Local Loop Enabled 0=Disabled)
REQH1/TMUXDAT
TAIS3/TMUXA4
TAIS2/TMUXA3
TAIS1/TMUXA2
REQH3/TMUXA1
0.1
C10
CC
L16
REQH1/TMUXDAT
REQH2/TMUXA0
TMUXLAT
LBO2
XOE2
REFCLK
REQH2/TMUXA0
TNEG2/NC2
TPOS2/TNRZ2
TCLK2
TAIS2/TMUXA3
RLOS2
RCLK2
RPOS2/RNRZ2
RNEG2/RLCV2
LLOOP2
RLOOP2
PDB2
ENDECDIS
L17
+3_3V
LLOOP3
LBO3
XOE3
REQH3/TMUXA1
RNEG3/RLCV3
RPOS3/RNRZ3
RCLK3
RLOS3
REFCLK
TNEG3/NC3
TPOS3/TNRZ3
CC
E3MODE
DIGITAL GND
0.1
+3_3V
1
14
4
PDB1 76
RLOOP1 75
LLOOP1 74
REQH3/TMUXA1
31
80
RBIAS
RLINE3P
22
21
VGG 79
78
TMUXIO1
TMUXIO2 77
RLINE3M
23
XOE1 71
REQH1/TMUXDAT 70
RNEG3/RLCV3
32
2
13
PULSE
T3001
RLOS3
35
3
12
3
36
6
9
CC
REFCLK3
7
8
R1
TNEG3/NC3
37
4
11
31.6
RCLK3
34
REFCLK1 65
TPOS3/TNRZ3
38
RNEG1/RLCV1 69
RPOS1/RNRZ1 68
67
RCLK1
RLOS1 66
RPOS3/RNRZ3
33
TNEG1/NC1 64
TPOS1/TNRZ1 63
TCLK3
39
5
10
5
SW5
1
14
6
1
12
2
13
+3_3V
2
2
2
11
3
12
3
L1
3
4
11
4
13
1
4
9
10
5
10
5
12
CHANNEL 1 TRANSMIT
5
TCLK1 62
TAIS1/TMUXA2 61
TAIS3/TMUXA4
40
SW1
8
Conexant
6
B.1 Evaluation Module Schematic
7
SW2
6
9
6
9
BNC
SW3
1
14
7
8
7
8
11
B-2
10
J1
Appendix B
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Figure B-1. Recommended Schematic for the CX2833i-1x Device
100985_017
100985A
Conexant
2,3,4
J3
J4
J5
2,3,4
2,3,4
2,3,4
2,3,4
J2
2
2
J6
Pulse
4
Pulse
4
T3001
5
6
3
L2
2
1
4
Pulse
T3001
3
6
5
L3
2
1
4
Pulse
T3001
3
6
5
L4
2
1
1
Pulse
1
T3001
Pulse
L6
4
5
6
31.6
R1
1
1
1
RLOS2
RLOS3
0.01
C3
RLOS1
0.01
C2
0.01
C1
JP8
JP7
JP6
2
2
2
R16
R15
R14
402
402
402
Red Led
CR3
CR2
CR1
Note: All capacitors are in Microfarads
37.4
R12
37.4
R11
31.6
R10
31.6
R9
37.4
R8
37.4
R7
31.6
R6
31.6
R5
37.4
R4
37.4
R3
31.6
R2
CH3_RLOS
CH2_RLOS
CH1_RLOS
0.1
C7
L13
+3.3V
0.1
C6
L12
+3.3V
TLOS3
TLOS2
TLOS1
+3.3V
+3.3V
1
1
1
JP11
JP10
2
2
2
0.1
C5
JP9
bead
L15
bead
L14
L11
+3.3V
402
402
R62 402
R61
R60
8
7
Out
14
Gnd
+3.3V
Vcc
1
Y1
Socket
CH3_TLOS
CH2_TLOS
CH1_TLOS
C9
0.1
C8
0.1
0
R21
0
0
0
0
0
R20
R19
R18
Red Led
CR62
CR61
CR60
R52
R53
42.2
R17
C13
.1
C12
0.1
REFCLK
TMON1P
TLINE1P
TLINE1M
TMON1M
TVDD1
RVDD1
RLINE1P
RLINE1M
RVSS1
TVSS2
TMON2P
TLINE2P
TLINE2M
TMON2M
TVDD2
RVDD2
RLINE2P
RLINE2M
RVSS2
TVSS3
TMON3P
TLINE3P
TLINE3M
TMON3M
TVDD3
12.1K
R13
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
J7
44.736/34.368/51.256Mhz +/- 20ppm
NC
0.1
C4
L10
+3.3V
+3.3V
+5V
TMUXIO1
TMUXIO2
PD1
RLOOP1
LLOOP1
CX28333 DS3/E3/STS-1 LIU
U1
DVDDC
ENDECDIS
PD2
RLOOP2
LLOOP2
RNEG2/RLCV2
RPOS2/RNRZ2
RCLK2
RLOS2
N/C7
N/C6
N/C5
TAIS2
TCLK2
TPOS2/TNRZ2
TNEG2/NC2
TLOS2
REFCLK2
REQH2
XOE2
LBO2
TMONTST
E3MODE
NC11
DVSSC
REFCLK
1k
3
4
R25
+3.3V
Reset Device
2
SW10
TMUXIO1 1
REQH3/TMUXA1
XOE3
LBO3
LLOOP3
RLOOP3
PD3
1
2
3
4
5
6
7
+3.3V
SW3
Chn 3
TAIS3/TMUXA4
TCLK3
TPOS3/TNRZ3
TNEG3/NC3
TLOS3
REFCLK
RLOS3
RCLK3
RPOS3/RNRZ3
RNEG3/RLCV3
14
13
12
11
10
9
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
C11
0.1
LBO1
XOE1
REQH1/TMUXDAT
RNEG1/RLCV1
RPOS1/RNRZ1
RCLK1
RLOS1
REFCLK
TLOS1
TNEG1/NC1
TPOS1/TNRZ1
TCLK1
TAIS1/TMUXA2
TMUXIO1
TMUXIO2
L17
+3.3V
+3.3V
2
SW9
TMUXLAT1
PD3
RLOOP3
LLOOP3
LBO3
XOE3
TAIS3/TMUXA4
REQH3/TMUXA1
RCLK3
RPOS3/RNRZ3
RNEG3/RLCV3
TCLK3
TPOS3/TNRZ3
TNEG3/NC3
E3MODE
TMUXLAT
3
4
J21
+3.3V
Date:
Size
C
Title
PD3
RLOOP3
LLOOP3
LBO3
XOE3
TAIS3/TMUXA4
REQH3/TMUXA1
TMUXLAT
TAIS2/TMUXA3
TCLK2
TCLK2
TPOS2/TNRZ2
TPOS2/TNRZ2
TNEG2/NC2
TNEG2/NC2
TLOS2
REFCLK
+3.3V
REQH2/TMUXA0
XOE2
1
LBO2
ENDECDIS
PD2
RLOOP2
LLOOP2
RNEG2/RLCV2
RNEG2/RLCV2
RPOS2/RNRZ2
RPOS2/RNRZ2
RCLK2
RCLK2
RLOS2
C10
0.1
L16
bead
TNEG1/NC1
TPOS1/TNRZ1
TCLK1
RNEG1/RLCV1
RPOS1/RNRZ1
RCLK1
R23
+3.3V
1k
1
2
3
4
5
6
7
R22
14
13
12
11
10
9
8
SW2
Chn 2
REQH1/TMUXDAT
REQH2/TMUXA0
REQH3/TMUXA1
TAIS1/TMUXA2
TAIS2/TMUXA3
TAIS3/TMUXA4
Conexant Systems
9868 Scranton Road
San Diego,Ca 92121
SW7
12
11
10
9
8
7
SW4
4
3
1k
Sheet
1
of
2
Rev
A
PD2
RLOOP2
LLOOP2
LBO2
XOE2
TAIS2/TMUXA3
REQH2/TMUXA0
R24
+3.3V
PD2
RLOOP2
LLOOP2
LBO2
XOE2
TAIS2/TMUXA3
REQH2/TMUXA0
CX 28333 (LIU) w/Jitter Attenuator Circuit
1
2
3
4
5
6
14
13
12
11
10
9
8
PD1
PD1
RLOOP1
RLOOP1
LLOOP1
LLOOP1
LBO1
LBO1
XOE1
XOE1
TAIS1/TMUXA2
TAIS1/TMUXA2
REQH1/TMUXDAT
REQH1/TMUXDAT
E3MODE 1
ENDECDIS2
1
2
3
4
5
6
7
Document Number
BT01-D630-
R36
1k
+3.3V
E3MODE
1k
+3.3V
SW1
Chn 1
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Notes: Seven Position Dip switch for all Channels (SW1,2,3)
Position 1 PDB#
( 0 = Powerdown
1 = Active)
Position 2 RLOOP#
( 0 = RLPBK Disable 1 = RLPBK Enable)
Position 3 LLOOP#
( 0 = LPBK Disable
1 = LPBK Enable)
Position 4 LBO#
( 0 = Tx Cable > 250ft 1 = Tx Cable < 250ft)
Position 5 XOE#
( 0 = Tx Disable
1 = Tx Enable)
Position 6 TAIS#
( 0 =Tx AIS Disable 1 = Tx AIS Enable)
Position 7 REQH#
( 0 =EQ Disable
1 = EQ Enable)
3
2
1
Channel 3 Receive
T3001
4
3
6
5
L5
2
1
Channel 3 Transmit
1
Channel 2 Receive
1
Channel 2 Transmit
1
Channel 1 Receive
T3001
5
6
3
L1
2
1
bead
Channel 1 Transmit
bead
1
bead
2
2
2
bead
bead
2,3,4
2
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
TVSS1
RBAIS
VGG
RESET
GPD
PD1
RLOOP1
LLOOP1
DVDDIO
LBO1
XOE1
REQH1
N/C10
N/C9
N/C8
RNEG1/RLCV1
RPOS1/RNRZ1
RCLK1
RLOS1
REFCLK1
TLOS1
TNEG1/NC1
TPOS1/TNRZ1
TCLK1
TAIS1
RVDD3
RLINE3P
RLINE3M
RVSS3
PD3
RLOOP3
LLOOP3
DVSSIO
LBO3
XOE3
REQH3
N/C1
N/C2
N/C3
RNEG3/RLCV3
RPOS3/RNRZ3
RCLK3
RLOS3
REFCLK3
TLOS3
TNEG3/NC3
TPOS3/TNRZ3
TCLK3
TAIS3
N/C4
100985A
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
J1
CX28331/CX28332/CX28333
Appendix B
B.1 Evaluation Module Schematic
Figure B-2. Recommended Schematic for the CX2833i-3x Device (1 of 2)
100985_010
B-3
1Meg
R32
1Meg
1Meg
R37
VCO3_CNTRL
VCO3
VCO2_CNTRL
VCO2
R34
VCO1_CNTRL
VCO1
DJATNEG1
DJATPOS1
CHANNEL2_STATUS
CHANNEL3_STATUS
DJATPOS3
TMS
DJATNEG3
DJATPOS2
DJATNEG2
RPOS1/RNRZ1
TDI
1Meg
R38
C24
0.1
1Meg
R35
C18
0.1
1Meg
R33
C16
0.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
R26
1Meg
RNEG2/RLCV2
RNEG1/RLCV1
RPOS3
RPOS2
GND_1
TDI
NC/1
NC/2
NC/3
NC/4
NC/5
RPOS1
NC/6
DJATNEG2
GND_2
NC/7
DJATNEG3
DJATPOS2
GND_3
STATUS3
DJATPOS3
TMS
NC/8
NC/9
NC/10
VCCIO_1
DJATNEG1
DJATPOS1
STATUS2
NC/11
NC/12
NC/13
NC/14
NC/15
GND_4
NC/16
NC/17
NC/18
D14
C26
10
DIODE
Conexant
Jitter
Attenuator
144 Pin - TQFP
U3
C25
C19
C17
DJATCLK1
RCLK1
RNEG3/RLCV3
DJATCLK2
0.1
0.1
0.1
8
14
Y3
8
14
8
14
VCO DIJITCK3
7
1
Y4
VCO DIJITCK2
7
VCO2_CNTRL 1
VCO3_CNTRL
Y2
VCO DIJITCK1
7
VCO1_CNTRL 1
VCO3
RPOS3/RNRZ3
RPOS2/RNRZ2
RCLK3
+3.3V
VCO2
DJATCLK3
RCLK2
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
NC/73
NC/72
NC/71
GND_10
TDO
NC/70
NC/69
NC/68
NC/67
NC/66
NC/65
NC/64
NC/63
VCCIO_5
NC/62
NC/61
STATUS1
VCO1
NC/60
TCK
NC/59
NC/58
NC/57
GND_9
NC/56
NC/55
NC/54
NC/53
NC/52
NC/51
NC/50
NC/49
VCCIO_4
NC/48
NC/47
VCCIO_3
VCCIO_7
RNEG1
NC/89
RNEG2
NC/88
NC/87
NC/86
DJATCK3
RCLK2
GND_15
DJATCK1
RCLK1
RNEG3
DJATCK2
VCCI_4
GND_14
GND_13
RSTN
GND_12
RCLK3
GND_11
VCCI_3
NC/85
NC/84
NC/83
NC/82
NC/81
NC/80
NC/79
VCCIO_6
VCO2
NC/78
NC/77
NC/76
NC/75
NC/74
NC/19
NC/20
NC/21
NC/22
NC/23
NC/24
NC/25
NC/26
NC/27
NC/28
NC/29
NC/30
NC/31
VCCIO_2
VCCI_1
GND_5
NC/32
VCO3
NC/33
NC/34
GND_6
VCCI_2
GND_7
NC/35
NC/36
NC/37
NC/38
GND_8
NC/39
NC/40
NC/41
NC/42
NC/43
NC/44
NC/45
NC/46
DJATCLK3
+3.3V
DJATCLK2
+3.3V
DJATCLK1
+3.3V
C29
.1
C28
.1
C27
.1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Conexant
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
TCK
CHANNEL1_STATUS
VCO1
TDO
TDI
TCK
TDO
TMS
1 2
3 4
5 6
7 8
9 10
J20
+3.3V
CR13
C20
0.1
Green Led
R40
330
C21
220
U2
2
1
JP4
2
C22
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
RLOOP1
E3MODE
XOE1
REQH2/TMUXA0
TMUXLAT
XOE3
RLOOP3
XOE2
RLOOP2
10
25V
+
+3.3V
C23
0.1
Optional external 3.3V Supply
Please remove JP3 when in
use
J24
Blue Banana - Jack
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
J13
1
3
5
7
9
11
13
15
17
19
21
23
25
27
J12
2
4
6
8
10
12
14
16
18
20
22
24
26
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Header
JP2
JP1
Header
CHANNEL1_STATUS
CHANNEL2_STATUS
CHANNEL3_STATUS
PD1
LLOOP1
LBO1
TAIS1/TMUXA2
PD2
LLOOP2
LBO2
TAIS2/TMUXA3
PD3
LLOOP3
LBO3
TAIS3/TMUXA4
REQH1/TMUXDAT
REQH3/TMUXA1
TMUXLAT
REQH2/TMUXA0
REQH3/TMUXA1
TAIS1/TMUXA2
TAIS2/TMUXA3
TAIS3/TMUXA4
REQH1/TMUXDAT
1 square inch copper plane
used for heat sink
LT1086-3.3
Black- Banana - Jack
J23
3
1
+5V
VIN VOUT
GND
+5VSRC
J22
Red - Banana - Jack
PD1
LLOOP1
LBO1
TAIS1/TMUXA2
PD2
LLOOP2
LBO2
TAIS2/TMUXA3
PD3
LLOOP3
LBO3
TAIS3/TMUXA4
REQH1/TMUXDAT
REQH3/TMUXA1
TMUXLAT
REQH2/TMUXA0
REQH3/TMUXA1
TAIS1/TMUXA2
TAIS2/TMUXA3
TAIS3/TMUXA4
REQH1/TMUXDAT
1
B-4
JP5
DJATCLK1
+3.3V
+3.3V
Date:
Size
C
Title
0.1
C15
TMUXIO1
1
J15
TMUXIO2
TMUXIO1
REFCLK
TCLK3
RCLK3
TPOS3/TNRZ3
RPOS3/RNRZ3
TNEG3/NC3
RNEG3/RLCV3
TCLK2
RCLK2
TPOS2/TNRZ2
RPOS2/RNRZ2
TNEG2/NC2
RNEG2/RLCV2
TCLK1
RCLK1
TPOS1/TNRZ1
RPOS1/RNRZ1
TNEG1/NC1
RNEG1/RLCV1
Conexant Systems
9868 Scranton Road
San Diego,Ca 92121
REQH2/TMUXA0
TMUXLAT
XOE3
RLOOP3
XOE2
RLOOP2
RLOOP1
E3MODE
XOE1
TMUXIO2
J14
REFCLK
TCLK3
RCLK3
TPOS3/TNRZ3
RPOS3/RNRZ3
TNEG3/NC3
RNEG3/RLCV3
TCLK2
RCLK2
TPOS2/TNRZ2
RPOS2/RNRZ2
TNEG2/NC2
RNEG2/RLCV2
TCLK1
RCLK1
TPOS1/TNRZ1
RPOS1/RNRZ1
TNEG1/NC1
RNEG1/RLCV1
Sheet
2
of
CX 28333 (LIU) w/Jitter Attenuator Evualation Module
1
Header
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
JP3
Document Number
BT01-D630-
330
R28
330
R27
C14
0.1
DJATNEG3
DJATPOS3
DJATCLK3
DJATNEG2
DJATPOS2
DJATCLK2
DJATNEG1
DJATPOS1
2
Rev
A
B.1 Evaluation Module Schematic
2
Appendix B
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Figure B-3. Recommended Schematic for the CX2833i-3x Device (2 of 2)
100985_011
100985A
0.0 Sales Offices
Further Information:
[email protected]
1-800-854-8099 (North America)
33-14-906-3980 (International)
Web Site
www.conexant.com
World Headquarters
Conexant Systems, Inc.
4311 Jamboree Road,
P.O. Box C
Newport Beach, CA 92658-8902
Phone: (949) 483-4600
Fax: (949) 483-6375
U.S. Florida/South America
Phone: (727) 799-8406
Fax: (727) 799-8306
U.S. Los Angeles
Phone: (805) 376-0559
Fax: (805) 376-8180
U.S. Mid-Atlantic
Phone: (215) 244-6784
Fax: (215) 244-9292
U.S. North Central
Phone: (630) 773-3454
Fax: (630) 773-3907
U.S. Northeast
Phone: (978) 692-7660
Fax: (978) 692-8185
U.S. Northwest/Pacific West
Phone: (408) 249-9696
Fax: (408) 249-7113
U.S. South Central
Phone: (972) 733-0723
Fax: (972) 407-0639
U.S. Southeast
Phone: (919) 858-9110
Fax: (919) 858-8669
U.S. Southwest
Phone: (949) 483-9119
Fax: (949) 483-9090
APAC Headquarters
Conexant Systems Singapore,
Pte. Ltd.
1 Kim Seng Promenade
Great World City
#09-01 East Tower
Singapore 237994
Phone: (65) 737 7355
Fax: (65) 737 9077
Australia
Phone: (61 2) 9869 4088
Fax: (61 2) 9869 4077
China
Phone: (86 2) 6361 2515
Fax: (86 2) 6361 2516
Hong Kong
Phone: (852) 2 827 0181
Fax: (852) 2 827 6488
India
Phone: (91 11) 692 4780
Fax: (91 11) 692 4712
Korea
Phone: (82 2) 565 2880
Fax: (82 2) 565 1440
Europe Headquarters
Conexant Systems France
Les Taissounieres B1
1681 Route des Dolines
BP 283
06905 Sophia Antipolis Cedex
France
Phone: (33 4) 93 00 33 35
Fax: (33 4) 93 00 33 03
Europe Central
Phone: (49 89) 829 1320
Fax: (49 89) 834 2734
Europe Mediterranean
Phone: (39 02) 9317 9911
Fax: (39 02) 9317 9913
Europe North
Phone: (44 1344) 486 444
Fax: (44 1344) 486 555
Europe South
Phone: (33 1) 41 44 36 50
Fax: (33 1) 41 44 36 90
Middle East Headquarters
Conexant Systems
Commercial (Israel) Ltd.
P.O. Box 12660
Herzlia 46733, Israel
Phone: (972 9) 952 4064
Fax: (972 9) 951 3924
Japan Headquarters
Conexant Systems Japan Co., Ltd.
Shimomoto Building
1-46-3 Hatsudai,
Shibuya-ku, Tokyo
151-0061 Japan
Phone: (81 3) 5371 1567
Fax: (81 3) 5371 1501
Taiwan Headquarters
Conexant Systems, Taiwan Co., Ltd.
Room 2808
International Trade Building
333 Keelung Road, Section 1
Taipei 110, Taiwan, ROC
Phone: (886 2) 2720 0282
Fax: (886 2) 2757 6760