W194 Frequency Multiplier and Zero Delay Buffer Features Table 1. Configuration Options • Two outputs • Configuration options allow various multiplications of the reference frequency—refer to Table 1 to determine the specific option which meets your multiplication needs • Available in 8-pin SOIC package Key Specifications Operating Voltage: .............................. 3.3V±5% or 5.0±10% Operating Range: .......................10 MHz < fOUT1 < 133 MHz Absolute Jitter: ......................................................... ±500 ps Output to Output Skew: .............................................. 250 ps FBIN FS0 FS1 OUT1 OUT2 OUT1 0 0 2 X REF REF OUT1 1 0 4 X REF 2 X REF OUT1 0 1 REF REF/2 OUT1 1 1 8 X REF 4 X REF OUT2 0 0 4 X REF 2 X REF OUT2 1 0 8 X REF 4 X REF OUT2 0 1 2 X REF REF OUT2 1 1 16 X REF 8 X REF Propagation Delay: ................................................... ±350 ps Propagation delay is affected by input rise time. Block Diagram Pin Configuration SOIC External feedback connection to OUT1 or OUT2, not both FBIN FS0 FS1 IN Reference Input ÷Q Phase Detector FBIN 1 8 OUT2 IN 2 7 VDD GND 3 6 OUT1 FS0 4 5 FS1 Charge Pump Loop Filter Output Buffer OUT1 Output Buffer OUT2 VCO ÷2 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 January 5, 2000, rev. *A W194 Pin Definitions Pin No. Pin Type IN 2 I Reference Input: The output signals will be synchronized to this signal. FBIN 1 I Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to ensure proper functionality. If the trace between FBIN and the output pin being used for feedback is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the REF signal input (IN). OUT1 6 O Output 1: The frequency of the signal provided by this pin is determined by the feedback signal connected to FBIN, and the FS0:1 inputs (see Table 1). OUT2 8 O Output 2: The frequency of the signal provided by this pin is one-half of the frequency of OUT1. See Table 1. VDD 7 P Power Connections: Connect to 3.3V or 5V. This pin should be bypassed with a 0.1-µF decoupling capacitor. Use ferrite beads to help reduce noise for optimal jitter performance. GND 3 P Ground Connection: Connect all grounds to the common system ground plane. FS0:1 4, 5 I Function Select Inputs: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per Table 1. Pin Name Pin Description Overview “How to Implement Zero Delay,” and “Inserting Other Devices in Feedback Path.” The W194-70 is a two-output zero delay buffer and frequency multiplier. It provides an external feedback path allowing maximum flexibility when implementing the Zero Delay feature. This is explained further in the sections of this data sheet titled The W194-70 is a pin-compatible upgrade of the Cypress W42C70-01. The W194-70 addresses some application dependent problems experienced by users of the older device. Ferrite Bead CA G V+ 10 µF Power Supply Connection C8 G 0.01 µF OUT 2 FBIN 1 7 IN OUTPUT 2 VDD C9 = 0.1 µF G 2 OUT 1 3 GND FS0 22Ω 8 22Ω OUTPUT 1 6 G 5 4 Figure 1. Schematic/Suggested Layout 2 FS1 W194 How to Implement Zero Delay device (ASIC, multiple output clock buffer/driver, etc.) which is put into the feedback path. Typically, zero delay buffers (ZDBs) are used because a designer wants to provide multiple copies of a clock signal in phase with each other. The whole concept behind ZDBs is that the signals at the destination chips are all going HIGH at the same time as the input to the ZDB. In order to achieve this, layout must compensate for trace length between the ZDB and the target devices. The method of compensation is described below. Referring to Figure 2, if the traces between the ASIC/Buffer and the destination of the clock signal(s) (A) are equal in length to the trace between the buffer and the FBIN pin, the signals at the destination(s) device will be driven HIGH at the same time the Reference clock provided to the ZDB goes HIGH. Synchronizing the other outputs of the ZDB to the outputs from the ASIC/Buffer is more complex however, as any propagation delay from the ZDB output to the ASIC/Buffer output must be accounted for. External feedback is the trait that allows for this compensation. The PLL on the ZDB will cause the feedback signal to be in phase with the reference signal. When laying out the board, match the trace lengths between the output being used for feedback and the FBIN input to the PLL. Reference Signal If it is desirable to either add a little delay, or slightly precede the input signal, this may also be affected by either making the trace to the FBIN pin a little shorter or a little longer than the traces to the devices being clocked. Feedback Input Zero Delay Buffer ASIC/ Buffer A Inserting Other Devices in Feedback Path Figure 2. 6 Output Buffer in the Feedback Path Another nice feature available due to the external feedback is the ability to synchronize signals to the signal coming from some other device. This implementation can be applied to any 3 W194 Absolute Maximum Ratings above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . Parameter Description Rating Unit V VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 –65 to +150 °C 0 to +70 °C –55 to +125 °C 0.5 W TSTG Storage Temperature TA Operating Temperature TB Ambient Temperature under Bias PD Power Dissipation DC Electrical Characteristics: TA = 0°C to 70°C, VDD = 3.3V ±5% Parameter Description Test Condition Min Typ Max Unit 17 35 mA 0.8 V IDD Supply Current VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage IOL = 12 mA IOL = 8 mA VOH Output High Voltage IOL = 12 mA IOL = 8 mA IIL Input Low Current VIN = 0V 5 µA IIH Input High Current VIN = VDD 5 µA Max Unit 35 mA 0.8 V Unloaded, 100 MHz 2.0 V 0.4 2.4 V V DC Electrical Characteristics: TA = 0°C to 70°C, VDD = 5V ±10% Parameter Description Test Condition Min Unloaded, 100 MHz Typ IDD Supply Current VIL Input Low Voltage 17 VIH Input High Voltage VOL Output Low Voltage IOL = 12 mA IOL = 8 mA VOH Output High Voltage IOL = 12 mA IOL = 8 mA IIL Input Low Current VIN = 0V 5 µA IIH Input High Current VIN = VDD 5 µA 2.0 V 0.4 2.4 4 V V W194 AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±5% Parameter fIN Description Input Frequency Test Condition  OUT1 15-pF load tR Output Rise Time tF Output Fall Time Input Clock Rise Time Input Clock Fall Time FBIN to REF Skew tPD Max 10 133 MHz 2.0V to 0.8V, 15-pF load 3.5 ns 2.0V to 0.8V, 15-pF load 2.5 ns 10 ns 10 ns   [3, 4] Unit MHz  Output Frequency tICLKF Typ OUT2 = REF fOUT tICLKR Min Measured at VDD/2  tD Duty Cycle 15-pF load tLOCK PLL Lock Time Power supply stable tJC Jitter, Cycle-to-Cycle –2 0.6 2 ns 40 50 60 % 1.0 ms 300 ps Max Unit AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 5.0V ±10% Parameter Description Input Frequency fIN Test Condition  MHz  Output Frequency OUT1 15-pF load tR Output Rise Time tF Output Fall Time tICLKF tPD Input Clock Rise Time Input Clock Fall Time FBIN to REF Skew Typ OUT2 = REF fOUT tICLKR Min 10 133 MHz 2.0V to 0.8V, 15-pF load 2.5 ns 2.0V to 0.8V, 15-pF load 1.5 ns 10 ns 10 ns   [3, 4] Measured at VDD/2 [5, 7] tD Duty Cycle 15-pF load tLOCK PLL Lock Time Power supply stable tJC Jitter, Cycle-to-Cycle –2 0.6 2 ns 40 50 60 % 1.0 ms 200 ps Notes: 1. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration). 2. Longer input rise and fall time will degrade skew and jitter performance. 3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V. 4. Skew is measured at 1.4V on rising edges. 5. Duty cycle is measured at 1.4V. 6. For the higher drive -11, the load is 20 pF. 7. Duty Cycle measured at 120 MHz. For 133 MHz, degrades to 35/65 worst case. Ordering Information Ordering Code W194 Option Package Name -70 G Package Type 8-pin SOIC (150-mil) Document #: 38-00794-A 5 W194 Package Diagram 8-Pin Small Outlined Integrated Circuit (SOIC, 150-mil) © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. 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