SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC (Enhanced-Performance Implanted CMOS) 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC, TA = 25°C ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Flat (W) Packages, Chip Carriers (FK), and (J) 300-mil DIPs description 1CLR 1D 1CLK 1PRE 1Q 1Q GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LV74 . . . FK PACKAGE (TOP VIEW) 1CLK NC 1PRE NC 1Q 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2D NC 2CLK NC 2PRE 1Q GND NC 2Q 2Q These dual positive-edge-triggered D-type flipflops are designed for 2.7-V to 5.5-V VCC operation. SN54LV74 . . . J OR W PACKAGE SN74LV74 . . . D, DP, OR PW PACKAGE (TOP VIEW) 1D 1CLR NC VCC 2CLR D A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are NC – No internal connection inactive (high), data at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The SN74LV74 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LV74 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LV74 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996 FUNCTION TABLE OUTPUTS INPUTS PRE CLR CLK D Q Q L H X X H L H L X X H H† L L X X L H† H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 † This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. logic symbol† 4 1PRE 1CLK 1D 1 1CLR 6 9 11 2CLK 1Q R 10 2PRE 1Q C1 2 1D 5 S 3 2Q 12 2D 8 13 2CLR 2Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for D, DB, J, PW, and W packages. logic diagram, each flip-flop (positive logic) PRE CLK C C C Q TG C C C C D TG TG TG C C C Q CLR 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): D package . . . . . . . . . . . . . . . . . . . 1.25 W DB or PW package . . . . . . . . . . . . . 0.5 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. recommended operating conditions (see Note 4) VCC Supply voltage VIH High level input voltage High-level VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL Low level input voltage Low-level VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VI VO Input voltage SN54LV74 SN74LV74 MIN MAX MIN MAX 2.7 5.5 2.7 5.5 2 2 3.15 3.15 0 Output voltage 0 IOH High level output current High-level VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V IOL Low level output current Low-level VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature NOTE 4: Unused inputs must be held high or low to prevent them from floating. 0.8 1.65 1.65 0 0 V V 0.8 VCC VCC UNIT UNIT VCC VCC –6 –6 –12 –12 6 6 12 12 V V V mA mA 0 100 0 100 ns/V –55 125 –40 85 °C PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VCC† TEST CONDITIONS IOH = –100 µA IOH = –6 mA VOH MIN TYP SN74LV74 MAX MIN to MAX VCC – 0.2 3V 2.4 IOH = –12 mA IOL = 100 µA VOL SN54LV74 4.5 V II VI = VCC or GND ICC VI = VCC or GND IO = 0 nICC One input at VCC – 0.6 V Other inputs at VCC or GND Ci VI = VCC or GND TYP MAX VCC – 0.2 2.4 3.6 UNIT V 3.6 MIN to MAX IOL = 6 mA IOL = 12 mA MIN 0.2 0.2 3V 0.4 0.4 4.5 V 0.55 0.55 3.6 V ±1 ±1 5.5 V ±1 ±1 3.6 V 20 20 5.5 V 20 20 3 V to 3.6 V 500 500 3.3 V 2.5 2.5 5V 3 3 V µA µA µA pF † For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) SN54LV74 VCC = 5 V ± 0.5 V fclock Clock frequency tw Pulse duration duration, LE high tsu time data before CLK↑ Setup time, th Hold time, data after CLK↑ VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN MAX MIN MAX MIN MAX 0 70 0 60 0 50 PRE or CLR low 15 20 25 CLK high or low 15 20 25 Data 6 8 12 PRE or CLR inactive 5 6 8 3 3 3 UNIT ns ns ns ns timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) SN74LV74 VCC = 5 V ± 0.5 V fclock Clock frequency tw Pulse duration duration, LE high tsu time data before CLK↑ Setup time, th Hold time, data after CLK↑ MIN MAX 0 70 MIN MAX 0 60 VCC = 2.7 V MIN MAX 0 50 PRE or CLR low 15 20 25 CLK high or low 15 20 25 Data 6 8 12 PRE or CLR inactive 5 6 8 3 3 3 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 VCC = 3.3 V ± 0.3 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LV74 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V ± 0.5 V MIN TYP MAX fmax tpd 70 PRE or CLR Q or Q CLK VCC = 3.3 V ± 0.3 V MIN TYP MAX 100 60 90 VCC = 2.7 V MIN MAX 50 UNIT MHz 11 19 18 27 34 10 17 17 26 28 ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74LV74 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V ± 0.5 V MIN TYP MAX fmax tpd 70 PRE or CLR Q or Q CLK VCC = 3.3 V ± 0.3 V MIN TYP MAX 100 60 90 VCC = 2.7 V MIN MAX 50 UNIT MHz 11 19 18 27 34 10 17 17 26 28 ns operating characteristics, TA = 25°C PARAMETER Cpd d TEST CONDITIONS Power dissipation capacitance per flip-flop flip flop CL = 50 pF, pF f = 10 MHz VCC 3.3 V 5V TYP 32 68 UNIT pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION S1 1 kΩ From Output Under Test Vz Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Vz GND 1 kΩ WAVEFORM CONDITION Vm Vi Vz LOAD CIRCUIT VCC = 4.5 V to 5.5 V 0.5 × VCC VCC 2 × VCC VCC = 2.7 V to 3.6 V 1.5 V 2.7 V 6V Vi Vm Timing Input 0V tw tsu Vi Input Vm th Vi Vm Vm Data Input Vm 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Vi Vm Input 0V VOH Vm Output Vm VOL Output VOH Vm 0V Vm VOL tPLZ Output Waveform 1 S1 at Vz (see Note B) tPLH tPHL Vm Vm tPZL tPHL tPLH Vi Output Control Vm Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Vm tPZH 0.5 × Vz VOL + 0.3 V VOL tPHZ Vm VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. 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