Rev 0; 2/04 Parallel-Interface Elapsed Time Counter The DS1318 parallel-interface elapsed time counter (ETC) is a 44-bit counter that maintains the amount of time that the device operates from main and/or backup power or during an external event. The internal frequency of the counter clock is 4.096kHz, which provides a 244µs resolution and a maximum count of over 136 years. A built-in power-sense circuit detects power failures, automatically switches to the backup supply, and controls the timer. If an external event timer is desired, the control input EXT can control the counter operation. An open-drain output provides an interrupt, and a square-wave output provides a programmable square wave. The DS1318 is accessed through a bytewide parallel interface, and operates over the industrial temperature range. Applications Power Meters Features ♦ Byte-Wide Parallel Interface ♦ 44-Bit Binary Counter Provides Timer with 244µs Resolution ♦ Automatic Power-Fail Detect and Switch Circuitry Selects Power Source from the Primary Power and the Battery, and Write Protects the Internal Registers ♦ Internal Power-Fail Circuit Allows Timer to Provide Primary or Battery Operation Times ♦ Timer can Alternately Provide an Event Timer of Either an Active-High or Active-Low Pulse ♦ Interrupt Output Generated Periodically or When the Upper 32 Bits of the Counter Match an Alarm Register ♦ Square-Wave Output with 16 Selectable Frequencies from 32.768kHz to 0.5Hz ♦ +3.3V Operation ♦ Industrial Temperature Range: -40°C to +85°C Industrial Controls Servers Ordering Information PART DS1318 TEMP RANGE PINPACKAGE TOP MARK -40°C to +85°C 24 TSSOP, 4.4mm DS1318 Pin Configuration Typical Operating Circuit TOP VIEW VCC RPU X1 0.1µF VCC SQW IRQ WE CPU EXT OE CE A3–A0 DS1318 VBAT X1 - DQ–DQ7 GND X2 EXTERNAL COUNTER ENABLE (EVENT TIMER) X2 GND EXT A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 DS1318 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC VBAT IRQ SQW WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 TSSOP ______________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS1318 General Description DS1318 Parallel-Interface Elapsed Time Counter ABSOLUTE MAXIMUM RATINGS Voltage Range on any Pin Relative to Ground ......-0.3V to +6.0V Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature ......................................See IPC/JEDEC J-STD-020A Specification Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VCC (Note 2) 3.0 3.3 3.6 V Battery Voltage VCC (Note 2) 1.6 3.3 3.7 V Logic 1 Voltage VIH (Note 2) 0.7 x VCC VCC + 0.5 V Logic 0 Voltage VIL (Note 2) -0.5 +0.3 x VCC V MAX UNITS DC ELECTRICAL CHARACTERISTICS (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP Logic 0 Output Current (VOL = 0.15 x VCC) IOL 3 mA Logic 1 Output Current (VOH = 0.85 x VCC) IOH 1 mA IOLSI 5 mA SQW, INT Logic 0 Output (VOL = 0.15 x VCC) Input Leakage ILI (Note 3) I/O Leakage ILO (Note 4) ICCA (Note 5) ICCS (Note 6) Active Supply Current Standby Current Battery Input-Leakage Current Power-Fail Voltage 2 1 -1 IBATLKG VPF (Note 2) _____________________________________________________________________ 2.70 µA +1 µA 10 mA 100 150 µA 10 100 nA 2.97 V Parallel-Interface Elapsed Time Counter (VCC = 0V, VBACKUP = 3.7V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS Battery Input Current (ENOSC = 1) IBAT (Note 7) Battery Input Current (ENOSC = 0) IBATDR (Note 7) MIN TYP MAX UNITS 750 1100 nA 100 nA MAX UNITS AC ELECTRICAL CHARACTERISTICS (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER Read Cycle Time SYMBOL CONDITIONS tRC MIN TYP 80 ns Address Access Time tAA CE to DQ Low-Z tCEL CE Access Time tCEA CE Data Off-Time tCEZ OE to DQ Low-Z tOEL OE Access Time tOEA OE Data Off-Time tOEZ Output Hold from Address tOH 5 ns Write Cycle Time tWC 80 ns Address Setup Time 80 ns 80 ns 30 ns 70 ns 30 ns 0 ns 0 ns tAS 0 ns WE Pulse Width tWEW 40 ns CE Pulse Width tCEW 70 ns Data Setup Time tDS 40 ns Data Hold Time tDH 0 ns Address Hold Time tAH 0 ns WE Data Off-Time tWEZ Write Recovery Time tWR Oscillator Stop Flag (OSF) Delay tOSF 30 10 (Note 8) ns ns 4 ms _____________________________________________________________________ 3 DS1318 DC ELECTRICAL CHARACTERISTICS Parallel-Interface Elapsed Time Counter DS1318 Read Cycle Timing tRC A0–A4 tAA CE tOH tCEZ tCEA tCEL OE tOEZ tOEA tOEL VALID DQ0–DQ7 Write Cycle Timing, Write-Enable Controlled tWC A0–A4 VALID VALID tAS tAH CE tWEW tAS tWR WE tWEZ DQ0–DQ7 tDS DATA OUTPUT tDH DATA INPUT DATA INPUT Write Cycle Timing, Chip-Enable Controlled tWC A0–A4 VALID tAS VALID tCEW tAH CE tWR tAS WE tDS DQ0–DQ7 4 tDH DATA INPUT _____________________________________________________________________ DATA INPUT Parallel-Interface Elapsed Time Counter VCC VPF(MAX) VPF(MIN) tVCCF tVCCR tREC INPUTS RECOGNIZED RECOGNIZED DON'T CARE HIGH-Z OUTPUTS VALID VALID POWER-UP/POWER-DOWN CHARACTERISTICS (TA = -40°C to +85°C) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP (Note 9) MAX UNITS 150 ms Recovery at Power-Up tREC VCC Fall Time; VPF(MAX) to VPF(MIN) tVCCF 300 µs VCC Rise Time; VPF(MIN) to VPF(MAX) tVCCR 0 µs CAPACITANCE (TA = +25°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Capacitance on All Input Pins CIN 10 pF Capacitance on IRQ, SQW, and DQ Pins CIO 10 pF _____________________________________________________________________ 5 DS1318 Power-Up/Power-Down Timing AC TEST CONDITIONS PARAMETER TEST CONDITION Input Pulse Levels 0 to 2.7V Output Load Including Scope and Jig 25pF + 1TTL Gate Input and Output Timing Measurement Reference Levels VCC / 2 Input-Pulse Rise and Fall Times 4ns WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in write protection. Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Limits at -40°C are guaranteed by design and not production tested. All voltages are referenced to ground. OE, CE, WE, EXT, and A3–A0. DQ7–DQ0, SQW, and IRQ, when the outputs are high impedance. Outputs open. Specified with parallel bus inactive. Measured with a 32,768kHz crystal attached to the X1 and X2 pins. The parameter tOSF is the period of time that the oscillator must be stopped for the OSF flag to be set over the voltage range of 0V ≤ VCC ≤ VCC(MAX) and 1.3V ≤ VBACKUP ≤ 3.7V. This delay applies only if the oscillator is enabled and running. If the ENOSC bit is 0, tREC is disabled, and the device is immediately accessible. If CE and OE are low on power-up, the DQ outputs are active. Valid data out is not available until after tREC. Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) OSCILLATOR FREQUENCY vs. VOLTAGE IBAT vs. VBAT VCC = 0 32768.50 DS1318 toc02 850 DS1318 toc01 850 VCC = 0 800 32768.45 32768.40 750 700 FREQUENCY (Hz) SUPPLY CURRENT (nA) 800 750 700 650 32768.35 32768.30 32768.25 32768.20 32768.15 600 650 32768.10 550 600 32768.05 32768.00 500 -40 -20 0 20 40 TEMPERATURE (°C) 6 DS1318 toc03 IBAT vs. TEMPERATURE VBAT = 3.0V SUPPLY CURRENT (nA) DS1318 Parallel-Interface Elapsed Time Counter 60 80 1.5 1.9 2.3 2.7 3.1 3.5 VBACKUP (V) _____________________________________________________________________ 2.0 2.5 3.0 INPUT VOLTAGE (V) 3.5 4.0 Parallel-Interface Elapsed Time Counter X1 32,768Hz 32,768Hz CRYSTAL OSCILLATOR AND PRESCALER COUNTER 4,096Hz X2 CLOCK CONTROL CIRCUITRY 4,096Hz EXT SQUARE-WAVE RATE SELECTOR AND PRESCALER SQW BUFFERED COUNTER REGISTERS, CONTROL AND STATUS REGISTERS VCC VBAT VCC LEVEL DETECT, POWER SWITCH, AND WRITE PROTECT SUBSECONDS0 SUBSECONDS1 SUBSECONDS1 SECONDS0 SECONDS0 SECONDS1 SECONDS1 SECONDS2 SECONDS2 SECONDS3 INTERNAL DIVIDERS AND COUNTERS CE OE WE A3–A0 BYTE-WIDE RAM INTERFACE TRANSFER ENABLE (TE) SUBSECONDS0 SECONDS3 ALARM0 ALARM1 ALARM2 ALARM3 CONTROL A CONTROL B DQ7–DQ0 DS1318 PF/ALMF MUX IRQ STATUS _____________________________________________________________________ 7 DS1318 Functional Diagram Parallel-Interface Elapsed Time Counter DS1318 Pin Description PIN NAME FUNCTION 1 X1 2 X2 3, 12 GND Ground. This pin must be connected to ground for proper operation. External Counter-Enable Input Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a 12.5pF specified load capacitance (CL). X1 is the input to the oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the internal oscillator, X2, is floated if an external oscillator is connected to X1. 4 EXT 5–8 9, 10, 11, 13–17 18 A3–A0 DQ0–DQ7 CE Chip-Enable Input, Active Low 19 OE Output-Enable Input, Active Low 20 WE Write-Enable Input, Active Low 21 SQW Square-Wave Output 22 IRQ Interrupt Output. This active-low open-drain pin requires a pullup resistor. 23 VBAT Battery/Backup Power-Supply Input 24 VCC DC Power for Primary Power Supply Address Bus Inputs Bidirectional Data Pins Table 1. Operation Modes for Power-Supply Conditions WE DQ0–DQ7 X X X VIL VIL VIL VIH VIL VIH VIH VSO < VCC < VPF X X X VCC < VSO < VPF X X X VCC VCC > VPF CE OE VIH VIL Detailed Description The parallel-interface ETC contains a 44-bit up counter that maintains the amount of time the counter is enabled. The resolution of the timer is 244µs. A control register selects which events enable and disable the counter. The counter is double-buffered into two register sets, and the TE bit controls the updating of the user-readable copy. The counter can be used to maintain the cumulative amount of time the primary power source or the battery powers the device. In this mode, the counter starts when the internal power-switching circuit enables the selected power source and stops when the circuit enables the other source. The counter can also be used as an external event timer. In this mode, the counter starts when the signal EXT tog8 A0–A4 MODE POWER High-Z X Deselect Standby DIN AIN Write Active DOUT AIN Read Active High-Z AIN Read Active High-Z X CMOS Standby High-Z X Deselect Data Battery Current gles to the active sate and stops when it toggles to the inactive state. The active state of the EXT signal is configurable as high or low. EXT is ignored and the counter is disabled while the device is in power fail. The interrupt output pin provides two maskable interrupt sources. A 32-bit alarm register allows an interrupt to be generated whenever the upper 32 bits of the counter match the alarm register. A periodic interrupt can also be generated from once every 244µs to once every 1/12,097,152Hz (24.27 days). The alarm and interrupt output operate when the device is operating from either supply. Table 1 shows the factors that control the device operation. VSO is the battery switchover voltage and is the lesser of VBAT and VPF. While the device is operating from the battery with the oscillator running, the battery _____________________________________________________________________ Parallel-Interface Elapsed Time Counter DS1318 Table 2. Crystal Specifications* PARAMETER SYMBOL Nominal Frequency fO Series Resistance ESR Load Capacitance CL MIN TYP MAX UNITS 32.768 kHz 50 kΩ 12.5 pF *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications. RTC LOCAL GROUND PLANE (LAYER 2) COUNTDOWN CHAIN X1 CRYSTAL X2 C L1 CL2 RTC REGISTERS NOTE: AVOID ROUTING SIGNAL LINES IN THE CROSSHATCHED AREA (UPPER LEFT QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE DEVICE PACKAGE. X2 X1 GND CRYSTAL Figure 1. Oscillator Circuit Showing Internal Bias Network Figure 2. Layout Example input current is IBAT. The oscillator consumes most of the current. If the oscillator is disabled, the data in the registers remain static, and the battery input current is IBATDR, which is primarily due to the leakage of the static memory cells. The DS1318 uses a standard parallel byte-wide interface to access the register map. Table 1 summarizes the modes of operation at various power-supply conditions. An external 32.768kHz oscillator can also drive the DS1318. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. Oscillator Circuit The DS1318 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 2 specifies several crystal parameters for the external crystal, and Figure 1 shows a functional schematic of the oscillator circuit. An enable bit in the control register controls the oscillator. Oscillator startup times are highly dependent upon crystal characteristics, PC board leakage, and layout. High ESR and excessive capacitive loads are the major contributors to long startup times. A circuit using a crystal with the recommended characteristics and proper layout usually starts within one second. Clock Accuracy The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Figure 2 shows a typical PC board layout for isolation of the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks for more detailed information. _____________________________________________________________________ 9 DS1318 Parallel-Interface Elapsed Time Counter Table 3. Address Map ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE 00H SS3 SS2 SS1 SS0 0 0 0 SQWS Subseconds0 00–F0h 01H SS11 SS10 SS9 SS8 SS7 SS6 SS5 SS4 Subseconds1 00–FFh 02H S7 S6 S5 S4 S3 S2 S1 S0 Seconds0 00–FFh 03H S15 S14 S13 S12 S11 S10 S9 S8 Seconds1 00–FFh 04H S23 S22 S21 S20 S19 S18 S17 S16 Seconds2 00–FFh 05H S31 S30 S29 S28 S27 S26 S25 S24 Seconds3 00–FFh 06H ALM7 ALM6 ALM5 ALM4 ALM3 ALM2 ALM1 ALM0 Alarm0 00–FFh 07H ALM15 ALM14 ALM13 ALM12 ALM11 ALM10 ALM9 ALM8 Alarm1 00–FFh 08H ALM23 ALM22 ALM21 ALM20 ALM19 ALM18 ALM17 ALM16 Alarm2 00–FFh 00–FFh 09H ALM31 ALM30 ALM29 ALM28 ALM27 ALM26 ALM25 ALM24 Alarm3 0AH TE ENOSC CCFG1 CCFG0 EPOL SQWE PIE AIE ControlA 00–FFh 0BH PRS3 PRS2 PRS1 PRS0 SRS3 SRS2 SRS1 SRS0 ControlB 00–FFh 0CH OSF UIP 0 0 0 0 PF ALMF Status — Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. Counter Operation The binary time information is obtained by reading the appropriate register bytes. Registers 02h through 05h contain the time in seconds from an arbitrary reference time determined by the user. Registers 00h and 01h contain the fractional seconds count. A buffered copy of the clock registers (A0–A5), updated every 244µs, allows the user to read and write the registers while the internal registers continue to increment. However, it is possible to read or write inconsistent data, or for a write to corrupt the current buffered read copy, if an update occurs during the read or write. Several methods may be used to ensure that the data is accurate. The clock registers can be read, with the least-significant byte (LSB) being read once at the beginning and again after the other registers have been read (i.e., A2–A5, A2). If the LSB register data has changed, the registers should be re-read until the LSB register data matches. If the subseconds0 register is used, the user never has more than 244µs to read all the registers before a mismatch occurs. In addition, if the routine used to read the registers takes approximately 1.95ms to read the registers, it is possible that the subseconds0 register could roll over to the same value as previously read. Other methods use the TE and UIP bits to synchronize accessing the clock registers to ensure that the data are valid. These methods are discussed in later sections. 10 Alarm To use the alarm function, the user writes registers 06h through 09h with a time in seconds. When the current time in seconds becomes equal to the alarm value, the ALMF bit in the status register (0Ch) is set to 1. If the AIE bit in control register A is set to 1 by the user, then the IRQ pin is driven low when the ALMF bit is set to 1. The alarm and IRQ output operate when the device is running from either supply. Periodic Flag Writing a non-zero value into the periodic flag rateselect bits in control register B enables the periodic flag operation. The periodic flag is set to logic 1 when the internal counter reaches the selected value. Writing the PF bit to 0 resets the periodic flag. If the flag is not reset, it remains high. Once the PF bit is set, the internal counter continues counting, and attempts to set the PF bit again when the count again matches the selected rate value. Clearing the PF bit has no effect on the internal counter. If the PIE bit in control register A is set to 1, the IRQ output goes low when the PF bit is set. The periodic flag and IRQ output operates when the device is running from either supply. Note that writing to the subseconds or seconds registers affects the setting of the PF flag and IRQ output. The square-wave output uses a separate prescaler and is not affected by changes to the subseconds or seconds bits. ____________________________________________________________________ Parallel-Interface Elapsed Time Counter BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TE ENOSC CCFG1 CCFG0 EPOL SQWE PIE AIE Special-Purpose Registers The DS1318 has three additional registers (control A, control B, and status) that control the clock, alarms, square wave, and interrupt output. The subseconds0 register has a square-wave synchronization (SQWS) bit in the bit 0 location. Writing the SQWS bit to 1 clears the square-wave prescaler and holds it in reset. Only the frequencies below 4096Hz are reset. Writing the bit back to 0 takes the prescaler out of reset and starts the square wave running. Bit 7: Transfer Enable (TE). When TE is set to logic 1, the DS1318 continues to update the user copy of the time value as it receives 4,096Hz clock pulses from the oscillator. To ensure reading valid time data from the part, the user should set TE to logic 0 before reading registers 00–05h. TE must be enabled (logic 1) for at least 244µs to ensure that a transfer occurs. Note that because of the 244µs restriction, sequential values of the subseconds0 register cannot be read when TE is used. It is possible that TE could be set to logic 0 while a transfer is taking place. In that case, the buffered data could be invalid. To prevent this, the UIP bit, described later, should be used. To write data to the clock registers, the user should set TE to logic 0, write the registers, and set TE to logic 1. Bit 3: External Polarity (EPOL). This bit controls the polarity on the EXT pin input when the CCFG1 and CCFG0 bits are equal to 0 and 1, respectively. When EPOL is set to logic 1, the registers count when the EXT pin is 1. When EPOL is set to logic 0, the registers count when the EXT pin is logic 0. Bit 2: Square-Wave Enable (SQWE). When SQWE is set to logic 1, a frequency determined by the SRSx bits in control register B (0Bh) is output on the SQW pin. When SQWE is logic 0, the SQW pin is always 0. When the part is in power-fail, the SQW pin is always highimpedance. The square-wave output uses a separate prescaler from the one used by PF, IRQ, UIP, and the up counter. The SQWS bit in control register A can be used to synchronize the square-wave output to within 244µs of the other events. Bit 1: Periodic Interrupt Enable (PIE). When PIE is set to logic 1, the DS1318 sets the IRQ pin low whenever the PF flag is set to 1. When PIE is 0, the PF flag does not affect the IRQ pin. Bit 0: Alarm Interrupt Enable (AIE). When AIE is set to logic 1, the DS1318 sets the IRQ pin low whenever the ALMF flag is set to 1. When AIE is 0, the ALMF flag does not affect the IRQ pin. Bit 6: Enable Oscillator (ENOSC). When ENOSC is set to logic 1, the DS1318 crystal oscillator becomes enabled. Actual startup time for the oscillator depends on many external variables and is not a specified parameter. Bits 5, 4: Clock Configuration 1, 0 (CCFG1, CCFG0). These bits determine which of the four possible modes the DS1318 uses to clock its timekeeping registers: CCFG1 CCFG0 MODE 0 0 Always clocks the registers (normal mode) 0 1 Clocks when the EXT pin is “active” and VCC is greater than VPF (event-timer mode, depends on EPOL bit) 1 0 Clocks registers when part is running on VCC 1 1 Clocks registers when part is running on VBAT ____________________________________________________________________ 11 DS1318 Control Register A (0Ah) DS1318 Parallel-Interface Elapsed Time Counter Control Register B (0Bh) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PRS3 PRS2 PRS1 PRS0 SRS3 SRS2 SRS1 SRS0 Bits 7 to 4: Periodic Rate Select (PRS3–PRS0). When the oscillator is enabled (ENOSC = 1) the PF flag is set at the rates determined by the following table: Periodic Flag Frequency When ENOSC = 1 PRS3 PRS2 PRS0 PERIODIC FLAG FREQUENCY 0 0 0 0 Periodic Flag Not Set 0 0 0 1 4096Hz 0 0 1 0 2048Hz 0 0 1 1 1024Hz 0 1 0 0 512Hz 0 1 0 1 256Hz 0 1 1 0 128Hz 0 1 1 1 8Hz 1 0 0 0 4Hz 1 0 0 1 2Hz 1 0 1 0 1Hz 1 0 1 1 1/64Hz (Once per 1.067 Minutes) 1 1 0 0 1/4096Hz (Once per 1.138 Hours) 1 12 PRS1 1 0 1 Bits 3 to 0: Square-Wave Rate Select (SRS3–SRS0). When the oscillator is enabled (ENOSC = 1) and running, and the square-wave pin is enabled (SQWE = 1), the SQW pin outputs a square-wave signal determined by the SRS bits according to the following table: Square-Wave Output Frequency When SQWE = 1, ENOSC = 1 SRS3 SRS2 SRS1 SRS0 SQUARE-WAVE OUTPUT FREQUENCY (Hz) 0 0 0 0 32,768 0 0 0 1 8192 0 0 1 0 4096 0 0 1 1 2048 0 1 0 0 1024 0 1 0 1 512 0 1 1 0 256 0 1 1 1 128 1 0 0 0 64 1 0 0 1 32 1 0 1 0 16 1 0 1 1 8 1 1 0 0 4 1/65536Hz (Once per 1.318 Days) 1 1 0 1 2 1 1 1 0 1 1 1 1 1 0.5 1 1 1 0 1/524288Hz (Once per 0.8669 Weeks) 1 1 1 1 1/2097152Hz (Once per 24.27 Days) ____________________________________________________________________ Parallel-Interface Elapsed Time Counter BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OSF UIP 0 0 0 0 PF ALMF Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is or was stopped for some period of time and may be used to judge the validity of the timekeeping data. This bit is set to logic 1 any time the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) 3) 4) The voltage present on both V CC and V BAT is insufficient to support oscillation. The ENOSC bit is turned off in battery-backed mode. External influences on the crystal (i.e., noise, leakage, etc.) Any write to the status register while this flag is active clears the bit to 0. Bit 6: Update-In-Progress Flag (UIP). A logic 1 in the update-in-progress bit indicates that the internal clock registers may be in the process of updating the user registers. Writing to any seconds or subseconds registers when this bit is logic 1 may cause a collision with the internal update and corrupt one or more of the user registers until the next update occurs. If the UIP bit is read and is logic 0, the user has at least 60µs to write to the device without the possibility of causing a collision with the internal update. The internal timekeeping update is gated by the falling edge of UIP. Bit 1: Periodic Flag (PF). The periodic flag bit is set to 1 at the rate determined by the PRS bits in register 0Bh. If the PF bit is already 1 when the selected frequency attempts to set it to 1 again, no change occurs. The user must clear the PIF flag faster than the part attempts to set it to see the desired PF rate. If the PIE bit in register 0Ah is also set to logic 1, the IRQ pin is driven low in response to PF transitioning to 1. Any write to the status register while this flag is active clears the bit to 0. Bit 0: Alarm Flag (ALMF). A logic 1 in the alarm flag bit indicates that the contents of the seconds registers matched the contents of the alarm registers. If the AIE bit in register 0Ah is also set to logic 1, the IRQ pin is driven low in response to ALMF transitioning to 1. Any write to the status register while this flag is active clears the bit to 0. Reading the subseconds and or seconds registers while UIP is logic 1 may result in reading inconstant values. If the UIP bit is read and is logic 0, the user has at least 60µs to read from the device without the possibility of getting inconstant values. UIP vs. Update Timing 8kHz 4kHz UIP 60µs ____________________________________________________________________ 13 DS1318 Status Register (0Ch) DS1318 Parallel-Interface Elapsed Time Counter Chip Information TRANSISTOR COUNT: 10,517 PROCESS: CMOS SUBSTRATE CONNECTED TO GROUND Package Information For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. Thermal Information Theta-JA: 125°C/W Theta-JC: 26°C/W Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.