DS1558 Watchdog Clock with NV RAM Control www.maxim-ic.com § § § § § § § § ORDERING INFORMATION PART DS1558Y DS1558W PINPACKAGE 48 TQFP 48 TQFP VCC (V) TOP MARK 5 3.3 DS1558B DS1558D N.C. A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 GND X1 X2 GND A17 N.C. VCC N.C. VCCO NC RST VBAT2 TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 § Integrated real-time clock (RTC), power-fail control circuit, and NV RAM controller Clock registers are accessed identically to the static RAM; these registers are resident in the 16 top RAM locations Century register Greater than 10 years of timekeeping and data retention in the absence of power with small lithium coin cell(s) and low-leakage SRAM Precision power-on reset Programmable watchdog timer and RTC alarm BCD-coded year, month, date, day, hours, minutes, and seconds with automatic leapyear compensation valid up to the year 2100 Battery voltage-level indicator flag Power-fail write protection allows for ±10% VCC power-supply tolerance Underwriters Laboratory (UL) recognized 1 2 3 4 5 6 7 8 9 10 11 12 DS1558 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 § PIN CONFIGURATION A15 VBAT1 WE IRQ/FT A13 A8 A9 A11 OE A10 CE OER N.C. A0 DQ0 DQ1 DQ2 GND DQ3 DQ4 DQ5 DQ6 DQ7 CER FEATURES TQFP Package Dimension Information: www.maxim-ic.com/DallasPackInfo PIN DESCRIPTION A0–A18 DQ0–DQ7 IRQ /FT RST CE CER OE OER WE VCC VCCO GND N.C. X1, X2 VBAT1 VBAT2 - Address Input - Data Input/Outputs - Interrupt, Frequency-Test Output (Open Drain) - Power-On Reset Output (Open Drain) - Chip-Enable Input - Chip-Enable RAM - Output-Enable Input - Output-Enable RAM - Write Enable - Power-Supply Input - VCC Out to RAM - Ground - No Connection - Crystal Connection - +3V Battery Input - +3V Battery Input Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.. 1 of 18 REV: 082503 DS1558 TYPICAL OPERATING CIRCUIT DESCRIPTION The DS1558 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar with an RTC alarm, watchdog timer, power-on reset, battery monitor, and NV SRAM controller. User access to all registers within the DS1558 is accomplished with a byte-wide interface as shown in Figure 1. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for day of month and leap year are made automatically. The DS1558 maps the RTC registers into the SRAM address space and constantly monitors A0–A18. When any of the upper 16 address locations are accessed, the DS1558 inhibits CER and OER to the SRAM, and redirects reads and writes to the RTC registers within the DS1558. The DS1558 can be used with SRAMs up to 524,272 addresses. Smaller SRAMs can be used, provided that the unused upper address lines on the DS1558 are connected to VCC. The RTC registers are double-buffered into an internal and external set. The user has direct access to the external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers is continuously updated; this occurs regardless of external register settings to guarantee that accurate RTC information is always maintained. The DS1558 has interrupt ( IRQ /FT) and reset ( RST ) outputs that can be used to control CPU activity. The IRQ /FT interrupt output can be used to generate an external interrupt when the RTC register values match user-programmed alarm values. The interrupt is always available while the device is powered from the system supply, and it can be programmed to occur when in the battery-backed state to serve as a system wake-up. The IRQ /FT output can also be used as a CPU watchdog timer. CPU activity is monitored and an interrupt or reset output are activated if the correct activity is not detected within 2 of 18 DS1558 programmed limits. The DS1558 power-on reset can be used to detect a system power-down or failure and hold the CPU in a safe reset state until normal power returns and stabilizes; the RST output is used for this function. The DS1558 also contains its own power-fail circuitry, which automatically protects the data in the clock and SRAM against out-of-tolerance VCCI conditions by inhibiting the CE input when the VCC supply enters an out-of-tolerance condition. When VCCI goes below the level of VBAT, the external battery is switched on to supply energy to the clock and the external SRAM. This feature provides a high degree of data security during unpredictable system operation brought on by low VCC levels. Figure 1. BLOCK DIAGRAM Note: Any unused upper address pins must be connected to VCC to properly address the RTC. SIGNAL DESCRIPTIONS A0–A18 – Address inputs for address decode. The DS1558 uses the address inputs to determine whether or not a read or write cycle should be directed to the attached SRAM or to the RTC registers. DQ0–DQ7 – Data input/output pins for the RTC registers. IRQ /FT – This pin is used to output the alarm interrupt or the frequency test signal. It is open drain and requires an external pullup resistor. RST – This pin is an output used to signal that VCC is out of tolerance. On power-up, RST is held low for a period of time to allow the system to stabilize. The RTC and SRAM are not accessible while RST is active. This pin is open drain and requires an external pullup resistor. CE – Chip-enable input that is used to access the RTC and the external SRAM. 3 of 18 DS1558 – Chip-enable RAM output. CE is passed through to CER , with an added propagation delay. When the signals on A0–A18 match an RTC address, CER is held high, disabling the SRAM. If OE is also low, the RTC outputs data on DQ0–DQ7. CER OE – Output-enable input that is used to access the RTC and the external SRAM. – Output-enable RAM output. OE is passed through to OER , with an added propagation delay. When the signals on A0–A18 match an RTC address, CER is held high, disabling the SRAM. If CE is also low, the RTC outputs data on DQ0–DQ7. OER WE – Write-enable input that is used to write data to the RTC registers. VCC, GND – DC power is provided to the device on these pins. VCC is the +5V input. When 5V (or 3.3V for the 3.3V version) is applied within normal limits, the device is fully accessible and data can be written and read. Reads and writes are inhibited when a 3V battery is connected to the device and VCC is VTP. However, the timekeeping function continues unaffected by the lower input voltage. As VCC falls below VBAT, the RAM and RTC are switched over to the external power supply (nominal 3.0V DC) at VBAT. VCCO – VCC output to RAM. While VCC is above VBAT, the external SRAM is powered by VCC. When VCC is below the battery level, the SRAM is powered by one of the VBAT inputs. N.C. – No internal connection. X1, X2 – Connections for a standard 32.768kHz quartz crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 6pF. For more information about crystal selection and crystal layout considerations, refer to Application Note 58 “Crystal Considerations with Dallas Real-Time Clocks.” The DS1558 can also be driven by an external 32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. VBAT1, VBAT2 – Battery inputs for any standard 3V lithium cell or other energy source. Battery voltage must be held between 2.5V and 3.7V for proper operation. UL recognized to ensure against reverse charging current when used with a lithium battery. If only one battery is used, it should be attached to VBAT1, and VBAT2 should be grounded. See “Conditions of Acceptability” at http://www.maxim-ic.com/TechSupport/QA/ntrl.htm. 4 of 18 DS1558 Table 1. OPERATING MODES VCC X VIL VIH VIH X DQ0–DQ7 High-Z DIN DOUT High-Z High-Z MODE Deselect Write Read Read Deselect POWER Standby Active Active Active CMOS Standby X High-Z Data Retention Battery Current CE OE WE VSO < VCC < VPF VIH VIL VIL VIL X X X VIL VIH X VCC < VSO < VPF X X VCC > VPF DATA READ MODE The DS1558 is in the read mode whenever CE is low and WE is high. The device architecture allows ripple-through access to any valid address location. Valid data is available at the DQ pins within tAA after the last address input is stable, provided that CE and OE access times are satisfied. If CE or OE access times are not met, valid data is available at the latter of chip-enable access (tCEA) or at output-enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data remains valid for output-data hold time (tOH), but then goes indeterminate until the next address access. DATA WRITE MODE The DS1558 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout the cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent read or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for tDH afterward. In a typical application, the OE signal is high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low, the data bus can become active with read data defined by the address inputs. A low transition on WE then disables the outputs tWEZ after WE goes active. DATA RETENTION MODE The 5V device is fully accessible and data can be written and read only when VCC is greater than VPF. However, when VCC is below the power-fail point VPF (point at which write protection occurs), the internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The 3.3V device is fully accessible and data can be written and read only when VCC is greater than VPF. When VCC falls below VPF, access to the device is inhibited. If VPF is less than VSO, the device power is switched from VCC to the internal backup lithium battery when VCC drops below VPF. If VPF is greater than VSO, the device power is switched from VCC to the internal backup lithium battery when VCC drops below VSO. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. All control, data, and address signals must be powered down when VCC is powered down. 5 of 18 DS1558 BATTERY LONGIVITY The battery lifetime is dependent on the RAM battery standby current and the DS1558 internal clock oscillator current. The total battery current is IOSC + ICCO. When VCC is above VPF, IBAT current is less than 50nA. The DS1558 has an internal circuit to prevent battery charging. No external protection components are required, and none should be used. The DS1558 has two battery pins that operate independently; the DS1558 selects the higher of the two inputs. If only one battery is used, the battery should be attached to VBAT1, and VBAT2 should be grounded. INTERNAL BATTERY MONITOR The DS1558 constantly monitors the battery voltage of the internal battery. The battery-low flag (BLF) bit of the flags register (B4 of 7FFF0h) is not writable and should always be a 0 when read. If a 1 is ever present, both battery inputs are below 1.8V and both the contents of the RTC and RAM are questionable. POWER-ON RESET A temperature-compensated comparator circuit monitors the level of VCC. When VCC falls to the powerfail trip point, the RST signal (open drain) is pulled low. When VCC returns to nominal levels, the RST signal continues to be pulled low for a period of 40ms to 200ms. The power-on reset function is independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled. 6 of 18 DS1558 CLOCK OPERATIONS Table 2 and the following paragraphs describe the operation of the RTC, alarm, and watchdog functions. Table 2. DS1558 REGISTER MAP ADDRESS DATA B7 B6 7FFFFh B5 B4 B3 B2 10 YEAR 10 M B0 FUNCTION/RANGE YEAR YEAR 00–99 MONTH MONTH 01–12 DATE DATE 01–31 DAY 01–07 HOUR 00–23 7FFFEh X X 7FFFDh X X 7FFFCh X FT 7FFFBh X X 7FFFAh X 10 MINUTES MINUTES MINUTES 00–59 SECONDS SECONDS 00–59 7FFF8h OSC W 10 SECONDS R CENTURY CONTROL 00–39 7FFF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 WATCHDOG — 7FFF6h AE Y ABE Y Y Y Y Y INTERRUPTS — 7FFF5h AM4 Y 10 DATE DATE ALARM DATE 01–31 7FFF4h AM3 Y 10 HOURS HOURS ALARM HOURS 00–23 7FFF9h X B1 10 DATE X X X DAY 10 HOUR HOUR 10 CENTURY 7FFF3h AM2 10 MINUTES MINUTES ALARM MINUTES 00–59 7FFF2h AM1 10 SECONDS SECONDS ALARM SECONDS 00–59 7FFF1h Y Y Y Y Y Y Y Y UNUSED — 7FFF0h WF AF 0 BLF 0 0 0 0 FLAGS — X = Unused, Read/Writeable Under Write and Read Bit Control AE = Alarm Flag Enable FT = Frequency Test Bit Y = Unused, Read/Writeable Without Write and Read Bit Control OSC = Oscillator Start/Stop Bit ABE = Alarm in Backup-Battery Mode Enable W = Write Bit AM1–AM4 = Alarm Mask Bits R = Read Bit WF = Watchdog Flag WEN = Watchdog Enable Bit AF = Alarm Flag BMB0–BMB4 = Watchdog Multiplier Bits 0 = Reads as a 0 and Cannot Be Changed RB0–RB1 = Watchdog Resolution Bits BLF = Battery Low Flag CLOCK OSCILLATOR CONTROL The oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB of the seconds register (B7 of 7FFF9h). Setting OSC to a 1 stops the oscillator; setting to a 0 starts the oscillator. The initial state of OSC is not guaranteed. When power is applied for the first time, the OSC bit should be enabled. Oscillator operation and frequency can be verified by setting the FT bit and monitoring the IRQ /FT pin for 512Hz. OSCILLATOR STARTUP TIME Oscillator startup times are highly dependent upon crystal characteristics and layout. High ESR and excessive capacitive loads are the major contributors to long startup times. A circuit using a crystal with the recommended characteristics and following the recommended layout usually starts within 1 second. 7 of 18 DS1558 READING THE CLOCK When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC registers. This puts the external registers into a static state, allowing data to be read without register values changing during the read process. Normal updates to the internal registers continue while in this state. External updates are halted when a 1 is written into the read bit, B6 of the control register (7FFF8h). As long as a 1 remains in the control register read bit, updating is halted. After a halt is issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt command is issued. Normal updates to the external set of registers resume within 1 second after the read bit is set to a 0 for a minimum of 500ms. The read bit must be a 0 for a minimum of 500ms to ensure the external registers are updated. SETTING THE CLOCK The MSB bit, B7, of the control register is the write bit. Setting the write bit to a 1, like the read bit, halts updates to the 7FFF8h–7FFFFh registers. After setting the write bit to a 1, RTC registers can be loaded with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the write bit to a 0 then transfers the values written to the internal RTC registers and allows normal operation to resume. CLOCK ACCURACY The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by the crystal-frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Refer to Application Note 58 “Crystal Considerations with Dallas Real-Time Clocks” for detailed information. FREQUENCY TEST MODE The DS1558 frequency test mode uses the open-drain IRQ /FT output. With the oscillator running, the IRQ /FT output toggles at 512Hz when the FT bit is a 1, the alarm-flag enable bit (AE) is a 0, and the watchdog-enable bit (WDS) is a 1, or the watchdog register is reset (register 7FFF7h = 00h). The IRQ /FT output and the frequency test mode can be used as a measure of the actual frequency of the 32.768kHz RTC oscillator. The IRQ /FT pin is an open-drain output that requires a pullup resistor for proper operation. The FT bit is cleared to a 0 on power-up. USING THE CLOCK ALARM The alarm settings and control for the DS1558 reside within registers 7FFF2h–7FFF5h. Register 7FFF6h contains two alarm-enable bits: alarm enable (AE) and alarm in backup enable (ABE). The AE and ABE bits must be set as described below for the IRQ /FT output to be activated for a matched alarm condition. The alarm can be programmed to activate on a specific day of the month or repeat every day, hour, minute, or second. It can also be programmed to go off while the DS1558 is in the battery-backed state of operation to serve as a system wake-up. Alarm mask bits AM1–AM4 control the alarm mode. Table 3 shows the possible settings. Configurations not listed in the table default to the once-per-second mode to notify the user of an incorrect alarm setting. 8 of 18 DS1558 Table 3. ALARM MASK BITS AM4 1 1 1 1 0 AM3 1 1 1 0 0 AM2 1 1 0 0 0 AM1 1 0 0 0 0 ALARM RATE Once per second When seconds match When minutes and seconds match When hours, minutes, and seconds match When date, hours, minutes, and seconds match When the RTC register values match alarm register settings, AF is set to a 1. If AE is also set to a 1, the alarm condition activates the IRQ /FT pin. The IRQ /FT signal is cleared by a read or write to the flags register (address 7FFF0h). When CE is active, the IRQ /FT signal can be cleared by having the address stable for as short as 15ns and either OE or WE active, but is not guaranteed to be cleared unless tRC is fulfilled (Figure 2). Once the address has been selected for at least 15ns, the IRQ /FT signal can be cleared immediately, but is not guaranteed to be cleared until tRC is fulfilled (Figure 3). The alarm flag is also cleared by a read or write to the flags register, but the flag does not change states until the end of the read/write cycle and the IRQ /FT signal has been cleared. The IRQ /FT pin can also be activated in the battery-backed mode. The IRQ /FT goes low if an alarm occurs and both ABE and AE are set. The ABE and AE bits are cleared during the power-up transition, but an alarm generated during power-up sets AF. Therefore, the AF bit can be read after system power-up to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates alarm timing during the backup-battery mode and power-up states. Figure 2. CLEARING IRQ WAVEFORMS ACTIVE Figure 3. CLEARING IRQ WAVEFORMS 9 of 18 DS1558 Figure 4. BACKUP MODE ALARM WAVEFORMS USING THE WATCHDOG TIMER The watchdog timer can be used to detect an out-of-control processor. The user programs the watchdog timer by setting the desired amount of timeout into the 8-bit watchdog register (address 7FFF7h). The five watchdog register bits BMB4–BMB0 store a binary multiplier and the two lower-order bits RB1–RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The watchdog timeout value is then determined by the multiplication of the 5-bit multiplier value with the 2-bit resolution value. (For example: writing 00001110 in the watchdog register = 3 x 1 second or 3 seconds.) If the processor does not reset the timer within the specified period, the watchdog flag (WF) is set and a processor interrupt is generated and stays active until either WF is read or the watchdog register (7FFF7h) is read or written. The MSB of the watchdog register is the watchdog steering bit (WDS). When set to a 0, the watchdog activates the IRQ /FT output when the watchdog times out. WDS should not be written to a 1, and should be initialized to a 0 if the watchdog function is enabled. The watchdog timer resets when the processor performs a read or write of the watchdog register. The timeout period then starts over. The watchdog timer is disabled by writing a value of 00h to the watchdog register. The watchdog function is automatically disabled upon power-up and the watchdog register is cleared. POWER-ON DEFAULT STATES Upon application of power to the device, the following register bits are set to a 0: WDS = 0, BMB0–BMB4 = 0, RB0–RB1 = 0, AE = 0, and ABE = 0 All other bits are undefined. 10 of 18 DS1558 ABSOLUTE MAXIMUM RATINGS* Voltage Range on Any Pin Relative to Ground Storage Temperature Range Soldering Temperature Range -0.3V to +6.0V -55°C to +125°C See IPC/JEDEC J-STD-020A *This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability. RECOMMENDED DC OPERATING CONDITIONS (VCC = 3.3V ±10% or 5V ±10%, TA = -40°C to +85°C) PARAMETER Logic 1 Voltage (All Inputs) SYMBOL MIN VCC = +5V ±10% VCC = +3.3V ±10% Logic 0 Voltage (All Inputs) VIH VIH VCC = +5V ±10% VCC = +3.3V ±10% Battery Voltage MAX UNITS NOTES 2.2 2.0 VCC + 0.3V VCC + 0.3V V V 1 1 VIL VIL -0.3 -0.3 +0.8 +0.6 VBAT 2.5 11 of 18 TYP 3.3 3.7 1 1 V DS1558 DC ELECTRICAL CHARACTERISTICS (VCC = +3.3V ±10% or +5V ±10%, TA = -40°C to +85°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Active Supply Current, +5V ICC 6 25 mA 2, 3 Active Supply Current, +3.3V ICC 4 15 mA 2, 3 TTL Standby, +5V ( CE = VIH) ICC1 3 6 mA 2, 3 TTL Standby, +3.3V ( CE = VIH) ICC1 2 6 mA 2, 3 ICC2 2 6 mA 2, 3 ICC2 1 2 mA 2, 3 CMOS Standby Current, +5V ( CE ³ VCC - 0.2V) CMOS Standby Current, +3.3V ( CE ³ VCC - 0.2V) Input Leakage Current (Any Input) Output Leakage Current (Any Output) Output Logic 1 Voltage (IOUT = -1.0mA) Output Logic 0 Voltage IOUT = 2.1mA, DQ0–DQ7 Outputs IOUT = 7.0mA, IRQ /FT and RST Outputs IIL -1 +1 mA IOL -1 +1 mA VOH 2.4 V 1 VOL1 0.4 V 1 VOL2 0.4 V 1, 5 Write Protection Voltage, +5V VPF 4.20 4.37 4.50 V 1 Write Protection Voltage, +3.3V VPF 2.75 2.88 2.97 V 1 Battery Switchover Voltage, +5V VSO VBAT V 1 Battery Switchover Voltage, +3.3V VSO VPF V 1, 4 Battery Current OSC On IOSC 0.3 0.5 µA 6,7 Battery Current OSC Off IBACKUP 100 nA 7 Output Voltage ICCO = 70mA, +5V VCC01 VCC1 - 0.3 V Output Voltage ICCO = 40mA, +3.3V VCC01 VCC1 - 0.3 V Output Voltage ICCO = 10µA VCC02 VBAT - 0.2 VBAT - 0.031 V 10 CRYSTAL SPECIFICATIONS* PARAMETER Nominal Frequency Series Resistance Load Capacitance SYMBOL MIN FO ESR CL TYP MAX UNITS 45 kHz kΩ pF 32.768 6 NOTES *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58 “Crystal Considerations for Dallas Real-Time Clocks” for additional specifications. 12 of 18 DS1558 READ CYCLE, AC CHARACTERISTICS (VCC = +3.3V ±10% or +5V ±10%, TA = -40°C to +85°C) PARAMETER Read Cycle Time Address Access Time to DQ Low-Z CE Access Time CE Data Off Time OE to DQ Low-Z OE Access Time OE Data Off Time Output Hold from Address CE to CER Propagation Delay, +5V OE to OER Propagation Delay, +5V CE to CER Propagation Delay, +3.3V OE to OER Propagation Delay, +3.3V CE SYMBOL tRC tAA tCEL tCEA tCEZ tOEL tOEA tOEZ tOH VCC = +5.5V ±10% MIN 70 MAX VCC = +3.3V ±10% MIN 120 70 5 MAX 120 5 70 25 5 120 40 5 35 25 5 100 35 5 UNITS NOTES ns ns ns ns ns ns ns ns ns tCEPD 15 ns tOEPD 20 ns tCEPD 30 ns tOEPD 40 ns Figure 5. READ CYCLE TIMING DIAGRAM 13 of 18 DS1558 WRITE CYCLE, AC CHARACTERISTICS (VCC = +3.3V ±10% or +5V ±10%, TA = -40°C to +85°C) PARAMETER SYMBOL Write Cycle Time Address Access Time tWC tAS Pulse Width CE Pulse Width Data Setup Time Data Hold Time Data Hold Time Address Hold Time Address Hold Time tWEW tCEW tDS tDH1 tDH2 tAH1 tAH2 tWEZ tWR WE Data Off Time Write Recovery Time WE VCC = +5.0V ±10% MIN 70 0 50 60 30 5 5 5 5 MAX VCC = +3.3V ±10% MIN 120 0 100 110 80 5 5 0 5 25 5 MAX UNITS NOTES 40 10 Figure 6. WRITE CYCLE TIMING, WRITE-ENABLE CONTROLLED 14 of 18 ns ns ns ns ns ns ns ns ns ns ns 8 9 8 9 DS1558 Figure 7. WRITE CYCLE TIMING, CHIP-ENABLE CONTROLLED 15 of 18 DS1558 POWER-UP/DOWN CHARACTERISTICS PARAMETER (VCC = +5V ±10%, TA = -40°C to +85°C) SYMBOL MIN tPD 0 ms tF 300 ms VCC Fall Time: VPF(MIN) to VSO tFB 10 ms VCC Rise Time: VPF(MIN) to VPF(MAX) tR 0 ms tREC 40 CE or WE at VIH, Before Power-Down VCC Fall Time: VPF(MAX) to VPF(MIN) VPF to RST High TYP Figure 8. +5V POWER-UP/DOWN WAVEFORM TIMING 16 of 18 MAX 200 UNITS ms NOTES DS1558 POWER-UP/DOWN CHARACTERISTICS PARAMETER CE or WE at VIH, Before Power-Down VCC Fall Time: VPF(MAX) to VPF(MIN) VCC Rise Time: VPF(MIN) to VPF(MAX) VPF to RST High (VCC = +3.3V ±10%, TA = -40°C to +85°C) SYMBOL MIN TYP MAX tPD 0 ms tF 300 ms tR 0 ms tREC 40 200 UNITS NOTES ms Figure 9. +3.3V POWER-UP/DOWN WAVEFORM TIMING CAPACITANCE PARAMETER (TA = +25°C) SYMBOL MIN TYP MAX UNITS NOTES Capacitance On All Input Pins CIN 7 pF 1 Capacitance On IRQ /FT, RST , and DQ Pins CIO 10 pF 1 17 of 18 DS1558 AC TEST CONDITIONS Output Load: 25pF Input Pulse Levels: 0V to +3V Timing Measurement Reference Levels: Input: +1.5V Output: +1.5V Input Pulse Rise and Fall Times: 5ns NOTES: 1) Voltage referenced to ground. 2) Typical values are at +25°C and nominal supplies. 3) Outputs are open. 4) Battery switchover occurs at the lower of either the battery voltage or VPF. 5) The IRQ /FT and RST outputs are open drain. 6) Using the recommended crystal on X1 and X2. 7) VCCO, CER , and OER pins open. 8) tAH1, tDH1 are measured from WE going high. 9) tAH2, tDH2 are measured from CE going high. 10) Typical measured with VBAT at 3.0V. Typical with ICCO = 100µA and VBAT = 3.0V is VBAT - 0.322. 18 of 18