DS1677 Portable System Controller www.dalsemi.com FEATURES PIN ASSIGNMENT Provides Real Time Clock: - Counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap year compensation valid up to 2100 - Power control circuitry supports system power on from day/time alarm Microprocessor monitor: - Halts microprocessor during power–fail - Automatically restarts microprocessor after power failure - Monitors push–button for external override - Halts and resets an out of control microprocessor =NV RAM control: - Automatic battery backup and write protection to external SRAM 3–channel, 8–bit analog–to–digital converter Simple 3–wire interface +5.0V operation =1.25V threshold detector for power–fail warning VBAT 1 20 ST VCCO 2 19 VCC SCLK 3 18 X1 I/O 4 17 X2 CS 5 16 AIN0 CEI 6 15 AIN1 CEO 7 14 AIN2 NC 8 13 RST INT 9 12 PFI GND 10 11 PFO 20-Pin TSSOP ORDERING INFORMATION DS1677E 20–Pin TSSOP DESCRIPTION The Portable System Controller is a circuit which incorporates many of the functions necessary for low power portable products integrated into one chip. The DS1677 provides a Real Time Clock, NV RAM controller, micro-processor monitor, power–fail warning, and a 3–channel, 8–bit analog–to–digital converter. Communication with the DS1677 is established through a simple 3–wire interface. The Real Time Clock (RTC) provides seconds, minutes, hours, day, date, month, and year information with leap year compensation. The RTC also provides an alarm interrupt. This interrupt works when the DS1677 is powered by the system power supply or when in battery backup operation so the alarm can be used to wake up a system that is powered down. 1 of 17 050200 DS1677 Automatic backup and write protection of an external SRAM is provided through the VCCO and CE0 pins. The backup energy source used to power the RTC is also used to retain RAM data in the absence of VCC through the VCCO pin. The chip-enable output to SRAM, CE0 , is controlled during power transients to prevent data corruption. The microprocessor monitor circuitry of the DS1677 provides three basic functions. First, a precision temperature–compensated reference and comparator circuit monitors the status of VCC. When an out–of– tolerance condition occurs, an internal power–fail signal is generated which forces the to RST the active state. When VCC returns to an in–tolerance condition, the RST signal is kept in the active state for 250 ms to allow the power supply and processor to stabilize. The DS1677 debounces a push–button input and guarantees an active RST pulse width of 250 ms. The third function is a watchdog timer. The DS1677 has an internal timer that forces the RST signal to the active state if the strobe input is not driven low prior to watchdog time–out. The DS1677 also provides a 3–channel 8–bit successive approximation analog–to–digital converter. The converter has an internal 2.55 volt (typical) reference voltage generated by an on–board band–gap circuit. The A/D converter is monotonic (no missing codes) and has an internal analog filter to reduce high frequency noise. OPERATION The block diagram in Figure 1 shows the main elements of the DS1677. The following paragraphs describe the function of each pin. DS1677 BLOCK DIAGRAM Figure 1 2 of 17 DS1677 SIGNAL DESCRIPTIONS VCC, GND – DC power is provided to the device on these pins. VCC is the +5.0 volt input. VBAT (Backup Power Supply) – Battery input for standard 3 volt lithium cell or other energy source. SCLK (Serial Clock Input) – SCLK is used to synchronize data movement on the serial interface. I/O (Data Input/Output) – The I/O pin is the bi–directional data pin for the 3–wire interface. CS (Chip Select) – The Chip Select signal must be asserted high during a read or a write for communication over the 3–wire serial interface. VCCO (External SRAM Power Supply Output) – This pin is internally connected to VCC when VCC is within nominal limits. However, during power–fail VCCO is internally connected to the VBAT pin. Switchover occurs when VCC drops below VCCSW. INT (Interrupt Output) – The INT pin is an active high output of the DS1677 that can be used as an interrupt input to a microprocessor. The INT output remains high as long as the status bit causing the interrupt is present and the corresponding interrupt–enable bit is set. The INT pin operates when the DS1677 is powered by VCC or VBAT. CEI (SRAM Chip Enable In) – CEI must be driven low to enable the external SRAM. CEO (SRAM Chip Enable Output) – Chip enable output for SRAM. PFI (Power–Fail Input) – Power–Fail comparator input. When PFI is less than 1.25V, PFO goes low; otherwise PFO remains high. Connect PFI to GND or VCC when not used. PFO (Power–Fail Output) – Power–Fail output goes low and sinks current when PFI is less than 1.25V; otherwise PFO remains high. ST (Strobe Input) – The Strobe input pin is used in conjunction with the watchdog timer. If the ST pin is not driven low within the watchdog time period, the RST pin is driven low. RST (Reset) – The RST pin functions as a microprocessor reset signal. This pin is driven low 1) when VCC is outside of nominal limits; 2) when the watchdog timer has “timed out”; 3) during the power–up reset period; and 4) in response to a push–button reset. The RST pin also functions as a push– button reset input. When the RST pin is driven low, the signal is debounced and timed such that a RST signal of at least 250 ms is generated. This pin has an internal 47 kΩ pull up resistor. AIN0, AIN1, AIN2 (Analog Inputs) – These pins are the three analog inputs for the 3–channel analog– to–digital converter. 3 of 17 DS1677 X1, X2 – Connections for a standard 32.768 kHz quartz crystal. For greatest accuracy, the DS1677 must be used with a crystal that has a specified load capacitance of 6 pF. There is no need for external capacitors or resistors. Note: X1 and X2 are very high impedance nodes. It is recommended that they and the crystal be guard–ringed with ground and that high frequency signals be kept away from the crystal area. For more information on crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal Considerations with Dallas Real Time Clocks”. The DS1677 will not function without a crystal. POWER–UP/POWER–DOWN CONSIDERATIONS When VCC is applied to the DS1677 and reaches a level greater than VCCTP (power–fail trip point), the device becomes fully accessible after tRPU (250 ms typical). Before tRPU elapses, all inputs are disabled. When VCC drops below VCCSW, the device is switched over to the VBAT supply. During power–up, when VCC returns to an in–tolerance condition, the RST pin is kept in the active state for 250 ms (typical) to allow the power supply and microprocessor to stabilize. ADDRESS/COMMAND BYTE The command byte for the DS1677 is shown in Figure 2. Each data transfer is initiated by a command byte. Bits 0 through 6 specify the address of the registers to be accessed. The MSB (bit 7) is the Read/Write bit. This bit specifies whether the accessed byte will be read or written. A read operation is selected if bit 7 is a zero and a write operation is selected if bit 7 is a one. The address map for the DS1677 is shown in Figure 3. ADDRESS/COMMAND BYTE Figure 2 7 RD WR 6 5 4 3 2 1 0 A6 A5 A4 A3 A2 A1 A0 4 of 17 DS1677 DS1677 ADDRESS MAP Figure 3 BIT7 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 0 0 0 0 0 0 M M M M BIT0 10 SECONDS SECONDS 10 MINUTES MINUTES 10 HR 12 10 HR HOURS 24 A/P 0 0 0 0 DAY 0 10 DATE DATE 0 0 10 MO. MONTH 10 YEAR YEAR 10 SEC ALARM SECONDS ALARM 10 MIN ALARM MINUTES ALARM 10 HR 10 HR 12 HOUR ALARM 24 A/P 0 0 0 DAY ALARM CONTROL REGISTER STATUS REGISTER WATCHDOG REGISTER ADC REGISTER RESERVED 7F CLOCK, CALENDAR AND ALARM The time and calendar information is accessed by reading/writing the appropriate register bytes. Note that some bits are set to zero. These bits will always read zero regardless of how they are written. Also note that registers 0Fh to 7Fh are reserved. These registers will always read zero regardless of how they are written. The contents of the time, calendar, and alarm registers are in the Binary–Coded Decimal (BCD) format. The DS1677 can run in either 12–hour or 24–hour mode. Bit 6 of the hours register is defined as the 12– or 24–hour mode select bit. When high, the 12–hour mode is selected. In the 12–hour mode, bit 5 is the AM/PM bit with logic one being PM. In the 24–hour mode, bit 5 is the second 10–hour bit (20–23 hours). The DS1677 also contains a time of day alarm. The alarm registers are located in registers 07h to 0Ah. Bit 7 of each of the alarm registers are mask bits (see Table 1). When all of the mask bits are logic 0, an alarm will occur once per week when the values stored in timekeeping registers 00h to 03h match the values stored in the time of day alarm registers. An alarm will be generated every day when mask bit of the day alarm register is set to one. An alarm will be generated every hour when the day and hour alarm mask bits are set to one. Similarly, an alarm will be generated every minute when the day, hour, and minute alarm mask bits are set to one. When day, hour, minute, and seconds alarm mask bits are set to one, an alarm will occur every second. 5 of 17 DS1677 TIME OF DAY ALARM BITS Table 1 ALARM REGISTER MASK BITS (BIT 7) SECONDS MINUTES HOURS DAYS 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 Alarm once per second. Alarm when seconds match. Alarm when minutes and seconds match. Alarm when hours, minutes and seconds match. Alarm when day, hours, minutes and seconds match. SPECIAL PURPOSE REGISTERS The DS1677 has two additional registers (control register and status register) that control the Real Time Clock and interrupts. CONTROL REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EOSC WP AIS1 AIS0 0 0 0 AIE EOSC (Enable Oscillator) – This bit, when set to logic 0 will start the oscillator. When this bit is set to a logic 1, the oscillator is stopped and the DS1677 is placed into a low–power standby mode with a current drain of less than 200 nanoamps when in battery back–up mode. When the DS1677 is powered by VCC, the oscillator is always on regardless of the status of the EOSC bit; however, the real time clock is incremented only when EOSC is a logic 0. WP (Write Protect) – Before any write operation to the real time clock or any other registers, this bit must be logic 0. When high, the write protect bit prevents a write operation to any register. AIS0–AIS1 (Analog Input Select) – These 2 bits are used to determine the analog input for the analog–to–digital conversion. Table 2 lists the specific analog input that is selected by these 2 bits. AIE (Alarm Interrupt Enable) – When set to a logic 1, this bit permits the Interrupt Request Flag (IRQF) bit in the status register to assert INT. When the AIE bit is set to logic 0, the IRQF bit does not initiate the INT signal. ANALOG INPUT SELECTION Table 2 AIS1 0 0 1 1 AIS0 0 1 0 1 ANALOG INPUT NONE AIN0 AIN1 AIN2 STATUS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CU LOBAT 0 0 0 0 0 IRQF 6 of 17 DS1677 CU (Conversion Update In Progress) – When this bit is a one, an update to the ADC Register (register 0Eh) will occur within 488 µs. When this bit is a zero, an update to the ADC Register will not occur for at least 244 µs. LOBAT (Low Battery Flag) – This bit reflects the status of the backup power source connected to the VPAT pin. When VPAT is greater than 2.5 volts, LOBAT is set to a logic 0. When VPAT is less than 2.3 volts, LOBAT is set to a logic 1. IRQF (Interrupt Request Flag) – A logic 1 in the Interrupt Request Flag bit indicates that the current time has matched the time of day Alarm registers. If the AIE bit is also a logic 1, the INT pin will go high. IRQF is cleared by reading or writing to any of the alarm registers. NONVOLATILE SRAM CONTROLLER The DS1677 provides automatic backup and write protection for an external SRAM. This function is pro-vided by gating the chip enable signal and by providing a constant power supply through the VCCO pin. The DS1677 nonvolatizes the external SRAM by write protecting the SRAM and by providing a back–up power supply in the absence of VCC. When VCC falls below VPF , access to the external SRAM is prohibited by forcing CE0 high regardless of the level of CEI . Upon power–up, access is prohibited until the end of tRPU . POWER–FAIL COMPARATOR The PFI input is connected to an internal reference. If PFI is less than 1.25V, PFO goes low. The power– fail comparator can be used as an undervoltage detector to signal an impending power supply failure. PFO can be used as a µP interrupt input to prepare for power–down. For battery conservation, the comparator is turned off and PFO is held low when in battery–backed mode ADDING HYSTERESIS TO THE POWER–FAIL COMPARATOR Hysteresis adds a noise margin to the power–fail comparator and prevents PFO from oscillating when VIN is near the power–fail comparator trip point. Figure 8 shows how to add hysteresis to the power–fail comparator. Select the ratio of R1 and R2 such that PFI sees 1.25 volt when VIN falls to the desired trip point (VTRIP). Resistors R2 and R3 adds hysteresis. R3 will typically be an order of magnitude greater than R1 or R2. R3 should be chosen in manner to prevent it from loading down the PFO pin. Capacitor C1 adds noise filtering and has a value of typically 1.0 uF. See Figure 8 for a schematic diagram and equations. 7 of 17 DS1677 MICROPROCESSOR MONITOR The DS1677 monitors three vital conditions for a micro-processor: power supply, software execution, and external override. First, a precision temperature–compensated reference and comparator circuit monitors the status of VCC. When an out–of–tolerance condition occurs, an internal power–fail signal is generated which forces the RST pin to the active state thus warning a processor–based system of impending power failure. When VCC returns to an in–tolerance condition upon power–up, the reset signal is kept in the active state for 250 ms (typical) to allow the power supply and microprocessor to stabilize. Note however that if the EOSC bit is set to a logic 1 (to disable the oscillator during battery back–up mode), the RST signal will be kept in an active state for 250 ms plus the start–up time of the oscillator. The second monitoring function is push-button reset control. The DS1677 provides for a push–button switch to be connected to the RST output pin. When the DS1677 is not in a reset cycle, it continuously monitors the RST signal for a low going edge. If an edge is detected, the DS1677 will debounce the switch by pulling the RST line low. After the internal 250 ms timer has expired, the DS1677 will continue to monitor the RST line. If the line is still low, the DS1677 will continue to monitor the line looking for a rising edge. Upon detecting release, the DS1677 will force the RST line low and hold it low for 250 ms. The third microprocessor monitoring function provided by the DS1677 is a watchdog timer. The watchdog timer function forces RST to the active state when the ST input is not stimulated within the predetermined time period. The time period is set by the Time Delay (TD) bits in the Watchdog Register. The time delay can be set to 250 ms, 500 ms, or 1000 ms (see Figure 4). If TD0 and TD1 are both set to zero, the watchdog timer is disabled. When enabled, the watchdog timer starts timing out from the set time period as soon as RST is inactive. The default setting is for the watchdog timer to be enabled with 1000 ms time delay. If a high–to–low transition occurs on the ST input pin prior to time–out, the watchdog timer is reset and begins to time–out again. If the watchdog timer is allowed to time–out, then the RST signal is driven to the active state for 250 ms (typical). The ST input can be derived from microprocessor address signals, data signals, and/or control signals. To guarantee that the watchdog timer does not time–out, a high–to–low transition must occur at or less than the minimum period. WATCHDOG TIME–OUT CONTROL Figure 4 WATCHDOG REGISTER BIT 7 BIT 6 BIT 5 0 0 WATCHDOG REGISTER TD1 TD0 0 0 0 1 1 0 1 1 0 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 TD1 TD0 WATCHDOG TIME-OUT WATCHDOG DISABLED 250 ms 500 ms 1000 ms 8 of 17 DS1677 ANALOG–TO–DIGITAL CONVERTER The DS1677 provides a 3–channel 8–bit analog–to–digital converter. The A/D reference voltage (2.55 volt typical) is derived from an on–chip band–gap circuit. Three multiplexed analog inputs are provided through the AIN0, AIN1, and AIN2 pins. The A/D converter is monotonic (no missing codes) and uses a successive approximation technique to convert the analog signal into a digital code. An A/D conversion is the process of assigning a digital code to an analog input voltage. This code represents the input value as a fraction of the full scale voltage (FSV) range. Thus the FSV range is then divided by the A/D converter into 256 codes (8 bits). The FSV range is bounded by an upper limit equal to the reference voltage and the lower limit which is ground. The DS1677 has a FSV of 2.55 volt (typical) which provides a resolution of 10 mV. An input voltage equal to the reference voltage converts to FFh while an input voltage equal to ground converts to 00h. The relative linearity of the A/D converter is ±0.5 LSB. The A/D converter selects from one of three different analog inputs (AIN0 – AIN2). The input that is selected is determined by the Analog Input Select (AIS) bits in the Control Register. Table 2 lists the specific analog input that is selected by these 2 bits. Note also that the converter can be turned off by these bits to reduce power. When the A/D is turned on by setting AIS0 and AIS1 to any value other than 0,0 the analog input voltage is converted and written to the ADC Register within 488 µs. An internal analog filter at the input reduces high frequency noise. Subsequent updates occur approximately every 10 ms. If AIS0 and/or AIS1 are changed, updates will occur at the next 10 ms conversion time. The Conversion Update In Progress (CU) bit in the Status Register indicates when the ADC Register can be read. When this bit is a one, an update to the ADC Register will occur within 488 µs maximum. However, when this bit is zero an update will not occur for at least 244 µs. The CU bit should be polled before reading the ADC Register to insure that the contents are stable during a read cycle. Once a read cycle to the ADC Register has been started, the DS1677 will not update that register until the read cycle has been completed. It should also be mentioned that taking CS low will abort the read cycle and will allow the ADC Register to be updated. Figure 5 illustrates the timing of the CU bit relative to an instruction to begin conversion and the completion of that conversion. 9 of 17 DS1677 CU BIT TIMING Figure 5 3–WIRE SERIAL INTERFACE Communication with the DS1677 is accomplished through a simple 3–wire interface consisting of the Chip Select (CS), Serial Clock (SCLK) and Input/Output (I/O) pins. All data transfers are initiated by driving the CS input high. The CS input serves two functions. First, CS turns on the control logic which allows access to the shift register for the address/command sequence. Second, the CS signal provides a method of terminating either single byte or multiple byte (burst) data transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For data input, data must be valid during the rising edge of the clock and data bits are output on the falling edge of the clock. If the CS input goes low, all data transfer terminates and the I/O pin goes to a high impedance state. Address and data bytes are always shifted LSB first into the I/O pin. Any transaction requires the address/command byte to specify a read or write to a specific register followed by one or more bytes of data. The address byte is always the first byte entered after CS is driven high. The most significant bit ( RD /WR) of this byte determines if a read or write will take place. If this bit is 0, one or more read cycles will occur. If this bit is 1, one or more write cycles will occur. Data transfers can occur one byte at a time or in multiple byte burst mode. After CS is driven high an address is written to the DS1677. After the address, one or more data bytes can be read or written. For a single byte transfer one byte is read or written and then CS is driven low. For a multiple byte transfer, multiple bytes can be read or written to the DS1677 after the address has been written. Each read or write cycle causes the register address to automatically increment. Incrementing continues until the device is disabled. After accessing register 0Eh, the address wraps to 00h. Data transfer for single byte transfer and multiple byte burst transfer is illustrated in Figures 6 and 7. 10 of 17 DS1677 SINGLE BYTE DATA TRANSFER Figure 6 MULTIPLE BYTE BURST TRANSFER Figure 7 POWER–FAIL COMPARATOR Figure 8 = 11 of 17 DS1677 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature –0.3V to +7.0V 0°C to 70°C –55°C to +125°C See J-STD-020A * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER Power Supply Voltage 5V Operation Input Logic 1 Input Logic 0 Battery Voltage SYMBOL VCC MIN 4.5 VIH VIL VBAT 2.0 -0.3 2.5 DC ELECTRICAL CHARACTERISTICS PARAMETER Input Leakage CS Leakage Logic 1 Output Logic 0 Output Active Supply Current (CS=VCC -0.2) A/D Converter Current Standby Current (CS=VIL) Oscillator Current Battery Standby Current (Oscillator Off) Internal RST Pull-Up Resistor VCC Trip Point VCC Switchover A/D Reference Voltage Pushbutton Detect Pushbutton Release Output Voltage PFI Input Threshold PFI Input Current PFO Output voltage IOH = -1 µA Output voltage IOL = 3.2 µA VCCO Output Current (Source=VCC) VCCO Output Current (Source=VBAT) PFO (0°C to 70°C) TYP 5.0 MAX 5.5 UNITS V NOTES 1 VCC+0.3 +0.8 3.7 V V V 1 1 1 (0°C to 70°C; VCC=5.0V±10%) SYMBOL ILI ILO VOH VOL ICCA MIN -1 TYP MAX +1 150 NOTES 0.4 2.0 UNITS µA µA V V mA 500 300 500 200 µA µA nA nA 5 6 0.3 60 4.50 2.80 2.63 2.0 0.8 1.25 0.01 1.30 25 kΩ V V V V V V V nA 2.4 1.5 IADC ICCS IOSC IBAT 300 RP VCCTP VCCSW VADC PBDV PBRD VCCO VPFI IPFI VCC-0.3 1.20 0.25 VOH VCC-1.5 35 4.25 2.60 2.47 0.8 47 4.35 2.70 2.55 7 2 3 4 12 11 V VOL 0.4 V ICCO1 150 mA 13 ICCO2 150 µA 14 12 of 17 DS1677 CAPACITANCE PARAMETER Input Capacitance I/O Capacitance Crystal Capacitance (tA=25°C) SYMBOL CI CI/O CX MIN AC ELECTRICAL CHARACTERISTICS PARAMETER Data to Clock Setup CLK to Data Hold CLK to Data Delay CLK to Low Time CLK to High Time CLK Frequency CLK Rise and Fall CS to CLK Setup CLK to CS Hold CS Inactive Time CS to I/O High-Z VCC Slew Rate (4.5V to 2.3V) VCC Slew Rate (2.3V to 4.5V) VCC Detect to RST (VCC Falling) Reset Active Time Pushbutton Debounce VCC Detect to RST (VCC Rising) ST Pulse Width Chip Enable Propagation Delay to External SRAM Nominal Voltage to VCC Switchover Fall Time TYP 10 15 6 MAX UNITS pF pF pF NOTES (0°C to 70°C; VCC=5.0V±10%) SYMBOL tDC tCDH tCDD tCL tCH tCLK tR, tF tCC tCCH tCWH tCDZ tF tR tRPD tRST PBDB tRPU tST tCED MIN 50 70 tFB 200 TYP MAX 200 250 250 2.0 500 1 60 1 70 1 0 100 250 250 250 20 8 15 UNITS ns ns ns ns ns MHz ns µs ns µs ns ms ns ns ms ms ms ns ns µs PFI Low to PFO Low tPFD 2 µs PFI High to PFO High tPFU 2 µs 13 of 17 NOTES 8 8 8, 9, 10 8 8 8 8 8 8 8 15 15 15, 16 DS1677 TIMING DIAGRAM: READ DATA Figure 9 TIMING DIAGRAM: WRITE DATA Figure 10 PUSH–BUTTON RESET Figure 11 14 of 17 DS1677 POWER–UP Figure 12 POWER–Down Figure 13 15 of 17 DS1677 POWER–FAIL WARNING Figure 14 NOTES: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. All voltages are referenced to ground. Logic one voltages are specified at a source current of 0.4 mA at VCC=3.0V, VOH=VCC for capacitive loads. Logic zero voltages are specified at a sink current of 1.5 mA at VCC=3.0, VOL=GND for capacitive loads. ICCA is specified with outputs open, CS set to a logic 1, SCLK=500 kHz, oscillator enabled, and A/D converter enabled. IADC is specified with CS, VCCO open and I/O, SCLK at logic zero. A/D converter is enabled. ICCS is specified with CS, VCCO open and I/O, SCLK at logic zero. A/D converter is disabled. CS has a 40 kΩ pull–down resistor to ground. Measured at VIH =2.0V or VIL =0.8V and 10 ns maximum rise and fall time. Measured at VOH =2.4V or VOL =0.4V. Load capacitance= 25 pF. ICCO=100 mA, VCC > VCCTP . VCCO switchover from VCC to VBAT occurs when VCC drops below the lower of VCCSW and VBAT . Current from VCC input pin to VCCO output pin. Current from VBAT input pin to VCCO output pin. Timebase is generated by very accurate crystal oscillator. Accuracy of this time period is based on the crystal that is used. A typical crystal with a specified load capacitance of 6 pF will provide an ccuracy within ±100 ppm over the 0°C to 70°C temperature range. For greater accuracy see DS32KHz data sheet. If the EOSC bit in the Control Register is set to a logic 1, tRPU is equal to 250 ms plus the start–up time of the crystal oscillator. 16 of 17 DS1677 20 – PIN TSSOP PKG DIM A MM A1 MM A2 MM C MM L MM e1 MM B MM D MM E MM G MM H MM phi 20-PIN MIN MAX 1.10 0.05 0.75 1.05 0.09 0.18 0.50 0.70 0.65 BSC 0.18 0.30 6.40 6.90 4.40 NOM. 0.25 REF. 6.25 6.55 0° 8° 17 of 17