DALLAS DS1710

DS1710
Partitioned NV Controller
www.dalsemi.com
FEATURES
Converts CMOS RAMs into nonvolatile
memories
Automatically selects +3.0V or +5.0V
operation
SOIC version is pin-compatible with the
Dallas Semiconductor DS1210S and
DS1610S NV Controllers
Unconditionally write protects all of memory
when VCC is out of tolerance
Write protects selected blocks of memory
regardless of VCC status when programmed
Automatically switches to battery backup
supply when power-fail occurs
Provides for multiple batteries
Consumes less than 100 nA of battery current
Test battery on power-up by inhibiting the
second memory cycle
Optional 5% or 10% power-fail detection
16-pin DIP or 16-pin SOIC surface mount
package or 20-pin TSSOP package
Low forward voltage drop on the VCC switch
with currents of up to 150 mA
Optional industrial temperature range of
-40°C to +85°C
PIN ASSIGNMENT
AW
1
16
PFO
VCCO
2
15
VCCI
AX
3
14
AZ
VBAT1
AY
4
13
VBAT2
5
12
WEO
TOL
6
11
CEO
DIS
7
10
WEI
GND
8
9
CEI
16-Pin DIP and 16-Pin SOIC
AW
1
20
PFO
VCCO
2
3
19
VCCI
18
AZ
4
5
17
16
VBAT2
AY
NC
6
15
WEO
TOL
7
14
NC
NC
8
13
CEO
DIS
9
12
WEI
GND
10
11
CEI
AX
VBAT1
NC
20-Pin TSSOP
PIN DESCRIPTION
VCCI
VBAT1
VBAT2
VCCO
GND
CEI
CEO
WEI
WEO
TOL
AW - AZ
DIS
PFO
NC
1 of 14
- Input 2.7 to 5.5 Volt Supply
- + Battery 1 Input
- + Battery 2 Input
- RAM Power (VCC) Supply
- Ground
- Chip Enable Input
- Chip Enable Output
- Write Enable Input
- Write Enable Output
- Power Supply Tolerance Select
- Address Inputs
- Memory Partition Disable
- Power-fail Output
- No Connect
111999
DS1710
DESCRIPTION
The DS1710 is a low-power CMOS circuit which solves the application problems of converting CMOS
RAMS into nonvolatile memories. In addition the device has the ability to unconditionally write protect
blocks of memory so that inadvertent write cycles do not corrupt program and special data space. The
incoming power supply voltage at the VCCI input pin is constantly monitored for an out-of-tolerance
condition. When such a condition is detected, both the chip enable and write enable outputs are inhibited
to protect stored data. The battery inputs are used to supply VCCO with power when VCCI is less than the
battery input voltages. Special circuitry uses a low leakage CMOS process which affords precise voltage
detection at extremely low current consumption. By combining the DS1710 Partitioned NV Controller
chip with a CMOS memory and batteries, nonvolatile RAM operation can be achieved.
The DS1710 Partitioned NV Controller incorporates all the functions of the DS1610 with the additional
feature of either +3.0V or +5.0V operation. The DS1710 functions like the Dallas Semiconductor DS1210
NV controller when the ( DIS ) disable pin is grounded and also incorporates the power-up auto sensing.
An internal pulldown resistor to ground on the DIS pin of the DS1710S allows it to retrofit into DS1210S
applications. When the DIS pin is grounded the address inputs AW - AZ and the write enable input WEI
are ignored. Also the power-fail output PFO and the write enable output WEO are tristated.
POWER-UP AUTO SENSING
VCCI will accept either +3.0V or +5.0V input. Selection of 3V operation is automatically invoked when
VCC rises and remains between VCCTP2 and VCCTP1 for tREC. 5V operation is automatically selected if VCC
rises and remains above both VCCTP2 and VCCTP1 for tREC. In either case, tREC is measured from the time
VCC first rises above VCCTP2. The DS1710 will not change modes until VCC falls below VCCTP2.
OPERATION - DISABLE PIN CONNECTED TO VCCO
The DS1710 performs five circuit functions required to battery-backup a RAM. First, a switch is provided
to direct power from the battery or the incoming power supply (VCCI) depending on which is greater. This
switch has a voltage drop of less than 0.2 volts. The second function provided by the DS1710 is powerfail detection. The incoming supply (VCCI) is constantly monitored. When the supply goes out of
tolerance a precision comparator detects power failure and inhibits both the chip enable output ( CEO ) and
the write enable output ( WEO ). A third function of write protection is accomplished by holding both the
chip enable output CEO and write enable output WEO to within 0.2 volts of VCCO when VCCI is out of
tolerance. If CEI is low at the time that power-fail detection occurs the CEO signal is kept low until CEI
is brought high again. However, CEO is forced high after 1.5 µs regardless of the state of CEI . Similarly,
if WEI is low at the time that power-fail detection occurs, the WEO signal will remain low until WEI is
brought high or 1.5 µs elapses. The delay of write protection until the current memory cycle is complete
prevents corrupted data. Power-fail detection occurs in the range of 4.75 to 4.5 volts with the tolerance
pin TOL grounded and in 5-volt mode. If the tolerance pin is connected to VCCO while in 5-volt mode,
then power-fail detection occurs in the range of 4.5 volts to 4.25 volts. If in 3-volt mode, the power-fail
detection will occur in the range of 2.7 to 2.5 volts. The PF0 signal is driven low and remains low until
VCCI returns to nominal conditions. During nominal supply conditions CEO will follow CEI and WEO
will follow WEI . The fourth function which the DS1710 performs is a battery status warning so that
potential data loss is avoided. Each time VCCI is applied to the device battery status is checked with a
precision comparator. If during battery backup, no switch occurred from one battery to the other, the
voltage of the battery supplying power when VCCI is applied is checked. If this voltage is less than 2.0
volts the second chip enable cycle after power is applied is inhibited. If any switch from one battery to
another did occur the voltage of both batteries is checked. If either voltage is less than 2.0 volts the
second chip enable cycle will be inhibited. Battery status can therefore be determined by performing a
2 of 14
DS1710
read cycle after power-up to any location in memory, verifying that memory location’s contents. A
subsequent write cycle can then be executed to the same memory location altering the data. If the next
read cycle fails to verify the written data then the data is in danger of being corrupted. The fifth function
of the DS1710 provides for battery redundancy. When data integrity is extremely important it is wise to
use two batteries to insure reliability. The DS1710 controller provides an internal isolation switch which
allows the connection of two batteries. When entering battery backup operation, the battery with the
highest voltage is selected for use. If one battery should fail, the other would then supply energy to the
connected load. The switch to a redundant battery is transparent to circuit operation and to the user. In
applications where battery redundancy is not a major concern a single battery should be connected to the
BAT1 pin. The BAT2 battery pin must be grounded. When batteries are first connected to one or both of
the VBAT pins VCCO will not show the battery potential until VCCI is applied and removed for the first time.
OPERATION - WRITE PROTECTION PROGRAMMING MODE
When the disable pin is connected to VCCI or VCCO, the DS1710 performs all of the functions described
earlier with the addition of a partition switch which selectively write protects blocks of memory. The state
of the DIS pin is strobed and latched as VCCI crosses the power-fail trip point so that the DS1710
maintains its configuration during power loss. If the strobed value of DIS is high, the internal pulldown
resistor on the DIS pin will be disconnected in the power-fail state to eliminate the possibility of battery
discharge. The register controlling the partition switch is selected by recognition of a specific binary
pattern which is sent on address lines AW - AZ. These address lines are normally the four upper order
address lines being sent to RAM. The pattern is sent by 20 consecutive read cycles with the exact pattern
as shown in Table 1. Pattern matching must be accomplished using read cycles; any write cycles will
reset the pattern matching circuitry. If this pattern is matched perfectly, then the 21st through 24th read
cycle will load the partition switch. Since there are 16 possible write protected partitions, the size of each
partition is determined by the size of the memory. For example, a 128k X 8 memory would be divided
into 16 partitions of 128k/16 or 8k X 8. Each partition is represented by one of the 16 bits contained in
the 21st through 24th read cycle as defined by AW through AZ and shown in Table 2. A logical 1 in a bit
location sets that partition to write protect. A logical 0 in a bit location disables write protection. For
example, if during the pattern match sequence bit 22 on address pin AX were a 1, this would cause the
partition register location for partition 5 to be set to a 1. This in turn would cause the DS1710 to inhibit
WEO from going low as WEI goes low whenever AZAYAXAW=0101. Note that while setting the partition
register, data which is being accessed from the RAM should be ignored as the purpose of the 24 read
cycles is to set the partition switch and not for the purpose of accessing data from RAM. Also note that
on initial battery attach the partition register can power-up in any state.
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DS1710
PATTERN MATCH TO WRITE PARTITION REGISTER Table 1
AW
AX
AY
AZ
1
1
1
1
1
2
0
1
1
1
3
1
1
1
0
4
1
1
1
0
5
1
1
0
0
6
1
0
0
1
7
0
0
1
1
8
0
1
1
1
9
1
1
1
0
10
1
1
0
0
11
1
0
0
1
12
0
0
1
0
13
0
1
0
0
14
0
0
1
0
15
0
1
0
1
16
0
1
1
0
17
1
0
0
1
18
1
0
0
0
19
0
0
0
0
20
1
0
1
0
21
X
X
X
X
22
X
X
X
X
23
X
X
X
X
24
X
X
X
X
PARTITION REGISTER MAPPING Table 2
Address
Pin
AW
AX
AY
AZ
AW
AX
AY
AZ
AW
AX
AY
AZ
AW
AX
AY
AZ
Bit number in pattern
Match sequence
BIT 21
BIT 21
BIT 21
BIT 21
BIT 22
BIT 22
BIT 22
BIT 22
BIT 23
BIT 23
BIT 23
BIT 23
BIT 24
BIT 24
BIT 24
BIT 24
Partition Number
PARTITION 0
PARTITION 1
PARTITION 2
PARTITION 3
PARTITION 4
PARTITION 5
PARTITION 6
PARTITION 7
PARTITION 8
PARTITION 9
PARTITION 10
PARTITION 11
PARTITION 12
PARTITION 13
PARTITION 14
PARTITION 15
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Address State Affected
(AZ AY AX AW)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DS1710
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
*
-0.5V to +7.0V
0°C to 70°C
-55°C to +125°C
260°C for 10 seconds
This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Pin 6 = GND Supply Voltage
(5V Operation)
Pin 6 = VCCO Supply Voltage
(5V Operation)
Pin 6 = GND Supply Voltage
(3V Operation)
Logic 1 Input
Logic 0 Input
Battery Input
SYMBOL
VCCI
MIN
4.75
TYP
5.0
MAX
5.5
UNITS
V
NOTES
1
VCCI
4.5
5.0
5.5
V
1
VCCI
2.7
3.0
4.0
V
1
VIH
VIL
VBAT1,
VBAT2
2.0
-0.3
2.0
VCC+0.3
+0.8
4.0
V
V
V
1
1
1, 2
DC ELECTRICAL CHARACTERISTICS
PARAMETER
CEO Output
WEO Output
VBAT1 or VBAT1
Battery Current
Battery Backup Current @
VCCO = VBAT -0.2V
(0°C to 70°C)
SYMBOL
VOHL
VOHL
IBAT
(0°C to 70°C; VCCI<VBAT, VCCI<VCCTP2)
MIN
VBAT-0.2
VBAT-0.2
TYP
ICCO2
MAX
NOTES
100
UNITS
V
V
nA
150
µA
6, 8
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
2, 3
(TA = 25°C)
SYMBOL
CIN
COUT
MIN
5 of 14
TYP
MAX
5
7
UNITS
pF
pF
NOTES
DS1710
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Operating Current
Standby Current
Supply Voltage
Supply Current
Input Leakage
Output Leakage
PFO , WEO Output @ 2.4V
PFO , WEO Output @ 0.4V
VCC Trip Point (TOL=GND)
VCC Trip Point (TOL=VCC)
VCC Trip Point
CEI to CEO Impedance
DIS Pulldown Resistance
SYMBOL
ICC1
ICC2
VCCO
ICCO1
IIL
ILO
IOH
IOL
VCCTP1
VCCTP1
VCCTP2
ZCE
RDIS
(0°C to 70°C; VCCI=4.5V to 5.5V)
MIN
TYP
MAX
5
200
VCC-0.2
150
+1.0
+1.0
-1.0
-1.0
-1.0
4.50
4.25
2.50
4.62
4.37
2.60
50k
4.0
4.75
4.50
2.70
30
250k
UNITS
mA
µA
V
mA
µA
µA
mA
mA
V
V
V
Ω
Ω
NOTES
3, 14
3, 15
1
4
10, 16
10, 16
1, 16
1, 16
1, 16
5
(0°C to 70°C; VCCI=4.75V to 5.50V, TOL=GND)
AC ELECTRICAL CHARACTERISTICS
(VCCI=4.50V to 5.50V, TOL=VCCO)
PARAMETER
Address Setup
Address Hold
Read Recovery
CEI , WEI Pulse Width
CEI to CEO Falling
Propagation Delay
Later of CEI , WEI to WEO
Falling Propagation Delay
CEI to CEO Rising
Propagation Delay
Earlier of CEI , WEI to WEO
Rising Propagation Delay
Write Recovery
SYMBOL
tAS
tAH
tRR
tCW
tPDF
MIN
0
50
20
75
NOTES
5
UNITS
ns
ns
ns
ns
ns
tPDF
20
ns
10, 11
tPDR
5
ns
10
tPDR
5
ns
10, 11
ns
11
tWR
TYP
10
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Recovery at Power-up
VCC Slew Rate Power-down
VCC Slew Rate Power-down
VCC Slew Rate Power-up
CEO Pulse Width
WEI Pulse Width
SYMBOL
tREC
tF
tFB
tR
tCE
tCE
MAX
9
10
(0°C to 70°C, 5V Operation)
MIN
100
300
10
0
TYP
MAX
200
1.5
1.5
6 of 14
UNITS
ms
µs
µs
µs
µs
µs
NOTES
12
13
7, 8
7, 8
DS1710
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Operating Current
Standby Current
Supply Voltage
Supply Current
Input Leakage
Output Leakage
PFO , WEO Output @ 2.4V
PFO , WEO Output @ 0.4V
VCC Trip Point
CEI to CEO Impedance
DIS Pulldown Resistance
SYMBOL
ICC1
ICC2
VCCO
ICCO1
IIL
ILO
IOH
IOL
VCCTP2
ZCE
RDIS
(0°C to 70°C; VCCI=2.7V to 4.0V)
MIN
100
+1.0
+1.0
-1.0
-1.0
-1.0
2.50
2.60
50k
SYMBOL
tAS
tAH
tRR
tCW
tPDF
4.0
2.70
60
250k
UNITS
mA
µA
V
mA
µA
µA
mA
mA
V
Ω
Ω
NOTES
3, 14
3, 15
1
4
10, 16
10, 16
1, 16
5
(0°C to 70°C; VCCI=2.7V to 4.0V)
MIN
0
50
20
75
NOTES
5
UNITS
ns
ns
ns
ns
ns
tPDF
50
ns
10, 11
tPDR
5
ns
10
tPDR
20
ns
10, 11
ns
11
tWR
TYP
SYMBOL
tREC
tF
tR
tCE
tCE
MAX
10
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Recovery at Power-up
VCC Slew Rate Power-down
VCC Slew Rate Power-up
CEO Pulse Width
WEI Pulse Width
MAX
3
200
VCC-0.2
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Address Setup
Address Hold
Read Recovery
CEI , WEI Pulse Width
CEI to CEO Falling
Propagation Delay
Later of CEI , WEI to WEO
Falling Propagation Delay
CEI to CEO Rising
Propagation Delay
Earlier of CEI , WEI to WEO
Rising Propagation Delay
Write Recovery
TYP
9
10
(0°C to 70°C, 3V Operation)
MIN
100
300
0
TYP
MAX
200
1.5
1.5
7 of 14
UNITS
ms
µs
µs
µs
µs
NOTES
12
13
7, 8
7, 8
DS1710
TIMING DIAGRAM: POWER-UP (5 VOLT)
TIMING DIAGRAM: POWER-DOWN (5 VOLT)
8 of 14
DS1710
TIMING DIAGRAM: POWER-UP (3 VOLT)
TIMING DIAGRAM: POWER-DOWN (3 VOLT)
9 of 14
DS1710
TIMING DIAGRAM: LOADING PARTITION REGISTER
OUTPUT LOAD Figure 1
10 of 14
DS1710
NOTES:
1. All voltages are reference to ground
2. Only one battery input is required.
3. Measured with outputs open circuited.
4. ICC01 is the maximum average load which the DS1710 can supply to the memories.
5. ZCE is an average input-to-output impedance as the input is swept from ground to VCCI and less than 4
mA is forced through ZCE.
6. ICC02 is the maximum average load current which the DS1710 can supply to the memories in the
battery backup mode.
7. tCE max must be met to insure data integrity on power loss.
8. Chip Enable Output CEO can only sustain leakage current in the battery mode.
9. Applies only when loading partition switch.
10. Measured with a load as shown in Figure 1.
11. Measured with DIS at a logic high level.
12. CEO and WEO will be held high for a time equal to tREC after VCCI crosses VCCTP2.
13. tR is the slew rate of VCCI from 4.25V to 4.75V or 2.50 to +2.70 volts.
14. CEI , WEI , AW - AZ run at minimum timing set and at voltage levels of 0V to 3V.
15. All inputs within 0.3V of ground or VCCI and CEI within 0.3V of VCCI.
16. The power-fail output signal ( PFO ) is driven active (VOL = 0.4V) when the VCC trip point occurs.
While active, the PFO pin can sink 4 mA and will maintain a maximum output voltage of 0.4 volts.
When inactive, the voltage output of PFO is 2.4 volts minimum and will source a current of 1 mA.
11 of 14
DS1710
DS1710 16-PIN DIP (300-MIL)
PKG
DIM
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
16-PIN
MIN
MAX
0.740
0.780
18.80
19.81
0.240
0.260
6.10
6.60
0.120
0.140
3.05
3.56
0.300
0.325
7.62
8.26
0.015
0.040
0.38
1.02
0.120
0.140
3.04
3.56
0.090
0.110
2.29
2.79
0.320
0.370
8.13
9.40
0.008
0.012
0.20
0.30
0.015
0.021
0.38
0.53
12 of 14
DS1710
DS1710 16-PIN SOIC (300-MIL)
PKG
DIM
A IN.
MM
B IN.
MM
C IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
L IN.
MM
PHI
16-PIN
MIN
MAX
0.402
0.412
10.21
10.46
0.290
0.300
7.37
7.65
0.089
0.095
2.26
2.41
0.004
0.012
0.102
0.30
0.094
0.105
2.38
2.68
.050 BSC
1.27 BSC
0.398
0.416
10.11
10.57
0.009
0.013
0.229
0.33
0.013
0.019
0.33
0.48
.016
.040
.40
1.02
0°
8°
13 of 14
DS1710
DS1710 20-PIN TSSOP
DIM
A MM
A1 MM
A2 MM
C MM
L MM
e1 MM
B MM
D MM
E MM
G MM
H MM
PHI
MIN
MAX
1.10
0.05
0.75
1.05
0.09
0.18
0.50
0.70
0.65 BSC
0.18
0.30
6.40
6.90
4.40 NOM
0.25 REF
6.25
6.55
0°
8°
14 of 14