DS3803 1024k Flexible NV SRAM SIMM www.dalsemi.com FEATURES 256K SRAM 72 256K SRAM 256K SRAM 256K SRAM Flexibly organized as 32k x 32, 64k x 16 or 128k x 8bits 10 years minimum data retention in the absence of external power Nonvolatile circuitry transparent to and independent from host system Automatic write protection circuitry safeguards against data loss Separate control and data signals for each SRAM allow byte, word or doubleword access Fast access time of 70 ns Full VCC ± 10% operating range Employs popular JEDEC standard 72-position SIMM connector Extremely thin design built using TSOPpackage IC components 1 PIN ASSIGNMENT DS3803 72-Pin SIMM PIN DESCRIPTION A0 - A14 D0A - D7A D0B - D7B D0C - D7C D0D - D7D CEA - CED WEA - WED OEA - OED VCC GND NC - Address Inputs Data Inputs/Outputs, Byte A Data Inputs/Outputs, Byte B Data Inputs/Outputs, Byte C Data Inputs/Outputs, Byte D Chip Enable Inputs Write Enable Inputs Output Enable Inputs +5V Power Supply Ground No Connect DESCRIPTION The DS3803 is a self-contained, 1,048,576-bit, nonvolatile static RAM which can be flexibly organized as 32k x 32, 64k x 16 or 128k x 8. Built using four 32k x 8 SRAMs, four nonvolatile control ICs and four lithium batteries, this nonvolatile memory contains all necessary control circuitry and lithium energy sources to maintain data integrity in the absence of power for more than 10 years. The DS3803 employs the popular JEDEC standard 72-position SIMM connection scheme and requires no additional circuitry. 1 of 10 112299 DS3803 READ MODE The DS3803 executes a read cycle whenever WE (Write enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs (A0 A14) defines which byte of data is to be accessed from the selected SRAMs. Valid data will be available to the data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output Enable) access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later occurring signal and the limiting parameter is either tCO for CE or tOE for OE rather than tACC . WRITE MODE The DS3803 executes a write cycle whenever both WE and CE signals are in the active (low) state after address inputs are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active), then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The DS3803 provides full functional capability for VCC greater than 4.5 volts and write-protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAM constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically write-protects itself, all inputs become don’t care, and all outputs become high impedance. As VCC falls below approximately 3.0 volts, power switching circuits connect the lithium energy sources to the RAMs to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuits connect external VCC to the RAMs and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.5 volts. The DS3803 checks battery status to warn of potential data loss. Each time that VCC power is restored to the DS3803, the battery voltages are checked with precision comparators. If both batteries providing backup power to a particular SRAM are less than 2.0 volts, the second memory access to that SRAM is inhibited. Battery status for each SRAM can therefore be determined by a three-step process. First, a read cycle is performed to any location within that SRAM in order to save the contents of that location. A subsequent write cycle can then be executed to the same memory location, altering data. If a subsequent read cycle fails to verify the written data, then battery voltage for that SRAM is less than 2.0V and data is in danger of being lost. The DS3803 also provides battery redundancy. In many applications data integrity is paramount. The DS3803 provides two batteries for each SRAM and an internal isolation switch to select between them. During battery backup, the battery with the highest voltage is selected for use. If one battery fails, the other automatically takes over. The switch between batteries is transparent to the user. 2 of 10 DS3803 PIN DESCRIPTION Table 1 PIN SIGNAL PIN NAME SIGNAL NAME PIN SIGNAL NAME 1 VCC 16 D2B 31 D5C 46 NC 61 A9 2 D0A 17 D3B 32 D6C 47 CED 62 A10 3 D1A 18 D4B 33 D7C 48 OED 63 A11 4 D2A 19 D5B 34 NC 49 WED 64 A12 5 D3A 20 D6B 35 CEC 50 GND 65 A13 6 D4A 21 D7B 36 OEC 51 VCC 66 A14 7 D5A 22 NC 37 WEC 52 A0 67 NC 8 D6A 23 CEB 38 D0D 53 A1 68 NC 9 D7A 24 CEB 39 D1D 54 A2 69 NC 10 NC 25 WEB 40 D2D 55 A3 70 NC 11 CEA 26 D0C 41 D3D 56 A4 71 NC 12 OEA 27 D1C 42 D4D 57 A5 72 GND 13 WEA 28 D2C 43 D5D 58 A6 14 D0B 29 D3C 44 D6D 59 A7 15 D1B 30 D4C 45 D7D 60 A8 3 of 10 PIN SIGNAL NAME PIN SIGNAL NAME DS3803 BLOCK DIAGRAM Figure 1 4 of 10 DS3803 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature -0.3V to +7.0V 0ºC to 70ºC -40ºC to +85ºC * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER (TA = 0ºC to 70ºC) SYMBOL MIN TYP MAX UNITS Power Supply Voltage VCC 4.5 5.0 5.5 V Logic 1 input Voltage VIH 2.2 VCC+0.3 V Logic 0 input Voltage VIL -0.3 +0.8 V DC ELECTRICAL CHARACTERISTICS PARAMETER NOTES (TA = 0ºC to 70ºC; VCC = 5V ±10%) SYMBOL TEST CONDITION MIN Input Leakage Current IIL 0V ≤ VIN ≤ VCC Output Leakage Current ILO 0V ≤ VIN ≤ VCC, all CE = VIH Operating Current ICCO Standby Current TYP MAX UNITS -4 +4 µA -1 +1 µA min cycle, duty=100% all CE = VIL, II/O = 0, VIN = VIH or VIL 300 mA ICCS all CE = VIH 20 mA Output High Current IOH VOH = 2.4V -1.0 mA Output Low Current IOL VOL = 0.4V 2.1 mA CAPACITANCE PARAMETER (TA = 25ºC) SYMBOL MIN TYP MAX UNITS Input Capacitance CIN 8 pF Output Capacitance CI/O 10 pF 5 of 10 NOTES DS3803 AC ELECTRICAL CHARACTERISTICS PARAMETER (TA = 0ºC to 70ºC; VCC = 5V ±10%) SYMBOL MIN 70 CE to Output Valid tRC tACC tOE tCO OE or CE to Output Active tCOE 5 Deselection to Output High Z Output Hold after Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time tOD tOH Read Cycle Time Access Time OE to Output Valid WE Active to Output High Z WE Inactive to Output Active Data Setup Time Data Hold Time tWC tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2 TYP MAX UNITS 70 35 70 ns ns ns ns 25 5 70 55 0 5 15 5 30 0 10 TIMING DIAGRAM: READ CYCLE 6 of 10 ns 5 ns ns 5 ns ns ns ns 25 NOTES ns ns ns ns 3 11 12 5 5 4 11 12 DS3803 TIMING DIAGRAM: WRITE CYCLE 1 ( WE Controlled) TIMING DIAGRAM: WRITE CYCLE 2 ( CE Controlled) 7 of 10 DS3803 TIMING DIAGRAM: POWER-DOWN AND POWER-UP POWER-DOWN AND POWER-UP TIMING PARAMETER SYMBOL VCC Fail Detect to MIN TYP tPD MAX UNITS 1.5 µs NOTES CE and WE Inactive VCC Slew from VTP to 0V tF 300 µs VCC Slew from 0V to VTP tR 300 µs VCC Valid to tPU 2 ms tREC 125 ms CE and WE Inactive VCC Valid to End of Write Protection (TA = 25ºC) PARAMETER Expected Data Retention Time SYMBOL MIN tDR 10 TYP MAX UNITS NOTES years 9 WARNING Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode. NOTES: 1. WE is high throughout read cycle. 2. OE = VIH or VIL. If state. OE = V IH during write cycle, the output buffers remain in a high impedance 8 of 10 DS3803 3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDS is measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output buffers remain in a high impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. 9. Each DS3803 has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. 10. In a power-down condition the voltage on any pin may not exceed the voltage on VCC. 11. tWR1, tDH1 are measured from WE going high. 12. tWR2, tDH2 are measured from CE going high. DC TEST CONDITIONS Outputs Open Cycle = 200 ns All Voltages are Referenced to Ground AC TEST CONDITIONS Output Load: 100 pF + 1TTL gate Input Pulse Levels: 0 - 3.0 V Timing Measurements Reference Levels: Input - 1.5V Output - 1.5V Input Pulse Rise and Fall Times: 5 ns 9 of 10 DS3803 DS3803 72-PIN SIMM MODULE DIM A B C D E F G H I J K L M N O P 72-PIN MIN MAX 4.245 4.255 3.979 3.989 0.845 0.855 0.395 0.405 0.245 0.255 0.050 BASIC 0.075 0.085 0.245 0.255 1.750 BASIC 0.120 0.130 2.120 2.130 2.245 2.255 0.057 0.067 0.173 0.110 0.047 0.054 10 of 10