TI SN74ALS563BN

SN54ALS563B, SN74ALS563B
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SDAS163A – DECEMBER 1982 – REVISED JANUARY 1995
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
description
These 8-bit D-type transparent latches feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
SN54ALS563B . . . FK PACKAGE
(TOP VIEW)
2D
1D
While the latch-enable (LE) input is high, the Q
outputs follow the complements of data (D) inputs.
When LE is taken low, the outputs are latched at
the inverses of the levels set up at the D inputs.
3D
4D
5D
6D
7D
4
2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2Q
3Q
4Q
5Q
6Q
8D
GND
LE
8Q
7Q
A buffered output-enable (OE) input places the
eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and increased high logic
level provide the capability to drive bus lines
without interface or pullup components.
3
1Q
•
•
SN54ALS563B . . . J OR W PACKAGE
SN74ALS563B . . . DW OR N PACKAGE
(TOP VIEW)
3-State Buffer-Type Outputs Drive Bus
Lines Directly
Bus-Structured Pinout
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), Standard Plastic (N) and
Ceramic (J) 300-mil DIPs, and Ceramic Flat
(W) Packages
OE
VCC
•
OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The SN54ALS563B is characterized for operation over the full military temperature range of – 55°C to 125°C.
The SN74ALS563B is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
LE
D
L
H
H
L
L
H
H
H
L
L
X
Q0
H
X
X
Z
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN54ALS563B, SN74ALS563B
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SDAS163A – DECEMBER 1982 – REVISED JANUARY 1995
logic symbol†
OE
LE
1D
2D
3D
4D
5D
6D
7D
8D
1
11
2
logic diagram (positive logic)
EN
OE
C1
19
1D
3
18
4
17
5
16
6
15
7
14
8
13
9
12
LE
1
11
1Q
C1
2Q
3Q
1D
2
19
1Q
1D
4Q
5Q
6Q
7Q
To Seven Other Channels
8Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, TA: SN54ALS563B . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
SN74ALS563B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54ALS563B
SN74ALS563B
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.7
0.8
High-level output current
–1
– 2.6
mA
IOL
tw
Low-level output current
12
24
mA
Pulse duration, LE high
15
15
ns
tsu
th
Setup time, data before LE↓
20
10
ns
Hold time, data after LE↓
12
10
ns
TA
Operating free-air temperature
2
High-level input voltage
2
– 55
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2
125
0
V
V
70
V
°C
SN54ALS563B, SN74ALS563B
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SDAS163A – DECEMBER 1982 – REVISED JANUARY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = – 18 mA
IOH = – 0.4 mA
5V
VCC = 4
4.5
IOH = – 1 mA
IOH = – 2.6 mA
VOL
VCC = 4
4.5
5V
IOL = 12 mA
IOL = 24 mA
IOZH
IOZL
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.4 V
II
IIH
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
IIL
IO‡
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.4 V
VO = 2.25 V
VOH
ICC
SN54ALS563B
TYP†
MAX
TEST CONDITIONS
VCC = 5.5 V
MIN
SN74ALS563B
TYP†
MAX
MIN
– 1.2
VCC – 2
2.4
– 1.2
UNIT
V
VCC – 2
V
3.3
2.4
0.25
– 20
3.2
0.4
0.25
0.4
0.35
0.5
V
µA
20
20
– 20
– 20
µA
0.1
0.1
mA
20
20
µA
– 0.1
– 0.1
mA
– 112
mA
– 112
– 30
Outputs high
10
17
10
17
Outputs low
16
26
16
26
mA
Outputs disabled
17
29
17
29
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX§
SN54ALS563B
tPLH
tPHL
D
Q
tPLH
tPHL
LE
Q
tPZH
tPZL
OE
Q
tPHZ
tPLZ
OE
Q
UNIT
SN74ALS563B
MIN
MAX
MIN
MAX
3
26
3
18
3
15
3
14
8
29
6
22
4
22
6
21
4
25
3
18
4
21
4
18
2
12
1
10
3
22
1
15
ns
ns
ns
ns
§ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
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SN54ALS563B, SN74ALS563B
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SDAS163A – DECEMBER 1982 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
RL = R1 = R2
VCC
S1
RL
R1
Test
Point
From Output
Under Test
CL
(see Note A)
From Output
Under Test
RL
Test
Point
From Output
Under Test
CL
(see Note A)
CL
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3.5 V
Timing
Input
Test
Point
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
High-Level
Pulse
1.3 V
R2
1.3 V
1.3 V
0.3 V
0.3 V
tsu
Data
Input
tw
th
3.5 V
1.3 V
3.5 V
Low-Level
Pulse
1.3 V
0.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
tPZL
Waveform 1
S1 Closed
(see Note B)
tPLZ
[3.5 V
1.3 V
tPHZ
tPZH
Waveform 2
S1 Open
(see Note B)
1.3 V
VOL
0.3 V
VOH
1.3 V
0.3 V
[0 V
3.5 V
1.3 V
Input
1.3 V
0.3 V
tPHL
tPLH
VOH
In-Phase
Output
1.3 V
1.3 V
VOL
tPLH
tPHL
VOH
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
4
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Copyright  1998, Texas Instruments Incorporated