TPS5206CN SWITCHING-POWER-SUPPLY CONTROL CIRCUIT SLVS082A – APRIL 1994 – REVISED SEPTEMBER 1994 • • • • • • • • Single-Chip Switching-Power-Supply Control With Limited External Components Built-In PWM Control Circuit Open-Collector Output for Direct Drive of Transformer Variable Dead-Time Control Overvoltage and Undervoltage Detection and Latch-Up for Each Supply Voltage: 5 V, 12 V, – 5 V, and – 12 V System Overcurrent Protection Wide Supply Range From 7 V to 40 V Power-Good Indicator Function N PACKAGE (TOP VIEW) REF PGO SVP5 SVP12 CPR DT CUV SVN5 SVN12 D1 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 CPG PGI EA + EA – EAO VCC SC CT D2 GND description The TPS5206CN is a bipolar monolithic integrated circuit designed for push-pull-type switching-power-supply (SPS) control in desktop PC applications. It offers pulse-width-modulation (PWM) control and power-supply supervisor functions, including detection of undervoltage and overvoltage conditions on ± 5 V and ± 12 V system supplies. It also detects overcurrent conditions on the SPS system output. This single chip reduces the total component count and provides additional design flexibility, which minimizes cost and printed-circuit-board (PCB) space requirements in present and new SPS designs. overvoltage-protection lockout feature The overvoltage-protection lockout feature monitors four different supply voltages. When an overvoltage (OV) condition is detected, the power-good output (PGO) is set low and the PWM function is disabled. The OV condition is detected on the SVP5, SVP12, SVN5, and SVN12 inputs. Threshold voltages are typically 5.9 V, 14.1 V, – 8.4 V, and – 15.3 V, respectively. undervoltage-protection lockout feature The undervoltage-protection lockout feature monitors four different supply voltages. When an undervoltage (UV) condition is detected, the power-good output (PGO) is set low and the PWM function is disabled. The UV condition is detected on the SVP5, SVP12, SVN5, and SVN12 inputs. Threshold voltages are typically 3.9 V, 9.5 V, – 3.4 V, and – 9.3 V, respectively. overcurrent-protection lockout feature The overcurrent (OC) protection lockout feature is designed to protect the SPS from excessive load or short-circuit conditions. The circuit converts the output current of the SPS to a voltage, which is then monitored at SC. It sets PG low and shuts down the PWM circuit when the sensed voltage is higher than 5 V. reference regulator The internal 5-V reference regulator is designed primarily to provide the internal circuitry with a stable supply rail for varying input voltages. The regulator employs a band-gap circuit as its primary reference to maintain thermal stability of less than 100-mV variation over the operating free-air temperature range of 0°C to 70°C. In addition to supplying an internal reference, the regulator provides a precision 5-V reference that can support 5 mA of load current for external bias circuits. The regulated voltage has a margin of error of 2%. Short-circuit protection is provided to protect the internal circuit from overload or short-circuit conditions. Copyright 1994, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251–1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 1 TPS5206CN SWITCHING-POWER-SUPPLY CONTROL CIRCUIT SLVS082A – APRIL 1994 – REVISED SEPTEMBER 1994 oscillator The timing capacitor (CT) is charged by the oscillator with a 350-µA current source set by the timing resistor (RT) (10 kΩ), internally. This produces a linear-ramp voltage waveform across CT. When the voltage across CT reaches 3 V, it is discharged by the oscillator circuit and the charging cycle is reinitiated. The frequency of the oscillator is programmable over a range of 1 kHz to 300 kHz by the selection of CT. The programmed frequency of the oscillator can be calculated with the equation f = 1/ (104 × CT). The PWM output frequency is one-half of the oscillator frequency. dead-time (DT) control The DT input provides control of minimum dead time (off time). An input offset of 110 mV ensures a minimum dead time of 3% with the DT input grounded. Additional dead time can be imposed by applying voltage to the DT input. This provides a linear control of the dead time from its minimum of 3% to its maximum of 100% as the DT input voltage varies from 0 V to 3.3 V. The DT input is a relatively high-impedance input and is used where additional control of the output duty cycle is required. The input must be terminated; leaving this terminal open causes an undefined condition. pulse-width modulation The ramp voltage across CT is compared to the output of the error amplifier. The CT input incorporates a series diode, which is omitted from the DT control input. This requires the error-amplifier output to be 0.7-V greater than the voltage across CT to inhibit the PWM output. This also ensures PWM maximumduty-cycle operation without requiring the control voltage to sink to true ground potential. The output pulse width varies from 97% of the period to 0 as the voltage at the error-amplifier output varies from 0.5 V to 3.5 V. error amplifier The high-gain error amplifier receives bias from the VCC power rail. The inverting input, EA –, is biased by Vref /2 internally. The amplifier output is biased low by a current sink to provide PWM maximum duty cycle when the amplifier is off. Since the amplifier output is biased low only through IO(sink) of 300 µA (see functional block diagram), bias current required by external circuitry into the amplifier output for feedback must not exceed the capability of IO(sink); otherwise, the PWM maximum duty cycle is limited. 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • TPS5206CN SWITCHING-POWER-SUPPLY CONTROL CIRCUIT SLVS082A – APRIL 1994 – REVISED SEPTEMBER 1994 functional block diagram 1 + _ 14 SC SVP5 Reference Regulator 3 VCC Overvoltage/ Undervoltage Protection 8 4 SVN5 SVP12 15 REF 9 SVN12 5 CPR 7 CUV 19 PGI + _ Vref† 2 20 CPG + _ Vref† 2 2 10 PGO D1 110 mV‡ 6 DT + _ 13 CT _ OSC 0.7 V‡ 18 EA + + _ 17 EA – 11 D CLK GND + 12 D2 300 µA Vref† 2 16 EAO † Internally generated voltage ‡ Fixed-voltage offset Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. CPG 20 O Power-good-capacitor connection. Connects a capacitor to power-good signal delay. CPR 5 O Protection-delay-capacitor connection. Connects a capacitor to protection-delay circuit to bypass high-frequency noise. 13 O Timing capacitor. Connects a capacitor to sawtooth oscillator circuit for programming the operating frequency. 7 O UV capacitor connection. Connects a capacitor to UV power-on delay circuit to avoid malfunction in the initial state. D1 10 O PWM driver-1 output D2 12 O PWM driver-2 output DT 6 I Dead time. Control input to control the PWM minimum dead time (off time). EA – 17 I Error-amplifier inverting input EA + 18 I Error-amplifier noninverting input EAO 16 I/O CT CUV Error-amplifier output GND 11 PGI 19 I Power-good input PGO 2 O Power-good output REF 1 O 5-V reference voltage output 14 I Overcurrent sense input. When an OV/UV condition is sensed, the TLS1206 output is locked and PGO is set to low. SC Ground • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 3 TPS5206CN SWITCHING-POWER-SUPPLY CONTROL CIRCUIT SLVS082A – APRIL 1994 – REVISED SEPTEMBER 1994 Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION SVN5 8 I – 5-V OV/UV detection input. When an OV/UV condition is sensed, the TLS1206 output is locked and PGO is set to low. SVN12 9 I – 12-V OV/UV detection input. When an OV/UV condition is sensed, the TLS1206 output is locked and PGO is set to low. SVP5 3 I 5-V OV/UV detection input. When an OV/UV condition is sensed, the TLS1206 output is locked and PGO is set to low. SVP12 4 I 12-V OV/UV detection input. When an OV/UV condition is sensed, the TLS1206 output is locked and PGO is set to low. VCC 15 Supply voltage absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 V Amplifier input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3 V Collector output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 V Collector output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA Total power dissipation at (or below) 25°C free-air temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 70°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING OPERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING N 1150 mW 9.2 mW/°C 736 mW recommended operating conditions Supply voltage, VCC MIN MAX 7 40 V 40 V Collector output voltage, VO(D1), VO(D2) Collector output current, IO(D1), IO(D2) Timing capacitor, CT Operating free-air temperature, TA 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • UNIT 150 mA 0.47 10 000 nF 0 70 °C TPS5206CN SWITCHING-POWER-SUPPLY CONTROL CIRCUIT SLVS082A – APRIL 1994 – REVISED SEPTEMBER 1994 electrical characteristics over recommended operating free-air temperature range, VCC = 15 V PARAMETER Vref TEST CONDITIONS Reference output voltage VIH(SC) High-level input voltage, SC overcurrent protection VIL(SC) Low-level input voltage, SC overcurrent protection IO = 5 mA SVP5 = 5 V, SVN5 = – 5 V, VO(DT) ≥ 3.5 V SVP5 = 5 V, SVN5 = – 5 V, VO(DT) ≤ 0.4 V SVP12 = 12 V, SVN12 = – 12 V, MIN TYP MAX 4.9 5 5.1 5.1 SVP12 = 12 V, SVN12 = – 12 V, 4.9 SVP12 = 12 V, SVN12 = – 12 V, SVN5 = – 5 V, VO(DT) ≤ 0.4 V 3.5 3.9 4.5 SVP12 SVP5 = 5 V, SVN12 = – 12 V, SVN5 = – 5 V, VO(DT) ≤ 0.4 V 9 9.5 10.5 SVN5 SVP5 = 5 V, SVN12 = – 12 V, SVP12 = 12 V, VO(DT) ≤ 0.4 V –3 – 3.4 –4 SVN12 SVP5 = 5 V, SVN5 = – 5 V, SVP12 = 12 V, VO(DT) ≤ 0.4 V –8 – 9.3 – 10 SVP5 SVP12 = 12 V, SVN12 = – 12 V, SVN5 = – 5 V, VO(DT) ≤ 0.4 V 5.5 5.9 6.3 SVP12 SVP5 = 5 V, SVN12 = – 12 V, SVN5 = – 5 V, VO(DT) ≤ 0.4 V 13.5 14.1 14.8 SVN5 SVP5 = 5 V, SVN12 = – 12 V, SVP12 = 12 V, VO(DT) ≤ 0.4 V –7 – 8.4 –9 SVN12 SVP5 = 5 V, SVN5 = – 5 V, SVP12 = 12 V, VO(DT) ≤ 0.4 V – 14 – 15.3 – 16 Low level output voltage Low-level voltage, output drivers VO(DT) ≥ 3 3.5 5V IOL = 0 IOL = 150 mA VO(DT) VIH(PGI) Dead-time output voltage SVP5 = 7 V, High-level input voltage, PGI VIL(PGI) Low-level input voltage, PGI VO(PGO) ≥ 4 V, VO(PGO) ≤ 0.4 V, VIT(UV) VIT(OV) VOL(D1), VOL(D2) g , Input threshold voltage, overvoltage sense IO(DT) = –250 µA See Figure 3 VO(PGO) ≥ 4 V, VIH(CPG) High-level input voltage, CPG VIL(CPG) Low-level input voltage, CPG VI(PGI) = 4 V, See Figure 4 VO(PGO) ≤ 0.4 V, VOH(PGO) High-level output voltage, PGO VCPG = 4 V, See Figure 5 IO(PGO) = – 240 µA, VOL(PGO) Low-level output voltage, PGO VCPG = 0 V, See Figure 6 IO(PGO) = 9.6 mA, ICC fosc Standby supply current All other inputs and outputs open Oscillator frequency CT = 1200 pF V V V 0.4 1.6 2.5 V 3.5 V 2.8 V See Figure 3 VI(PGI) = 4 V, See Figure 4 V V SVP5 Input threshold voltage, g , undervoltage sense UNIT 2.42 2.95 V V 2.6 4.75 V V 0.4 V 32 mA 80 kHz switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER tr Rise time of power good td Delay time of power good TEST CONDITIONS VCPG L → H, VO(PGO) L → H, RL = 150 kΩ, CPG = 2.2 µF, VI(PGI) H → L, VO(PGO) H → L, • See Figures 4 and 6 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • MIN TYP See Figures 4 and 6 500 MAX UNIT 100 ns 600 µs 5 TPS5206CN SWITCHING-POWER-SUPPLY CONTROL CIRCUIT SLVS082A – APRIL 1994 – REVISED SEPTEMBER 1994 APPLICATION INFORMATION VCC = 15 V DT Test Output 1500 pF EAO SVP12 CT EA + SVN5 Open Test Input EA – Test Output Test Input VCC = 15 V SVP5 Test Input SVN12 1 kΩ PGO D1 D2 CUV Open PGI REF CPR CPG Open Open CS 1 kΩ 1 kΩ Figure 1. Test Circuit 2.5 V _ PGI + + _ CPG 2.5 V _ PGI = 4 V + PGO + _ 2.5 V † PGO 2.5 V † CPG (open) Figure 2. PGI Input Voltage Test Circuit Figure 3. CPG Input Voltage and PGO Output Voltage Test Circuit 5V 2.5 V _ PGI + + _ 2.2 µF PGO 2.5 V † Figure 4. PG Delay Time and Rise Time Test Circuit † Internally biased at Vref /2 or 2.5 V VIH PGI PGO 10% VIL VOH 90% 10% 10% tr td Figure 5. PG Output Voltage Waveform 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • VOL IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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