SN54HC540, SN74HC540 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS007B – MARCH 1984 – REVISED MAY 1997 D D SN54HC540 . . . J OR W PACKAGE SN74HC540 . . . DW OR N PACKAGE (TOP VIEW) High-Current 3-State Outputs Drive Bus Lines Directly or up to 15 LSTTL Loads Data Flow-Through Pinout (All Inputs on Opposite Side From Outputs) Package Options Include Plastic (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND description These octal buffers and line drivers feature the performance of the popular ’HC240 series and offer a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly enhances printed circuit board layout. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 SN54HC540 . . . FK PACKAGE (TOP VIEW) A2 A1 The 3-state control gate is a 2-input NOR. If either output-enable (OE1 or OE2) input is high, all eight outputs are in the high-impedance state. The ’HC540 provide inverted data at the outputs. A3 A4 A5 A6 A7 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 Y1 Y2 Y3 Y4 Y5 A8 GND Y8 Y7 Y6 The SN54HC540 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74HC540 is characterized for operation from –40°C to 85°C. OE1 VCC OE2 D FUNCTION TABLE (each buffer/driver) INPUTS A OUTPUT Y L L H L H L H X X Z X H X Z OE1 OE2 L L Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HC540, SN74HC540 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS007B – MARCH 1984 – REVISED MAY 1997 logic symbol† 1 OE1 & 19 EN OE2 A1 A2 A3 A4 A5 A6 A7 A8 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OE1 OE2 A1 1 19 2 18 Y1 To Seven Other Channels absolute maximum ratings over operating free-air temperature range‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HC540, SN74HC540 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS007B – MARCH 1984 – REVISED MAY 1997 recommended operating conditions SN54HC540 VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO Low-level input voltage Input voltage Output voltage Input transition (rise and fall) time TA Operating free-air temperature NOM MAX 2 5 6 VCC = 2 V VCC = 4.5 V VCC = 6 V MIN NOM MAX 2 5 6 1.5 1.5 3.15 3.15 4.2 VCC = 4.5 V VCC = 6 V tt SN74HC540 MIN UNIT V V 4.2 0 0.5 0 0.5 0 1.35 0 1.35 0 1.8 0 1.8 0 0 0 VCC VCC 0 VCC VCC 0 1000 0 1000 0 500 0 500 0 400 0 400 –55 125 –40 85 V V V ns °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS VI = VCC or 0, SN54HC540 MIN MAX SN74HC540 MIN MAX UNIT 2V 1.9 1.998 1.9 1.9 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 IOH = –6 mA IOH = –7.8 mA 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 5.34 2V 0.002 0.1 0.1 0.1 IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 6V ±0.01 ±0.5 ±10 ±5 µA 8 160 80 µA 10 10 10 pF IOL = 6 mA IOL = 7.8 mA ICC Ci TA = 25°C TYP MAX 4.5 V VI = VIH or VIL VI = VCC or 0 VO = VCC or 0 MIN IOH = –20 µA VI = VIH or VIL II IOZ VCC IO = 0 6V 2 V to 6 V POST OFFICE BOX 655303 3 • DALLAS, TEXAS 75265 V V 3 SN54HC540, SN74HC540 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS007B – MARCH 1984 – REVISED MAY 1997 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) A ten OE tdis OE tt TO (OUTPUT) Y Y Y Y VCC MIN TA = 25°C TYP MAX SN54HC540 MIN MAX SN74HC540 MIN MAX 2V 35 100 149 125 4.5 V 10 20 30 25 6V 8 17 25 21 2V 75 150 224 188 4.5 V 15 30 45 38 6V 13 26 38 32 2V 40 150 224 188 4.5 V 18 30 45 38 6V 17 26 38 32 2V 28 60 90 75 4.5 V 8 12 18 15 6V 6 10 15 13 UNIT ns ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) TA = 25°C MIN TYP MAX SN54HC540 SN74HC540 PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V 60 150 224 188 tpd A Y 4.5 V 15 30 45 38 ten tt OE Y Y MIN MAX MIN MAX 6V 13 26 38 32 2V 100 200 298 250 4.5 V 20 40 60 50 6V 17 34 51 43 2V 45 210 315 265 4.5 V 17 42 63 53 6V 13 36 53 45 UNIT ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance per buffer/driver POST OFFICE BOX 655303 No load • DALLAS, TEXAS 75265 TYP 35 UNIT pF SN54HC540, SN74HC540 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS007B – MARCH 1984 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION VCC PARAMETER Test Point From Output Under Test S1 tPZH ten RL CL (see Note A) 1 kΩ tPZL tPHZ tdis S2 RL 1 kΩ CL S1 S2 50 pF or 150 pF Open Closed Closed Open Open Closed Closed Open Open Open 50 pF tPLZ tpd or tt –– LOAD CIRCUIT 50 pF or 150 pF VCC Input 50% 50% 0V tPLH In-Phase Output 50% 10% tPHL 90% VOH 50% 10% V OL tf 90% tr tPHL Out-of-Phase Output 90% tPLH 50% 10% 50% 10% 90% VOH VOL tf tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES Output Control (Low-Level Enabling) VCC 50% 50% 0V tPZL Output Waveform 1 (See Note B) tPLZ ≈ VCC 50% 10% ≈ VCC VOL tPZH Input 50% 10% 90% VCC 90% 50% 10% 0 V tr Output Waveform 2 (See Note B) 90% VOH ≈0V tPHZ tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES 50% VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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