MA31755 MA31755 16-Bit Feedthrough Error Detection & Correction Unit (EDAC) Replaces June 1999 version, DS3572-3.0 The MA31755 is a 16 bit Error Detection and Correction Unit intended for use in high integrity systems for monitoring and correcting data values retrieved from memory. The EDAC is placed in the data bus between the processor and the memory to be protected. Extra check bits added at each memory location are programmed transparently by the EDAC during a processor write cycle. The entire checkword and data combination is verified on read cycles. If any one bit in the incoming data stream is at fault the EDAC can correct the fault transparently, presenting the corrected 16-bit value to the processor. An error in two bits can be detected but cannot be corrected. Both the correctable and uncorrectable error conditions are signalled to the system to allow the processor to take action as required. Parity is passed through the device unchanged as data bus bit 16. Tri-statable bus transceivers with a high drive capability are incorporated at the MD and CB busses which allows the usual bus driver devices to be removed and reduces the overall timing overhead imposed on the data bus. Although designed primarily for MA31750 application, this part may be used in almost any 16-bit processor system requiring high data integrity. DS3572-4.0 January 2000 8 8 VDD MD[0:16] VSS CB[0:5] MA31755 EDAC PD[0:16] XERRN ENCOR ENFLG CERRN NCERRN CS0 RDWN CS1N CS2N FEATURES ■ Fast Feedthrough (35ns Detect and Correct Cycle) Figure 1: Chip Signals ■ 16-Bit Operation with 6 Check Bits ■ Radiation Hard CMOS/SOS Technology ■ Feedthrough Operation ■ Error Corrected/Uncorrected Flags ■ High Drive Capability on Memory Busses 1/13 MA31755 1. PIN DESCRIPTIONS POWER VDD x8 VSS x8 Input Input - Supply - 5V nominal (all must be connected) Circuit 0V reference (all must be connected) I/O I/O I/O Active High Active High Active High Processor data bus + parity bit (bit 16) Memory data bus + parity bit (bit 16) Memory check bit bus BUSSES PD[0:16] MD[0:16] CB[0:5] ERROR FLAGS AND CONTROL CERRN Output Active Low NCERRN Output Active Low XERRN ENCOR Input Input Active Low Active High ENFLG Input Active High Asserted low when a correctable (1 bit) error occurs (ENFLG must be asserted high) Asserted low when an uncorrectable error occurs (ENFLG must be asserted high) External error feedthrough to NCERRN line. Enables correction of data when high. Data is passed through uncorrected when this line is low. Enables the flagging of incorrect data when high. When this line is low the two error flag lines are held inactive. DEVICE AND BUFFER CONTROL CS2N CS1N CS0 RDWN Input Input Input Input Active Low Active Low Active High - Enables device and output buffers. Enables device and output buffers. Enables device and output buffers. High indicates a read cycle, low indicates a write cycle. 2. FUNCTIONAL DESCRIPTION 2.0 GENERAL 2.1 TESTING THE EDAC AND MEMORY SYSTEM The EDAC is of feedthrough type with 16 data bits, 1 parity bit and 6 check bits, giving the ability to correct all single bit errors and detect all double bit errors. Errors in more than two bits may result in any combination of error flags being raised and the data may be arbitrarily modified by the correction circuitry. The EDAC is placed in the data bus between the processor and the memory to be protected. It forms the interface between the 23-bit memory bus and the 17-bit processor bus. Tri-statable bus transceivers with a high drive capability are incorporated at both busses. No specific hardware for testing is provided by the MA31755 since this would compromise the speed performance of the part in normal operation. However, it is possible to fully test the EDAC function and the generation of the error signals without this. The system should provide a means by which the check bit memory may be dynamically write-enabled and disabled - this may be provided by gating write strobe on the check bit memory with a latched control bit. By writing first with check bits enabled, then with them disabled, suitable seed values may be constructed which have the required pattern of bits to test each feature of the EDAC operation. A similar approach may be taken when testing the check bit memory. By disabling the EDAC (asserting ENCOR low) the processor may have direct access to the unmodified 17-bit data from the memory. Suitable test patterns may be applied to test each memory location as required. 2/13 MA31755 2.2 BUS CONTROL There are four signals which control the drive status of the EDAC external busses: RDWN, CS2N, CS1N and CS0. The relationship to each other and to the EDAC busses is shown in Figure 2 below. The timing of these signals is shown in Figures 6 and 7. RDWN CS2N CS1N CS0 X X X High Low High X X Low Low X High X Low Low X X Low High High Bus state Processor Memory Tristate Tristate Tristate Tristate Tristate Tristate Output Input Input Output Figure 2: Bus Control 2.3 INTERNAL OPERATION 2.3.1 Check Bit Generation On write cycles the processor data word, PD[0:15], and the processor parity bit ,PD[16], are passed directly to the memory data bus, MD[0:15], and the memory parity bit, MD[16]. The check bits, CB[0:5], are derived by 6 parity generators operating on sets of 8 bits of the processor data word, PD[0:15], as shown in Figure 3 below: CB Parity 0 1 2 3 4 5 Even Even Odd Odd Even Even PD 15 14 13 X 12 X X X X X 11 10 9 X X X X X X X X X X X X X X 8 X X 7 X 6 X X 5 X 4 X X X X X X X X 3 2 X X X X X X X 1 X X X 0 X X X X Figure 3: Check Bit Generation 2.3.2 Syndrome Generation The syndrome generation logic checks the sense of the check bits with respect to the memory data word. Six 9-input parity checkers generate the syndrome bits, SY[0:5], according to figure 4 below: SY 0 1 2 3 4 5 Parity Even Even Odd Odd Even Even MD 15 14 13 X X X X X X X X X 12 11 10 X X X X X X X X X 9 X X 8 X X 7 X 6 X X 5 X 4 X X X X X X X X 3 2 X X X X X X X X 1 X X X 0 X X X CB 0 1 X X 2 3 4 5 X X X X Figure 4: Syndrome Generation If there are no errors in the memory data word, MD[0:15], or the check bits, CB[0:5], then all of the syndrome bits, SY[0:5], will be set low. A single bit error in the memory data word, MD[0:15], will cause 3 syndrome bits to be set high. However, a single bit error in the check bits, CB[0:5], will cause only 1 syndrome bit to be set high. A two bit error in the memory data word and/or the check bits will cause either 2, 4, 5 or 6 syndrome bits to be set. Three or more errors in the memory data word and/or the check bits will cause an undefined number of syndrome bits to be set. This will cause the operation of the device in respect of the states of CERRN, NCERRN and data on the PD bus to be unpredictable. 3/13 MA31755 2.3.3 Correction With no syndrome bits set data will pass through from the MD bus to the PD bus unchanged. When a single bit error occurs in the memory data word, MD[0:15], the three syndrome bits which are set identify which data bit is in error. The correction logic decodes these syndrome bits and will correct the error provided the correction enable input, ENCOR, is high. 2.3.4 Flag Generation The correctable error flag,CERRN, is driven low whenever 1 or 3 syndrome bits are set and flags are enabled (ENFLG=1). The non-correctable error flag, NCERRN, is driven low whenever 2, 4, 5 or 6 Syndrome bits are set and flags are again enabled (ENFLG=1). NCERRN will also be driven low Check bit generation PD[0:16] Tri-statable Buffer Correction should the external error input, XERRN, be driven low at any time. Note: this external error feedthrough from XERRN to NCERRN operates independently of ENFLG and the Chip Select inputs (CS0, CS1N & CS2N). Flags are enabled provided the ENFLG input is high and the device is selected. Note: the flags are not disabled on write cycles and therefore can indicate errors on write operations caused by faults on the Memory Data Bus and the Check Bit Bus. 2.3.5 Internal Structure Figure 5 below shows the internal block diagram representing the internal architecture of the MA31755. Tri-statable Buffer MD[0:16] CB[0:5] Syndrome Generation ENCOR ENFLG XERRN RDWN CS0 CS1N CS2N Buffer Control Flags Generation Figure 5: Block Diagram of the Internal Architecture of the MA31755 4/13 CERRN NCERRN MA31755 3. TIMING DIAGRAMS PD[0:16] Data from processor MD[0:16] CB[0:5] Data and check bits to memory T1 CERRN NCERRN T4 Valid Flags T6 T8 CS0 T9 T10 CS1N CS2N RDWN Figure 6 : Processor Write Timings (ENFLG = 1) T3 CB[0:5] Check bits from memory MD[0:16] Data from memory T2 PD[0:16] Valid Data T4 CERRN NCERRN Valid Flags T6 T8 RDWN CS0 T5 T7 CS1N CS2N Figure 7: Processor Read Timings (ENCOR and ENFLG=1) 5/13 MA31755 XERRN T13 T13 NCERRN Figure 8: External Error Feedthrough Timing (ENFLG=X ,CS0=X, CS1N /CS2N=X) Uncorrected Data PD[0:16] Corrected Data CERRN NCERRN Uncorrected Data Flags Valid T11 T11 ENFLG T12 T12 ENCOR Figure 9: Correction and Error flag enable/disable timings (CS0=1, CS1N/CS2N = 0) 6/13 MA31755 4. AC CHARACTERISTICS Parameter T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 Description PD[0:16] to MD[0:16] , CB[0:5] valid MD[0:16] to PD[0:16] valid CB[0:5] to PD[0:16] valid MD[0:16] to CERRN and NCERRN valid CB[0:5] to CERRN and NCERRN valid RDWN, CS0 rising to PD[0:16] driven (processor read) CS1N, CS2N falling to PD[0:16] driven (processor read) CS0 rising to error flags changing CS1N, CS2N falling to error flags changing RDWN, CS0 falling to PD[0:16] Hi-Z CS1N,CS2N rising to PD[0:16] Hi-Z CS0 falling to error flags high CS1N, CS2N rising to error flags high RDWN, CS1N and CS2N falling to MD[0:16] and CB[0:5] driven (processor write) CS0 rising to MD[0:16] and CB[0:5] driven (processor write) CS0 falling to MD[0:16] and CB[0:5] Hi-Z RDWN, CS1N, CS2N rising to MD[0:16] and CB[0:5] Hi-Z ENFLG to CERRN and NCERRN valid ENCOR to PD[0:16] valid XERRN to NCERRN valid Min - Max 25 30 35 40 Units ns ns ns ns Notes CL = 150pF CL = 50pF CL = 50pF CL = 50pF 5 20 ns CL = 50pF - 25 ns CL = 50pF - 30 ns CL = 50pF - 25 ns CL = 50pF 5 20 ns CL = 150pF 5 25 ns CL = 150pF - 20 20 10 ns ns ns CL = 50pF CL = 50pF CL = 50pF Mil-Std-883, method 5005, subgroups 9, 10, 11 Figure 10: Timing Parameters 5. DC CHARACTERISTICS AND RATINGS Symbol VDD VI TA TS Description Supply voltage Input voltage Operating temperature Storage temperature Min. -0.5 -0.3 -55 -65 Max. 7 VDD+0.3 +125 +150 Units V V oC oC Figure 11: Absolute Maximum Ratings Note: Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions, or at any other condition above those indicated in the operations section of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter VOH Description Output high voltage Min Vdd- 0.5 Max - Unit V VOL Output low voltage - Vss+0.5 V Notes IOH = 15mA on MD[0:16] / CB[0:5] IOH = 5mA on other outputs. IOL = -15mA on MD[0:16] / CB[0:5] IOL = -5mA on other outputs. VIH Input high voltage Vdd-1.5 V VIL Input low voltage Vss+1.5 V IIL, IIH (Note 1) Input current high/low 10 uA IOZ (Note 1) Output tri-state leakage 0.1 mA VO = 0 to VDD ISS Standby current 10 mA IDD Operating current 100 mA Conditions VDD = 4.5 to 5.5V, TA = -55 to +125°C Mil-Std-883, method 5005, subgroups 1, 2, 3 Note 1: Worst case at TA = +125°C, guaranteed but not tested at TA = -55°C. Figure 12: Operating Electrical Characteristics 7/13 MA31755 Subgroup Definition 1 Static characteristics specified in Figure 12 at +25°C 2 Static characteristics specified in Figure 12 at +125°C 3 Static characteristics specified in Figure 12 at -55°C 7 Functional characteristics specified at +25°C 8A Functional characteristics specified at +125°C 8B Functional characteristics specified at -55°C 9 Switching characteristics specified in Figure 10 at +25°C 10 Switching characteristics specified in Figure 10 at +125°C 11 Switching characteristics specified in Figure 10 at -55°C Figure 13: Definition of Subgroups 6. APPLICATIONS INFORMATION To memory system CONTROL VDD PWRDN INT02N INT08N INT10N INT11N INT13N INT15N IOI1N IOI2N MA31750 RDYN CLK TCLK ABN DPARN DTON CONREQN RESETN GND RDYN PD[0:16] VDD0-3 PD[0:16] RDWN MD[0:16] CB[0:5] MA31755 SUREN TGON INTAKN NPU ILLADN CS2N CS1N XERRN CS0 CERRN NCERRN VSS0-3 Figure 14: Basic System Diagram for the MA31755 with the MA31750 8/13 MD[0:16] CB[0:5] RDWN ENMDN ENPDN AS[0-3] PS[0-3] PB[0-3] REQN GRANTN LOCKN RESETN A[0-15] ASTB ASTB DSN DSN M/ION M/ION RDWN R/WN O/IN O/IN RDN RDN WRN WRN MPROEN PEN EXADEN FLT7N SYSFN CLK TCLK A[0-15] D[0-16] XERRN MA31755 7. PACKAGING The device will be supplied in a 68-pin PGA for development with a 68-pin flatpack option for flight parts. 1 Pin A1 Index 0.100 2 3 4 5 TOP VIEW 0.900 ±0.010 BOTTOM VIEW 1.060 sq ±0.020 6 7 8 9 10 A B C D E F G H J K 0.050 ±0.010 0.105 max XG451 Outline 0.045 ±0.005 0.018 ±0.002 0.180 ±0.010 Figure 15: Dimensioned Drawing for the 68-pin PGA Package Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 Function CB05 NCERRN RDWN PD16 PD14 VDD PD13 PD11 PD10 PD08 CB03 GND CERRN XERRN PD15 GND PD12 PD09 GND PD06 Pin C1 C2 C3 C8 C9 C10 D1 D2 D9 D10 E1 E2 E9 E10 F1 F2 F9 F10 G1 G2 Function CB02 CB04 VDD VDD PD07 PD04 CB00 CB01 PD05 PD03 GND NC PD02 PD01 VDD NC GND VDD MD16 MD14 Pin G9 G10 H1 H2 H3 H8 H9 H10 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 Function CS0 PD00 MD15 MD12 VDD VDD ENFLG CS1N MD13 GND MD10 MD07 GND MD05 MD02 MD00 GND CS2N MD11 MD09 Pin K3 K4 K5 K6 K7 K8 K9 K10 Function MD08 MD06 VDD NC MD04 MD03 MD01 ENCOR Figure 16: Pinout for the 68-pin PGA Package 9/13 MA31755 Ref Millimetres Inches Min. Nom. Max. Min. Nom. Max. A - - 2.72 - - 0.107 A1 1.83 - 2.24 0.072 - 0.088 b 0.41 - 0.51 0.016 - 0.020 c 0.20 - 0.30 0.008 - 0.012 D1, D2 23.88 - 24.51 0.940 - 0.960 e - 2.54 - - 0.050 - j1 - 1.02 - - 0.040 - j2 - 0.51 - - 0.020 - L 10.16 - 10.54 0.400 - 0.415 Z 1.65 - 2.16 0.065 - 0.085 XG540 A A1 c L D1 j1 Z Pin 1 b D2 Top View e j2 Figure 17: Dimensioned Drawing for the 68-pin Flatpack Package Topbraze 10/13 VDD MD11 MD9 MD10 MD8 MD7 GND MD6 NC VDD MD5 MD4 MD3 MD1 MD2 MD0 GND MA31755 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 27 GND ENCOR 28 8 MD12 ENFLG 29 7 MD13 CS2N 30 6 MD14 CS1N 31 5 MD15 CS0 32 4 MD16 PD0 33 3 NC GND 34 VDD PD1 35 2 1 VDD GND 68 NC PD2 37 67 CB0 PD3 38 66 CB1 PD4 39 65 CB2 PD5 40 64 CB3 VDD TOP VIEW Pin 1 Index 36 GND CERRN NCERRN RDWN XERRN PD16 PD15 VDD PD14 GND VDD PD13 61 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PD12 CB5 GND PD9 CB4 62 PD10 PD11 63 42 PD8 41 VDD PD6 PD7 Figure 18: Pinout for the 68-pin Flatpack Package 11/13 MA31755 8. RADIATION TOLERANCE 8.1 TOTAL DOSE RADIATION TESTING For product procured to guaranteed total dose radiation levels, each wafer lot will be approved when all sample devices from each lot pass the total dose radiation test. The sample devices will be subjected to the total dose radiation level (Cobalt-60 Source), defined by the ordering code, and must continue to meet the electrical parameters specified in the data sheet. Electrical tests, pre and post irradiation, will be read and recorded. Dynex Semiconductor can provide radiation testing compliant with Mil-Std-883 test method 1019, Ionizing Radiation (Total Dose). Total Dose (Function to specification)* 5x105 Rad(Si) Transient Upset (Stored data loss) 1x1011 Rad(Si)/sec Transient Upset (Survivability) >1x1012 Rad(Si)/sec Neutron Hardness (Function to specification) >1x1015 n/cm2 Single Event Upset** <1x10-10 Errors/bit day Latch Up Not possible * Other total dose radiation levels available on request ** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit Figure 19: Radiation Hardness Parameters 9. ORDERING INFORMATION Unique Circuit Designator Radiation Tolerance S R Q MAx31755xxxxx Radiation Hard Processing 100 kRads (Si) Guaranteed 300 kRads (Si) Guaranteed Package Type A F QA/QCI Process (See Section 9 Part 4) Test Process (See Section 9 Part 3) Pin Grid Array Flatpack (Solder Seal) Assembly Process (See Section 9 Part 2) Reliability Level For details of reliability, QA/QC, test and assembly options, see ‘Manufacturing Capability and Quality Assurance Standards’ Section 9. 12/13 L C D E B S Rel 0 Rel 1 Rel 2 Rel 3/4/5/STACK Class B Class S MA31755 http://www.dynexsemi.com e-mail: [email protected] HEADQUARTERS OPERATIONS DYNEX SEMICONDUCTOR LTD Doddington Road, Lincoln. Lincolnshire. LN6 3LF. United Kingdom. Tel: 00-44-(0)1522-500500 Fax: 00-44-(0)1522-500550 DYNEX POWER INC. Unit 7 - 58 Antares Drive, Nepean, Ontario, Canada K2E 7W6. Tel: 613.723.7035 Fax: 613.723.1518 Toll Free: 1.888.33.DYNEX (39639) CUSTOMER SERVICE CENTRES France, Benelux, Italy and Spain Tel: +33 (0)1 69 18 90 00. Fax: +33 (0)1 64 46 54 50 North America Tel: 011-800-5554-5554. Fax: 011-800-5444-5444 UK, Germany, Scandinavia & Rest Of World Tel: +44 (0)1522 500500. Fax: +44 (0)1522 500020 SALES OFFICES France, Benelux, Italy and Spain Tel: +33 (0)1 69 18 90 00. Fax: +33 (0)1 64 46 54 50 Germany Tel: 07351 827723 North America Tel: (613) 723-7035. Fax: (613) 723-1518. Toll Free: 1.888.33.DYNEX (39639) / Tel: (831) 440-1988. Fax: (831) 440-1989 / Tel: (949) 733-3005. Fax: (949) 733-2986. UK, Germany, Scandinavia & Rest Of World Tel: +44 (0)1522 500500. Fax: +44 (0)1522 500020 These offices are supported by Representatives and Distributors in many countries world-wide. © Dynex Semiconductor 2000 Publication No. DS3572-4 Issue No. 4.0 January 2000 TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRINTED IN UNITED KINGDOM Datasheet Annotations: Dynex Semiconductor annotate datasheets in the top right hard corner of the front page, to indicate product status. The annotations are as follows:Target Information: This is the most tentative form of information and represents a very preliminary specification. No actual design work on the product has been started. Preliminary Information: The product is in design and development. The datasheet represents the product as it is understood but details may change. Advance Information: The product design is complete and final characterisation for volume production is well in hand. No Annotation: The product parameters are fixed and the product is available to datasheet specification. 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