MA5114 MA5114 Radiation hard 1024x4 Bit Static RAM Replaces June 1999 version, DS3591-4.0 DS3591-5.0 January 2000 The MA5114 4k Static RAM is configured as 1024 x 4 bits and manufactured using CMOS-SOS high performance, radiation hard, 3µm technology. The design uses a 6 transistor cell and has full static operation with no clock or timing strobe required. Address input buffers are deselected when Chip Select is in the HIGH state. Operation Mode CS WE I/O Power FEATURES ■ 3µm CMOS-SOS Technology ■ Latch-up Free ■ Fast Access Time 90ns Typical ■ Total Dose 106 Rad(Si) ■ Transient Upset >1010 Rad(Si)/sec ■ SEU <10-10 Errors/bitday Read L H D OUT Write L L D IN Standby H X High Z Figure 1: Truth Table ISB1 ■ Single 5V Supply ■ Three State Output ISB2 ■ Low Standby Current 50µA Typical ■ -55°C to +125°C Operation ■ All Inputs and Outputs Fully TTL or CMOS Compatible ■ Fully Static Operation ■ Data Retention at 2V Supply Figure 2: Block Diagram 1/12 MA5114 CHARACTERISTICS AND RATINGS Symbol Parameter Min. Max. Units Supply Voltage -0.5 7 V VI Input Voltage -0.3 VDD+0.3 V TA Operating Temperature -55 125 °C TS Storage Temperature -65 150 °C VCC Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functlonal operation of the device at these condltions, or at any other condition above those indicated in the operations section of this specification, is not Implied Exposure to absolute maxlmum rating conditions for extended perlods may affect device reliability. Figure 3: Absolute Maximum Ratings Notes for Tables 4 and 5: 1. Characteristics apply to pre radiation at TA = -55°C to +125°C with VDD = 5V ±10% and to post 100k Rad(Si) total dose radiation at TA = 25°C with VDD = 5V ±10% (characteristics at higher radiation levels available on request). 2. Worst case at TA = +125°C, guaranteed but not tested at TA = -55°C. GROUP A SUBGROUPS 1, 2, 3. Symbol Parameter Conditions Min. Typ. Max. Units VDD Supply voltage - 4.5 5.0 5.5 V VlH Input High Voltage - VDD/2 - VDD V VlL Input Low Voltage - VSS - 0.8 V VOH Output High Voltage IOH1 = -1mA 2.4 - - V VOL Output Low Voltage IOL = 2mA - - 0.4 V ILI Input Leakage Current (note 2) All inputs except CS - - ±10 µA ILO Output Leakage Current (note 2) Output disabled, VOUT = VSS or VDD - - ±20 µA IPUI Input Pull-Up Current VIN = VSS on CS input only - - -100 µA IPDI Input Leakage Current VIN = VSS on CS input only - - 5 µA IDD Power Supply Current fRC = 1MHz, CS = 50% mark:space- 12 16 mA ISB1 Selected Supply Current CS = VSS - 25 35 mA ISB2 Standby Supply Current Chip disabled - 50 3000 µA Figure 4: Electrical Characteristics Symbol Parameter Conditions Min. Typ. Max. Units VDR VCC for Data Retention CS = VDR 2.0 - - V IDDR Data Retention Current CS = VDR, VDR = 2.0V - 30 2000 µA Figure 5: Data Retention Characteristics 2/12 MA5114 AC CHARACTERISTICS Conditions of Test for Tables 5 and 6: 1. Input pulse = VSS to 3.0V. 2. Times measurement reference level = 1.5V. 3. Transition is measured at ±500mV from steady state. 4. This parameter is sampled and not 100% tested. Notes for Tables 6 and 7: Characteristics apply to pre-radiation at TA = -55°C to +125°C with VDD = 5V±10% and to post 100k Rad(Si) total dose radiation at TA = 25°C with VDD = 5V ±10%. GROUP A SUBGROUPS 9, 10, 11. Symbol Parameter Min Max Units TAVAVR Read Cycle Time 135 - ns TAVQV Address Access Time - 135 ns TELQV Chip Select to Output Valid - 135 ns TELQX (3,4) Chip Select to Output Active 10 - ns TELQZ (3,4) Chip Select to Output Tri State 10 50 ns Output Hold from Address Change 10 - ns Parameter Min Max Units TAVAVW Write Cycle Tlme 135 - ns TAVWL Address Set Up Time 10 - ns TWLWH Write Pulse Width 50 - ns TWHAV Write Recovery Time 5 - ns TDVWH Data Set Up Time 35 - ns TNHDX Data Hold Time 5 - ns Write Enable to Output Tri State 10 50 ns TELWL Chip Selection to Write Low 25 - ns TELWH Chip Selection to End of Write 85 - ns TAVWH Address Valid to End of Write 80 - ns Output Active from End to Write 5 - ns TAXQX Figure 6: Read Cycle AC Electrical Characteristics Symbol TWLQZ (3,4) TWHQX (3,4) Figure 7: Write Cycle AC Electrical Characteristics Symbol CIN COUT Parameter Conditions Min. Typ. Max. Units Input Capacitance Vl = 0V - 6 10 pF Output Capacitance VO = 0V - 8 12 pF Note: TA = 25°C and f = 1MHz. Data obtained by characterisation or analysis; not routinely measured. Figure 8: Capacitance 3/12 MA5114 Symbol FT Parameter Conditions Basic Functionality VDD = 4.5V - 5.5V, FREQ = 1MHz VIL = VSS, VIH = VDD, VOL ≤ 1.5V, VOH ≥ 1.5V TEMP = -55°C to +125°C, GPS PATTERN SET GROUP A SUBGROUPS 7, 8A, 8B Figure 9: Functionality Subgroup Definition 1 Static characteristics specified in Tables 4 and 5 at +25°C 2 Static characteristics specified in Tables 4 and 5 at +125°C 3 Static characteristics specified in Tables 4 and 5 at -55°C 7 Functional characteristics specified in Table 9 at +25°C 8A Functional characteristics specified in Table 9 at +125°C 8B Functional characteristics specified in Table 9 at -55°C 9 Switching characteristics specified in Tables 6 and 7 at +25°C 10 Switching characteristics specified in Tables 6 and 7 at +125°C 11 Switching characteristics specified in Tables 6 and 7 at -55°C Figure 10: Definition of Subgroups 4/12 MA5114 TIMING DIAGRAMS TAVAVR ADDRESS TAVQV TAXQX TELQV CS TELQX DATA OUT TEHQZ HIGH IMPEDANCE DATA VALID 1. WE is high for Read Cycle. 2. Address Vaild prior to or coincident with CS transition low. Figure 11a: Read Cycle 1 TAVAVR ADDRESS TAVQV DATA OUT TAXQX DATA VALID 1. WE is high for Read Cycle. 2. Device is continually selected. CS low. Figure 11b: Read Cycle 2 5/12 MA5114 TAVAVW ADDRESS TAVWH TWHAV (3) TWLWH (2) TAVWL (4) WE TAXQX TWLQZ TELWL TWLQH (5) (7) DATA OUT HIGH IMPEDANCE TDVWH DATA IN TWHDX DATA VALID TELWH CS 1. WE must be high during all address transitions. 2. A write occurs during the overlap (TWLWH) of a low CS and a low WE. 3. TWHAV is measured from either CS or WE going high, whichever is the earlier, to the end of the write cycle. 4. If the CS low transition occurs simultaneously with, or after, the WE low transition, the output remains in the high impedance state. 5. DATA OUT is in the active state, so DATA IN must not be in opposing state. 6. DATA OUT is the write data of the current cycle, if selected. 7. DATA OUT is the read data of the next address, if selected. 8. TELWL must be met to prevent memory corruption. Figure 12: Write Cycle 6/12 (6) MA5114 OUTLINES AND PIN ASSIGNMENTS D 9 1 10 18 W ME Seating Plane A1 A C H e1 e Ref b Z Millimetres 15° Inches Min. Nom. Max. Min. Nom. Max. A - - 5.715 - - 0.225 A1 0.38 - 1.53 0.015 - 0.060 b 0.35 - 0.59 0.014 - 0.023 A6 1 18 Vdd A5 2 17 A7 A4 3 16 A8 4 c 0.20 - 0.36 0.008 - 0.014 A3 15 A9 D - - 23.11 - - 0.910 A0 5 13 D2 Top View 14 D1 e - 2.54 Typ. - - 0.100 Typ. - A1 6 e1 - 8.13 Typ. - - 0.300 Typ. - A2 7 12 D3 H 4.44 - 5.38 0.175 - 0.212 CS 8 11 D4 Me - - 8.28 - - 0.326 Vss 9 Z - - 1.27 - - 0.050 10 WE W - - 1.53 - - 0.060 XG406 Figure 13: 18-Lead Ceramic DIL (Solder Seal) - Package Style C 7/12 MA5114 M b D Z e L A c ME A1 Pin 1 Ref Millimetres Inches Min. Nom. Max. Min. Nom. Max. A - - 3.07 - - 0.121 A1 0.66 - - 0.026 - - b 0.38 - 0.48 0.015 - 0.019 c 0.08 - 0.152 0.003 - 0.006 D 14.99 - 15.50 0.590 - 0.610 e - 2.54 - - 0.050 - L 6.73 - 7.75 0.265 - 0.305 0.408 M 9.96 - 10.36 0.392 - Me 7.6 - - 0.30 - - Z 0.13 - 1.14 0.005 - 0.045 XG544 Vdd 24 1 NC A7 23 2 A6 A8 22 3 A5 A9 21 4 A4 NC 20 5 A3 NC 19 D1 18 Bottom View D2 17 7 A0 8 A1 D3 16 9 A2 D4 15 10 NC NC 14 11 CS WE 13 12 Vss Figure 14: 24-Lead Ceramic Flatpack (Solder Seal) - Package Style F 8/12 6 NC MA5114 D A e b 23 A8 22 A3 NC A0 A1 A2 9 Bottom View 21 10 NC 11 CS 12 Vss 13 WE 14 NC D4 20 19 18 17 16 15 D3 24 A7 8 D2 Vdd 7 D1 1 6 NC 2 5 NC A6 4 A9 E 3 NC Pad 1 Bottom View A5 A4 1 Radius r 3 corners Ref Millimetres Min. Inches Nom. Max. Min. Nom. Max. A - - 2.16 - - 0.096 b1 - 0.51 - - 0.020 - D 8.76 - 9.14 0.345 - 0.360 E 8.76 - 9.14 0.345 - 0.360 e - 1.02 - - 0.040 - r - 0.19 - - 0.0075 - XG470 Figure 15: 24-Pad Leadless Chip Carrier - Package Style L 9/12 MA5114 P a c k a ge O pt ion Func t ion A6 A5 A4 A3 A0 A1 A2 NCS VSS NWE D4 D3 D2 D1 A9 A8 A7 VDD F 2 3 4 5 7 8 9 11 12 13 15 16 17 18 21 22 23 24 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 L 2 3 4 5 7 8 9 11 12 13 15 16 17 18 21 22 23 24 Burnin V ia R R R R R R R R Direct R R R R R R R R Direct S t a t ic 1 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 5V S t a t ic 2 5V 5V 5V 5V 5V 5V 5V 5V 0V 5V 5V 5V 5V 5V 5V 5V 5V 5V 1. F0=150KHz, F1=F0/2, F2=F0/4, F3=F0/8 etc. 2. Burnin R=1k 3. Radiation R=10k Figure 16: Burnin and Radiation Configuration 10/12 Dy na mic F6 F5 F4 F3 F0 F1 F2 0V 0V 5V LOAD LOAD LOAD LOAD F9 F8 F7 5V Ra dia t ion 5V 5V 5V 5V 5V 5V 5V 5V 0V 5V 5V 5V 5V 5V 5V 5V 5V 5V MA5114 RADIATION TOLERANCE Total Dose Radiation Testing For product procured to guaranteed total dose radiation levels, each wafer lot will be approved when all sample devices from each lot pass the total dose radiation test. The sample devices will be subjected to the total dose radiation level (Cobalt-60 Source), defined by the ordering code, and must continue to meet the electrical parameters specified in the data sheet. Electrical tests, pre and post irradiation, will be read and recorded. GEC Plessey Semiconductors can provide radiation testing compliant with MIL-STD-883 test method 1019, Ionizing Radiation (Total Dose). Total Dose (Function to specification)* 1x105 Rad(Si) Transient Upset (Stored data loss) 5x1010 Rad(Si)/sec Transient Upset (Survivability) >1x1012 Rad(Si)/sec Neutron Hardness (Function to specification) >1x1015 n/cm2 Single Event Upset** 3.4x10-9 Errors/bit day Latch Up Not possible * Other total dose radiation levels available on request ** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit Figure 17: Radiation Hardness Parameters SINGLE EVENT UPSET CHARACTERISTICS UPSET BIT CROSS-SECTION (cm2/bit) Ion LET (MeV.cm2/mg) Figure 18: Typical Per-Bit Upset Cross-Section vs Ion LET 11/12 MA5114 ORDERING INFORMATION Unique Circuit Designator MAx5114xxxxx Radiation Tolerance S L C R Radiation Hard Processing 30 kRads (Si) Guaranteed 50 kRads (Si) Guaranteed 100 kRads (Si) Guaranteed QA/QCI Process (See Section 9 Part 4) Test Process (See Section 9 Part 3) Package Type C F L Ceramic DIL (Solder Seal) Flatpack (Solder Seal) Leadless Chip Carrier Assembly Process (See Section 9 Part 2) Reliability Level L C D E B S For details of reliability, QA/QC, test and assembly options, see ‘Manufacturing Capability and Quality Assurance Standards’ Section 9. Rel 0 Rel 1 Rel 2 Rel 3/4/5/STACK Class B Class S http://www.dynexsemi.com e-mail: [email protected] HEADQUARTERS OPERATIONS DYNEX SEMICONDUCTOR LTD Doddington Road, Lincoln. Lincolnshire. LN6 3LF. United Kingdom. Tel: 00-44-(0)1522-500500 Fax: 00-44-(0)1522-500550 DYNEX POWER INC. Unit 7 - 58 Antares Drive, Nepean, Ontario, Canada K2E 7W6. Tel: 613.723.7035 Fax: 613.723.1518 Toll Free: 1.888.33.DYNEX (39639) CUSTOMER SERVICE CENTRES France, Benelux, Italy and Spain Tel: +33 (0)1 69 18 90 00. Fax: +33 (0)1 64 46 54 50 North America Tel: 011-800-5554-5554. Fax: 011-800-5444-5444 UK, Germany, Scandinavia & Rest Of World Tel: +44 (0)1522 500500. Fax: +44 (0)1522 500020 SALES OFFICES France, Benelux, Italy and Spain Tel: +33 (0)1 69 18 90 00. Fax: +33 (0)1 64 46 54 50 Germany Tel: 07351 827723 North America Tel: (613) 723-7035. Fax: (613) 723-1518. Toll Free: 1.888.33.DYNEX (39639) / Tel: (831) 440-1988. Fax: (831) 440-1989 / Tel: (949) 733-3005. Fax: (949) 733-2986. UK, Germany, Scandinavia & Rest Of World Tel: +44 (0)1522 500500. Fax: +44 (0)1522 500020 These offices are supported by Representatives and Distributors in many countries world-wide. © Dynex Semiconductor 2000 Publication No. DS3581-5 Issue No. 5.0 January 2000 TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRINTED IN UNITED KINGDOM Datasheet Annotations: Dynex Semiconductor annotate datasheets in the top right hard corner of the front page, to indicate product status. The annotations are as follows:Target Information: This is the most tentative form of information and represents a very preliminary specification. No actual design work on the product has been started. Preliminary Information: The product is in design and development. The datasheet represents the product as it is understood but details may change. Advance Information: The product design is complete and final characterisation for volume production is well in hand. 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It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request. All brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners. 12/12