EL4093C EL4093C 300 MHz DC-Restored Video Amplifier Features General Description # High accuracy DC restoration for video # Low supply current of 9.5 mA typ. # 300 MHz bandwidth # 1500V/ms slew rate # 0.04% differential gain and 0.02§ differential phase into 150X for NTSC # 1.5 mV max. restored DC offset # Sample and hold amplifier with fast enable and low leakage # TTL-compatible HOLD logic input The EL4093C is a complete DC-restored video amplifier subsystem, featuring low power consumption and high slew rate. It contains a current feedback amplifier and a sample and hold amplifier designed to stabilize video performance. When the HOLD logic input is low, the sample and hold may be used as a general purpose op amp to null the DC offset of the video amplifier. When the HOLD input goes high the sample and hold stores the correction voltage on the hold capacitor to maintain DC correction during the subsequent video scan line. Applications # Input amplifier in video equipment # Restoration amplifier in video mixers The sample and hold amplifier contains a current output stage that greatly simplifies its connection to the video amplifier. Its high output impedance also helps to preserve video linearity at low supply voltages. For ease of interfacing, the HOLD input is TTL-compatible. This device has an operational temperature of b 40§ C to a 85§ C and is packaged in plastic 16-pin DIP and 16lead SOIC. Connection Diagram Ordering Information Part No. Temp. Range Package Outline Ý EL4093CN -40§ C to a 85§ C 16-pin P-DIP MDP0031 EL4093CS -40§ C to a 85§ C 16-Lead SOIC MDP0027 Demo Board A demo PCB is available for this product. Request ‘‘EL4093 Demo Board.’’ 44093 – 1 January 1996 Rev B Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a ‘‘controlled document’’. Current revisions, if any, to these specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation. © 1995 Elantec, Inc. TD is 1.7in EL4093C Absolute Maximum Ratings g 10 mA IOUT2S/H amplifier output current g 6 mA IIN Maximum current into other pins PD Maximum Power Dissipation See Curves TA Operating Ambient Temperature Range b40§ C to a 85§ C TJ Operating Junction Temperature 150§ C b 65§ C to a 150§ C TST Storage Temperature Range VS V a to Vb Supply Voltage 12.6V VHOLD Voltage at HOLD input (DGNDb0.7) to (DGND a 5.5V) VIN Voltage at any other input V a to Vb g 8V DVIN Difference between Sample and Hold inputs g 30 mA IOUT1 Video amplifier output current TD is 0.7in TAB WIDE 300 MHz DC-Restored Video Amplifier Important Note: All parameters having Min/Max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality inspection. Elantec performs most electrical tests using modern high-speed automatic test equipment, specifically the LTX77 Series system. Unless otherwise noted, all tests are pulsed tests, therefore TJ e TC e TA. Test Level I II III IV V Test Procedure 100% production tested and QA sample tested per QA test plan QCX0002. 100% production tested at TA e 25§ C and QA sample tested at TA e 25§ C , TMAX and TMIN per QA test plan QCX0002. QA sample tested per QA test plan QCX0002. Parameter is guaranteed (but not tested) by Design and Characterization Data. Parameter is typical value at TA e 25§ C for information purposes only. Open-Loop DC Electrical Characteristics Power supplies at g 5V, TA e 25§ C Parameter Description Min Typ Max Test Level Units IS,HOLD Total Supply current in HOLD mode 9.5 11.5 I mA IS,SAMPLE Total Supply current in SAMPLE mode 8.5 10.5 I mA Parameter Description Min Typ Max Test Level Units VOS Input Offset Voltage 10 110 I mV IB a Non-Inverting Input Bias Current 10 25 I mA IBb Inverting Input Bias Current 15 50 I mA ROL Transimpedance VOUT e g 2.5V, RL e 150X 150 400 I kX VO Output Voltage Swing RL e 150X g3 g 3.5 I V ISC Output Short-Circuit Current 60 100 I mA 2 TD is 1.7in Video Amplifier Section (Not Restored) TD is 1.5in EL4093C 300 MHz DC-Restored Video Amplifier Open-Loop DC Electrical Characteristics Power supplies at g 5V, TA e 25§ C Ð Contd. Sample and Hold Section Parameter Description Min Typ Max Test Level Units 0.5 1.5 I mV VOS Input Offset Voltage TCVOS Average Offset Voltage Drift 6 V mV/§ C IB Input Bias Current 1 2 I mA IOS Input Offset Current 10 200 I nA TCIOS Average Offset Current Drift nA/§ C VCM Common Mode Input Range gm 0.1 V g 2.5 g 2.8 I V Transconductance (RL e 500X) 5 15 I A/V CMRR Common Mode Rejection Ratio (VCM b2.5V to a 2.5V) 70 90 I dB VIL HOLD Logic Input Low (referenced to Digital GND) I V VIH HOLD Logic Input High (referenced to Digital GND) I V VGND Digital GND Reference Voltage IDROOP Hold Mode Droop Current ICHARGE Charge Current Available to CHOLD g 5.5 VO Output Voltage Swing (RL e 10kX) IO Output Current Swing (RL e 0X) 0.8 2.0 (Vb) (V a ) b 4.0 I V 70 I nA g 8.5 I mA g3 g 3.5 I V g 4.5 g 5.5 I mA 10 Closed-Loop AC Electrical Characteristics Power supplies at g 5V, TA e 25§ C, RF e RG e 750X, RL e 150X, CL e 5 pF, CINb(parasitic) e 1.8 pF Parameter Description Min Typ Max Test Levels Units BW, b3 dB b 3 dB Small-Signal Bandwidth 300 V MHz BW, g 0.1 dB 0.1 dB Flatness Bandwidth 50 V MHz Peaking Frequency Response Peaking 0 V dB SR Slew rate, VOUT between b2V and a 2V 1500 V V/ms dG Differential Gain Error, Voffset between b714 mV and a 714 mV 0.04 V % di Differential Phase Error, Voffset between b714 mV and a 714 mV 0.02 V § 3 TD is 1.5in Video Amplifier Section EL4093C 300 MHz DC-Restored Video Amplifier Closed-Loop AC Electrical Characteristics Power supplies at g 5V, TA e 25§ C, RF e RG e 750X, RL e 150X, CL e 5 pF, CHOLD e 2.2 nF Parameter Description Min Typ Max Test Levels Units DISTEP Change in Sample to Hold Output Current Due to Hold Step 0.1 V mA DTSH Sample to Hold Delay Time 15 V ns DTHS Hold to Sample Delay Time 40 V ns TAC Settling Time to 1% (DC Restored Amplifier Output) Video Amplifier Input from 0 to 1V 2.2 V ms Typical Application 44093 – 2 4 TD is 1.2in Sample and Hold Section EL4093C 300 MHz DC-Restored Video Amplifier Typical Performance Curves Non-inverting Frequency Response (Gain) Non-inverting Frequency Response (Phase) 44093 – 4 Inverting Frequency Response (Gain) 44093 – 5 Inverting Frequency Response (Phase) 44093 – 7 Frequency Response for Various RF and RG Frequency Response for Various RL 44093 – 6 Frequency Response for Various CL 44093 – 8 44093 – 9 3 dB Bandwidth vs Temperature (Video Amp) Frequency Response for Various CIN 44093 – 12 44093 – 10 44093 – 11 5 EL4093C 300 MHz DC-Restored Video Amplifier Typical Performance Curves Ð Contd. Peaking vs Temperature (Video Amp) Output Voltage Swing vs Frequency 44093 – 13 2nd and 3rd Harmonic Distortion vs Frequency 44093 – 14 Voltage and Current Noise vs Frequency 44093 – 17 44093 – 16 Input Offset Voltage vs Die Temperature (Video Amp, 3 Sample) 44093 – 15 Supply Current vs Temperature Input Bias Current vs Temperature (Video Amp) 44093 – 18 44093 – 19 6 Transimpedance vs Temperature (Video Amp) 44093 – 20 EL4093C 300 MHz DC-Restored Video Amplifier Typical Performance Curves Ð Contd. Input Offset Voltage vs Die Temperature (Sample & Hold, 3 Samples) Input Bias Current vs Die Temperature (Sample & Hold) 44093 – 21 Transconductance vs Temperature (Sample & Hold) 44093 – 22 Transconductance vs Die Temperature (Sample & Hold) 44093 – 23 Output Current Swing vs Temperature (Sample & Hold) 44093 – 25 44093 – 38 Droop Current vs Temperature (Sample & Hold) Charge Current vs Temperature (Sample & Hold) 44093 – 26 Hold Step (DIOUT) vs Temperature 44093 – 27 7 44093 – 28 EL4093C 300 MHz DC-Restored Video Amplifier Typical Performance Curves Ð Contd. Differential Gain and Phase vs DC Input Voltage at 3.58 MHz Differential Gain and Phase vs DC Input Voltage at 3.58 MHz 44093 – 29 Slew Rate vs Die Temperature (Video Amp) 44093 – 30 Small-Signal Step Response Large-Signal Step Response 44093 – 32 Settling Time vs Settling Accuracy (Video Amp) 44093 – 31 44093 – 33 Maximum Power Dissipation vs Ambient Temperature, 16-Pin P-DIP Package 44093 – 35 44093 – 34 8 Maximum Power Dissipation vs Ambient Temperature, 16-Pin SO Package 44093 – 36 EL4093C 300 MHz DC-Restored Video Amplifier Applications Information Product Description The EL4093C is a high speed DC-restore system containing a current feedback amplifier (CFA) and a sample & hold (S/H) amplifier. The CFA offers a wide 3 dB bandwidth of 300 MHz and a slew rate of 1500 V/ms, making it ideal for high speed video applications such as SVGA. The CFA’s excellent differential gain and phase at 3.58 MHz also makes it suitable for NTSC applications. Drawing only 9.5 mA on g 5V supplies, the EL4093C serves as an excellent choice for those applications requiring both low power and high bandwidth. The connection between the CFA and sample & hold (the Autozero interface) has been greatly simplified. The output of the sample & hold is a high impedance current source, allowing direct connection to the CFA inverting input for autozero purposes. In addition, special circuitry within the sample & hold provides a charge current of 8.5 mA in sample mode, resulting in a sample hold current ratio (ratio of charging current to droop current) of approx. 1,000,000. 44093 – 3 Figure 1 The autozero mechanism is typically active for only a short period of each video line. Figure 2 shows a NTSC video signal along with the EL4581C back porch output. The back porch signal is used to drive the HOLD input of the EL4093C, and we see that the EL4093C is in sample mode for only 3.5 ms of each line. It is during this time that the autozero mechanism attempts to drive the CFA output towards the reference voltage, at the same time putting a correction voltage onto the hold capacitor CHOLD. During the rest of the line (60 ms) the EL4093C is in hold mode, but DC correction is maintained by the voltage on CHOLD. Theory of Operation In video applications, DC restoration moves the backporch or black level to a fixed DC reference. The EL4093C uses a CFA in feedback with a sample & hold to provide DC restoration. Figure 1 shows how the two are connected to provide this function; the S/H compares the output of the CFA to a DC reference, and any difference between them causes an output current from the S/H. This ‘‘autozero’’ current is fed to the CFA inverting input, the effect of which is to move the CFA output towards the reference voltage. This autozero mechanism settles when the CFA output is one VOS away from the reference (the VOS here refers to the S/H offset voltage). 44093 – 37 Figure 2 9 EL4093C 300 MHz DC-Restored Video Amplifier Applications Information Ð Contd. conjunction with the feedback and gain resistors) creates a pole in the feedback path of the amplifier. This pole, if low enough in frequency, has the same destabilizing effect as a zero in the forward open-loop response. Hence it is important to minimize the stray capacitance at this node by removing the nearby ground plane. In addition, since the S/H output connects to this node, it is important to minimize the trace capacitance. Good practice here would be to connect the two pins with a short trace directly underneath the chip. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended. Lead lengths should be as short as possible. The power supply pins must be well bypassed to reduce the risk of oscillation. In the EL4093C there are two sets of supply pins: V a 1/V b 1 provide power for the CFA, and V a 2/V b 2 are for the S/H amplifier. Good performance can be achieved using only one set of bypass capacitors, although they must be close to the V a 1/V-1 pins since that is where the high frequency currents flow. The combination of a 4.7 mF tantalum capacitor in parallel with a 0.01 mF capacitor has been shown to work well. Chip capacitors are recommended for the 0.01 mF bypass to minimize lead inductance. Feedback Resistor Values The EL4093C has been optimized for a gain of a 2 with RF e 750X. This value of feedback resistor gives a 3 dB bandwidth of 300 MHz at a gain of a 2 driving a 150X load. Since the amplifier inside the EL4093C uses current mode feedback, it is possible to change the value of RF to adjust the bandwidth. Shown in the table below are optimum feedback resistor values for different closed loop gains. For good AC performance, parasitic capacitance should be kept to a minimum, especially at the CFA inverting input. Ground plane construction should be used, but it should be removed from the area near the inverting input to minimize any stray capacitance at that node. Chip resistors are recommended for RF and RG, and use of sockets should be avoided if possible. Sockets add parasitic inductance and capacitance which will result in some additional peaking and overshoot. Gain Optimum RF BW (MHz) Peaking (dB) a1 910 314 0.2 a2 750 300 0 a5 470 294 0.2 b1 680 300 0 Autozero Interface If the CFA is configured for non-inverting gain, then one should also pay attention to the trace leading to the a input. The inductance of a long trace ( l 3’’) can form a resonant network with the amplifier input, resulting in high frequency oscillations around 700 MHz. In such cases a 50X – 100X series resistor placed close to the a input would isolate this inductance and damp out the resonance. The autozero interface refers to the connection between the S/H output and the CFA inverting input. This interface has been greatly simplified compared to that of the EL2090C, in that the S/H output is a high impedance current source. The S/H output can be connected directly to the inverting input, and its high impedance greatly reduces the interaction between the sample & hold and the gain setting resistors. Another virtue of this interface is better gain linearity as the autozero current changes. For example, at an autozero current of 0 mA the output impedance is about 5 MX, dropping to 1 MX as the autozero current increases to 3 mA. Using RF e RG e 750X, the closed loop gain changes only by 0.025% in this interval. Capacitance at the Inverting Input Any manufacturer’s high-speed voltage or current feedback amplifier can be affected by stray capacitance at the inverting input. For inverting gains this parasitic capacitance has little effect because the inverting input is a virtual ground, but for non-inverting gains this capacitance (in 10 EL4093C 300 MHz DC-Restored Video Amplifier Applications Information Ð Contd. As another example, consider the case where we are restoring to a reference voltage of a 0.75V. Using the same reasoning as above, a current IRF e (VDC b 0.75V)/RF must flow through RF, and a current IRG e VDC/RG must go into RG. Again, our boundary condition is that IRF a IRG s g 5.5 mA, and we can solve for the allowable VDC values using the following: Autozero Range The autozero range is defined as the difference between the input DC level and the reference voltage to restore to. The size of this range is a function of the gain setting resistors used and the S/H output current swing. For a gain of a 2 the optimum feedback resistor is 750X, and the available S/H output current is g 5.5 mA minimum. To determine the autozero range for this case, we refer to Figure 3 below. g 5.5 mA e VDC b 0.75V V a DC 750X 750X Hence VDC must be between a 2.4V to b 1.7V. This example illustrates that when the reference changes, the autozero range also changes. In general, the user should determine the autozero range for his/her application, and ensure that the input signal is within this range during the autozero period. Autozero Loop Bandwidth The gain-bandwidth product (GBWP) of the autozero loop is determined by the size of the hold capacitor, the value of RF, and the transconductances (gm’s) of the S/H amplifier. To begin, the S/H amplifier is modeled as in Figure 4 below. First, the input stage transconductance is represented by gm1, with the compensation capacitor given by CHOLD. This stage’s GBWP is thus gm1/(2q # CHOLD) e 1/(2q # (350X)(2.2 nF)) e 207 kHz. Next, since the S/H has a current output, its output stage can be modeled as a transconductance gm2, in this case having a value of 1/(500X). The current from gm2 then flows through the I to V converter made up of the CFA and RF to produce a voltage gain. Thus the GBWP of the overall loop is given by: 4093 – 39 Figure 3 Suppose that the input DC level is a VDC, and that the reference voltage is 0V. We know that in feedback, the following two conditions will exist on the CFA: first, its output will be equal to 0V (due to autozero), and second, its VIN b voltage is equal to the VIN a voltage (i.e. VIN b e a VDC). So we have a potential difference of a VDC across both RF and RG, resulting in a current IRF e IRG e VDC/750X that must flow into each of them. This current IAZ e (IRF a IRG) must come from the S/H output. Since the maximum that IAZ can be is 5.5 mA, we can solve for VDC using the following: IAZ e g 5.5 mA e 2 # VDC 750X GBWP e J and see that VDC e g 2V. This range can easily accommodate most video signals. 11 gm1 (gm2 # RF) 2q # CHOLD EL4093C 300 MHz DC-Restored Video Amplifier Applications Information Ð Contd. 4093 – 40 Figure 4 With RF e 750X, a GBWP of 310 kHz is obtained. Note however that this is the small signal GBWP. As mentioned earlier, the sample and hold has special boost circuits built in which provides g 8.5 mA of charge current during full slew. These boost circuits turn on when the S/H input differential voltage exceeds g 50 mV. When the boosters are turned on, gm1 greatly increases and the circuit becomes nonlinear. Thus some stability issues are associated with the boosters, and they will be addressed in a later section. For CHOLD e 2.2 nF and gm2 e 1/(500X), DISTEP has a typical value of 100 nA. This change in S/H output current flows through RF, shifting the CFA output voltage. However, as we shall soon see, this shift is negligible. Assuming RF e 750X, DISTEP is impressed across RF to give (750X)(100 nA) e 0.08 mV of change at the CFA output. Droop Rate When the S/H amplifier is in HOLD mode, there is a small current that leaks from the switch into the hold capacitor. This quantity is termed the droop current, and is typically 10 nA in the EL4093. This droop current produces a ramp in the hold capacitor voltage, which in turn produces a similar effect at the CFA output. The Droop Rate at the CFA output can be found using the equation below: Charge Injection and Hold Step Charge injection refers to the charge transferred to the hold capacitor when switching to the HOLD mode. The charge should ideally be 0, but due to stray capacitive coupling and other effects, is typically 0.1 pC in the EL4093. This charge changes the hold capacitor voltage by DV e DQ/ CHOLD, and this DV is multiplied by the output stage transconductance (gm2) to produce a change in S/H output current. This last quantity is listed as the spec DISTEP, and is calculated using the following: DISTEP e #C DQ HOLD IDROOP Droop e (gm2 # RF) CHOLD Assuming RF e 750X and CHOLD e 2.2 nF, the drift in the CFA output due to droop current is about 7 mV/ms. Recall that in NTSC applications, there is about 60 ms between autozero periods. Thus there is 7 mV/ms)(60 ms) e 0.4 mV, or less than 0.1 IRE, of drift over each NTSC scan line. This drift is negligible in most applications. J # gm2 12 EL4093C 300 MHz DC-Restored Video Amplifier Applications Information Ð Contd. In the other direction, decreasing CHOLD would increase the droop and hold step but shorten the acquisition time. There is, however, a caveat to reducing CHOLD: too small a CHOLD would cause the autozero loop to oscillate. The reason is that when the S/H boost circuit turns on, the input stage gm increases drastically and the circuit becomes nonlinear. A sufficiently large CHOLD must be used to suppress the non-linearity and force the loop to settle. For example, it has been found that a CHOLD of 470 pF results in 1 VP-P oscillation around 10 MHz at the CFA output. Choice of Hold Capacitor The EL4093 has been designed to work with a hold capacitor of 2.2 nF. With this value of CHOLD, the droop rate and hold step are negligibly small for most applications. In addition, with the special boost circuits inside the S/H, fast acquisition is possible even using a hold capacitor of this size. Figure 5 below shows the input and output of the DC-restored amplifier while the S/H is in sample mode. Applying a a 1V step to the non-inverting input of the CFA, the output of the CFA jumps to a 2V. The S/H, however, then tries to autozero the system by driving the CFA output back to the reference voltage. Since the input differential across the S/H is initially a 2V, the boost circuits turn on and supply 8.5 mA of charge current to the hold capacitor. The boost circuit remains on until the CFA output has come to within 50 mV of the reference. Note that this event took only 320 ns; settling to within 1% of the final value takes another 2 ms. Thus for a 1V input step, acquisition takes only one to two NTSC scan lines. The minimum recommended value for CHOLD is 2.2 nF. With this value the loop remains stable over the entire operating temperature range ( b 40§ C to a 85§ C). The greatest instability occurs at low temperatures, where we observe from the performance curves that the S/H gm’s, and hence the GBWP, are at their maximum. If the operating range is restricted to room temperature or above, then 1.5 nF is sufficient to keep the loop stable. At this value of CHOLD the acquisition time reduces to about 1.5 ms. Video Performance and Application Although the EL4093 is intended for high speed video applications such as SVGA, it also offers excellent performance for NTSC, with 0.04% dG and 0.02§ dP at 3.58 MHz. Some application considerations, however, are required for handling NTSC signals. Referring back to Figure 2, recall that typically, the autozero interval lies in the back porch portion of video containing the colorburst pulse. When the S/H compares the video to the reference voltage during this period, the colorburst (40 IREP-P) triggers the S/H boost circuit and prevents the autozero loop from settling. 4093 – 41 Figure 5. Autozero Mechanism Restores Amplifier Output to Ground after a 1V Step at Input A natural question arises as to whether there are other CHOLD values that can be used. In one direction, increasing CHOLD will further reduce the droop and hold step, but lengthen the acquisition time. Since the droop and hold step are already small to begin with, there is no apparent advantage to increasing CHOLD. 13 EL4093C 300 MHz DC-Restored Video Amplifier Applications Information Ð Contd. A remedy for this situation is to attenuate the colorburst before applying it to the S/H input. Figure 6 below shows a 3.58 MHz chroma trap which would notch out the colorburst while preserving the video DC level. 4093 – 43 Figure 7. Caution: Lowpass Filter Does Not Work in NTSC Applications Although we can cancel this pole by introducing a zero, the RC network introduces a time delay between the CFA output and the S/H input. This has undesirable effects in some NTSC applications, as Figure 8 below illustrates. There is only 0.6 ms from the rising edge of sync to the colorburst. If we are autozeroing over the back porch, the autozero period would begin somewhere in this 0.6 ms interval. Since the edge of sync is now delayed by the RC network, autozero begins before the video back porch reaches its final value. Consequently, the autozero loop performs a correction on every line and never settles. 4093 – 42 Figure 6. Colorburst Trap for NTSC Applications One may be tempted to use a RC lowpass filter to suppress the colorburst, as shown in Figure 7 below. This technique, however, poses several problems. First, to obtain enough attenuation, we need to set the pole frequency 10 to 20 times lower than 3.58 MHz. This pole, being close to the auto zero loop pole, would destabilize the system and cause the loop to oscillate. 4093 – 44 Figure 8. Lowpass Filter Delays Input to Sample and Hold 14 EL4093C 300 MHz DC-Restored Video Amplifier Applications Information Ð Contd. If the video does not contain any AC components during the autozero level (e.g. RGB video), then the above networks are not needed and the CFA output can be connected directly to the S/H input. VOUTMAX e Maximum Output Voltage of RL e Load Resistance Application The EL4093 current feedback amplifier has an absolute maximum of g 30 mA output current drive. This is slightly more than the current required to drive g 2V into 75X. To see how much the junction temperature is raised in this worst case, we refer to the equations below: For the EL4093, the maximum supply current is 11.5 mA on VS e g 5V. Assume that in the worst case, the CFA output swings g 2V into 75X. Since the S/H has a current output, we assume that it is at maximum current swing ( g 5.5 mA) but at a mid-rail output voltage (0V). With the above assumptions, PDMAX for the EL4093 is 223 mW, and using the thermal resistance of a narrow SO package (120§ C/W), this yields a temperature increase of 27§ C. Since the maximum ambient temperature is 85§ C, the resulting junction temperature of 112§ C is still below the maximum. TJMAX e TMAX a (iJA # PDMAX) where: TMAX e Maximum Ambient Temperature e Thermal Resistance of the Package iJA PDMAX e Maximum Power Dissipation of the CFA and S/H amplifier in the Package Please note that there is no short-circuit protection on the EL4093 CFA output, and hence the minimum short circuit current (60 mA) is greater than the absolute maximum output current. Maintaining the EL4093 in this state for more than a few seconds may cause the part to exceed TJMAX, in addition to metal migration problems. PDMAX for either the CFA or the S/H amplifier can be calculated as follows: (2 # VS # ISMAX) a (VS b VOUTMAX) e Supply Voltage e Maximum Supply Current of Amplifier Power Dissipation PDMAX e where: VS ISMAX # (VOUTMAX/RL) 15 EL4093C EL4093C 300 MHz DC-Restored Video Amplifier General Disclaimer Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. January 1996 Rev B WARNING Ð Life Support Policy Elantec, Inc. products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec, Inc. Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death. Users contemplating application of Elantec, Inc. products in Life Support Systems are requested to contact Elantec, Inc. factory headquarters to establish suitable terms & conditions for these applications. Elantec, Inc.’s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages. Elantec, Inc. 1996 Tarob Court Milpitas, CA 95035 Telephone: (408) 945-1323 (800) 333-6314 Fax: (408) 945-9305 European Office: 44-71-482-4596 16 Printed in U.S.A.