Quad 4ns High Speed Comparators Features General Description • • • • • • The EL5485C and EL5486C comparators are designed for operation in single supply and dual supply applications with 5V to 12V between VS+ and VS-. For single supplies, the inputs can operate from 0.1V below ground for use in ground sensing applications. • • • • • 4ns typ. propagation delay 5V to 12V input supply +2.7V to +5V output supply True-to-ground input Rail-to-rail outputs Separate analog and digital supplies Active low latch Single (EL5185C) available Dual (EL5285C) available Window available (EL5287C) Pin-compatible 8ns family available (EL5x81C, EL5283C & EL5482C) Applications • • • • • • The output side of the comparators can be supplied from a single supply of 2.7V to 5V. The rail-to-rail output swing enables direct connection of the comparator to both CMOS and TTL logic circuits. The latch input of the EL5485C and EL5486C can be used to hold the comparator output value by applying a low logic level to the pin. The EL5485C is available in the 16-pin SO package and the EL5486C in the 24-pin QSOP package. Both are specified for operation over the full -40°C to +85°C temperature range. Also available are single (EL5185C), dual (EL5285C), and window comparator (EL5287C) versions. Pin Configurations Threshold detection High speed sampling circuits High speed triggers Line receivers PWM circuits High speed V/F converters Package INA- 1 24 IND- INA+ 2 23 IND+ NC 3 GND 4 Ordering Information Part No Tape & Reel Outline # EL5485CS 16-Pin SO - MDP0027 EL5485CS-T7 16-Pin SO 7” MDP0027 EL5485CS-T13 16-Pin SO 13” MDP0027 EL5486CU 24-Pin QSOP - MDP0040 EL5486CU-T13 24-Pin QSOP 13” MDP0040 INA- 1 INA+ 2 GND 3 + - - + 22 NC + - - + 21 VS+ 16 IND- LATCHA 5 20 LATCHD 15 IND+ OUTA 6 19 OUTD 14 VS+ OUTB 7 18 OUTC OUTA 4 13 OUTD LATCHB 8 OUTB 5 12 OUTC VS- 9 11 VSD NC 10 INB+ 7 10 INC+ INB+ 11 14 INC+ INB- 8 9 INC- INB- 12 13 INC- VS- 6 - - + 17 LATCHC + - - + 16 VSD 15 NC EL5486CU (24-Pin QSOP) Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a “controlled document”. Current revisions, if any, to these specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation. September 7, 2001 + EL5485CS (16-Pin SO) © 2001 Elantec Semiconductor, Inc. EL5485C, EL5486C - Preliminary EL5485C, EL5486C - Preliminary EL5485C, EL5486C - Preliminary EL5485C, EL5486C - Preliminary Quad 4ns High Speed Comparators Absolute Maximum Ratings (T A = 25°C) Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied Analog Supply Voltage (VS+ to VS-) +12.6V Digital Supply Voltage (VSD to GND) +7V Differential Input Voltage [(VS-) -0.2V] to [(VS+) +0.2V] Common-Mode Input Voltage [(VS-) -0.2V] to [(VS+) +0.2V] Latch Input Voltage Storage Temperature Range Ambient operating Temperature Operating Junction Temperature Power Dissipation ESD Voltage -0.2V to [(VSD) +0.2V] -65°C to +150°C -40°C to +85°C 125°C TBDmW 2kV Important Note: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA. Electrical Characteristics VS = ±5V, VSD = 5V, RL = 2.3kΩ, CL = 15pF, TA = 25°C, unless otherwise specified. Parameter Description Condition Min Typ Max Unit 1 4 mV -10 -5 Input VOS Input Offset Voltage IB Input Bias Current CIN Input Capacitance IOS Input Offset Current VCM = 0V, VO = 2.5V µA 5 VCM = 0V, VO = 2.5V VCM Input Voltage Range CMRR Common-mode Rejection Ratio -5V < V CM < +2.75V, VO = 2.5V VOH Output High Voltage VIN > 250mV VOL Output Low Voltage VIN > 2 50mV -2.5 0.5 (VS-) - 0.1 -65 pF 2.5 (VS+) - 2.25 -90 µA V dB Output VSD - 0.6 VSD - 0.4 V GND + 0.25 GND + 0.5 V Dynamic Performance tpd+ Latch Disable to High Delay VIN = 1VP-P, VOD = 50mV 4 6 ns tpd- Latch Disable to Low Delay VIN = 1VP-P, VOD = 50mV 4 6 ns IS + Positive Analog Supply Current (per comparator) 12 13 mA IS - Negative Analog Supply Current (per comparator) 7.5 8.5 mA ISD Digital Supply Current (per comparator) All inputs high 5.5 6.5 mA (per comparator) All inputs low 0.9 1.2 mA Supply PSRR Power Supply Rejection Ratio -60 -80 dB Latch VLH Latch Input Voltage High VLL Latch Input Voltage Low 2.0 ILH Latch Input Current High VLH = 3.0V -30 -18 µA ILL Latch Input Current Low VLL = 0.3V -30 -24 µA td+ Positive Going Delay Time VOD = 5mV, CL = 15pF, IO = 2mA 4 ns td- Negative Going Delay Time VOD = 5mV, CL = 15pF, IO = 2mA 4 ns ts Minimum Setup Time 2 ns 0.8 V V th Minimum Hold Time 1 ns tpw(D) Minimum Latch Disable Pulse Width 5 ns 2 Quad 4ns High Speed Comparators Typical Performance Curves 7.8 Propagation Delay vs Overdrive VIN=5VSTEP 15 VS=±5V VSD=5V RL=2.2k 7.6 TPD- Propagation Delay vs Source Resistance VIN=1VSTEP VS=±5V VSD=5V VOD=50mV RL=2.2k 13 Delay Time (ns) Delay Time (ns) 7.4 7.2 TPD+ 7 11 TPD9 TPD+ 6.8 7 6.6 6.4 0.2 5 0.6 1 1.4 1.8 2.2 2.6 0.4 0 0.8 10 Supply Current vs Supply Voltage (per comparator) VIN=50mV RL=2.2k 1.6 2 Output High Voltage vs Temperature 4.832 4.83 IS+ 8 1.2 Source Resistance (kΩ) VOD (V) VOH (V) IS (mA) 4.828 6 I S- 4 4.826 4.824 4.822 2 0 4.82 0 1 2 3 4 5 4.818 -50 6 -30 -10 10 30 50 70 90 50 70 90 Temperature (°C) ±VS (V) Offset Voltage vs Temperature Input Bias Current vs Temperature 3 8 7 2.5 6 5 IB (µA) VOS (mV) 2 1.5 4 3 1 2 0.5 0 -50 1 -30 -10 10 30 50 70 0 -50 90 Temperature (°C) -30 -10 10 30 Temperature (°C) 3 EL5485C, EL5486C - Preliminary EL5485C, EL5486C - Preliminary Quad 4ns High Speed Comparators Typical Performance Curves Output Low Voltage vs Temperature 0.285 12 Supply Current (mA) VOL (V) Supply Current vs Temperature (per comparator) 11 0.275 0.265 0.255 0.245 I S+ 10 9 8 IS- 7 0.235 -50 -30 -10 10 30 50 70 6 -50 90 -30 -10 Temperature (°C) Propagation Delay vs Supply Voltage 25 VSD=VS+ VOD=50mV RL=2.2k 6.6 30 50 70 90 Digital Supply Current vs Switching Frequency (per comparator) VS=±5V TA=25°C 20 6.4 6.2 ISD (mA) Delay Time (ns) 10 Temperature (°C) 6.8 TPD- 15 VSD=5V 10 VSD=3V 6 5.8 5.6 5 TPD+ 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 0 6 0 10 20 ±VS (V) Propagation Delay vs Overdrive VIN=1VSTEP 8 VS=±5V VSD=5V RL=2.2k 6 5.9 5.8 40 50 Propagation Delay vs Overdrive VIN=3VSTEP VS=±5V VSD=5V RL=2.2k 7.5 TPD- 5.7 5.6 5.5 TPD- 7 6.5 TPD+ 6 TPD+ 5.4 5.5 5.3 5.2 50 30 Frequency (MHz) Delay Time (ns) 6.1 Delay Time (ns) EL5485C, EL5486C - Preliminary EL5485C, EL5486C - Preliminary 5 0.2 100 150 200 250 300 350 400 450 500 550 600 VOD (mV) 0.4 0.6 0.8 1 1.2 VOD (mV) 4 1.4 1.6 1.8 2 Quad 4ns High Speed Comparators Typical Performance Curves Propagation Delay vs Load Capacitance VIN=1VSTEP VS=±5V VSD=5V VOD=50mV RL=2.2k 8.5 8 Delay Time (ns) Power Dissipation vs Ambient Temperature 1.4 1.2 7.5 Power Dissipation (W) 9 TPD- 7 6.5 TPD+ 6 1087mW 1 909mW 0.8 QS OP 24 SO 16 θ 0.6 11 5 °C /W JA = 0.4 11 0° C/ W 0.2 5.5 5 0 0 10 20 30 40 50 60 70 80 90 100 0 CLOAD (pF) 25 50 75 85 100 Ambient Temperature (°C) Output with 50MHz Input VIN=3VP-P Output with 50MHz Input VIN=1VP-P Output (5ns/div, 2V/div) Output (5ns/div, 2V/div) Input (5ns/div, 0.5nV/div) Input (5ns/div, 2V/div) 5 125 150 EL5485C, EL5486C - Preliminary EL5485C, EL5486C - Preliminary EL5485C, EL5486C - Preliminary EL5485C, EL5486C - Preliminary Quad 4ns High Speed Comparators Timing Diagram Compare Compare Latch Enable Input 1.4V Latch Latch Differential Input Voltage ts Latch th tpw(D) VIN VOS VOD tpd- td+ Comparator Output 2.4V Definition of Terms Term Definition VOS Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output VIN Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications VOD Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications tpd+ Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS logic threshold of an output low to high transition tpd- Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS logic threshold of an output high to low transition td+ Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high transition to the point of the output crossing CMOS threshold in a low to high transition td- Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high transition to the point of the output crossing CMOS threshold in a high to low transition ts Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be present in order to be acquired and held at the outputs th Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged in order to be acquired and held at the output tpw (D) Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an input signal change 6 Quad 4ns High Speed Comparators Pin Descriptions EL5485C 16-Pin SO (0.150") EL5486C 24-Pin QSOP Pin Name 1 1 INA- Function Equivalent Circuit Negative input, channel A VS+ IN- IN+ VSCircuit 1 2 3 2 INA+ 3,10,15,22 NC 4 GND 5 LATCHA Positive input, channel A (Reference circuit 1) Not Connected Digital ground Latch input, channel A VS+ VSD LATCH VSCircuit 2 4 6 OUTA Output, channel A VSD VS+ OUT V SCircuit 3 5 7 OUTB 8 LATCHB Output, channel B (Reference circuit 3) Latch input, channel B 6 9 VS- (Reference circuit 2) 7 11 INB+ Positive input, channel B (Reference circuit 1) 8 12 INB- Negative input, channel B (Reference circuit 1) 9 13 INC- Negative input, channel C (Reference circuit 1) 10 14 INC+ Positive input, channel C (Reference circuit 1) 11 16 VSD Digital supply voltage Negative supply voltage 17 LATCHC Latch input, channel C (Reference circuit 2) 12 18 OUTC Output, channel C (Reference circuit 3) 13 19 OUTD Output, channel D (Reference circuit 3) 20 LATCHD Latch input, channel D (Reference circuit 2) 7 EL5485C, EL5486C - Preliminary EL5485C, EL5486C - Preliminary EL5485C, EL5486C - Preliminary EL5485C, EL5486C - Preliminary Quad 4ns High Speed Comparators Pin Descriptions EL5485C 16-Pin SO (0.150") EL5486C 24-Pin QSOP Pin Name 14 21 VS+ Positive supply voltage 15 23 IND+ Positive input, channel D (Reference circuit 1) 16 24 IND- Negative input, channel D (Reference circuit 1) Function Equivalent Circuit 8 Quad 4ns High Speed Comparators Applications Information Power Supplies and Circuit Layout imum slew rate requirements. In some applications, it may be helpful to apply some positive feedback (hysteresis) between the output and the positive input. The hysteresis effectively causes one comparator's input voltage to move quickly past the other, thus taking the input out of the region where oscillation occurs. For the EL5485C and EL5486C, the propagation delay increases when the input slew rate increases for low overdrive voltages. With high overdrive voltages, the propagation delay does not change much with the input slew rate. The EL5485C and EL5486C comparators operate with single and dual supply with 5V to 12V between VS+ and VS-. The output side of the comparator is supplied by a single supply from 2.7V to 5V. The rail to rail output swing enables direct connection of the comparator to both CMOS and TTL logic circuits. As with many high speed devices, the supplies must be well bypassed. Elantec recommends a 4.7µF tantalum in parallel with a 0.1µF ceramic. These should be placed as close as possible to the supply pins. Keep all leads short to reduce stray capacitance and lead inductance. This will also minimize unwanted parasitic feedback around the comparator. The device should be soldered directly to the PC board instead of using a socket. Use a PC board with a good, unbroken low inductance ground plane. Good ground plane construction techniques enhance stability of the comparators. Latch Pin Dynamics The EL5486C contains a “transparent” latch for each channel. The latch pin is designed to be driven with either a TTL or CMOS output. When the latch is connected to a logic high level or left floating, the comparator is transparent and immediately responds to the changes at the input terminals. When the latch is switched to a logic low level, the comparator output remains latched to its value just before the latch’s highto-low transition. To guarantee data retention, the input signal must remain the same state at least 1ns (hold time) after the latch goes low and at least 2ns (setup time) before the latch goes low. When the latch goes high, the new data will appear at the output in approximately 6ns (latch propagation delay). The EL5485C does not have latch inputs. Input Voltage Considerations The EL5485C and EL5486C’s input range is specified from 0.1V below VS- to 2.25V below VS+. The criterion for the input limit is that the output still responds correctly to a small differential input signal. The differential input stage is a pair of PNP transistors, therefore, the input bias current flows out of the device. When either input signal falls below the negative input voltage limit, the parasitic PN junction formed by the substrate and the base of the PNP will turn on, resulting in a significant increase of input bias current. If one of the inputs goes above the positive input voltage limit, the output will still maintain the correct logic level as long as the other input stays within the input range. However, the propagation delay will increase. When both inputs are outside the input voltage range, the output becomes unpredictable. Large differential voltages greater than the supply voltage should be avoided to prevent damages to the input stage. Hysteresis Hysteresis can be added externally. The following two methods can be used to add hysteresis. Inverting comparator with hysteresis: VREF R3 R2 R1 VIN + - Input Slew Rate Most high speed comparators oscillate when the voltage of one of the inputs is close to or equal to the voltage on the other input due to noise or undesirable feedback. For clean output waveform, the input must meet certain min- R3 adds a portion of the output to the threshold set by R1 and R2 . The calculation of the resistor values are as follows: 9 EL5485C, EL5486C - Preliminary EL5485C, EL5486C - Preliminary EL5485C, EL5486C - Preliminary EL5485C, EL5486C - Preliminary Quad 4ns High Speed Comparators The above two methods will generate hysteresis of up to a few hundred millivolts. Beyond that, the impedance of R3 is low enough to affect the bias string and adjustment of R1 may be required. Select the threshold voltage VTH and calculate R1 and R2. The current through R1/R2 bias string must be many times greater than the input bias current of the comparator: R1 V T H = V REF × ------------------R +R 1 Power Dissipation 2 When switching at high speeds, the comparator's drive capability is limited by the rise in junction temperature caused by the internal power dissipation. For reliable operation, the junction temperature must be kept below TJMAX (125°C). Let the hysteresis be VH, and calculate R3: VO R 3 = ------- × ( R 1 || R 2 ) VH An approximate equation for the device power dissipation is as follows. Assume the power dissipation in the load is very small: where: VO=VSD-0.8V (swing of the output) Recalculate R2 to maintain the same value of VTH: P DISS = ( V S × I S + V SD × I SD ) V TH V T H – 0.5V SD R 2 1 = ( V REF – V T H ) ÷ ----------+ ------------------------------------- R3 R1 where: VS is the analog supply voltage from VS+ to VS- Non inverting comparator with hysteresis: IS is the analog quiescent supply current per comparator R3 VIN R1 VREF VSD is the digital supply voltage from VSD to ground + - ISD is the digital supply current per comparator ISD strongly depends on the input switching frequency. Please refer to the performance curve to choose the input driving frequency. Having obtained the power dissipation, the maximum junction temperature can be determined as follows: R3 adds a portion of the output to the positive input. Note that the current through R3 should be much greater than the input bias current in order to minimize errors. The calculation of the resistor values as follows: T JMAX = T MAX + Θ JA × P DISS Pick the value of R1. R1 should be small (less than 1kΩ) in order to minimize the propagation delay time. where: Choose the hysteresis VH and calculate R3: TMAX is the maximum ambient temperature R R 3 = ( V SD – 0.8 ) × -------1VH θJA is the thermal resistance of the package Threshold Detector Check the current through R3 and make sure that it is much greater than the input bias current as follows: The inverting input is connected to a reference voltage and the non-inverting input is connected to the input. As the input passes the VREF threshold, the comparator's 0.5VSD – V REF I = --------------------------------------R3 10 Quad 4ns High Speed Comparators output changes state. The non-inverting and inverting inputs may be reversed. VIN VREF + - back to the non-inverting input. The circuit will operate with most AT-cut crystal from 1MHz to 8MHz over a 2V to 7V supply range. The output duty cycle for this circuit is roughly 50% at 5V VCC, but it is affected by the tolerances of the resistors. The duty cycle can be adjusted by changing VCC value. VOUT 5V Crystal Oscillator A simple crystal oscillator using one comparator of an EL5485C and EL5486C is shown below. The resistors R1 and R2 set the bias point at the comparator's noninverting input. Resistors R3, R4, and C1 set the inverting input node at an appropriate DC average voltage based on the output. The crystal's path provides resonant positive feedback and stable oscillation occurs. Although the EL5485C and EL5486C will give the correct logic output when an input is outside the common mode range, additional delays may occur when it is so operated. Therefore, the DC bias voltages at the inputs are set about 500mV below the center of the common mode range and the 200Ω resistor attenuates the feed- 11 200Ω R1 5kΩ R2 1.5kΩ + - 1MHz to 8MHz VOUT R3 C1 R4 0.01µF 2kΩ 2kΩ EL5485C, EL5486C - Preliminary EL5485C, EL5486C - Preliminary EL5485C, EL5486C - Preliminary EL5485C, EL5486C - Preliminary Quad 4ns High Speed Comparators General Disclaimer Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. September 7, 2001 WARNING - Life Support Policy Elantec, Inc. products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec, Inc. Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death. Users contemplating application of Elantec, Inc. Products in Life Support Systems are requested to contact Elantec, Inc. factory headquarters to establish suitable terms & conditions for these applications. Elantec, Inc.’s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages. 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