SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 FEATURES D 16-Bit Resolution D 14-Bit Linearity D Resolution/Speed Trade-Off: D D D D D D D D D 10-Bit Effective Resolution with 10µs Signal Delay (12-Bit with 19µs) ±2.5V Input Range at 2.5V Internal Reference Voltage: 2% Gain Error: 0.5% Four Independent Delta-Sigma Modulators Four Input Reference Buffers Onboard 20MHz Oscillator Selectable Internal or External Clock Operating Temperature Range: −40°C to +85°C QFN-32 (5x5) Package APPLICATIONS D Motor Control D Current Measurement D Industrial Process Control D Instrumentation D Smart Transmitters D Portable Instruments D Weight Scales D Pressure Transducers DESCRIPTION The ADS1204 is a four-channel, high-performance device, with four delta-sigma (∆Σ) modulators with 100dB dynamic range, operating from a single +5V supply. The differential inputs are ideal for direct connection to transducers in an industrial environment. With the appropriate digital filter and modulator rate, the device can be used to achieve 16-bit analog-to-digital (A/D) conversion with no missing code. Effective resolution of 12 bits can be obtained with a digital filter data rate of 160kHz at a modulator rate of 10MHz. The ADS1204 is designed for use in medium- to high-resolution measurement applications including current measurements, smart transmitters, industrial process control, weight scales, chromatography, and portable instrumentation. It is available in a QFN-32 (5x5) package. AV DD CH A+ CH A− 2nd−Order ∆Σ Modulator BV DD OUT A Output Interface Circuit REFIN A OUT B OUT C OUT D CLKOUT CH B+ CH B− 2nd−Order ∆Σ Modulator REFIN B Divider CH C+ CH C− 2nd−Order ∆Σ Modulator Clock Select REFIN C CH D+ CH D− 2nd−Order ∆Σ Modulator CLKSEL EN RC Oscillator 20MHz REFIN D REFOUT Out CLKIN Reference Voltage 2.5V AGND BGND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2003−2004, Texas Instruments Incorporated !"#$ " % & % '(& ) & &% '&%& ' * % "+ # ,-) & '& &- & % ') www.ti.com www.ti.com SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR (LSB) MAXIMUM GAIN ERROR (%) PACKAGELEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ADS1204 ±3 ±0.5 QFN-32 RHB −40°C to +85°C ADS1204I ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS1204IRHBT Tape and Reel, 250 ADS1204IRHBR Tape and Reel, 3000 (1) For the most current specification and package information, refer to our web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) ADS1204 UNIT Supply Voltage, AVDD to AGND −0.3 to 6 V Supply Voltage, BVDD to BGND −0.3 to 6 V Analog Input Voltage with Respect to AGND AGND − 0.3 to AVDD + 0.3 V Reference Input Voltage with Respect to AGND AGND − 0.3 to AVDD + 0.3 V Digital Input Voltage with Respect to BGND BGND − 0.3 to BVDD + 0.3 V Ground Voltage Difference, AGND to BGND ±0.3 V Voltage Differences, BVDD to AGND −0.3 to 6 V ±10 mA Input Current to Any Pin Except Supply Power Dissipation See Dissipation Rating Table Operating Virtual Junction Temperature Range, TJ −40 to +150 °C Operating Free-Air Temperature Range, TA −40 to +85 °C Storage Temperature Range, TSTG −65 to +150 °C Lead Temperature (1.6mm or 1/16″ from case for 10s) 260 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS PARAMETER MIN NOM MAX UNIT Supply Voltage, AVDD to AGND 4.75 5 5.25 V Supply Voltage, BVDD to BGND Low-Voltage Levels 2.7 3.6 V 5V Logic Levels 4.5 5 5.5 V 0.5 2.5 2.6 V AVDD ±REFIN V 24 MHz 105 °C Reference Input Voltage Operating Common-Mode Signal 0 Analog Inputs +IN − (−IN) 0 External Clock(1) 16 Operating Junction Temperature Range, TJ −40 (1) With reduced accuracy, clock can go from 1MHz up to 32MHz; see Typical Characteristic curves. 20 V DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C(1) TA = 70°C POWER RATING TA = 85°C POWER RATING QFN-32 (5x5) 2725mW 27.25mW/°C 1499mW 1090mW (1) This is the inverse of the traditional junction-to-ambient thermal resistance (Rq JA). Thermal resistances are not production tested and are for informational purposes only. 2 www.ti.com SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range at −40°C to +85°C, AVDD = 5V, BVDD = 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc3 filter with decimation by 256, unless otherwise noted. PARAMETER Resolution TEST CONDITIONS MIN ADS1204I TYP(1) MAX 16 UNITS Bits DC Accuracy INL Integral linearity error(2) ±1 ±3 ±0.001 ±0.005 6 Integral linearity match DNL Differential nonlinearity(3) VOS Input offset error 0.009 −1.4 Input offset error match TCVOS GERR Input offset error drift Gain error(4) Referenced to VREF Gain error match TCGERR PSRR Gain error drift Power-supply rejection ratio 4.75V < AVDD < 5.25V LSB % FSR LSB % FSR ±1 LSB ±3 mV 2 mV 2 8 µV/°C 0.08 ±0.5 % FSR 0.185 0.5 % FSR 2 ppm/°C 78 dB Analog Input FSR Full-scale differential range (CH x+) − (CH x−); CH x− = 2.5V ±2.5 V Specified differential range (CH x+) − (CH x−); CH x− = 2.5V ±2 V Maximum operating input range(3) 0 Input capacitance Common-mode Input leakage current CLK turned off 3 100 Differential input capacitance Common-mode rejection ratio BW Bandwidth V pF ±1 Differential input resistance CMRR AVDD nA kΩ 2.5 pF At DC 100 dB VIN = ±1.25VPP at 40kHz FS sine wave, −3dB 110 dB 50 MHz Sampling Dynamics CLKIN Internal clock frequency CLKSEL = 1 8 10 12 MHz External clock frequency CLKSEL = 0 1 20 24 MHz −96 −88 dB AC Accuracy VIN = ±2VPP at 5kHz VIN = ±2VPP at 5kHz THD Total harmonic distortion SFDR Spurious-free dynamic range SNR Signal-to-noise ratio SINAD Signal-to-noise + distortion VIN = ±2VPP at 5kHz VIN = ±2VPP at 5kHz Channel-to-channel isolation(3) VIN = ±2VPP at 50kHz ENOB Effective number of bits 92 100 dB 86 89 dB 85 89 dB 14 85 dB 14.5 Bits (1) All typical values are at TA = +25°C. (2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve for CH x+ = −2V to +2V at 2.5V, expressed either as the number of LSBs or as a percent of measured input range (4V). (3) Ensured by design. (4) Maximum values, including temperature drift, are ensured over the full specified temperature range. (5) Applicable for 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V. (6) Applicable for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V. 3 www.ti.com SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating free-air temperature range at −40°C to +85°C, AVDD = 5V, BVDD = 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc3 filter with decimation by 256, unless otherwise noted. PARAMETER Voltage Reference Output VOUT dVOUT/dT Reference voltage output TEST CONDITIONS −40°C to +85°C MIN 2.450 MAX 2.5 2.550 UNITS V ±20 ppm/°C f = 0.1Hz to 10Hz, CL = 10µF 10 µVrms f =10Hz to 10kHz, CL = 10µF 12 µVrms dB Output voltage temperature drift Output voltage noise ADS1204I TYP(1) PSRR Power-supply rejection ratio 60 IOUT ISC Output current 10 µA Short-circuit current 0.5 mA 100 µs Turn-on settling time to 0.1% at CL = 0 Voltage Reference Input VIN Reference voltage input 0.5 Reference input resistance 2.5 2.6 100 Reference input capacitance 5 pF 1 µA BVDD+0.3 0.3×BVDD V ±50 nA Reference input current Digital Inputs(5) Logic family VIH VIL High-level input voltage IIN CI Input current V MΩ CMOS with Schmitt Trigger 0.7×BVDD −0.3 Low-level input voltage VI = BVDD or GND Input capacitance 5 V pF Digital Outputs(5) Logic family VOH VOL High-level output voltage CO CL Output capacitance Low-level output voltage CMOS BVDD = 4.5V, IOH = −100µA BVDD = 4.5V, IOL = +100µA 4.44 V 0.5 5 Load capacitance Data format V pF 30 pF Bit Stream (1) All typical values are at TA = +25°C. (2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve for CH x+ = −2V to +2V at 2.5V, expressed either as the number of LSBs or as a percent of measured input range (4V). (3) Ensured by design. (4) Maximum values, including temperature drift, are ensured over the full specified temperature range. (5) Applicable for 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V. (6) Applicable for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V. 4 www.ti.com SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating free-air temperature range at −40°C to +85°C, AVDD = 5V, BVDD = 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc3 filter with decimation by 256, unless otherwise noted. PARAMETER Digital Inputs(6) MIN TEST CONDITIONS Logic family ADS1204I TYP(1) MAX UNITS LVCMOS VIH VIL High-level input Voltage Low-level input voltage BVDD = 3.6V BVDD = 2.7V IIN CI Input current VI = BVDD or GND 2 −0.3 Input capacitance BVDD+0.3 0.8 V ±50 nA 5 V pF Digital Outputs(6) Logic family LVCMOS VOH VOL High-level output voltage CO CL Output capacitance BVDD = 2.7V, IOH = −100µA BVDD = 2.7V, IOL = +100µA Low-level output voltage BVDD−0.2 V 0.2 5 Load capacitance Data format V pF 30 pF Bit Stream Power Supply AVDD BVDD AIDD BIDD Analog supply voltage Buffer I/O supply voltage Analog operating supply current 4.5 5.5 V Low-voltage levels 2.7 3.6 V 5V logic levels 4.5 5.5 V CLKSEL = 1 22.5 30 mA CLKSEL = 0 22.4 29 mA 4 mA BVDD = 3V, CLKOUT = 10MHz BVDD = 5V, CLKOUT = 10MHz Buffer I/O operating supply current Power dissipation 4 mA CLKSEL = 0 122 145 mW CLKSEL = 1 112.5 150 mW (1) All typical values are at TA = +25°C. (2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve for CH x+ = −2V to +2V at 2.5V, expressed either as the number of LSBs or as a percent of measured input range (4V). (3) Ensured by design. (4) Maximum values, including temperature drift, are ensured over the full specified temperature range. (5) Applicable for 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V. (6) Applicable for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V. EQUIVALENT INPUT CIRCUIT BVDD AVDD R ON 650Ω C(SAMPLE) 1pF AIN DIN Diode Turn−On Voltage: 0.35V AGND Equivalent Analog Input Circuit BGND Equivalent Digital Input Circuit 5 www.ti.com SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 PIN ASSIGNMENTS 25 NC 26 AGND 27 AVDD 28 REFOUT 29 AVDD 30 AGND 31 REFIN B 32 REFIN A QFN PACKAGE (TOP VIEW) CH A+ 1 24 OUT A CH A− 2 23 OUT B CH B+ 3 22 OUT C CH B− 4 21 OUT D CH C− 5 20 CLKOUT CH C+ 6 19 BGND CH D− 7 18 BVDD CH D+ 8 17 CLKIN 15 16 CLKSEL 13 NC AGND 12 AVDD 14 11 AGND AVDD 10 REFIN C REFIN D 9 ADS1204 Terminal Functions TERMINAL TERMINAL NAME NAME NO. I/O CH A+ 1 AI NO. I/O Analog input of channel A: noninverting input CLKIN 17 I External clock input CH A− 2 AI Analog input of channel A: inverting input BVDD 18 P Digital interface power supply; from 2.7V to 5.5V CH B+ CH B− 3 AI Analog input of channel B: noninverting input BGND 19 4 AI Analog input of channel B: inverting input CLKOUT 20 O System clock output CH C− 5 AI Analog input of channel C: inverting input OUT D 21 O Bit stream from channel D modulator CH C+ 6 AI Analog input of channel C: noninverting input OUT C 22 O Bit stream from channel C modulator CH D− 7 AI Analog input of channel D: inverting input OUT B 23 O Bit stream from channel B modulator CH D+ 8 AI Analog input of channel D: noninverting input OUT A 24 O Bit stream from channel A modulator REFIN D 9 AI Reference voltage input of channel D: pin for external reference voltage NC 25 AGND 26 REFIN C 10 AI Reference voltage input of channel C: pin for external reference voltage AVDD 27 P AGND 11 REFOUT 28 AO AVDD 12 AVDD 29 P NC 13 AGND 30 AVDD 14 REFIN B 31 AI AGND 15 Reference voltage input of channel B: pin for external reference voltage CLKSEL 16 REFIN A 32 AI Reference voltage input of channel A: pin for external reference voltage DESCRIPTION Analog ground P Analog power supply; nominal 5V No connection; this pin is left unconnected P Analog power supply; nominal 5V Clock select between internal clock (CLKSEL = 1) or external clock (CLKSEL = 0) NOTE: AI = Analog Input; AO = Analog Output; I = Input; O = Output; P = Power Supply. 6 Interface ground No connection; this pin is left unconnected Analog ground Analog power supply; nominal 5V Reference voltage output: output pin of the internal reference source; nominal 2.5V Analog power supply; nominal 5V Analog ground Analog ground I DESCRIPTION www.ti.com SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION tC1 CLKIN t W1 tC2 tD1 tD2 CLKOUT tD3 tW2 tD4 OUT x Figure 1. ADS1204 Timing Diagram TIMING REQUIREMENTS: 5.0V over recommended operating free-air temperature range at −40°C to +85°C, AVDD = 5V, and BVDD = 5V, unless otherwise noted. PARAMETER MIN MAX UNIT tC1 tW1 CLKIN period 41.6 1000 ns CLKIN high time 10 CLKOUT period using internal oscillator (CLKSEL = 1) 83 tC1 − 10 125 ns tC2 2 × tC1 (tC2/2) − 5 0 (tC2/2) + 5 10 ns 0 10 ns (tC2/4) − 8 tW1 − 3 (tC2/4) + 8 tW1 + 7 ns CLKOUT period using external clock (CLKSEL = 0) tW2 tD1 CLKOUT high time tD2 tD3 CLKOUT falling edge delay after CLKIN rising edge CLKOUT rising edge delay after CLKIN rising edge Data valid delay after rising edge of CLKOUT (CLKSEL = 1) ns ns ns tD4 Data valid delay after rising edge of CLKOUT (CLKSEL = 0) ns : NOTE Applicable for 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V. All input signals are specified with tR = tF = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagram. TIMING REQUIREMENTS: 3.0V over recommended operating free-air temperature range at −40°C to +85°C, AVDD = 5V, and BVDD = 3V, unless otherwise noted. PARAMETER MIN tC1 tW1 CLKIN period tC2 CLKOUT period using internal oscillator (CLKSEL = 1) CLKIN high time CLKOUT period using external clock (CLKSEL = 0) tW2 tD1 CLKOUT high time tD2 tD3 MAX UNIT 41.6 1000 ns 10 tC1 − 10 125 ns 83 2 × tC1 ns ns (tC2/2) + 5 10 ns CLKOUT rising edge delay after CLKIN rising edge (tC2/2) − 5 0 CLKOUT falling edge delay after CLKIN rising edge 0 10 ns ns Data valid delay after rising edge of CLKOUT (CLKSEL = 1) (tC2/4) − 8 (tC2/4) + 8 ns tD4 Data valid delay after rising edge of CLKOUT (CLKSEL = 0) tW1 − 3 tW1 + 7 ns NOTE: Applicable for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V. All input signals are specified with tR = tF = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagram. 7 www.ti.com SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 TYPICAL CHARACTERISTICS AVDD = 5V, BVDD = 3V, CH x+ = +0.5V to +4.5V, CH x− = +2.5V, REFIN = external, CLKSEL = 0, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. INTEGRAL NONLINEARITY vs INPUT SIGNAL (CLKIN = 20MHz) INTEGRAL NONLINEARITY vs INPUT SIGNAL (CLKIN = 32MHz) 1.5 1.5 −40_ C 1.0 1.0 +85_ C +85_C 0.5 +25_ C INL (LSB) 0 −0.5 −0.5 −1.0 −1.0 −1.5 −2.5 −2.0 −1.5 −1.0 −0.5 0 0.5 1.0 1.5 2.0 −1.5 −2.5 −2.0 −1.5 −1.0 −0.5 2.5 Differential Input Voltage (V) 0.00061 0.3 0.00046 CLKIN = 32MHz 1.0 1.5 2.0 2.5 0 −0.1 −0.00015 −0.2 −0.00031 −0.3 −0.00046 1.5 2.0 INL (%) CLKIN = 20MHz 1.5 0.0023 1.2 0.0018 CLKIN = 20MHz 0.00015 INL (LSB) INL (LSB) 0.00031 0.1 −0.4 −2.5 −2.0 −1.5 −1.0 −0.5 0 0.5 1.0 Differential Input Voltage (V) 0.5 INTEGRAL LINEARITY vs TEMPERATURE 0.4 0 0 Differential Input Voltage (V) INTEGRAL LINEARITY MATCH OF CHANNELS vs INPUT SIGNAL 0.2 −40_ C +25_ C 0 0.9 0.0014 0.6 0.0009 CLKIN = 32MHz 0.0005 0.3 −0.00061 2.5 0 −40 −20 OFFSET vs TEMPERATURE 0 20 40 Temperature (_C) 60 80 0 100 OFFSET MATCH vs TEMPERATURE −1.30 0.45 0.44 −1.40 0.43 0.42 Offset (mV) Offset (mV) −1.35 CLKIN = 32MHz −1.45 CLKIN = 20MHz −1.50 CLKIN = 20MHz 0.41 0.40 0.39 CLKIN = 32MHz 0.38 0.37 −1.55 0.36 −1.60 −40 −20 0.35 0 20 40 Temperature (_C) 8 60 80 100 −40 −20 0 20 40 Temperature (_C) 60 80 100 INL (%) INL (LSB) 0.5 www.ti.com SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 TYPICAL CHARACTERISTICS (continued) AVDD = 5V, BVDD = 3V, CH x+ = +0.5V to +4.5V, CH x− = +2.5V, REFIN = external, CLKSEL = 0, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. OFFSET vs POWER SUPPLY REFERENCE VOLTAGE vs TEMPERATURE −1.2 2.530 2.528 −1.3 2.526 2.524 Offset (mV) CLKIN = 20MHz VREF (V) −1.4 −1.5 CLKIN = 32MHz 2.522 2.520 2.518 2.516 −1.6 2.514 2.512 −1.7 2.510 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 −40 −20 0 Power Supply (V) 20 40 GAIN vs TEMPERATURE 0.20 0.4 0.19 Gain (%) Gain (%) 0.2 CLKIN = 20MHz −20 CLKIN = 20MHz 0.17 0.16 20 40 60 80 100 −40 −20 0 20 40 60 Temperature (_C) Temperature (_C) SIGNAL−TO−NOISE RATIO vs TEMPERATURE SIGNAL−TO−NOISE + DISTORTION vs TEMPERATURE 89.5 80 100 80 100 89.2 CLKIN = 32MHz 89.4 89.0 CLKIN = 32MHz 89.3 88.8 89.1 SINAD (dB) 89.2 SNR (dB) 0.18 0.15 0 100 CLKIN = 32MHz CLKIN = 32MHz 0.3 0 −40 80 GAIN MATCH vs TEMPERATURE 0.5 0.1 60 Temperature (_ C) CLKIN = 20MHz 89.0 88.9 88.8 88.6 CLKIN = 20MHz 88.4 88.2 88.0 88.7 87.8 88.6 88.5 −40 −20 87.6 0 20 40 Temperature (_ C) 60 80 100 −40 −20 0 20 40 60 Temperature (_C) 9 www.ti.com SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 TYPICAL CHARACTERISTICS (continued) AVDD = 5V, BVDD = 3V, CH x+ = +0.5V to +4.5V, CH x− = +2.5V, REFIN = external, CLKSEL = 0, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs TEMPERATURE (CLKIN = 20MHz) 103 −101 101 99 −99 99 97 −97 95 −95 SFDR THD −103 −101 −99 THD 97 −97 95 −95 93 −93 91 −91 91 −91 89 −89 89 −87 87 −85 100 85 93 −93 −105 SFDR 4VPP 5kHz 87 85 −40 −20 0 20 40 Temperature (_ C) 60 80 SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (CLKIN = 20MHz) −87 −20 0 20 40 Temperature (_C) 60 80 −85 100 SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (CLKIN = 32MHz) −120 120 −89 4VPP 5kHz −40 THD (dB) 105 −103 SFDR (dB) −105 103 THD (dB) 105 101 SFDR (dB) SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs TEMPERATURE (CLKIN = 32MHz) −120 120 SFDR 90 −100 100 −90 −80 80 70 OSR = 256 Sinc3 Filter 60 1 10 Frequency (kHz) −110 −100 THD 90 −90 80 −80 −70 70 −60 100 60 1 FREQUENCY SPECTRUM (4096 point FFT f IN = 5kHz, 4VPP) 0 0 −20 −20 −40 −40 −60 −60 Magnitude (dB) Magnitude (dB) −60 100 10 Frequency (kHz) FREQUENCY SPECTRUM (4096 point FFT fIN = 1kHz, 4VPP) −80 −100 −120 −80 −100 −120 −140 −140 −160 −160 −180 −180 0 2 4 6 8 10 12 Frequency (kHz) 10 −70 OSR = 256 Sinc3 Filter 14 16 18 19 0 2 4 6 8 10 12 Frequency (kHz) 14 16 18 19 THD (dB) SFDR (dB) THD 110 SFDR (dB) SFDR 100 −110 THD (dB) 110 www.ti.com SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 TYPICAL CHARACTERISTICS (continued) AVDD = 5V, BVDD = 3V, CH x+ = +0.5V to +4.5V, CH x− = +2.5V, REFIN = external, CLKSEL = 0, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO POWER−SUPPLY CURRENT vs TEMPERATURE 110 18 30 Sinc3 Filter 16 98 14 86 Sinc2 Filter 10 62 8 50 Current (mA) 74 12 CLKSEL = 0, CLKIN = 32MHz SNR (dB) ENOB (Bits) 27 24 CLKSEL = 0, CLKIN = 20MHz 21 CLKSEL = 1 18 38 6 26 10k 4 10 100 1k 15 −40 −20 0 20 40 60 80 Decimation Ratio (OSR) Temperature (_C) COMMON−MODE REJECTION RATIO vs FREQUENCY POWER−SUPPLY REJECTION RATIO vs FREQUENCY 110 100 110 105 100 100 90 PSRR (dB) CMRR (dB) 95 90 85 80 80 70 75 70 60 65 60 50 1 10 Input Frequency (kHz) 100 0.1 CLOCK FREQUENCY vs TEMPERATURE 1 10 Frequency of Power Supply (kHz) 100 CLOCK FREQUENCY vs POWER SUPPLY 10.0 9.8 9.8 9.7 9.4 CLKOUT (MHz) CLKOUT (MHz) 9.6 9.2 9.0 8.8 8.6 8.4 9.6 9.5 9.4 9.3 8.2 8.0 −40 −20 9.2 0 20 40 Temperature (_ C) 60 80 100 4.5 4.7 4.9 5.1 Power Supply (V) 5.3 5.5 11 www.ti.com SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 GENERAL DESCRIPTION The ADS1204 is a four-channel, 2nd-order, CMOS device with four delta-sigma modulators, designed for medium- to high-resolution A/D signal conversions from DC to 39kHz (filter response −3dB) if an oversampling ratio (OSR) of 64 is chosen. The output of the converter (OUTX) provides a stream of digital ones and zeros. The time average of this serial output is proportional to the analog input voltage. The modulator shifts the quantization noise to high frequencies. A low-pass digital filter should be used at the output of the delta-sigma modulator. The filter serves two functions. First, it filters out high-frequency noise. Second, the filter converts the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). An application-specific integrated circuit (ASIC), or field-programmable gate array (FPGA) could be used to implement the digital filter. Figure 2 and Figure 3 show typical application circuits with the ADS1204 connected to an FPGA. The overall performance (that is, speed and accuracy) depends on the selection of an appropriate OSR and filter type. A higher OSR produces greater output accuracy while operating at a lower refresh rate. Alternatively, a lower OSR produces lower output accuracy, but operates at a higher refresh rate. This system allows flexibility with the digital filter design and is capable of A/D conversion results that have a dynamic range exceeding 100dB with an OSR = 256. 2 kΩ AVDD +5V BVDD 5kΩ ±5V 27Ω 0.1µF CH A+ OP A4350 0.1nF 5kΩ CH A− 2nd−Order ∆Σ Modulator 2kΩ OUT A Output Interface Circuit REFIN A OUT B OUT C CLKOUT 2kΩ CH B+ +5V CH B− 2nd−Order ∆Σ Modulator 0.1µF BGND 27Ω 0.1µF REFIN B OP A4350 Divider 0.1nF 5kΩ CH C+ 2kΩ CH C− 2nd−Order ∆Σ Modulator Clock Select REFIN C 2kΩ CH D+ +5V 5kΩ ±5V CH D− 27Ω 0.1µF +3V BVDD 5kΩ ±5V FPGA or ASIC OUT D 5kΩ REFOUT 2kΩ CLKSEL AVDD Out Reference Voltage 2.5V +5V EN RC Oscillator 20MHz REFIN D 2kΩ +3V +5V 2nd−Order ∆Σ Modulator OP A4350 0.1nF CLKIN AVDD AVDD AVDD AGND AGND AGND AGND +5V +5V 0.1µF 0.1µF 0.1µF 0.1µF +5V 5kΩ ±5V 27Ω 0.1µF OP A4350 +5V 0.1nF 5kΩ 2kΩ OPA 336 0.1µF Figure 2. Single-Ended Connection Diagram for the ADS1204 Delta-Sigma Modulator 12 0.1µF www.ti.com SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 +5V 27Ω R1 OP A 4354 IN+ 0.1nF R2 +5V 27Ω R1 OP A 4354 IN− R2 AVDD +5V BVDD 27Ω R1 CH A+ OP A 4354 IN+ CH A− 0.1nF 2nd−Order ∆Σ Modulator R2 OUT A Output Interface Circuit REFIN A OUT C CH B+ 27Ω CH B− OP A 4354 2nd−Order ∆Σ Modulator FPGA or ASIC OUT D CLKOUT +5V R1 OUT B +3V BVD D 0.1µF BGND IN− REFIN B R2 Divider CH C+ +5V CH C− 2nd−Order ∆Σ Modulator 27Ω R1 OP A 4354 Clock Select REFIN C IN+ 0.1nF R2 CH D+ CH D− OP A 4354 IN− REFOUT R2 +5V CLKSEL AVD D Out Reference Voltage 2.5V +5V EN RC Oscillator 20MHz REFIN D 27Ω +3V +5V 2nd−Order ∆Σ Modulator +5V R1 CLKIN AVD D AVD D +5V +5V 0.1µF 0.1µF 0.1µF AVD D AGND AGND AGND AGND 0.1µF 0.1µF 27Ω R1 OP A 4354 IN+ 0.1nF R2 +5V 27Ω R1 +5V OP A 4354 IN− R2 OP A 336 0.1µF Figure 3. Differential Connection Diagram for the ADS1204 Delta-Sigma Modulator 13 www.ti.com SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 THEORY OF OPERATION The differential analog input of the ADS1204 is implemented with a switched-capacitor circuit. This circuit implements a 2nd-order modulator stage, which digitizes the analog input signal into a 1-bit output stream. The clock source can be internal as well as external. Different frequencies for this clock allow for a variety of solutions and signal bandwidths. Every analog input signal is continuously sampled by the modulator and compared to a reference voltage that is applied to the REFINx pin. A digital stream, which accurately represents the analog input voltage over time, appears at the output of the corresponding converter. ANALOG INPUT STAGE Analog Input The topology of the analog inputs of ADS1204 is based on fully differential switched−capacitor architecture. This input stage provides the mechanism to achieve low system noise, high common-mode rejection (100dB), and excellent power-supply rejection. The input impedance of the analog input is dependent on the modulator clock frequency (fCLK), which is also the sampling frequency of the modulator. Figure 4 shows the basic input structure of one channel of the ADS1204. The relationship between the input impedance of the ADS1204 and the modulator clock frequency is: Z IN + 100kW f MODń10MHz (1) The input impedance becomes a consideration in designs where the source impedance of the input signal is high. This high impedance may cause degradation in gain, linearity, and THD. The importance of this effect depends on the desired system performance. There are two restrictions on the analog input signals, CH x+ and CH x−. If the input voltage exceeds the range (GND – 0.3V) to (VDD + 0.3V), the input current must be limited to 10mA because the input protection diodes on the front end of the converter will begin to turn on. In addition, the linearity and the noise performance of the device is ensured only when the differential analog voltage resides within ±2V (with VREF as a midpoint); however, the FSR input voltage is ±2.5V. Modulator The ADS1204 can be operated in two modes. When CKLSEL = 1, the four modulators operate using the internal clock, which is fixed at 20MHz. When CKLSEL = 0, the modulators operate using an external clock . In both modes, the clock is divided by two internally and functions as the modulator clock. The frequency of the external clock can vary from 1MHz to 32MHz to adjust for the clock requirements of the application. The modulator topology is fundamentally a 2nd-order, switched-capacitor, delta-sigma modulator, such as the one conceptualized in Figure 5. The analog input voltage and the output of the 1-bit digital-to-analog converter (DAC) are differentiated, providing analog voltages at X2 and X3. The voltages at X2 and X3 are presented to their individual integrators. The output of these integrators progresses in a negative or positive direction. When the value of the signal at X4 equals the comparator reference voltage, the output of the comparator switches from negative to positive, or positive to negative, depending on its original state. When the output value of the comparator switches from high to low or vice versa, the 1-bit DAC responds on the next clock pulse by changing its analog output voltage at X6, causing the integrators to progress in the opposite direction. The feedback of the modulator to the front end of the integrators forces the value of the integrator output to track the average of the input. 650Ω AIN+ 1.2pF 0.4pF VCM Switching Frequency = CLK 0.4pF AIN− High Impedance > 1GΩ 650Ω 1.2pF High Impedance > 1GΩ Figure 4. Input Impedance of the ADS1204 14 www.ti.com SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 fCLK X2 X(t) Integrator 1 X3 Integrator 2 X4 DATA fS VREF Comparator X6 D/A Converter Figure 5. Block Diagram of the 2nd-Order Modulator DIGITAL OUTPUT A differential input signal of 0V will ideally produce a stream of ones and zeros that are high 50% of the time and low 50% of the time. A differential input of +2V produces a stream of ones and zeros that are high 80% of the time. A differential input of –2V produces a stream of ones and zeros that are high 20% of the time. The input voltage versus the output modulator signal is shown in Figure 6. connection is realized between the delta-sigma modulator and an ASIC or FPGA (each with an implemented filter), the two standard signals per modulator (CLKOUT and OUTx) are provided from the modulator. The output clock signal is equal for all four modulators. If CLKSEL = 1, CLKIN must always be set either high or low. MODES OF OPERATION INTRODUCTION The system clock of the ADS1204 is 20MHz by default. The system clock can be provided either from the internal 20MHz RC oscillator or from an external clock source. For this purpose, the CLKIN pin is provided; it is controlled by the mode setting, CLKSEL. The analog signal connected to the input of the delta-sigma modulator is converted using the clock signal applied to the modulator. The result of the conversion, or modulation, is generated and sent to the OUTx pin from the delta-sigma modulator. In most applications where a direct The system clock is divided by two for the modulator clock. Therefore, the default clock frequency of the modulator is 10MHz. With a possible external clock range of 1MHz to 32MHz, the modulator operates between 500kHz and 16MHz. DIGITAL INTERFACE Modulator Output +FS (Analog Input) −FS (Analog Input) Analog Input Figure 6. Analog Input vs Modulator Output of the ADS1204 15 www.ti.com SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 FILTER USAGE 0 A very simple filter, built with minimal effort and hardware, is the Sinc3 filter: ǒ Ǔ −OSR H(z) + 1 * z −1 1*z OSR = 32 f DATA = 10MHz/32 = 312.5kHz −3dB: 81.9kHz −10 −20 Gain (dB) The modulator generates only a bitstream, which does not output a digital word like an A/D converter. In order to output a digital word equivalent to the analog input voltage, the bitstream must be processed by a digital filter. −30 −40 −50 −60 −70 3 −80 (2) 0 This filter provides the best output performance at the lowest hardware size (for example, a count of digital gates). For oversampling ratios in the range of 16 to 256, this is a good choice. All the characterizations in the data sheet are also done using a Sinc3 filter with an oversampling ratio of OSR = 256 and an output word width of 16 bits. This performance can be improved, for example, by a cascaded filter structure. The first decimation stage can be a Sinc3 filter with a low OSR and the second stage a high-order filter. For more information, see application note SBAA094, Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications, available for download at www.ti.com. 16 400 600 800 1000 Frequency (kHz) 1200 1400 1600 Figure 7. Frequency Response of Sinc3 Filter 30k In a Sinc3 filter response (shown in Figure 7 and OSR = 32 FSR = 32768 ENOB = 9.9 Bits Settling Time = 3 × 1/f DATA = 9.6µs 25k Output Code Figure 8), the location of the first notch occurs at the frequency of output data rate fDATA = fCLK/OSR. The –3dB point is located at half the Nyquist frequency or fDATA/4. For some applications, it may be necessary to use another filter type for better frequency response. 200 20k 15k 10k 5k 0 0 5 10 15 20 25 30 Number of Output Clocks 35 Figure 8. Pulse Response of Sinc3 Filter (fMOD = 10MHz) 40 www.ti.com SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 The effective number of bits (ENOB) can be used to compare the performance of ADCs and delta-sigma modulators. Figure 9 shows the ENOB of the ADS1204 with different filter types. In this data sheet, the ENOB is calculated from the SNR: SNR = 1.76dB + 6.02dB × ENOB (3) data clocks. The data clock is equal to the modulator clock divided by the OSR. For overcurrent protection, filter types other than Sinc3 might be a better choice. A simple example is a Sinc2 filter. Figure 10 compares the settling time of different filter types. The Sincfast is a modified Sinc2 filter: ǒ Ǔ 2 −OSR H(z) + 1 * z −1 ǒ1 ) z −2 1*z Ǔ OSR (4) 16 10 Sinc3 14 12 Sincfast 8 Sinc2 7 10 ENOB (Bits) ENOB (Bits) Sinc3 9 8 6 Sinc Sincfast Sinc2 6 5 Sinc 4 4 3 2 2 1 0 1 10 100 1000 OSR 0 0 2 4 6 8 10 Settling Time (µs) Figure 9. Measured ENOB vs OSR In motor control applications, a very fast response time for overcurrent detection is required. There is a constraint between 1µs and 5µs with 3 bits to 7 bits resolution. The time for full settling is dependent on the filter order. Therefore, the full settling of the Sinc3 filter needs three data clocks and the Sinc2 filter needs two Figure 10. Measured ENOB vs Settling Time For more information, see application note SBAA094, Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications, available for download at www.ti.com. 17 www.ti.com SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 LAYOUT CONSIDERATIONS POWER SUPPLIES For multiple converters, connect the two ground planes as close as possible to one central location for all of the converters. In some cases, experimentation may be required to find the best point to connect the two planes together. An applied external digital filter rejects high-frequency noise. PSRR and CMRR improve at higher frequencies because the digital filter suppresses high-frequency noise. DECOUPLING However, the suppression of the filter is not infinite, so high-frequency noise still influences the conversion result. Inputs to the ADS1204, such as CH x+, CH x−, and CLKIN, should not be present before the power supply is on. Violating this condition could cause latch-up. If these signals are present before the supply is on, series resistors should be used to limit the input current to a maximum of 10mA. Experimentation may be the best way to determine the appropriate connection between the ADS1204 and different power supplies. Good decoupling practices must be used for the ADS1204 and for all components in the design. All decoupling capacitors, specifically the 0.1µF ceramic capacitors, must be placed as close as possible to the pin being decoupled. A 1µF and 10µF capacitor, in parallel with the 0.1µF ceramic capacitor, can be used to decouple AVDD to AGND as well as BVDD to BGND. At least one 0.1µF ceramic capacitor must be used to decouple every AVDD to AGND and BVDD to BGND, as well as for the digital supply on each digital component. GROUNDING Analog and digital sections of the design must be carefully and cleanly partitioned. Each section should have its own ground plane with no overlap between them. Do not join the ground planes; instead, connect the two with a moderate signal trace underneath the converter. However, for different applications with DSPs and switching power supplies, this process might be different. 18 The digital supply sets the I/O voltage for the interface and can be set within a range of 2.7V to 5.5V. In cases where both the analog and digital I/O supplies share the same supply source, an RC filter of 10Ω and 0.1µF can be used to help reduce the noise in the analog supply. PACKAGE OPTION ADDENDUM www.ti.com 28-Jun-2004 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY ADS1204IRHBR ACTIVE QFN RHB 32 3000 ADS1204IRHBT ACTIVE QFN RHB 32 250 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. 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