ELPIDA UPD45128163G5-A75I-9JF-E

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD45128163-I-E
128M-bit Synchronous DRAM
4-bank, LVTTL
WTR (Wide Temperature Range)
Description
The µPD45128163 is high-speed 134,217,728-bit synchronous dynamic random-access memory, organized as
2,097,152 × 16 × 4 (word × bit × bank).
The synchronous DRAM achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAM is compatible with Low Voltage TTL (LVTTL).
This product is packaged in 54-pin TSOP (II).
Features
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0(A13) and BA1(A12)
• Byte control by LDQM and UDQM
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Ambient temperature (TA): −40 to + 85°C
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• ×16 organization
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64 ms
• Burst termination by Burst stop command and Precharge command
• TSOP (II) package with lead free solder (Sn-Bi)
 RoHS compliant
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0729N10 (Ver.1.0)
Date Published June 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
µPD45128163-I-E
Ordering Information
Part number
µPD45128163G5-A75I-9JF-E
Organization
(word × bit × bank)
Clock frequency
MHz (MAX.)
Package
Note
2M × 16 × 4
133
54-pin Plastic TSOP (II)
Ambient temperature
µPD45128163G5-A75LI-9JF-E
2
TA = −40 to + 85°C
Data Sheet E0729N10 (Ver. 1.0)
µPD45128163-I-E
Part Number
[ x16 ]
µPD45128163G5 - A75L I - E
Environment Code
NEC Memory
E: Lead Free
Synchronous DRAM
Wide temperature
range
Memory density
I : -40 to + 85°C
128 : 128M bits
Low Power
Organization
16 : x16
Minimum cycle time
75
: 7.5 ns (133 MHz @CL=3)
Number of banks
3 : 4 banks, LVTTL
Low voltage
A : 3.3 V ± 0.3 V
Package
G5 : TSOP (II)
Data Sheet E0729N10 (Ver. 1.0)
3
µPD45128163-I-E
Pin Configurations
/xxx indicates active low signal.
54-pin Plastic TSOP (II)
2M words × 16 bits × 4 banks
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
VCC
LDQM
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
A1
A2
A3
VCC
A0 to A11
Note
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Vss
DQ15
VssQ
DQ14
DQ13
VccQ
DQ12
DQ11
VssQ
DQ10
DQ9
VccQ
DQ8
Vss
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
: Address inputs
BA0(A13), BA1(A12) : Bank select
DQ0 to DQ15
: Data inputs / outputs
CLK
: Clock input
CKE
: Clock enable
/CS
: Chip select
/RAS
: Row address strobe
/CAS
: Column address strobe
/WE
: Write enable
LDQM
: Lower DQ mask enable
UDQM
: Upper DQ mask enable
VCC
: Supply voltage
VSS
: Ground
VCCQ
: Supply voltage for DQ
VSSQ
: Ground for DQ
NC
4
Note A0 to A11 : Row address inputs
: No connection
Data Sheet E0729N10 (Ver. 1.0)
A0 to A8 : Column address inputs
µPD45128163-I-E
Block Diagram
CLK
CKE
Clock
Generator
Bank D
Bank C
Address
Mode
Register
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
Bank B
Bank A
Data Sheet E0729N10 (Ver. 1.0)
DQM
Column Decoder &
Latch Circuit
Data Control Circuit
Input & Output
Buffer
/WE
Column
Address
Buffer
&
Burst
Counter
Latch Circuit
/CAS
Control Logic
/RAS
Command Decoder
Sense Amplifier
/CS
DQ
5
µPD45128163-I-E
CONTENTS
1.
Input / Output Pin Function ............................................................................................................. 8
2.
Commands ........................................................................................................................................ 9
3.
Simplified State Diagram ............................................................................................................... 12
4.
Truth Table ...................................................................................................................................... 13
4.1 Command Truth Table ............................................................................................................................ 13
4.2 DQM Truth Table ..................................................................................................................................... 13
4.3 CKE Truth Table ...................................................................................................................................... 13
4.4 Operative Command Table .................................................................................................................... 14
4.5 Command Truth Table for CKE ............................................................................................................. 17
5.
Initialization ..................................................................................................................................... 18
6.
Programming the Mode Register .................................................................................................. 19
7.
Mode Register ................................................................................................................................. 20
7.1 Burst Length and Sequence ................................................................................................................. 21
8.
Address Bits of Bank-Select and Precharge ............................................................................... 24
9.
Precharge ........................................................................................................................................ 23
10. Auto Precharge ............................................................................................................................... 24
10.1
Read with Auto Precharge .................................................................................................................. 24
10.2
Write with Auto Precharge ................................................................................................................. 25
11. Read / Write Command Interval ..................................................................................................... 26
11.1
Read to Read Command Interval ....................................................................................................... 26
11.2
Write to Write Command Interval ....................................................................................................... 26
11.3
Write to Read Command Interval ....................................................................................................... 27
11.4
Read to Write Command Interval ....................................................................................................... 28
12. Burst Termination ........................................................................................................................... 29
6
12.1
Burst Stop Command ......................................................................................................................... 29
12.2
Precharge Termination ....................................................................................................................... 30
12.2.1
Precharge Termination in READ Cycle ................................................................................... 30
12.2.2
Precharge Termination in WRITE Cycle .................................................................................. 31
Data Sheet E0729N10 (Ver. 1.0)
µPD45128163-I-E
13. Electrical Specifications ................................................................................................................ 32
13.1
AC Parameters for Read Timing ........................................................................................................ 37
13.2
AC Parameters for Write Timing ........................................................................................................ 39
13.3
Relationship between Frequency and Latency ................................................................................ 40
13.4
Mode Register Set ............................................................................................................................... 41
13.5
Power on Sequence and CBR (Auto) Refresh .................................................................................. 42
13.6
/CS Function ........................................................................................................................................ 43
13.7
Clock Suspension during Burst Read (using CKE Function) ......................................................... 44
13.8
Clock Suspension during Burst Write (using CKE Function) ......................................................... 46
13.9
Power Down Mode and Clock Mask .................................................................................................. 48
13.10 CBR (Auto) Refresh ............................................................................................................................. 49
13.11 Self Refresh (Entry and Exit) .............................................................................................................. 50
13.12 Random Column Read (Page with Same Bank) ............................................................................... 51
13.13 Random Column Write (Page with Same Bank) ............................................................................... 53
13.14 Random Row Read (Ping-Pong Banks) ............................................................................................ 55
13.15 Random Row Write (Ping-Pong Banks) ............................................................................................ 57
13.16 Read and Write .................................................................................................................................... 59
13.17 Interleaved Column Read Cycle ......................................................................................................... 61
13.18 Interleaved Column Write Cycle ......................................................................................................... 63
13.19 Auto Precharge after Read Burst ....................................................................................................... 65
13.20 Auto Precharge after Write Burst ....................................................................................................... 67
13.21 Full Page Read Cycle .......................................................................................................................... 69
13.22 Full Page Write Cycle .......................................................................................................................... 71
13.23 Byte Write Operation ........................................................................................................................... 73
13.24 Burst Read and Single Write (Option) ............................................................................................... 75
13.25 Full Page Random Column Read ....................................................................................................... 77
13.26 Full Page Random Column Write ....................................................................................................... 79
13.27 PRE (Precharge) Termination of Burst .............................................................................................. 81
14. Package Drawing ............................................................................................................................ 83
15. Recommended Soldering Conditions ........................................................................................... 84
Data Sheet E0729N10 (Ver. 1.0)
7
µPD45128163-I-E
1. Input / Output Pin Function
Pin name
CLK
Input / Output
Input
Function
CLK is the master clock input. Other inputs signals are referenced to the CLK rising
edge.
CKE
Input
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge
is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock is not
issued and the µPD45128xxx suspends operation.
When the µPD45128xxx is not in burst mode and CKE is negated, the device enters
power down mode. During power down mode, CKE must remain low.
/CS
Input
/CS low starts the command input cycle. When /CS is high, commands are ignored but
operations continue.
/RAS, /CAS, /WE
Input
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different
functions. For details, refer to the command table.
A0 - A11
Input
Row Address is determined by A0 - A11 at the CLK (clock) rising edge in the active
command cycle. It does not depend on the bit organization.
Column Address is determined by A0 - A9, A11 at the CLK rising edge in the read or
write command cycle. It depends on the bit organization: A0 - A8 for ×16 device.
A10 defines the precharge mode. When A10 is high in the precharge command cycle,
all banks are precharged; when A10 is low, only the bank selected by BA0(A13) and
BA1(A12) is precharged.
When A10 is high in read or write command cycle, the precharge starts automatically
after the burst access.
BA0, BA1
Input
BA0(A13) and BA1(A12) are the bank select signal. In command cycle, BA0(A13) and
BA1(A12) low select bank A, BA0(A13) high and BA1(A12) low select bank B, BA0(A13)
low and BA1(A12) high select bank C and then BA0(A13) and BA1(A12) high select bank
D.
UDQM, LDQM
Input
DQM controls I/O buffers. In ×16 products, UDQM and LDQM control upper byte and
lower byte I/O buffers, respectively.
In read mode, UDQM and LDQM controls the output buffers like a conventional /OE pin.
UDQM and LDQM high and UDQM and LDQM low turn the output buffers off and on,
respectively.
The UDQM and LDQM latency for the read is two clocks.
In write mode, UDQM and LDQM controls the word mask. Input data is written to the
memory cell if UDQM and LDQM is low but not if UDQM and LDQM is high.
The UDQM and LDQM latency for the write is zero.
DQ0 - DQ15
Input / Output
DQ pins have the same function as I/O pins on a conventional DRAM.
VCC, VSS, VCCQ, VSSQ
(Power supply)
VCC and VSS are power supply pins for internal circuits. VCCQ and VSSQ are power supply
pins for the output buffers.
8
Data Sheet E0729N10 (Ver. 1.0)
µPD45128163-I-E
2. Commands
Mode register set command
Fig.1 Mode register set command
CLK
(/CS, /RAS, /CAS, /WE = Low)
CKE
The µPD45128xxx has a mode register that defines how the device
/CS
operates. In this command, A0 through A11, BA0(A13) and BA1(A12)
/RAS
are the data input pins.
/CAS
After power on, the mode register set
command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state.
During 2 CLK (tRSC) following this command, the µPD45128xxx
cannot accept any other commands.
H
/WE
BA0(A13), BA1(A12)
A10
Add
Activate command
Fig.2 Row address strobe and
bank activate command
(/CS, /RAS = Low, /CAS, /WE = High)
CLK
The µPD45128xxx has four banks, each with 4,096 rows.
This command activates the bank selected by BA0(A13) and
BA1(A12) and a row address selected by A0 through A11.
This command corresponds to a conventional DRAM’s /RAS falling.
CKE
H
/CS
/RAS
/CAS
/WE
BA0(A13), BA1(A12)
Precharge command
A10
Row
Add
Row
Fig.3 Precharge command
CLK
(/CS, /RAS, /WE = Low, /CAS = High)
CKE
This command begins precharge operation of the bank selected by
/CS
BA0(A13) and BA1(A12). When A10 is High, all banks are
/RAS
precharged, regardless of BA0(A13) and BA1(A12). When A10 is Low,
/CAS
only the bank selected by BA0(A13) and BA1(A12) is precharged.
After this command, the µPD45128xxx can’t accept the activate
command to the precharging bank during tRP (precharge to activate
H
/WE
BA0(A13), BA1(A12)
A10
(Precharge select)
command period).
Add
This command corresponds to a conventional DRAM’s /RAS rising.
Data Sheet E0729N10 (Ver. 1.0)
9
µPD45128163-I-E
Write command
Fig.4 Column address and write command
CLK
(/CS, /CAS, /WE = Low, /RAS = High)
CKE
If the mode register is in the burst write mode, this command sets the
burst start address given by the column address to begin the burst
/RAS
write operation. The first write data in burst mode can input with this
/CAS
command with subsequent data on following clocks.
H
/CS
/WE
BA0(A13), BA1(A12)
A10
Add
Read command
Col.
Fig.5 Column address and read command
CLK
(/CS, /CAS = Low, /RAS, /WE = High)
CKE
Read data is available after /CAS latency requirements have been
H
/CS
met. This command sets the burst start address given by the column
/RAS
address.
/CAS
/WE
BA0(A13), BA1(A12)
A10
Add
CBR (auto) refresh command
Fig.6 CBR (auto) refresh command
(/CS, /RAS, /CAS = Low, /WE, CKE = High)
CLK
CKE
This command is a request to begin the CBR (auto) refresh operation.
The refresh address is generated internally.
/CS
/RAS
Before executing CBR (auto) refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and
ready for a row activate command.
/CAS
/WE
BA0(A13), BA1(A12)
During tRC period (from refresh command to refresh or activate
command), the µPD45128xxx cannot accept any other command.
10
Col.
Data Sheet E0729N10 (Ver. 1.0)
A10
Add
H
µPD45128163-I-E
Self refresh entry command
Fig.7 Self refresh entry command
CLK
(/CS, /RAS, /CAS, CKE = Low, /WE = High)
CKE
After the command execution, self refresh operation continues while
/CS
CKE remains low. When CKE goes high, the µPD45128xxx exits the
/RAS
self refresh mode.
/CAS
During self refresh mode, refresh interval and refresh operation are
/WE
performed internally, so there is no need for external control.
BA0(A13), BA1(A12)
Before executing self refresh, all banks must be precharged.
A10
Add
Burst stop command
Fig.8 Burst stop command in Full Page Mode
CLK
(/CS, /WE = Low, /RAS, /CAS = High)
CKE
This command can stop the current burst operation.
H
/CS
/RAS
/CAS
/WE
BA0(A13), BA1(A12)
A10
Add
No operation
Fig.9 No operation
CLK
(/CS = Low, /RAS, /CAS, /WE = High)
CKE
This command is not an execution command. No operations begin or
terminate by this command.
H
/CS
/RAS
/CAS
/WE
BA0(A13), BA1(A12)
A10
Add
Data Sheet E0729N10 (Ver. 1.0)
11
µPD45128163-I-E
3. Simplified State Diagram
12
Data Sheet E0729N10 (Ver. 1.0)
µPD45128163-I-E
4. Truth Table
4.1 Command Truth Table
Function
Symbol
CKE
/CS
n–1
n
/RAS
/CAS
/WE
BA1,
A10
BA0
A11,
A9 - A0
Device deselect
DESL
H
×
H
×
×
×
×
×
×
No operation
NOP
H
×
L
H
H
H
×
×
×
Burst stop
BST
H
×
L
H
H
L
×
×
×
Read
READ
H
×
L
H
L
H
V
L
V
Read with auto precharge
READA
H
×
L
H
L
H
V
H
V
Write
WRIT
H
×
L
H
L
L
V
L
V
Write with auto precharge
WRITA
H
×
L
H
L
L
V
H
V
Bank activate
ACT
H
×
L
L
H
H
V
V
V
Precharge select bank
PRE
H
×
L
L
H
L
V
L
×
Precharge all banks
PALL
H
×
L
L
H
L
×
H
×
Mode register set
MRS
H
×
L
L
L
L
L
L
V
Remark H = High level, L = Low level, × = High or Low level (Don't care), V = Valid data input
4.2 DQM Truth Table
Function
Symbol
CKE
DQM
n–1
n
U
L
Upper byte write enable / output enable
ENBU
H
×
L
×
Lower byte write enable / output enable
ENBL
H
×
×
L
Upper byte write inhibit / output disable
MASKU
H
×
H
×
Lower byte write inhibit / output disable
MASKL
H
×
×
H
Remark H = High level, L = Low level, × = High or Low level (Don't care)
4.3 CKE Truth Table
Current state
Function
Symbol
CKE
n–1
n
/CS
/RAS
/CAS
/WE
Address
Activating
Clock suspend mode entry
H
L
×
×
×
×
×
Any
Clock suspend mode
L
L
×
×
×
×
×
Clock suspend
Clock suspend mode exit
L
H
×
×
×
×
×
Idle
CBR (auto) refresh command
REF
H
H
L
L
L
H
×
Idle
Self refresh entry
SELF
H
L
L
L
L
H
×
Self refresh
Self refresh exit
L
H
L
H
H
H
×
L
H
H
×
×
×
×
Idle
Power down entry
H
L
×
×
×
×
×
Power down
Power down exit
L
H
H
×
×
×
×
L
H
L
H
H
H
×
Remark H = High level, L = Low level, × = High or Low level (Don't care)
Data Sheet E0729N10 (Ver. 1.0)
13
µPD45128163-I-E
4.4 Operative Command Table Note1
Current state
Idle
Row active
Read
Write
14
(1/3)
/CS /RAS /CAS /WE
Address
Command
Action
Notes
H
×
×
×
×
DESL
Nop or power down
2
L
H
H
×
×
NOP or BST
Nop or power down
2
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
Row activating
L
L
H
L
BA, A10
PRE/PALL
Nop
L
L
L
H
×
REF/SELF
CBR (auto) refresh or self refresh
L
L
L
L
Op-Code
MRS
Mode register accessing
4
H
×
×
×
×
DESL
Nop
L
H
H
×
×
NOP or BST
Nop
L
H
L
H
BA, CA, A10
READ/READA
Begin read : Determine AP
5
L
H
L
L
BA, CA, A10
WRIT/WRITA
Begin write : Determine AP
5
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Precharge
6
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
H
×
×
×
×
DESL
Continue burst to end → Row active
L
H
H
H
×
NOP
Continue burst to end → Row active
L
H
H
L
×
BST
Burst stop → Row active
L
H
L
H
BA, CA, A10
READ/READA
Terminate burst, new read : Determine AP
7
7, 8
L
H
L
L
BA, CA, A10
WRIT/WRITA
Terminate burst, start write : Determine AP
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE/PALL
Terminate burst, precharging
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
3
H
×
×
×
×
DESL
Continue burst to end → Write recovering
L
H
H
H
×
NOP
Continue burst to end → Write recovering
L
H
H
L
×
BST
Burst stop → Row active
L
H
L
H
BA, CA, A10
READ/READA
Terminate burst, start read : Determine AP
7, 8
L
H
L
L
BA, CA, A10
WRIT/WRITA
Terminate burst, new write : Determine AP
7
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Terminate burst, precharging
9
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Data Sheet E0729N10 (Ver. 1.0)
µPD45128163-I-E
(2/3)
Current state
/CS /RAS /CAS /WE
Address
Command
Action
Read with auto
H
×
×
×
×
DESL
Continue burst to end → Precharging
precharge
L
H
H
H
×
NOP
Continue burst to end → Precharging
Write with auto
precharge
Precharging
Row activating
Notes
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
H
×
×
×
×
DESL
Continue burst to end → Write
recovering with auto precharge
L
H
H
H
×
NOP
Continue burst to end → Write
recovering with auto precharge
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
H
×
×
×
×
DESL
Nop → Enter idle after tRP
L
H
H
H
×
NOP
Nop → Enter idle after tRP
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Nop → Enter idle after tRP
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
H
×
×
×
×
DESL
Nop → Enter bank active after tRCD
L
H
H
H
×
NOP
Nop → Enter bank active after tRCD
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3, 10
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Data Sheet E0729N10 (Ver. 1.0)
15
µPD45128163-I-E
(3/3)
Current state
Write recovering
/CS /RAS /CAS /WE
Address
Command
Action
H
×
×
×
×
DESL
Nop → Enter row active after tDPL
L
H
H
H
×
NOP
Nop → Enter row active after tDPL
Notes
L
H
H
L
×
BST
Nop → Enter row active after tDPL
L
H
L
H
BA, CA, A10
READ/READA
Start read, Determine AP
L
H
L
L
BA, CA, A10
WRIT/WRITA
New write, Determine AP
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Write recovering
H
×
×
×
×
DESL
Nop → Enter precharge after tDPL
with auto precharge
L
H
H
H
×
NOP
Nop → Enter precharge after tDPL
L
H
H
L
×
BST
Nop → Enter precharge after tDPL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3, 8
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
H
×
×
×
×
DESL
Nop → Enter idle after tRC
Refreshing
L
H
H
×
×
NOP/BST
Nop → Enter idle after tRC
L
H
L
×
×
READ/WRIT
ILLEGAL
L
L
H
×
×
ACT/PRE/PALL
ILLEGAL
L
L
L
×
×
REF/SELF/MRS
ILLEGAL
Mode register
H
×
×
×
×
DESL
Nop → Enter idle after tRSC
accessing
L
H
H
H
×
NOP
Nop → Enter idle after tRSC
L
H
H
L
×
BST
ILLEGAL
L
H
L
×
×
READ/WRIT
ILLEGAL
L
L
×
×
×
ACT/PRE/PALL/
ILLEGAL
8
REF/SELF/MRS
Notes 1.
2.
All entries assume that CKE was active (High level) during the preceding clock cycle.
If all banks are idle, and CKE is inactive (Low level), µPD45128xxx will enter Power down mode.
All input buffers except CKE will be disabled.
3.
Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
4.
If all banks are idle, and CKE is inactive (Low level), µPD45128xxx will enter Self refresh mode. All input
buffers except CKE will be disabled.
5.
Illegal if tRCD is not satisfied.
6.
Illegal if tRAS is not satisfied.
7.
Must satisfy burst interrupt condition.
8.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9.
Must mask preceding data which don't satisfy tDPL.
10. Illegal if tRRD is not satisfied.
Remark H = High level, L = Low level, × = High or Low level (Don’t care), V = Valid data
16
Data Sheet E0729N10 (Ver. 1.0)
µPD45128163-I-E
4.5 Command Truth Table for CKE
Current State
Self refresh
Self refresh recovery
Power down
All banks idle
CKE
/CS /RAS /CAS /WE
Address
Action
n–1
n
H
×
×
×
×
×
×
INVALID, CLK (n – 1) would exit self refresh
L
H
H
×
×
×
×
Self refresh recovery
L
H
L
H
H
×
×
Self refresh recovery
L
H
L
H
L
×
×
ILLEGAL
L
H
L
L
×
×
×
ILLEGAL
L
L
×
×
×
×
×
Maintain self refresh
H
H
H
×
×
×
×
Idle after tRC
H
H
L
H
H
×
×
Idle after tRC
H
H
L
H
L
×
×
ILLEGAL
H
H
L
L
×
×
×
ILLEGAL
H
L
H
×
×
×
×
ILLEGAL
H
L
L
H
H
×
×
ILLEGAL
H
L
L
H
L
×
×
ILLEGAL
×
ILLEGAL
H
L
L
L
×
×
H
×
×
×
×
×
L
H
H
×
×
×
×
EXIT power down → Idle
Notes
INVALID, CLK (n – 1) would exit power down
L
H
L
H
H
H
×
EXIT power down → Idle
L
L
×
×
×
×
×
Maintain power down mode
H
H
H
×
×
×
Refer to operations in Operative Command Table
H
H
L
H
×
×
Refer to operations in Operative Command Table
H
H
L
L
H
×
H
H
L
L
L
H
×
CBR (auto) Refresh
H
H
L
L
L
L
Op-Code
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
H
L
H
×
×
×
Refer to operations in Operative Command Table
H
L
L
H
×
×
Refer to operations in Operative Command Table
H
L
L
L
H
×
Refer to operations in Operative Command Table
H
L
L
L
L
H
×
Self refresh
H
L
L
L
L
L
Op-Code
Refer to operations in Operative Command Table
L
×
×
×
×
×
×
Power down
Row active
H
×
×
×
×
×
×
Refer to operations in Operative Command Table
L
×
×
×
×
×
×
Power down
Any state other than
H
H
×
×
×
×
listed above
H
L
×
×
×
×
×
Begin clock suspend next cycle
L
H
×
×
×
×
×
Exit clock suspend next cycle
L
L
×
×
×
×
×
Maintain clock suspend
1
1
1
Refer to operations in Operative Command Table
2
Notes 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all
banks idle or row active state.
2. Must be legal command as defined in Operative Command Table.
Remark H = High level, L = Low level, × = High or Low level (Don't care)
Data Sheet E0729N10 (Ver. 1.0)
17
µPD45128163-I-E
5. Initialization
The synchronous DRAM is initialized in the power-on sequence according to the following.
(1)
To stabilize internal circuits, when power is applied, a 100 µs or longer pause must precede any signal toggling.
(2)
After the pause, all banks must be precharged using the Precharge command (The Precharge all banks
command is convenient).
(3)
Once the precharge is completed and the minimum tRP is satisfied, the mode register can be programmed. After
the mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied as well.
(4)
Two or more CBR (Auto) refresh must be performed.
Remarks 1. The sequence of Mode register programming and Refresh above may be transposed.
2. CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z.
18
Data Sheet E0729N10 (Ver. 1.0)
µPD45128163-I-E
6. Programming the Mode Register
The mode register is programmed by the Mode register set command using address bits A11 through A0, BA0(A13)
and BA1(A12) as data inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has four fields;
Options
: A11 through A7, BA0(A13), BA1(A12)
/CAS latency : A6 through A4
Wrap type
: A3
Burst length
: A2 through A0
Following mode register programming, no command can be issued before at least 2 CLK have elapsed.
/CAS Latency
/CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse before
the data will be available.
The value is determined by the frequency of the clock and the speed grade of the device. 13.3 Relationship
between Frequency and Latency shows the relationship of /CAS latency to the clock period and the speed grade of
the device.
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become Hi-Z.
The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either
“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing.
7.1 Burst Length and Sequence shows the addressing sequence for each burst length using them. Both sequences
support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.
Data Sheet E0729N10 (Ver. 1.0)
19
µPD45128163-I-E
7. Mode Register
BA0 BA1
(A13) (A12) A11
0
0
0
BA0 BA1
(A13) (A12) A11
x
x
x
BA0 BA1
(A13) (A12) A11
BA0 BA1
(A13) (A12) A11
x
x
x
BA0 BA1
(A13) (A12) A11
0
0
0
A10
A9
A8
A7
0
0
0
1
A10
A9
A8
A7
x
1
0
0
A10
A9
A8
A7
1
0
A6
A5
A4
A3
A2
A1
A0
JEDEC Standard Test Set (refresh counter test)
A6
A5
A4
LTMODE
A6
A5
A3
A2
WT
A4
A3
A1
A0
BL
A2
A1
Burst Read and Single Write
(for Write Through Cache)
A0
Use in future
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
x
x
1
1
V
V
V
V
V
V
V
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
LTMODE
WT
Vender Specific
V = Valid
x = Don’t care
BL
Mode Register Set
Burst length
Bits2-0
000
001
010
011
100
101
110
111
Wrap type
0
1
Latency
mode
WT = 0
1
2
4
8
R
R
R
Full page
Sequential
Interleave
Bits6-4
000
001
010
011
100
101
110
111
Remark R : Reserved
Mode Register Set Timing
CLK
CKE
/CS
/RAS
/CAS
/WE
A0 - A11,
BA0(13), BA1(A12)
Mode Register Set
20
Data Sheet E0729N10 (Ver. 1.0)
/CAS latency
R
R
2
3
R
R
R
R
WT = 1
1
2
4
8
R
R
R
R
µPD45128163-I-E
7.1 Burst Length and Sequence
[Burst of Two]
Starting address
(column address A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
0
0, 1
0, 1
1
1, 0
1, 0
Starting address
(column address A1 - A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
00
0, 1, 2, 3
0, 1, 2, 3
01
1, 2, 3, 0
1, 0, 3, 2
10
2, 3, 0, 1
2, 3, 0, 1
11
3, 0, 1, 2
3, 2, 1, 0
Starting address
(column address A2 - A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
[Burst of Four]
[Burst of Eight]
Full page burst is an extension of the above tables of sequential addressing, with the length being 512 (for 8M ×16
device).
Data Sheet E0729N10 (Ver. 1.0)
21
µPD45128163-I-E
8. Address Bits of Bank-Select and Precharge
Row
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA1 BA0
(A12)
(A13)
(Activate command)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA1(A12) BA0(A13)
Result
Select Bank A
“Activate” command
Select Bank B
“Activate” command
0
0
0
1
1
0
Select Bank C
“Activate” command
1
1
Select Bank D
“Activate” command
BA1 BA0
(A12)
(A13)
A10 BA1(A12) BA0(A13)
0
0
0
0
1
0
0
0
1
0
1
1
1
x
x
(Precharge command)
Result
Precharge Bank A
Precharge Bank B
Precharge Bank C
Precharge Bank D
Precharge All Banks
x : Don’t care
0
Col.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
x
BA1 BA0
(A12)
(A13)
1
disables Auto-Precharge
(End of Burst)
enables Auto-Precharge
(End of Burst)
(/CAS strobes)
BA1(A12) BA0(A13)
22
Data Sheet E0729N10 (Ver. 1.0)
Result
enables Read/Write
commands for Bank A
enables Read/Write
commands for Bank B
0
0
0
1
1
0
enables Read/Write
commands for Bank C
1
1
enables Read/Write
commands for Bank D
µPD45128163-I-E
9. Precharge
The precharge command can be issued anytime after tRAS (MIN.) is satisfied.
Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters the
idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as
follows.
It is depending on the /CAS latency and clock cycle time.
Burst length=4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
/CAS latency = 2
Command
PRE
READ
Q1
DQ
Q2
Q3
Hi-Z
Q4
/CAS latency = 3
Command
READ
PRE
DQ
Q1
Q2
Q3
Hi-Z
Q4
(tRAS must be satisfied)
In order to write all data to the memory cell correctly, the asynchronous parameter “tDPL” must be satisfied. The tDPL
(MIN.)
specification defines the earliest time that a precharge command can be issued. Minimum number of clocks is
calculated by dividing tDPL (MIN.) with clock cycle time.
In summary, the precharge command can be issued relative to reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
/CAS latency
Read
Write
2
–1
+tDPL (MIN.)
3
–2
+tDPL (MIN.)
Data Sheet E0729N10 (Ver. 1.0)
23
µPD45128163-I-E
10. Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or
Write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is
selected and begins automatically.
The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the
next activate command to the bank being precharged cannot be executed until the precharge cycle ends.
In read cycle, once auto precharge has started, an activate command to the bank can be issued after tRP has been
satisfied.
In write cycle, the tDAL must be satisfied to issue the next activate command to the bank being precharged.
The timing that begins the auto precharge cycle depends on both the /CAS latency programmed into the mode
register and whether read or write cycle.
10.1 Read with Auto Precharge
During a read cycle, the auto precharge begins one clock earlier (/CAS latency of 2) or two clocks earlier (/CAS
latency of 3) the last data word output.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
/CAS latency = 2
Command
Auto precharge starts
READA B
Hi-Z
DQ
QB1
QB2
QB3
QB4
/CAS latency = 3
Command
Auto precharge starts
READA B
Hi-Z
QB1
DQ
QB2
QB3
QB4
(tRAS must be satisfied)
Remark READA means Read with Auto precharge
24
Data Sheet E0729N10 (Ver. 1.0)
µPD45128163-I-E
10.2 Write with Auto Precharge
During a write cycle, the auto precharge starts at the timing that is equal to the value of the tDPL (MIN.) after the last
data word input to the device.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
/CAS latency = 2
Auto precharge starts
WRITA B
Command
Hi-Z
DB1
DQ
DB2
DB3
DB4
tDPL(MIN.)
/CAS latency = 3
Command
Auto precharge starts
WRITA B
Hi-Z
DB1
DQ
DB2
DB3
DB4
tDPL(MIN.)
(tRAS must be satisfied)
Remark WRITA means Write with Auto Precharge
In summary, the auto precharge begins relative to a reference clock that indicates the last data word is valid.
In the table below, minus means clocks before the reference; plus means after the reference.
/CAS latency
Read
Write
2
–1
+tDPL (MIN.)
3
–2
+tDPL (MIN.)
Data Sheet E0729N10 (Ver. 1.0)
25
µPD45128163-I-E
11. Read / Write Command Interval
11.1 Read to Read Command Interval
During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the previous
read operation does not completed. READ will be interrupted by another READ.
The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock without
any restriction.
Burst length = 4, /CAS latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
QA1
QB1
QB2
QB3
QB4
T8
T9
CLK
Command
READ A
READ B
Hi-Z
DQ
1cycle
11.2 Write to Write Command Interval
During a write cycle, when a new Write command is issued, the previous burst will terminate and the new burst will
begin with a new Write command. WRITE will be interrupted by another WRITE.
The interval between the commands is minimum 1 cycle. Each Write command can be issued in every clock without
any restriction.
Burst length = 4, /CAS latency = 2
T0
T1
T2
T3
T4
T5
DB2
DB3
DB4
T6
CLK
Command
WRITE A
WRITE B
DA1
DB1
Hi-Z
DQ
1cycle
26
Data Sheet E0729N10 (Ver. 1.0)
T7
T8
µPD45128163-I-E
11.3 Write to Read Command Interval
Write command and Read command interval is also 1 cycle.
Only the write data before Read command will be written.
The data bus must be Hi-Z at least one cycle prior to the first DOUT.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
QB1
QB2
QB3
QB4
QB1
QB2
QB3
T8
CLK
/CAS latency = 2
Command
WRITE A
READ B
Hi-Z
DQ
DA1
/CAS latency = 3
Command
WRITE A
READ B
Hi-Z
DQ
DA1
Data Sheet E0729N10 (Ver. 1.0)
QB4
27
µPD45128163-I-E
11.4 Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE.
The Read and Write command interval is 1 cycle minimum. There is a restriction to avoid data conflict. The Data
bus must be Hi-Z using DQM before WRITE.
Burst length = 4
T0
T1
T2
T3
T4
T5
D2
D3
D4
T6
T7
T8
CLK
Command
READ
WRITE
DQM
Hi-Z
D1
DQ
1cycle
READ can be interrupted by WRITE. DQM must be High at least 3 clocks prior to the Write command.
Burst length = 8
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
D2
D3
D2
D3
CLK
/CAS latency = 2
Command
READ
WRITE
DQM
Q1
DQ
Q2
Q3
D1
Hi-Z is
necessary
/CAS latency = 3
Command
READ
WRITE
DQM
DQ
Q1
Q2
D1
Hi-Z is
necessary
28
Data Sheet E0729N10 (Ver. 1.0)
µPD45128163-I-E
12. Burst Termination
There are two methods to terminate a burst operation other than using a Read or a Write command. One is the burst
stop command and the other is the precharge command.
12.1 Burst Stop Command
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to Hi-Z after the /CAS latency from the burst stop command.
Burst length = X
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
READ
BST
/CAS latency = 2
Hi-Z
Q1
DQ
Q2
Q3
Q1
Q2
/CAS latency = 3
Hi-Z
DQ
Q3
Remark BST: Burst stop command
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes
to Hi-Z at the same clock with the burst stop command.
Burst length = X
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
WRITE
BST
/CAS latency = 2, 3
DQ
Hi-Z
D1
D2
D3
D4
Remark BST: Burst stop command
Data Sheet E0729N10 (Ver. 1.0)
29
µPD45128163-I-E
12.2 Precharge Termination
12.2.1 Precharge Termination in READ Cycle
During a read cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command.
To issue a precharge command, tRAS must be satisfied.
When /CAS latency is 2, the read data will remain valid until one clock after the precharge command.
Burst length = X, /CAS latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ
Command
ACT
PRE
Hi-Z
DQ
Q1
Q2
Q3
Q4
tRP
(tRAS must be satisfied)
When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Burst length = X, /CAS latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
READ
ACT
PRE
Hi-Z
DQ
Q1
Q2
Q3
Q4
tRP
(tRAS must be satisfied)
30
Data Sheet E0729N10 (Ver. 1.0)
µPD45128163-I-E
12.2.2 Precharge Termination in WRITE Cycle
During a write cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command.
To issue a precharge command, tRAS must be satisfied.
When /CAS latency is 2, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM must
be high at the same clock as the precharge command. This will mask the invalid data.
Burst length = X, /CAS latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE
Command
ACT
PRE
DQM
Hi-Z
DQ
D1
D2
D3
D4
D5
tRP
(tRAS must be satisfied)
When /CAS latency is 3, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM must
be high at the same clock as the precharge command. This will mask the invalid data.
Burst length = X, /CAS latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
WRITE
ACT
PRE
DQM
Hi-Z
DQ
D1
D2
D3
D4
D5
tRP
(tRAS must be satisfied)
Data Sheet E0729N10 (Ver. 1.0)
31
µPD45128163-I-E
13. Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute Power on sequence and CBR (auto) Refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Rating
Unit
VCC, VCCQ
−0.5 to +4.6
V
Voltage on any pin relative to GND
VT
−0.5 to +4.6
V
Short circuit output current
IO
50
mA
Power dissipation
PD
1
W
Operating ambient temperature
TA
−40 to + 85
°C
Storage temperature
Tstg
−55 to + 125
°C
Voltage on power supply pin relative to GND
Caution
Symbol
Condition
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
Condition
VCC, VCCQ
High level input voltage
VIH
Low level input voltage
VIL
Operating ambient temperature
TA
MIN.
TYP.
MAX.
Unit
3.0
3.3
3.6
V
Note1
2.0
−0.3
VCC+0.3
V
+0.8
V
85
°C
Note2
−40
Notes 1. VIH (MAX.) = VCC + 1.5 V (Pulse width ≤ 5 ns)
2. VIL (MIN.) = –1.5 V (Pulse width ≤ 5 ns)
Pin Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Symbol
Condition
MIN.
TYP.
MAX.
Unit
pF
CI1
CLK
2.5
3.5
CI2
A0 - A11, BA0(A13), BA1(A12), CKE,
2.5
3.8
4
6.5
/CS, /RAS, /CAS, /WE, UDQM, LDQM
Data input / output capacitance
32
CI/O
DQ0 - DQ15
Data Sheet E0729N10 (Ver. 1.0)
pF
µPD45128163-I-E
DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Symbol
ICC1
Test condition
/CAS latency
Maximum
×16
Burst length = 1,
CL = 2
110
tRC ≥ tRC (MIN.), Io = 0 mA,
CL = 3
115
Unit
Notes
mA
1
One bank active
Precharge standby current
in power down mode
Precharge standby current
ICC2P
ICC2PS
ICC2N
in non power down mode
CKE ≤ VIL (MAX.), tCK = 15 ns
1
CKE ≤ VIL (MAX.), tCK = ∞
1
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
20
mA
mA
Input signals are changed one time during 30
ns.
ICC2NS
CKE ≥ VIH (MIN.), tCK = ∞,
8
Input signals are stable.
Active standby current
in power down mode
Active standby current
ICC3P
ICC3PS
ICC3N
in non power down mode
CKE ≤ VIL (MAX.), tCK = 15 ns
5
CKE ≤ VIL (MAX.), tCK = ∞
4
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
30
mA
mA
Input signals are changed one time during 30
ns.
ICC3NS
CKE ≥ VIH (MIN.), tCK = ∞ ,
20
Input signals are stable.
Operating current
ICC4
(Burst mode)
CBR (auto) refresh current
ICC5
tCK ≥ tCK (MIN.), Io = 0 mA,
CL = 2
145
All banks active
CL = 3
185
tRC ≥ tRC (MIN.)
CL = 2
230
CL = 3
240
mA
2
mA
3
Self refresh current
ICC6
CKE ≤ 0.2 V
2
mA
Self refresh current
ICC6
CKE ≤ 0.2 V
0.8
mA
(L-version)
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC1 is measured condition that addresses are changed only one time during tCK (MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured condition that addresses are changed only one time during tCK (MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
Data Sheet E0729N10 (Ver. 1.0)
33
µPD45128163-I-E
DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input leakage current
II (L)
0 ≤ VI ≤ VCCQ, VCCQ = VCC
All other pins not under test = 0 V
−1.0
+1.0
µA
Output leakage current
IO (L)
0 ≤ VO ≤ VCCQ, DOUT is disabled
−1.5
+1.5
µA
High level output voltage
VOH
IO = −4 mA
2.4
Low level output voltage
VOL
IO = +4 mA
V
0.4
V
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
Parameter
AC high level input voltage / low level input voltage
Value
Unit
2.4 / 0.4
V
1.4
V
1
ns
1.4
V
Input timing measurement reference level
Transition time (Input rise and fall time)
Output timing measurement reference level
tCK
tCH
CLK
2.4 V
1.4 V
0.4 V
tSETUP tHOLD
Input
2.4 V
1.4 V
0.4 V
tAC
tOH
Output
34
Data Sheet E0729N10 (Ver. 1.0)
tCL
Note
µPD45128163-I-E
Synchronous Characteristics
Parameter
Clock cycle time
Access time from CLK
Symbol
MIN.
MAX.
Unit
/CAS latency = 3
tCK3
7.5
(133 MHz)
ns
/CAS latency = 2
tCK2
10
(100 MHz)
ns
/CAS latency = 3
tAC3
5.4
ns
1
/CAS latency = 2
tAC2
6
ns
1
CLK high level width
tCH
2.5
ns
CLK low level width
tCL
2.5
ns
Data-out hold time
tOH
2.7
ns
Data-out low-impedance time
tLZ
0
ns
/CAS latency = 3
tHZ3
2.7
5.4
ns
/CAS latency = 2
tHZ2
2.7
6
ns
Data-in setup time
tDS
1.5
Data-in hold time
tDH
0.8
ns
Address setup time
tAS
1.5
ns
Address hold time
tAH
0.8
ns
CKE setup time
tCKS
1.5
ns
CKE hold time
tCKH
0.8
ns
CKE setup time (Power down exit)
tCKSP
1.5
ns
Command (/CS, /RAS, /CAS, /WE, DQM)
setup time
Command (/CS, /RAS, /CAS, /WE, DQM)
hold time
tCMS
1.5
ns
tCMH
0.8
ns
Data-out high-impedance time
Note
1
ns
Note 1. Output load
Ω
Data Sheet E0729N10 (Ver. 1.0)
35
µPD45128163-I-E
Asynchronous Characteristics
Parameter
Symbol
MIN.
ACT to REF/ACT command period (operation)
tRC
67.5
ns
REF to REF/ACT command period (refresh)
tRC1
67.5
ns
ACT to PRE command period
tRAS
45
PRE to ACT command period
tRP
20
ns
Delay time ACT to READ/WRITE command
tRCD
20
ns
ACT (one) to ACT (another) command period
tRRD
15
ns
Data-in to PRE command period
tDPL
15
ns
1CLK
ns
Data-in to ACT (REF)
/CAS latency = 3
tDAL3
120,000
Unit
Note
ns
1
+22.5
command period
(Auto precharge)
MAX.
/CAS latency = 2
tDAL2
1CLK
ns
+20
Mode register set cycle time
Transition time
Refresh time (4,096 refresh cycles)
tRSC
2
tT
0.5
tREF
CLK
30
ns
64
ms
Note 1. The –A75 grade device can satisfy the tDAL3 spec of 1CLK+20 ns for up to and including 125MHz operation.
36
Data Sheet E0729N10 (Ver. 1.0)
13.1 AC Parameters for Read Timing (Manual Precharge, Burst Length = 4, /CAS Latency = 3)
T0
tCK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
;;;
;;;
;;;;
;;;
;;
;
;
;
;
;;
;
;
;
;;;;
;;;
;;
;
;
;
;
;;
;
;
;
;;;
;;
;
;
;
;;;
;;
;
;
;
;;;
;;
;
;
;
;;;
;;
;
;
;
;;;
;;
;
;
;
;;;
;;
;
;
;
;;;
;
;
;
;;;
;
;
;
;;;
;
;
;
;;;
;
;
;
;;;
;;;
;
;
;
CLK
tCH
tCL
CKE
tCKH
tCKS
tCMS tCMH
/CS
/RAS
/CAS
BA0
BA1
;;
;
Data Sheet E0729N10 (Ver. 1.0)
/WE
A10
ADD
tAS tAH
LDQM
L
UDQM
L
tLZ
tRCD
tRAS
tAC
tAC
tHZ
tOH
tOH
tOH
tOH
tRP
tRC
37
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
µPD45128163-I-E
DQ
tAC
;
;;
;;
tAC
Hi-Z
38
AC Parameters for Read Timing (Auto Precharge, Burst Length = 4, /CAS Latency = 3)
T0
tCK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
CLK
tCL
;;;;;
;;;;
;;
;;;
;
;;
;
;
;;
;
;;;
;
;;
;
;
;;
;
;;;
;
;
;;
;
;
;;
;;
;
;;
;
;;
;
;
;;
;;
;
;;
;
;;
;
;
;;
;;
;
;;
;
;;
;
;
;
;;
;;
;
;;
;
;;
;
;
;
;
;;
;
;;
;
;
;
;;
;
;;
;
;
;
;;
;
;;
;
;
;
;;
;
;;
;;
;
;;
;
;;
;
;;
;;
;
;;
;
;;
;
;;
;;
;
;;
;
;;
;;
;
;;
;
;;
;
;;
;;
;;
;
;;
;
tCH
CKE
tCKS
Auto Precharge
Start for Bank C
tCMS tCMH
tCKH
/CS
/RAS
/CAS
BA0
BA1
A10
ADD
tAS tAH
LDQM
L
UDQM
L
;;;;
;;;;
;;
Data Sheet E0729N10 (Ver. 1.0)
/WE
tAC
DQ
tAC
tAC
tAC
tHZ
Hi-Z
tLZ
tOH
tOH
tOH
tOH
tRAS
tRRD
tRC
Activate
Command
for Bank C
Read with
Auto Precharge
Command
for Bank C
Activate
Command
for Bank D
Activate
Command
for Bank C
µPD45128163-I-E
tRCD
13.2 AC Parameters for Write Timing (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;;
;
;
;
;
;
;
;
;;;;;;
;;;; ;;;;
;;;; ;;;;
;;;;;;;;;;
CKE
Auto Precharge
Start for Bank C
tCKS
tCMS tCMH
tCKH
;; ;; ;;
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
ADD
tAS tAH
LDQM
L
UDQM
L
tDS tDH
DQ
Hi-Z
tDAL
tRC
tRRD
tDPL
tRCD
tRP
tRAS
tRC
39
Activate
Command
for Bank C
Write with
Activate
Auto Precharge Command
Command
for Bank B
for Bank C
Write
Command
for Bank B
Activate Precharge
Command Command
for Bank C for Bank B
Activate
Command
for Bank B
µPD45128163-I-E
tRCD
µPD45128163-I-E
13.3 Relationship between Frequency and Latency
Speed version
-75
Clock cycle time [ns]
7.5
10
Frequency [MHz]
133
100
/CAS latency
3
2
[tRCD]
3
2
/RAS latency (/CAS latency + [tRCD])
6
4
[tRC]
9
7
[tRC1]
9
7
[tRAS]
6
5
[tRRD]
2
2
[tRP]
3
2
[tDPL]
2
2
[tDAL]
4
3
[tRSC]
2
2
40
Data Sheet E0729N10 (Ver. 1.0)
13.4 Mode Register Set (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
H
tRSC
2 CLK (MIN.)
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
ADDRESS KEY
ADD
LDQM
UDQM
Precharge
All Banks
Command
Mode
Register Set
Command
41
tRP
Activate
Command
is valid
µPD45128163-I-E
Hi-Z
DQ
42
13.5 Power On Sequence and CBR (Auto) Refresh
CLK
Clock cycle is necessary
CKE
tRSC
2 refresh cycles are necessary
;;;;
;;;;
;;
;
;;
;;
;
;
;;
;
;
;
;;
;
;;
;;
;
;
;
;;
;
;;
;
;;
;
;
;;
;
;;
;
;;
;
;
;;
;
;;
;
;;
;
;
;;
;
;
;;
;;
;
;
;;
;
;;
;;
;
;
;
;;
;
;;
;
;;
;
;
;;
;
;;
;
;;
;
;
;;
;
;;
;
;;
;
;
;;
;
;;
;
;;
;;
;;
;
;
;
;;
;
;
;
;;
;;
;
;
;;
;
;
;
;;
;
;;
;;
;;
;
;;
;
;
;;
;
;;
;
;;
;
;
;;
;
High level is necessary
/CS
/RAS
/CAS
/WE
Data Sheet E0729N10 (Ver. 1.0)
BA0
BA1
A10
ADDRESS KEY
ADD
LDQM
UDQM
High level is necessary
Hi-Z
DQ
Mode
Register Set
Command
is necessary
tRP
CBR (Auto)
Refresh
Command
is necessary
CBR (Auto)
Refresh
Command
is necessary
tRC1
Activate
Command
tRC1
µPD45128163-I-E
Precharge
All Banks
Command
is necessary
13.6 /CS Function (Burst Length = 4, /CAS Latency = 3)
Only /CS signal needs to be issued at minimum rate
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
H
/CS
/RAS
Data Sheet E0729N10 (Ver. 1.0)
/CAS
/WE
BA0
L
BA1
L
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
CAa
QAa1
DQ
Activate
Command
for Bank A
Read
Command
for Bank A
QAa2 QAa3
QAa4
DAb1
Write
Command
for Bank A
DAb2
DAb3
DAb4
Precharge
Command
for Bank A
43
µPD45128163-I-E
Hi-Z
CAb
44
13.7 Clock Suspension during Burst Read (using CKE Function) (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
;;;
;;;;;;
;;
;;;
;
;;
;;
;
;;
;;;
;
;;
;;
;
;;
;;;
;
;;
;;
;
;;
;;;
;
;;
;;
;
;;
;;;
;
;;
;;
;
;;
;;;
;
;;
;;
;
;;
;;;
;
;;
;;
;
;;
;;;
;
;;
;;
;
;;
;;;
;
;;
;;
;
;;
;;;
;
;;
;;
;
;;
;;;
;
;;
;;
;
;;
;;;
;
;;
;;
;
;;
;;;
;
;;
;;
;
;;
;
;;
;
;;
;;
;
;;;
;;
;;;
;
;
;;
;;
;
;;
;
;;
;
;;
;;;
;
;;
;;;
;
;;
;
;;
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
CAa
QAa1
Activate
Command
for Bank A
Read
Command
for Bank A
QAa2
QAa3
1-CLOCK
SUSPENDED
QAa4
2-CLOCK
SUSPENDED
3-CLOCK
Hi-Z (turn off)
SUSPENDED at the end of burst
µPD45128163-I-E
Hi-Z
DQ
Clock Suspension during Burst Read (using CKE Function) (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
;;;
;;;;;;
;;;
;
;;
;;
;;
;
;;;
;
;;
;;
;;
;
;;;
;
;;
;;
;;
;
;;;
;
;;
;;
;;
;
;;;
;
;;
;;
;;
;
;;;
;
;;
;;
;;
;
;;;
;
;;
;;
;;
;
;;;
;
;;
;;
;;
;
;;;
;
;;
;;
;;
;
;;;
;
;;
;;
;;
;
;;;
;
;;
;;
;;
;
;;;
;
;;
;;
;;
;
;;
;;
;;
;
;;;
;
;
;;;
;
;;
;
;;
;;
;;
;
;
;;
;;
;;
;
;;;
;
;;;
;
;
;;
;;
;
;;
;;;
;
;;
;;
;
;;
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
CAa
QAa1
Activate
Command
for Bank A
Read
Command
for Bank A
QAa2
1-CLOCK
SUSPENDED
QAa3
QAa4
2-CLOCK
SUSPENDED
3-CLOCK
SUSPENDED
Hi-Z (turn off)
at the end of burst
45
µPD45128163-I-E
Hi-Z
DQ
46
13.8 Clock Suspension during Burst Write (using CKE Function) (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
;;;;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
Hi-Z
Activate
Command
for Bank A
DAa1
DAa2
Write
1-CLOCK
Command SUSPENDED
for Bank A
DAa3
2-CLOCK
SUSPENDED
DAa4
3-CLOCK
SUSPENDED
µPD45128163-I-E
DQ
CAa
Clock Suspension during Burst Write (using CKE Function) (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
;;;;
;;;;;
;;;
;;
;
;;
;;
;
;;;
;;
;
;;
;;
;
;;;
;;
;
;;
;;
;
;;;
;;
;
;;
;;
;
;;;
;;
;
;;
;;
;
;;;
;;
;
;;
;;
;
;
;;;
;;
;
;;
;;
;
;
;;;
;;
;
;;
;;
;
;
;;;
;;
;
;;
;;
;
;
;;;
;;
;
;;
;;
;
;
;;;
;;
;
;;
;;
;
;;;
;;
;
;;
;;
;
;
;;
;;
;;
;
;;;
;
;
;
;;;
;
;
;
;;
;;
;;
;;
;
;;
;;
;;
;
;;;
;
;
;;;
;
;
;;
;;
;
;;
;;;
;;
;
;;
;
;;
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
CAa
DAa1
Activate
Command
for Bank A
DAa2
Write
1-CLOCK
Command SUSPENDED
for Bank A
DAa3
2-CLOCK
SUSPENDED
DAa4
3-CLOCK
SUSPENDED
47
µPD45128163-I-E
Hi-Z
DQ
48
13.9 Power Down Mode and Clock Mask (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
tCKSP
tCKSP
CKE
;;;
;;;;;;;;;
;
;;
;;;;;;;;;
;
;;
;;;;;;;;;
;;
;
;;;;;;;;;
;;
;
;;;;;;;;;
;
;
;;;;;;;;;
;;
;
;;;;;;;;;
;
;;;;;;;;
;;;
VALID
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
CAa
Hi-Z
QAa1 QAa2 QAa3
DQ
Read
Command
for Bank A
Power Down
Mode Entry
Power Down
Mode Exit
ACTIVE STANDBY
Precharge
Command
for Bank A
Clock Mask
Start
Clock Mask
End
Power Down
Mode Entry
Power Down
Mode Exit
PRECHARGE STANDBY
µPD45128163-I-E
Activate
Command
for Bank A
QAa4
13.10 CBR (Auto) Refresh
T0
T1
T2
T3
T4
T5
T6
Tn
Tn + 1 Tn + 2
Tn + 3 Tn + 4 Tn + 5 Tn + 6
Tm
Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tm + 6 Tm + 7
CLK
H
CKE
;;;;;
;;;;
;;
;;
;;
;;;
;
;
;;
;;
;;
;;;
;
;
;
;;
;;
;;
;;;
;
;;
;;
;;
;;;
;
;
;;
;;
;;;
;;
;
;
;;
;;
;;;
;;
;
;
;;
;;;
;;
;;
;
;
;;;
;;
;;
;;
;
;
;;;
;;
;;
;;
;
;
;;
;;
;;
;;;
;
;
;;
;;
;;
;;;
;
;
;;
;;
;;
;;;
;
;
;;
;;
;;
;;;
;
;
;;
;;
;;
;;;
;
;
;;
;;
;;
;;;
;;
;
;
;;
;;
;;
;
;;
;;
;;;;;;;;
;;
;
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
ADD
LDQM
L
UDQM
L
DQ
Hi-Z
Q1
49
tRP
CBR (Auto) Refresh
tRC1
Activate
Command
tRC1
Read
Command
µPD45128163-I-E
Precharge CBR (Auto) Refresh
Command
(if necessary)
50
13.11 Self Refresh (Entry and Exit)
T1
T2
T3
T4
Tn
Tn + 1 Tn + 2
Tm
Tm + 1
Tk
Tk + 1 Tk + 2 Tk + 3 Tk + 4
;;
;;;;
;;;;
;
;;
;
;;
;;
;
;
;
;;
;
;;
;;
;
;
;
;;
;;
;
;
;
;;
;
;
;;
;;
;
;
;;
;
;
;;
;;;;
;
;
;;
;
;
;;
;;
;
;
;;
;
;;
;
;;;;
;
;
;;
;
;;
;
;;
;
;
;;
;
;
;;
;;
;
;
;;
;
;
;;
;;;
;
;
;;
;
;
;;
;;
;
;
;;
;;;;;;
;
;
;;
;
;
;;
;
;
;;
;;
;
;
;
;;
;;
;
;;
;
;
;
;;
;;
;
;;
;
;
;
;;
;;
;
;;
;
;
;
;;
T0
CLK
CKE
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
ADD
LDQM
L
UDQM
L
Hi-Z
DQ
Self Refresh
Entry
Self Refresh Self Refresh
Entry
Exit
(or Activate Command)
Self Refresh
Exit
Activate
Command
Next Clock
Enable
Next Clock
Enable
tRP
tRC1
tRC1
µPD45128163-I-E
Precharge
Command
(if necessary)
13.12 Random Column Read (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2)
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;
;;;;;;;
;
;;
;
;;
;
;
;
;;
;
;
;;;;
;
;
;;
;;
;
;
;
;
;;;;;;
;
;
;;
;
;
;
;
;;
;;
;
;
;;;;
;
;
;;
;
;
;;
;
;;
;
;
;
;
;
;;
;;;;
;
;;;;
;;;;;;;;;;
;;;;;;
;
;
;
;;
;
;
;;
;
;
;;;;
;;
;
;
;;
;
;
;;
;
;
;
;;
;;;;
;
;
;
;;;;;;;;;
;;;;;
;;;;
T0
CLK
H
CKE
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
RAd
CAa
QAa1
DQ
Activate
Command
for Bank A
Read
Command
for Bank A
QAa2
QAa3
Read
Command
for Bank A
CAc
QAa4
QAb1
Read
Command
for Bank A
RAd
QAb2
QAc1
QAc2
QAc3
Precharge
Command
for Bank A
CAd
QAd1
QAc4
Activate
Command
for Bank A
Read
Command
for Bank A
QAd2
QAd3
51
µPD45128163-I-E
Hi-Z
CAb
52
Random Column Read (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;
CLK
H
CKE
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
RAa
QAa1
Read
Command
for Bank A
QAa2
Read
Command
for Bank A
CAc
QAa3
QAa4
Read
Command
for Bank A
QAb1
QAb2
QAc1
QAc2
Precharge
Command
for Bank A
QAc3
RAa
CAa
Activate
Command
for Bank A
Read
Command
for Bank A
QAc4
µPD45128163-I-E
Hi-Z
DQ
Activate
Command
for Bank A
CAb
CAa
13.13 Random Column Write (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2)
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;
;;;;;
;;;;
;
;
;;
;
;;
;
;;
;
;
;;
;;;;
;
;
;;
;
;
;;
;;
;
;
;;
;
;;;;;;
;
;;
;
;
;;
;
;
;
;;
;;
;
;;
;
;;;;
;
;;
;;
;
;
;
;;
;
;;
;
;
;;
;
;;;;
;
;
;;
;
;;
;;;;;;
;;;;
;;;;;;;;;;
;
;
;;
;;
;
;;
;
;
;
;;
;
;;;;
;;
;
;
;
;;
;;
;
;;
;
;
;
;;
;;;;
;
;
;
;;
;;;;
;;;;;
;;;;;;;
;;
;;;;
T0
CLK
CKE
H
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RDa
ADD
RDa
LDQM
L
UDQM
L
Hi-Z
Activate
Command
for Bank D
CDa
DDa1
CDb
DDa2
Write
Command
for Bank D
DDa3
DDa4
DDb1
CDc
DDb2
Write
Command
for Bank D
DDc1
Write
Command
for Bank D
RDd
DDc2
DDc3
DDd1
DDc4
Precharge
Command
for Bank D
CDd
Activate
Command
for Bank D
Write
Command
for Bank D
DDd2
DDd3
DDd4
53
µPD45128163-I-E
DQ
RDd
54
Random Column Write (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
CLK
CKE
H
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RDa
ADD
RDa
L
UDQM
L
DQ
Hi-Z
Activate
Command
for Bank D
CDa
DDa1
Write
Command
for Bank D
CDb
DDa2
DDa3
DDa4
DDb1
CDc
DDb2
Write
Command
for Bank D
DDc1
Write
Command
for Bank D
RDd
DDc2
DDc3
DDc4
Precharge
Command
for Bank D
CDd
DDd1 DDd2
Activate
Command
for Bank D
Write
Command
for Bank D
µPD45128163-I-E
LDQM
RDd
13.14 Random Row Read (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;;
;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
CLK
H
CKE
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RDa
ADD
RDa
LDQM
L
UDQM
L
CDa
Hi-Z
Activate
Command
for Bank D
RBa
CBa
RDb
QDa1 QDa2 QDa3 QDa4 QDa5 QDa6 QDa7 QDa8 QBa1
Read
Command
for Bank D
Activate
Command
for Bank B
Read
Command
for Bank B
55
Precharge
Command
for Bank D
QBa2 QBa3 QBa4
Activate
Command
for Bank D
CDb
QBa5 QBa6 QBa7
QBa8
Read
Command
for Bank D
µPD45128163-I-E
DQ
RDb
RBa
56
Random Row Read (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 3)
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;
;;;;
;;
;;;
;
;;
;;
;;
;
;
;;
;
;
;
;
;
;
;;
;;
;
;;
;
;
;
;;
;;
;
;;
;
;
;
;
;
;;
;;
;
;;
;
;
;
;;
;;
;
;
;;
;
;
;
;;
;
;
;;
;;
;
;;
;
;
;;
;;
;;
;
;
;;
;
;
;;
;;
;
;
;;
;
;
;
;;
;;
;
;
;;
;
;
;
;;
;;
;
;
;;
;
;
;
;;
;;
;
;
;;
;
;
;
;;
;;
;
;
;;
;
;
;
;
;;
;;
;;
;
;
;
;
;;
;
;;
;
;;
;
;
;
;;
;
;;
;
;
;
;;
;
;
;;
;
;;
;
;;
;
;
T0
CLK
CKE
H
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RBa
ADD
RBa
LDQM
L
UDQM
L
CBa
Hi-Z
Activate
Command
for Bank B
RAa
QBa1 QBa2
Read
Command
for Bank B
QBa3 QBa4
Activate
Command
for Bank A
CAa
QBa5 QBa6
Read
Command
for Bank A
RBb
QBa7 QBa8
Precharge
Command
for Bank B
QAa1 QAa2 QAa3 QAa4
Activate
Command
for Bank B
CBb
QAa5 QAa6 QAa7
Read
Command
for Bank B
Precharge
Command
for Bank A
µPD45128163-I-E
DQ
RBb
RAa
13.15 Random Row Write (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;;;;;
;;;;;;
;;
;
;;
;
;;;;;;;;
;;
;;
;;
;
;
;;
;;
;
;;;;;
;;
;
;;
;;
;
;;
;
;;
;;
;
;;;;
;;
;;;;;;;
;
;;
;;
;
;
;;
;;
;
;;;;
;;
;;;
;;
;;
;
;
;;
;
;
;
;;
;;
;;
;
;;;;;
;;
;;
;;
;
;
;
;;
;
;
;;
;;
;
;;;;
;;
;;;
;
;;
;;
;
;
;;
;
;
;;
;;
;
;;;;
;
;;
;;;
;
;;
;;
;
;
;;
;
;;
;
;;;;
;;;;;;
;;;
;;
;
;;
;
CLK
H
CKE
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
Hi-Z
Activate
Command
for Bank A
CAa
DAa1
RAb
RDa
DAa2
Write
Command
for Bank A
DAa3
DAa4
DAa5
DAa6
DAa7
RAb
CDa
DAa8
Activate
Command
for Bank D
DDa1 DDa2
DDa3 DDa4
Write
Command
for Bank D
57
Precharge
Command
for Bank A
CAb
DDa5
Activate
Command
for Bank A
DDa6 DDa7 DDa8
DAb1
DAb2
DAb3
Write
Command
for Bank A
Precharge
Command
for Bank D
µPD45128163-I-E
DQ
RDa
58
Random Row Write (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
;;;
;;;;;
;;;;;
;
;
;
;;
;;
;
;
;;
;;;;;;
;
;;
;;
;
;;
;;
;
;;
;;;;;;
;;
;;;;;;
;;
;
;;;;
;;
;
;
;;
;;
;
;
;
;;
;;
;
;;;;;
;
;;
;
;
;;
;;
;
;
;;
;;
;
;
;;;;;
;;;
;
;;
;;
;
;;
;
;
;
;;
;;
;;
;
;;
;;;;;
;;
;;
;
;;
;
;
;
;
;;
;;
;
;;
;;;;
;;;
;;
;
;;
;
;
;;
;
;;
;;
;;
;
;
;
;;
;;;;;
;
;;
;;
;
;
;;
;
;;
;
;;
;
;;;;
;;;;;;
;;;
;;
;
;;
H
CKE
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
Hi-Z
Activate
Command
for Bank A
RDa
CAa
DAa1
DAa2
Write
Command
for Bank A
DAa3
DAa4
DAa5
DAa6
CDa
DAa7
Activate
Command
for Bank D
DAa8
RAb
DDa1 DDa2
Write
Command
for Bank D
DDa3
Precharge
Command
for Bank A
DDa4 DDa5 DDa6
Activate
Command
for Bank A
CAb
DDa7 DDa8 DAb1
Write
Command
for Bank A
DAb2
Precharge
Command
for Bank D
µPD45128163-I-E
DQ
RAb
RDa
13.16 Read and Write (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
H
;;
;;;;;;
;
;;
;;
;
;
;
;
;;
;;
;
;
;
;
;;
;;
;
;
;
;
;;
;;
;
;
;
;
;;
;;
;
;
;
;;
;
;
;;
;
;
;
;;
;
;;;;;;;;;;
;
;;
;;;
;;
;
;
;
;
;;
;;
;
;
;
;
;;
;;
;
;
;
;
;;
;;
;
;
;
;
;;
;;
;
;
;
;
;
;
;
;;
;
;;
;
;
;
;;
;
;;
;;
;
;
;;
;
;
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
CAa
CAb
CAc
Write Latency = 0
LDQM
L
Word Masking
UDQM
L
Word Masking
DQ
(Upper)
Hi-Z
Activate
Command
for Bank A
Read
Command
for Bank A
QAa1
QAa2
QAa3
QAa4
DAb1
DAb2
DAb4
QAc1 QAc2
QAc4
QAa1
QAa2
QAa3
QAa4
DAb1
DAb2
DAb4
QAc1
QAc2
QAc4
Write
Command
for Bank A
59
Hi-Z at the end of wrap function
Read
Command
for Bank A
0-Clock Latency
2-Clock Latency
µPD45128163-I-E
DQ
(lower)
Hi-Z
60
Read and Write (2/2) (Burst Length = 4, /CAS Latency = 3)
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;;;;;;
;;
;;
;
;
;
;;
;
;;;;
;
;
;
;;
;
;;
;
;
;
;;
;
;;;;
;
;
;
;;
;
;;
;
;
;
;;
;
;;;;
;
;
;
;;
;
;
;
;
;
;;
;
;;;;
;
;;
;
;;;
;
;
;;
;
;
;
;;
;
;;;;
;
;
;
;;
;
;;
;
;
;
;;
;
;;;;
;
;
;
;;
;
;;
;
;;
;
;
;
;;;;
;
;
;
;;
;
;
;
;;
;
;;
;
;;;;
;
;
;;
;
;
T0
CLK
CKE
H
/CS
/RAS
/CAS
/WE
Data Sheet E0729N10 (Ver. 1.0)
BA0
BA1
A10
RAa
ADD
RAa
LDQM
CAb
CAa
CAc
Write Latency = 0
L
Word Masking
L
DQ
(lower)
Hi-Z
DQ
(upper)
Hi-Z
Activate
Command
for Bank A
Read
Command
for Bank A
QAa1
QAa2
QAa3
QAa4
DAb1
DAb2
DAb4
QAc1
QAc2
QAa1
QAa2
QAa3
QAa4
DAb1
DAb2
DAb4
QAc1
QAc2
Write
Command
for Bank A
Hi-Z at the end of wrap function
Read
Command
for Bank A
0-Clock Latency
2-Clock Latency
µPD45128163-I-E
UDQM
13.17 Interleaved Column Read Cycle (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
H
CKE
/CS
;;;;
;;;;
;;
;;;;
;
;;
;
;
;;
;;
;
;
;;
;
;;
;;;;
;
;;
;
;;;;;;
;;;;
;;;;
;;
;;
;;;
;
;
;;
;
;
;;
;
;;;
;;
;
;;
;;
;
;;;
;
;;
;
;;;;;
;;;;
;;;;
;;;;
;;;
;
;
;;;;
;;
;;;;
;;;
;;;;
;
;
;;
;;
;
;;;
;;;;;;
;;;;
;;;;
;;
;;;
;;
;;
;
;;
;
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
RDa
CAa
Aa1
Activate
Command
for Bank A
Read
Command
for Bank A
61
Activate
Command
for bank D
Aa2
Aa3
Read
Command
for Bank D
Aa4
Da1
Read
Command
for Bank D
Da2
Db1
Read
Command
for Bank D
Db2
Dc1
Read
Command
for Bank A
Dc2
Ab1
Ab2
Read
Command
for Bank D
Precharge
Command
for Bank A
Dd1
Dd2
Dd3
Precharge
Command
for Bank D
Dd4
µPD45128163-I-E
Hi-Z
DQ
CDd
CAb
CDc
CDb
CDa
RDa
62
Interleaved Column Read Cycle (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;;;;
;
;;;;;;
;;
;
;
;;
;;
;
;;
;
;;
;;
;
;
;;;;;
;;
;
;;
;
;
;;
;;
;
;;
;
;;
;;
;
;;;;;
;;
;;
;
;
;
;;
;;;
;
;;;;;;
;;
;
;;;;
;;
;
;;
;
;
;;
;;
;
;;
;;
;;
;
;
;
;;;;;
;;
;;
;
;;
;
;;
;
;
;;
;;
;;
;
;
;;;;;
;;
;;
;;
;
;;
;
;
;;
;
;;;;;
;;
;;
;
;
;;
;;
;
;;
;
;;
;;
;
;;;;;
;;
;
;
;;
;;
;
;;
;;;;
;;;
;
;;
;;
;
;;
CLK
CKE
H
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
CAa
RDa
Hi-Z
Activate
Command
for Bank A
CDa
Aa1
Read
Command
for Bank A
Activate
Command
for Bank D
Aa2
Read
Command
for Bank D
CDb
Aa3
Aa4
Read
Command
for Bank D
CAb
CDc
Da1
Da2
Read
Command
for Bank D
Db1
Db2
Dc1
Dc2
Ab1
Ab2
Read
Command
for Bank A
Precharge
Command
for Bank D
Precharge
Command
for Bank A
Ab3
Ab4
µPD45128163-I-E
DQ
RDa
13.18 Interleaved Column Write Cycle (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;
;
;;;;;;;;;;;;
CLK
CKE
H
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
Activate
Command
for Bank A
CAa
Aa1
Write
Command
for Bank A
Aa2
Aa3
Activate
Command
for Bank B
Aa4
Ba1
Write
Command
for Bank B
Ba2
Bb1
Write
Command
for Bank B
Bb2
Bc1
Write
Command
for Bank B
CBd
CAb
CBc
CBb
CBa
RBa
Bc2
Ab1
Write
Command
for Bank A
Ab2
Bd1
Write
Command
for Bank B
Bd2
Bd3
Bd4
Precharge
Command
for Bank A
63
Precharge
Command
for Bank B
µPD45128163-I-E
Hi-Z
DQ
RBa
64
Interleaved Column Write Cycle (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;;;;;;;;;;
;;
;;
;
;
;
;;;;;
;;
;
;
;;;
;
;;
;
;;
;
;
;
;
;
;;;;
;;
;
;
;
;
;;
;
;
;
;;
;;;;
;;
;
;;;
;
;;
;
;
;;
;;
;
;
;;;;;;;;;;
;;
;
;;
;;
;
;
;;
;
;;
;;;;;
;
;;
;
;
;;
;
;;
;;
;
;
;;;;;;
;;
;
;;
;
;
;
;;
;;
;;
;
;;
;
;;;;;;
;;
;;
;
;;
;
;;
;;
;;;;;
;;
;;
;
;;;;;
;;
;;
CLK
CKE
H
/CS
/RAS
/CAS
;;
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
Hi-Z
Activate
Command
for Bank A
CAa
RBa
Aa1
Aa2
Write
Command
for Bank A
Activate
Command
for Bank B
CBa
Aa3
Aa4
Ba1
Write
Command
for Bank B
CBb
Ba2
Bb1
Write
Command
for Bank B
Bb2
Bc1
Write
Command
for Bank B
CBd
CAb
CBc
Bc2
Ab1
Write
Command
for Bank A
Ab2
Bd1
Bd2
Bd3
Bd4
Write
Command
for Bank B
Precharge
Command
for Bank A
Precharge
Command
for Bank B
µPD45128163-I-E
DQ
RBa
13.19 Auto Precharge after Read Burst (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;;
;;;
;;;;;
;
;;
;
;
;;
;;
;
;;;;
;;
;;;
;
;;
;;
;
;;
;
;
;;
;
;;
;;;;
;;
;;;
;
;;
;
;;
;;
;
;
;
;
;;
;;
;;;;
;;
;;;
;;
;
;;
;
;
;;
;
;;
;;
;
;
;
;;;;
;;
;;;
;;
;
;;
;
;
;;
;
;
;;
;;
;
;;;;
;;
;;;
;
;;
;;
;
;;
;
;
;
;
;;
;;
;;;;
;;
;
;
;;;
;
;;
;;
;;
;
;
;
;;
;
;;
;
;;;;
;;
;;;
;
;;
;;
;
;
;;
;
;
;;
;;
;
;
;;;;
;;;
;;
;
;;
;
;;
CLK
CKE
H
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
CAa
RDa
RDb
CDa
CAb
RDb
RAc
CDb
RAc
CAc
Hi-Z
Activate
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank D
Read with
Auto Precharge
Command
for Bank D
65
Read with
Auto Precharge
Command
for Bank A
Auto Precharge
Start for Bank D
Activate
Command
for Bank D
Activate
Command
Read with
Read with for Bank A
Auto Precharge
Auto Precharge
Command
Command
for Bank A
for Bank D
Auto Precharge
Auto Precharge
Start for Bank A
Start for Bank D
µPD45128163-I-E
DQ
RDa
66
Auto Precharge after Read Burst (2/2) (Burst Length = 4, /CAS Latency = 3)
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;;;;;;
;;
;
;
;
;
;;;;
;
;
;
;
;;
;
;
;
;
;;;;
;
;
;
;
;;
;
;
;
;
;
;;;;
;
;
;
;;;;;;;;;;
;;;;
;;
;
;
;
;
;
;;;;
;
;
;
;
;;
;
;
;
;;;;
;
;
;
;
;
;;
;
;
;
;;;;
;
;
;
;
;;;;;;;;;;
;;;;
T0
CLK
CKE
H
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
DQ
RDa
CAa
RDa
RDb
CDa
CAb
RDb
CDb
Hi-Z
Activate
Command
for Bank D
Read
Command
for Bank A
Read with
Auto Precharge
Command
for Bank D
Read with
Auto Precharge
Command
for Bank A
Auto Precharge
Start for Bank D
Activate
Command
for Bank D
Read with
Auto Precharge
Command
for Bank D
Auto Precharge
Start for Bank A
µPD45128163-I-E
Activate
Command
for Bank A
13.20 Auto Precharge after Write Burst (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;;
;;;;
;;;;
;
;;
;
;;
;
;;
;
;;;;
;;
;;;
;;
;
;;
;
;;
;
;
;;
;
;;
;;;;
;;
;;;
;
;
;;
;;
;;
;
;
;
;;
;
;;
;;;;
;;
;;;
;;
;
;;
;
;
;;
;
;;
;
;;
;
;
;;;;
;;
;;;
;;
;
;;
;
;
;;
;
;;
;
;;
;
;;;;
;;
;;;
;;
;
;;
;
;;
;
;
;
;;
;
;;
;;;;
;;
;
;
;;;
;;
;
;;
;
;
;;
;
;;
;
;;
;
;;;;
;
;
;;
;;;
;;
;
;;
;
;
;;
;
;;
;
;;
;;;;
;;;
;;
;
;;
;
;
;;
CLK
CKE
H
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
DQ
RDa
CAa
RDa
RDb
CDa
CAb
RDb
RAc
CDb
RAc
CAc
Hi-Z
Activate
Command
for Bank D
Write
Command
for Bank A
Activate
Command
for Bank D
Write with
Auto Precharge
Command
for Bank D
Write with
Auto Precharge
Command
for Bank A
Activate
Command
for Bank A
67
Write with
Write with
Auto Precharge
Auto Precharge
Command
Command
for Bank D
for Bank A
Auto Precharge
Auto Precharge
Auto Precharge
Start for Bank D
Start for Bank A
Start for Bank D
µPD45128163-I-E
Activate
Command
for Bank A
68
Auto Precharge after Write Burst (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
;;;
;;;;
;;;
;
;
;;
;
;;
;;;;
;
;;;
;
;;
;;
;
;
;;
;
;;
;;;;
;
;
;;;
;;
;
;;
;
;
;;
;
;;
;
;;;;
;
;;;
;;
;
;;
;;
;;
;
;
;
;
;;;;
;
;;;
;;
;
;;
;
;
;;
;
;;
;;;;
;
;;;
;;
;
;;
;
;
;;
;
;;
;;;;
;
;;;
;;
;
;;
;
;
;;
;
;;
;;;;
;
;;;
;;
;
;;
;
;
;;
;
;;
;;;;
;;;
;;
;
;;
;
CKE
H
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
DQ
RDa
CAa
RDa
RDb
CDa
CAb
RDb
CDb
Hi-Z
Activate
Command
for Bank D
Write
Command
for Bank A
Write with
Auto Precharge
Command
for Bank D
Write with
Auto Precharge
Command
for Bank A
Auto Precharge
Start for Bank D
Activate
Command
for bank D
Auto Precharge
Start for Bank A
Write with
Auto Precharge
Command
for Bank D
µPD45128163-I-E
Activate
Command
for Bank A
13.21 Full Page Read Cycle (1/2) (/CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13
;;;;;;
;;;;;;;;;;;;
;
;
;
;
;;;;;;;
;
;
;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
CLK
H
CKE
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
CAa
Hi-Z
Activate
Command
for Bank A
RDa
Aa
Read
Command
for Bank A
69
Note: m is Full page burst length.
RDb
Activate
Command
for Bank D
CDa
Aa+1
Aa+2
Aa+m-2 Aa+m-1
Aa
Read
Command
for Bank D
RDb
Aa+1
Da
Da+1
Da+2
Da+3
Da+4
Burst Stop Command
Da+5
Da+6
Precharge
Command
for Bank D
Activate
Command
for Bank D
µPD45128163-I-E
DQ
RDa
70
Full Page Read Cycle (2/2) (/CAS latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12
CLK
;;;;;
;;;;;;;;;;
;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;
;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
CKE
H
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
DQ
RDa
CAa
RDa
Hi-Z
Note: m is Full page burst length.
CDa
Aa
Read
Command
for Bank A
Activate
Command
for Bank D
Aa+1
Aa+m-3 Aa+m-2 Aa+m-1
Read
Command
for Bank D
RDb
Aa
Aa+1
Da
Da+1
Da+2
Da+3
Burst Stop Command
Da+4
Da+5
Precharge
Command
for Bank D
Activate
Command
for Bank D
µPD45128163-I-E
Activate
Command
for Bank A
RDb
13.22 Full Page Write Cycle (1/2) (/CAS latency = 2)
T0
T1
T2
T3
T4
T5
Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13 Tn + 14 Tn + 15
;;;;;;;
;;
;
;;
;;
;
;;
;
;;
;
;;
;;;;;
;;
;
;;
;;
;
;;
;
;;
;
;;;;
;
;;
;;;;;;
;;;
;;
;
;;
;
;
;;
;;
;;;;
;
;;
;;;
;
;;
;;
;
;;
;
;
;;
;;
;;;;
;
;;
;;;
;
;;
;;
;
;;
;;
;
;;
;
;;
;;;;;
;
;;
;;
;
;;
;
;;
;;
;
;;
;
;;
;
;;;;;
;
;;
;;
;
;;
;
;
;;
;
;;
;
;;
;;;;
;
;;
;
;;;;;;;
;;
;
;;
;
;;
;
;;
;
;;;;
;;;
;;
;
;;
;
;;
CLK
CKE
H
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
DQ
RDa
CAa
Hi-Z
Write
Command
for Bank A
71
Note: m is Full page burst length.
RDa
Aa+1
Aa+2
Activate
Command
for Bank D
CDa
Aa+m-2
Aa+m-1
Aa
Aa+1
Da
RDb
Da+1
Da+2
Da+3
Da+4
Da+5
Precharge
Command
for Bank D
Write
Command
for Bank D
Burst Stop Command
Activate
Command
for Bank D
µPD45128163-I-E
Activate
Command
for Bank A
Aa
RDb
72
Full Page Write Cycle (2/2) (/CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13
CLK
;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
CKE
H
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
DQ
Hi-Z
Note: m is Full page burst length.
CAa
Aa
RDb
RDa
Aa+1
Write
Command
for Bank A
Aa+2
Activate
Command
for Bank D
CDa
Aa+3
Aa+m-1
Aa
Da
Aa+1
RDb
Da+1
Da+2
Da+3
Da+4
Da+5
Write
Command
for Bank D
Precharge
Command
for Bank D
Burst Stop Command
Burst is not completed
in the Full Page Mode
Activate
Command
for Bank D
µPD45128163-I-E
Activate
Command
for Bank A
RDa
13.23 Byte Write Operation (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
;;; ;;
;
;
;
;;;;;; ;;;
;;;
;
;
;;;;;; ;;;;
;;;
;;;;;; ;
;
;;;;;; ;
;
;;;;;; ;;;;
;
;
;;;;;; ;;;
;;;
;
;;;;;; ;;;
;
;
;
;;;;;; ;;;;
;;;
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
ADD
LDQM
UDQM
DQ
(upper)
73
Activate
Command
for Bank D
Read
Command
for Bank D
Upper Byte
not Read
Lower Byte Upper Byte Lower Byte
not Write
not Write
not Write
µPD45128163-I-E
DQ
(lower)
74
Byte Write Operation (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
;;; ;;
;
;
;
;;;;;; ;;;;
;;;
;
;;;;;; ;;;
;
;;;;;; ;;;;
;;;;;; ;
;
;
;;;;;; ;;;;
;;;
;
;;;;;; ;;;
;
;
;;;;;; ;;;
;
;
;;;;;; ;;;
;;;
;
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
ADD
LDQM
UDQM
DQ
(upper)
Activate
Command
for Bank D
Read
Command
for Bank D
Upper
Byte
not Read
Lower
Byte
not Read
Lower
Byte
not Write
Upper
Byte
not Write
Lower
Byte
not Write
Read
Command
for Bank D
Lower
Byte
not Read
Lower
Byte
not Read
µPD45128163-I-E
DQ
(lower)
13.24 Burst Read and Single Write (Option) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
H
;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;
;;;;;;;;;;;
;;;;;;;;;;;;
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
ADD
LDQM
UDQM
Hi-Z
DQ
(upper)
Hi-Z
75
Activate
Command
for Bank D
Read
Command
for Bank D
Qa1
Qa2
Qa3
Qa4
D1
Qb1
Qb2
Qb4
D2
Qa1
Qa2
Qa3
Qa4
D1
Qb1
Qb2
Qb4
D2
Single
Write
Command
for Bank D
Single
Write
Command
for Bank D
Read
Command
for Bank D
Single
Write
Command
for Bank D
µPD45128163-I-E
DQ
(lower)
76
Burst Read and Single Write (Option) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
H
;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;
;;;;;;;;;;;
;;;;;;;;;;;;
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
ADD
LDQM
UDQM
DQ
(upper)
Hi-Z
Hi-Z
Activate
Command
for Bank D
Read
Command
for Bank D
Qa1
Qa2
Qa3
Qa4
D1
Qb1
Qb2
Qb4
Qa1
Qa2
Qa3
Qa4
D1
Qb1
Qb2
Qb4
Single
Write
Command
for Bank D
Single
Write
Command
for Bank D
Read
Command
for Bank D
µPD45128163-I-E
DQ
(lower)
13.25 Full Page Random Column Read (Burst Length = Full Page, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
CKE
H
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
RDa
ADD
RAa
RDa
LDQM
L
UDQM
L
DQ
CAa
CDa
Hi-Z
Activate
Command
for Bank D
Read
Command
for Bank A
CDb
CAc
QAa1 QDa1
QAb1 QAb2
QDb1 QDb2
Read
Command
for Bank A
77
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank A
CDc
QAc1
QAc2
Read
Command
for Bank D
QAc3
QDc1
QDc2
QDc3
Precharge
Command
for Bank D
(PRE Termination of Burst)
µPD45128163-I-E
Activate
Command
for Bank A
CAb
78
Full Page Random Column Read (Burst Length = Full Page, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
CKE
H
/CS
/RAS
/CAS
Data Sheet E0729N10 (Ver. 1.0)
/WE
BA0
BA1
A10
RAa
RDa
ADD
RAa
RDa
LDQM
L
UDQM
L
DQ
CAa
CDa
CAb
Hi-Z
QAa1 QDa1
Activate
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank D
Read
Command
for Bank D
CDc
CAc
QAb1 QAb2
Read
Command
for Bank A
QDb1 QDb2
QAc1
Read
Command
for Bank D
QAc2
QAc3
QDc1
QDc2
QDc3
Precharge
Command
for Bank D
(PRE Termination of Burst)
Hi-Z
µPD45128163-I-E
Activate
Command
for Bank A
CDb
13.26 Full Page Random Column Write (Burst Length = Full Page, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;
;;;;;;;;
;;;;;;;;;;;;
CLK
CKE
H
/CS
/RAS
/CAS
/WE
Data Sheet E0729N10 (Ver. 1.0)
BA0
BA1
A10
RAa
RDa
ADD
RAa
RDa
L
UDQM
L
DQ
(lower)
Hi-Z
DQ
(upper)
Hi-Z
Activate
Command
for Bank A
CDa
CAb
CDb
CAc
CDc
DAa1 DDa1
DAb1
DAb2
DDb1 DDb2
DAc1
DAc2
DAc3
DDc1
DDc2
DDc3
DDc4
DAa1 DDa1
DAb1
DAb2
DDb1 DDb2
DAc1
DAc2
DAc3
DDc1
DDc2
DDc3
DDc4
Activate
Command
for Bank D
Write
Command
for Bank A
Write
Command
for Bank A
79
Write
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank A
Write
Command
for Bank D
Precharge
Command
for Bank D
(PRE Termination of Burst)
µPD45128163-I-E
LDQM
CAa
80
Full Page Random Column Write (Burst Length = Full Page, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;
;;;;;;;;
;;;;;;;;;;;;
CLK
CKE
H
/CS
/RAS
/CAS
/WE
Data Sheet E0729N10 (Ver. 1.0)
BA0
BA1
A10
RAa
RDa
ADD
RAa
RDa
L
UDQM
L
DQ
(lower)
Hi-Z
DQ
(upper)
Hi-Z
Activate
Command
for Bank A
CDa
CAb
CDb
CAc
CDc
DAa1 DDa1
DAb1
DAb2
DDb1 DDb2
DAc1
DAc2
DAc3
DDc1
DDc2
DDc3
DDc4
DAa1 DDa1
DAb1
DAb2
DDb1 DDb2
DAc1
DAc2
DAc3
DDc1
DDc2
DDc3
DDc4
Activate
Command
for Bank D
Write
Command
for Bank A
Write
Command
for Bank A
Write
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank A
Write
Command
for Bank D
Precharge
Command
for Bank D
(PRE Termination of Burst)
µPD45128163-I-E
LDQM
CAa
13.27 PRE (Precharge) Termination of Burst (1/2) (Burst Length = 8, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
;;;;;
;;;;;;;;;;
;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
CKE
H
/CS
/RAS
/CAS
/WE
Data Sheet E0729N10 (Ver. 1.0)
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
DQ
(lower)
Hi-Z
DQ
(upper)
RAc
RAb
CAa
RAb
RAc
CAb
Write
Masking
Hi-Z
DAa1
DAa2 DAa3
DAa4
DAa5
QAb1 QAb2
QAb3 QAb4 QAb5
DAa1
DAa2 DAa3
DAa4
DAa5
QAb1 QAb2
QAb3 QAb4 QAb5
Activate
Command
for Bank A
Read
Command
for Bank A
PRE Termination
of Burst
tRCD
Precharge
Command
for Bank A
tDPL
81
tRAS
Activate
Command
for Bank A
tRP
Hi-Z
PRE Termination
of Burst
tRAS
Precharge
Command
for Bank A
µPD45128163-I-E
Write
Command
for Bank A
Activate
Command
for Bank A
Hi-Z
82
PRE (Precharge) Termination of Burst (2/2) (Burst Length = 8, /CAS Latency = 3)
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;;;
;;
;;
;;;
;;
;
;
;
;;
;
;
;;
;;
;
;;
;
;
;
;
;;
;
;
;
;;
;
;
;;
;;
;
;
;;
;
;;
;
;
;;
;
;
;;
;
;;
;
;
;;
;
;
;;
;
;;
;
;
;;
;
;
;;
;
;;
;
;
;;
;
;
;;
;
;
;
;;
;;
;
;
;;
;
;;
;
;
;;
;
;;
;
;
;;
;;
;
;
;
;
;;
;
;;
;;
;
;
;
;
;;
;
;;
;;
;
;
;
;
;;
;
;;
;
;
;;
;
;
;;
;
;;
;
;
;;
;
;
;;
;
;;
;
;
;;
;;
;
;
;
;;
;
;;
;
T0
CLK
CKE
H
/CS
/RAS
/CAS
/WE
Data Sheet E0729N10 (Ver. 1.0)
BA0
BA1
A10
RAa
ADD
RAa
LDQM
L
UDQM
L
DQ
(lower)
Hi-Z
DQ
(upper)
Hi-Z
RAc
RAb
CAa
RAb
RAc
CAb
Write
Masking
DAa1
DAa2
DAa3
DAa4
DAa5
DAa1
DAa2
DAa3
DAa4
DAa5
Hi-Z
Hi-Z
PRE Termination
of Burst
tRCD
QAb1 QAb2
QAb3 QAb4
Read
Command
for Bank A
Precharge
Command
for Bank A
tDPL
tRAS
QAb3 QAb4
Activate
Command
for Bank A
tRP
PRE Termination
of Burst
tRAS
Activate
Command
for Bank A
Precharge
Command
for Bank A
µPD45128163-I-E
Write
Command
for Bank A
Activate
Command
for Bank A
QAb1 QAb2
µPD45128163-I-E
14. Package Drawing
54-pin Plastic TSOP (II)
Solder plating: Lead free (Sn-Bi)
Unit: mm
22.22 ± 0.10
A
PIN#1 ID
1
11.76 ± 0.20
28
10.16
54
27
B
0.80
0.25 to 0.40
0.16 M S A B
0.80
Nom
0.91 max.
0.25
0.10 +0.08
−0.05
0.10 S
0.09 to 0.20
S
1.2 max.
1.0 ± 0.05
0 to 8°
0.60 ± 0.15
Note: Dimension "A" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or
gate burrs shall not exceed 0.20mm per side.
ECA-TS2-0016-02
Data Sheet E0729N10 (Ver. 1.0)
83
µPD45128163-I-E
15. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD45128xxx.
Type of Surface Mount Device
µPD45128xxxG5 : 54-pin Plastic TSOP (II) < Lead free (Sn-Bi) >
84
Data Sheet E0729N10 (Ver. 1.0)
µPD45128163-I-E
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Data Sheet E0729N10 (Ver. 1.0)
85
µPD45128163-I-E
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
86
Data Sheet E0729N10 (Ver. 1.0)