EPSON NECVR4102

SED1374 Embedded Memory Color LCD Controller
SED1374
TECHNICAL MANUAL
Issue Date: 99/05/05
Document Number: X26A-Q-001-04
Copyright © 1998 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
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Vancouver Design Center
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SED1374
X26A-Q-001-04
TECHNICAL MANUAL
Issue Date: 99/05/05
Epson Research and Development
Vancouver Design Center
Page 3
Customer Support Information
Comprehensive Support Tools
Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a
complete set of resources and tools for the development of graphics systems.
Evaluation / Demonstration Board
• Assembled and fully tested graphics evaluation board with installation guide and schematics.
• To borrow an evaluation board, please contact your local Seiko Epson Corp. sales representative.
Chip Documentation
• Technical manual includes Data Sheet, Application Notes, and Programmer’s Reference.
Software
• OEM Utilities.
• User Utilities.
• Evaluation Software.
• To obtain these programs, contact Application Engineering Support.
Application Engineering Support
Engineering and Sales Support is provided by:
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
TECHNICAL MANUAL
Issue Date: 99/05/05
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
SED1374
X26A-Q-001-04
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Vancouver Design Center
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SED1374
X26A-Q-001-04
TECHNICAL MANUAL
Issue Date: 99/05/05
Epson Research and Development
Vancouver Design Center
Page 5
Table of Contents
INTRODUCTION
SED1374 Embedded Memory Color LCD Controller Product Brief
SPECIFICATION
SED1374 Hardware Functional Specification
PROGRAMMER’S REFERENCE
SED1374 Programming Notes and Examples
SED1374 Register Summary
UTILITIES
1374CFG.EXE File Configuration Program
1374SHOW Demonstration Program
1374SPLT Display Utility
1374VIRT Display Utility
1374PLAY Diagnostic Utility
1374BMP Demonstration Program
1374PWR Power Save Utility
DRIVERS
SED1374 Windows® CE Display Drivers
EVALUATION
SDU1374B0C Rev. 1 ISA Bus Evaluation Board User Manual
APPLICATION NOTES
Interfacing to the Toshiba MIPS TX3912 Processor
Power Consumption
Interfacing to the Motorola MC68328 Microprocessor
Interfacing to the NEC VR4102 Microprocessor
Interfacing the SED1374 to the PC Card Bus
Interfacing to the Motorola MPC821 Microprocessor
Interfacing to the Motorola MCF5307 Microprocessor
Interfacing to the Philips MIPS PR31500/PR31700 Processor
SDU1374/75-TMPR3912.22U CPU Module
Interfacing to an 8-Bit Processor
TECHNICAL MANUAL
Issue Date: 99/05/05
SED1374
X26A-Q-001-04
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SED1374
X26A-Q-001-04
TECHNICAL MANUAL
Issue Date: 99/05/05
ENERGY
S AV I N G
GRAPHICS
EPSON
SED1374
October 1998
SED1374 EMBEDDED MEMORY COLOR LCD CONTROLLER
■ DESCRIPTION
The SED1374 is a color/monochrome LCD graphics controller with an embedded 40K Byte SRAM display buffer.
The high integration of the SED1374 provides a low cost, low power, single chip solution to meet the requirements
of embedded markets such as Office Automation equipment, Mobile Communications devices, and Hand-Held
PCs where board size and battery life are major concerns.
Products requiring a “Portrait” display can take advantage of the Hardware Portrait Mode feature of the SED1374.
Virtual and Split Screen are just some of the display modes supported. The above features, combined with the
Operating System independence of the SED1374, make it the ideal solution for a wide variety of applications.
■ FEATURES
Memory Interface
• Embedded 40K byte SRAM display buffer.
CPU Interface
• Direct support of the following interfaces:
Hitachi SH-3.
Hitachi SH-4.
Motorola M68K.
MPU bus interface with programmable READY.
• Direct memory mapping of internal registers.
• CPU write buffer.
Display Support
• 4/8-bit monochrome LCD interface.
• 4/8-bit color LCD interface.
• 16-bit color LCD interface with minimal external
curcuitry.
• Single-panel, single-drive passive displays.
• Dual-panel, dual-drive passive displays.
• Active Matrix TFT / TFD interface.
• Example resolutions:
640x480 at a color depth of 1 bpp
640x240 at a color depth of 2 bpp
320x240 at a color depth of 4 bpp
240x160 at a color depth of 8 bpp
Clock Source
• Single clock input for both pixel and memory clocks.
• The SED1374 clock source can be internally
divided down for a higher frequency clock input.
• Dynamic switching of memory clocks in portrait
mode.
X26A-C-001-05
Display Modes
• Hardware Portrait Mode: direct hardware rotation
of display image for portrait mode display.
• 1/2/4 bit-per-pixel (bpp), 2/4/16-level grayscale
display.
• 1/2/4/8 bit-per-pixel, 2/4/16/256-level color display.
• Up to 16 shades of gray by FRM on monochrome
passive LCD panels.
• 256 simultaneous of 4096 colors on color passive
and active matrix LCD panels.
• Split screen display for all panel modes allows two
different images to be simultaneously displayed.
• Virtual display support (displays images larger
than the panel size through the use of panning).
Power Down Modes
• Hardware and software Suspend modes.
• LCD power-down sequencing.
General Purpose IO Pins
• Five General Purpose Input / Output pins are
available.
Operating Voltage
• 2.7 volts to 5.5 volts.
Package
• 80-pin QFP14 surface mount package.
1
GRAPHICS
SED1374
■ SYSTEM BLOCK DIAGRAM
CPU
Data and
Control Signals
SED1374
Digital Out
Flat Panel
Actual Size
CONTACT YOUR SALES REPRESENTATIVE FOR THESE
COMPREHENSIVE DESIGN TOOLS:
• SED1374 Technical Manual
• SDU1374 Evaluation Boards
• Windows CE Display Driver
• CPU Independent Software Utilities
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
FOR SYSTEM INTEGRATION SERVICES
FOR WINDOWS® CE CONTACT:
Epson Research & Development, Inc.
Suite #320 - 11120 Horseshoe Way
Richmond, B.C., Canada V7A 5H7
Tel: (604) 275-5151
Fax: (604) 275-2167
Email: [email protected]
http://www.erd.epson.com
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
Copyright ©1998 Epson Research and Development, Inc. All rights reserved.
VDC
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document
are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. Microsoft, Windows, and the Windows CE Logo are registered trademarks of Microsoft Corporation.
2
X26A-C-001-05
SED1374 Embedded Memory LCD Controller
Hardware Functional Specification
Document Number: X26A-A-001-02
Copyright © 1998, 1999 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Features . . . . . . . . . .
2.1 Integrated Frame Buffer
2.2 CPU Interface . . . .
2.3 Display Support . . . .
2.4 Display Modes . . . .
2.5 Clock Source . . . . .
2.6 Miscellaneous . . . .
2.7 Package . . . . . . .
3
Typical System Implementation Diagrams . . . . . . . . . . . . . . . . . . . . . . 12
4
Functional Block Diagram . . . . .
4.1 Functional Block Descriptions . .
4.1.1 Host Interface . . . . . . . .
4.1.2 Memory Controller . . . . .
4.1.3 Sequence Controller . . . . .
4.1.4 Look-Up Table . . . . . . .
4.1.5 LCD Interface . . . . . . . .
4.1.6 Power Save . . . . . . . . .
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5
Pins . . . . . . . . . . . . . . . . .
5.1 Pinout Diagram . . . . . . . .
5.2 Pin Description . . . . . . . .
5.2.1 Host Interface . . . . . . . .
5.2.2 LCD Interface . . . . . . . .
5.2.3 Clock Input . . . . . . . . .
5.2.4 Miscellaneous . . . . . . . .
5.2.5 Power Supply . . . . . . . .
5.3 Summary of Configuration Options
5.4 Host Bus Interface Pin Mapping .
5.5 LCD Interface Pin Mapping . . .
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D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7
A.C. Characteristics . . . . . . . . . . . . . . . .
7.1 Bus Interface Timing . . . . . . . . . . . .
7.1.1 SH-4 Interface Timing . . . . . . . . . . . .
7.1.2 SH-3 Interface Timing . . . . . . . . . . . .
7.1.3 Motorola M68K #1 Interface Timing . . . . .
Hardware Functional Specification
Issue Date: 99/04/29
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SED1374
X26A-A-001-02
Page 4
Epson Research and Development
Vancouver Design Center
7.1.4 Motorola M68K #2 Interface Timing . . . . . .
7.1.5 Generic #1 Interface Timing . . . . . . . . . . .
7.1.6 Generic #2 Interface Timing . . . . . . . . . . .
7.2 Clock Input Requirements . . . . . . . . . . .
7.3 Display Interface . . . . . . . . . . . . . . .
7.3.1 Power On/Reset Timing . . . . . . . . . . . . .
7.3.2 Power Down/Up Timing . . . . . . . . . . . .
7.3.3 Single Monochrome 4-Bit Panel Timing . . . .
7.3.4 Single Monochrome 8-Bit Panel Timing . . . .
7.3.5 Single Color 4-Bit Panel Timing . . . . . . . .
7.3.6 Single Color 8-Bit Panel Timing (Format 1) . .
7.3.7 Single Color 8-Bit Panel Timing (Format 2) . .
7.3.8 Dual Monochrome 8-Bit Panel Timing . . . . .
7.3.9 Dual Color 8-Bit Panel Timing . . . . . . . . .
7.3.10 9/12-Bit TFT/MD-TFD Panel Timing . . . . . .
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8
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
8.1 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
8.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
9
Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
10 Display Data Formats
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11 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
11.1 Gray Shade Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . .72
11.2 Color Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
12 SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1 Default SwivelView Mode . . . . . . . . . . . . . . .
12.1.1 How to Set Up Default SwivelView Mode . . . . . . . .
12.2 Alternate SwivelView Mode . . . . . . . . . . . . . .
12.2.1 How to Set Up Alternate SwivelView Mode . . . . . . .
12.3 Comparison Between Default and Alternate SwivelView Modes
12.4 SwivelView Mode Limitations . . . . . . . . . . . . .
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13 Power Save Modes . . . . . . . . . . .
13.1 Software Power Save Mode . . . .
13.2 Hardware Power Save Mode . . . .
13.3 Power Save Mode Function Summary
13.4 Panel Power Up/Down Sequence . .
13.5 Turning Off BCLK Between Accesses
13.6 Clock Requirements . . . . . . .
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14 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
Vancouver Design Center
Page 5
List of Tables
Table 5-1: Summary of Power On/Reset Options . . . . . . . . .
Table 5-2: Host Bus Interface Pin Mapping . . . . . . . . . . . .
Table 5-3: LCD Interface Pin Mapping . . . . . . . . . . . . . .
Table 6-1: Absolute Maximum Ratings . . . . . . . . . . . . . .
Table 6-2: Recommended Operating Conditions . . . . . . . . .
Table 6-3: Input Specifications . . . . . . . . . . . . . . . . . .
Table 6-4: Output Specifications. . . . . . . . . . . . . . . . . .
Table 7-1: SH-4 Timing . . . . . . . . . . . . . . . . . . . . . .
Table 7-2: SH-3 Bus Timing . . . . . . . . . . . . . . . . . . . .
Table 7-3: M68K #1 Bus Timing (MC68000) . . . . . . . . . .
Table 7-4: M68K #2 Timing (MC68030) . . . . . . . . . . . . .
Table 7-5: Generic #1 Timing . . . . . . . . . . . . . . . . . . .
Table 7-6: Generic #2 Timing . . . . . . . . . . . . . . . . . . .
Table 7-7: Clock Input Requirements . . . . . . . . . . . . . . .
Table 7-8: Power Down/Up Timing . . . . . . . . . . . . . . . .
Table 8-1: Panel Data Format . . . . . . . . . . . . . . . . . . .
Table 8-2: Gray Shade/Color Mode Selection . . . . . . . . . . .
Table 8-3: High Performance Selection . . . . . . . . . . . . . .
Table 8-4: Inverse Video Mode Select Options . . . . . . . . . .
Table 8-5: Hardware Power Save/GPIO0 Operation . . . . . . .
Table 8-6: Software Power Save Mode Selection . . . . . . . . .
Table 8-7: Look-Up Table Access . . . . . . . . . . . . . . . . .
Table 8-8: Selection of SwivelView Mode . . . . . . . . . . . .
Table 8-9: Selection of PCLK and MCLK in SwivelView Mode .
Table 11-1: Look-Up Table Configurations. . . . . . . . . . . . .
Table 12-1: Default and Alternate SwivelView Mode Comparison
Table 13-1: Power Save Mode Selection . . . . . . . . . . . . . .
Table 13-2: Software Power Save Mode Summary . . . . . . . . .
Table 13-3: Hardware Power Save Mode Summary . . . . . . . .
Table 13-4: Power Save Mode Function Summary . . . . . . . . .
Table 13-5: SED1374 Internal Clock Requirements . . . . . . . .
Hardware Functional Specification
Issue Date: 99/04/29
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SED1374
X26A-A-001-02
Page 6
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
Vancouver Design Center
Page 7
List of Figures
Figure 3-1:
Figure 3-2:
Figure 3-3:
Figure 3-4:
Figure 3-5:
Figure 3-6:
Figure 4-1:
Figure 5-1:
Figure 7-1:
Figure 7-2:
Figure 7-3:
Figure 7-4:
Figure 7-5:
Figure 7-6:
Figure 7-7:
Figure 7-8:
Figure 7-9:
Figure 7-10:
Figure 7-11:
Figure 7-12:
Figure 7-13:
Figure 7-14:
Figure 7-15:
Figure 7-16:
Figure 7-17:
Figure 7-18:
Figure 7-19:
Figure 7-20:
Figure 7-21:
Figure 7-22:
Figure 7-23:
Figure 7-24:
Figure 7-25:
Figure 8-1:
Figure 10-1:
Figure 11-1:
Figure 11-2:
Typical System Diagram (SH-4 Bus). . . . . . . . . . . .
Typical System Diagram (SH-3 Bus). . . . . . . . . . . .
Typical System Diagram (M68K #1 Bus) . . . . . . . . .
Typical System Diagram (M68K #2 Bus) . . . . . . . . .
Typical System Diagram (Generic #1 Bus) . . . . . . . .
Typical System Diagram (Generic #2 Bus - e.g. ISA Bus).
System Block Diagram Showing Data Paths . . . . . . . .
Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . .
SH-4 Timing . . . . . . . . . . . . . . . . . . . . . . . .
SH-3 Bus Timing . . . . . . . . . . . . . . . . . . . . . .
M68K #1 Bus Timing (MC68000) . . . . . . . . . . . . .
M68K #2 Timing (MC68030) . . . . . . . . . . . . . . .
Generic #1 Timing . . . . . . . . . . . . . . . . . . . . .
Generic #2 Timing . . . . . . . . . . . . . . . . . . . . .
Clock Input Requirements . . . . . . . . . . . . . . . . .
LCD Panel Power On/Reset Timing . . . . . . . . . . . .
Power Down/Up Timing . . . . . . . . . . . . . . . . . .
Single Monochrome 4-Bit Panel Timing . . . . . . . . . .
Single Monochrome 4-Bit Panel A.C. Timing . . . . . . .
Single Monochrome 8-Bit Panel Timing . . . . . . . . . .
Single Monochrome 8-Bit Panel A.C. Timing . . . . . . .
Single Color 4-Bit Panel Timing . . . . . . . . . . . . . .
Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . .
Single Color 8-Bit Panel Timing (Format 1) . . . . . . . .
Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . .
Single Color 8-Bit Panel Timing (Format 2) . . . . . . . .
Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . .
Dual Monochrome 8-Bit Panel Timing. . . . . . . . . . .
Dual Monochrome 8-Bit Panel A.C. Timing . . . . . . . .
Dual Color 8-Bit Panel Timing . . . . . . . . . . . . . . .
Dual Color 8-Bit Panel A.C. Timing . . . . . . . . . . . .
12-Bit TFT/MD-TFD Panel Timing . . . . . . . . . . . .
TFT/MD-TFD A.C. Timing . . . . . . . . . . . . . . . .
Screen-Register Relationship, Split Screen. . . . . . . . .
1/2/4/8 Bit-Per-Pixel Display Data Memory Organization.
2-Level Gray-Shade Mode Look-Up Table Architecture .
4-Level Gray-Shade Mode Look-Up Table Architecture .
Hardware Functional Specification
Issue Date: 99/04/29
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. 12
. 12
. 13
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. 15
. 17
. 26
. 28
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. 73
SED1374
X26A-A-001-02
Page 8
Figure 11-3:
Figure 11-4:
Figure 11-5:
Figure 11-6:
Figure 11-7:
Figure 11-8:
Figure 12-1:
Figure 12-2:
Figure 13-1:
Figure 14-1:
SED1374
X26A-A-001-02
Epson Research and Development
Vancouver Design Center
16-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . . .
Look-Up Table Bypass Mode Architecture. . . . . . . . . . . . . . . . . . . . .
2-Level Color Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . .
4-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . .
16-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . . .
256-Level Color Mode Look-Up Table Architecture. . . . . . . . . . . . . . . .
Relationship Between The Screen Image and the Image Refreshed by SED1374 .
Relationship Between The Screen Image and the Image Refreshed by SED1374 .
Panel On/Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Drawing QFP14 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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.73
.74
.75
.76
.77
.78
.79
.81
.86
.88
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
Vancouver Design Center
Page 9
1 Introduction
1.1 Scope
This is the Functional Specification for the SED1374 Embedded Memory LCD Controller
Chip. Included in this document are timing diagrams, AC and DC characteristics, register
descriptions, and power management descriptions. This document is intended for two
audiences: Video Subsystem Designers and Software Developers.
Please check the Epson Electronics America website at http://www.eea.epson.com for the
latest revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
1.2 Overview Description
The SED1374 is a color / monochrome LCD graphics controller with an embedded 40K
Byte SRAM display buffer. The high integration of the SED1374 provides a low cost, low
power, single chip solution to meet the requirements of embedded markets such as Office
Automation equipment, Mobile Communications devices, and Hand-Held PCs where
board size and battery life are major concerns.
Products requiring a “Portrait” display can take advantage of the Swivelview™ (90°
Hardware Rotate) feature of the SED1374. Virtual and Split Screen are just some of the
display modes supported. The above features, combined with the Operating System
independence of the SED1374, make it the ideal solution for a wide variety of applications.
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02
Page 10
Epson Research and Development
Vancouver Design Center
2 Features
2.1 Integrated Frame Buffer
• Embedded 40K byte SRAM display buffer.
2.2 CPU Interface
• Direct support of the following interfaces:
Hitachi SH-3.
Hitachi SH-4.
Motorola M68K.
MPU bus interface using WAIT# signal.
• Direct memory mapping of internal registers.
• Single level CPU write buffer.
• Registers are mapped into upper 32 bytes of 64K byte address space.
• The complete 40K byte frame buffer is directly and contiguously available through the
16-bit address bus.
2.3 Display Support
• 4/8-bit monochrome LCD interface.
• 4/8-bit color LCD interface.
• Single-panel, single-drive passive displays.
• Dual-panel, dual-drive passive displays.
• Active Matrix TFT / MD-TFD interface
• Register level support for EL panels.
• Example resolutions:
640x480 at a color depth of 1 bpp
640x240 at a color depth of 2 bpp
320x240 at a color depth of 4 bpp
240x160 at a color depth of 8 bpp
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
Vancouver Design Center
Page 11
2.4 Display Modes
• SwivelView™: direct 90° hardware rotation of display image for portrait mode display.
• 1/2/4 bit-per-pixel (bpp), 2/4/16-level grayshade display.
• 1/2/4/8 bit-per-pixel, 2/4/16/256-level color display.
• Up to 16 shades of gray by FRM on monochrome passive LCD panels; a 16x4 LookUp-Table is used to map 1/2/4-bpp modes into these shades.
• 256 simultaneous of 4096 colors on color passive and active matrix LCD panels; three
16x4 Look-Up Tables are used to map 1/2/4/8-bpp modes into these colors.
• Split screen display for all landscape panel modes allows two different images to be
simultaneously displayed.
• Virtual display support (displays images larger than the panel size through the use of
panning).
2.5 Clock Source
• Maximum operating clock (CLK) frequency of 25MHz.
• Operating clock (CLK) is derived from CLKI input.
CLK = CLKI
or
CLK = CLKI/2
• Pixel Clock (PCLK) and Memory Clock (MCLK) are derived from CLK.
2.6 Miscellaneous
• Hardware/Software Video Invert.
• Software Power Save mode.
• Hardware Power Save mode.
• LCD power-down sequencing.
• 5 General Purpose Input/Output pins are available.
• GPIO0 is available if Hardware Power Save is not required.
• GPIO[4:1] are available if upper LCD data pins (FPDAT[11:8]) are not required for
TFT/MD-TFD support or Hardware Video Invert.
• IO Operates from 3.0 volts to 5.5 volts
• Core operates from 3.0 volts to 3.6 volts.
2.7 Package
• 80 pin QFP14 package.
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02
Page 12
Epson Research and Development
Vancouver Design Center
3 Typical System Implementation Diagrams
.
CLKI
Oscillator
SH-4
BUS
CSn#
CS#
A[15:0]
AB[15:0]
D[15:0]
DB[15:0]
WE1#
BS#
RD/WR#
RD#
WE1#
BS#
FPDAT[7:0]
SED1374
RDY#
WAIT#
CKIO
BCLK
FPFRAME
FPFRAME
FPLINE
RD#
WE0#
FPSHIFT
8-bit
RD/WR#
WE0#
D[7:0]
FPSHIFT
DRDY
FPLINE
MOD
LCD
Display
LCDPWR
RESET#
RESET#
Figure 3-1: Typical System Diagram (SH-4 Bus)
.
CLKI
Oscillator
SH-3
BUS
CSn#
CS#
A[15:0]
AB[15:0]
D[15:0]
DB[15:0]
WE1#
BS#
RD/WR#
RD#
WE1#
BS#
RD/WR#
RD#
WE0#
WE0#
WAIT#
WAIT#
CKIO
BCLK
FPDAT[3:0]
SED1374
D[3:0]
FPSHIFT
FPSHIFT
FPFRAME
FPFRAME
4-bit
FPLINE
DRDY
FPLINE
MOD
LCD
Display
LCDPWR
RESET#
RESET#
Figure 3-2: Typical System Diagram (SH-3 Bus)
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
Vancouver Design Center
Page 13
.
Oscillator
A[23:16]
FC0, FC1, FC2
Decoder
CS#
A[15:1]
AB[15:1]
D[15:0]
DB[15:0]
LDS#
AB0#
UDS#
WE1#
AS#
CLKI
MC68000
BUS
FPDAT[3:0]
SED1374
R/W#
FPFRAME
FPFRAME
4-bit
DRDY
RD/WR#
DTACK#
FPSHIFT
FPLINE
BS#
D[3:0]
FPSHIFT
FPLINE
MOD
LCD
Display
WAIT#
LCDPWR
CLK
BCLK
RESET#
RESET#
Figure 3-3: Typical System Diagram (M68K #1 Bus)
.
Oscillator
A[31:16]
FC0, FC1, FC2
Decoder
CS#
A[15:0]
AB[15:0]
D[31:16]
DB[15:0]
DS#
WE1#
AS#
BS#
R/W#
CLKI
MC68030
BUS
RD/WR#
SIZ1
RD#
SIZ0
WE0#
DSACK1#
WAIT#
FPDAT[7:0]
SED1374
D[7:0]
FPSHIFT
FPSHIFT
FPFRAME
FPFRAME
8-bit
FPLINE
DRDY
FPLINE
LCD
Display
MOD
LCDPWR
CLK
RESET#
BCLK
RESET#
Figure 3-4: Typical System Diagram (M68K #2 Bus)
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02
Page 14
Epson Research and Development
Vancouver Design Center
.
CLKI
Oscillator
BS#
GENERIC #1
BUS
CSn#
CS#
A[15:0]
AB[15:0]
D[15:0]
DB[15:0]
WE0#
WE0#
WE1#
WE1#
RD0#
RD
RD1#
RD/WR#
WAIT#
WAIT#
BCLK
BCLK
FPDAT[11:0]
SED1374
D[11:0]
FPSHIFT
FPSHIFT
FPFRAME
FPFRAME
FPLINE
FPLINE
DRDY
12-bit
TFT
Display
DRDY
LCDPWR
RESET#
RESET#
Figure 3-5: Typical System Diagram (Generic #1 Bus)
.
CLKI
Oscillator
BS#
ISA
BUS
REFRESH
SA[19:16]
Decoder
CS#
SA[15:0]
AB[15:0]
SD[15:0]
DB[15:0]
SMEMW#
WE0#
SMEMR#
RD#
SBHE#
WE1#
FPDAT[8:0]
SED1374
D[8:0]
FPSHIFT
FPSHIFT
FPFRAME
FPFRAME
9-bit
FPLINE
FPLINE
DRDY
IOCHRDY
TFT
Display
DRDY
WAIT#
LCDPWR
BCLK
RESET
BCLK
RESET#
Figure 3-6: Typical System Diagram (Generic #2 Bus - e.g. ISA Bus)
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
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Page 15
4 Functional Block Diagram
20k x 16-bit SRAM
Memory
Controller
Register
Power Save
Clocks
LCD
Generic MPU
MC68K
SH-3
SH-4
Host
LCD
I/F
I/F
Look-Up
Table
Sequence Controller
Bus Clock
Memory Clock
Pixel Clock
Figure 4-1: System Block Diagram Showing Data Paths
4.1 Functional Block Descriptions
4.1.1 Host Interface
The Host Interface provides the means for the CPU/MPU to communicate with the display
memory and internal registers.
4.1.2 Memory Controller
The Memory Controller arbitrates between CPU accesses and display refresh accesses. It
also generates the necessary signals to control the SRAM frame buffer.
4.1.3 Sequence Controller
The Sequence Controller controls data flow from the Memory Controller through the LookUp Table and to the LCD Interface. It also generates memory addresses for display refresh
accesses.
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02
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4.1.4 Look-Up Table
The Look-Up Table contains three 16x4 Look-Up Tables or palettes, one for each primary
color. In monochrome mode only one of these Look-Up Tables is used.
4.1.5 LCD Interface
The LCD Interface performs frame rate modulation for passive LCD panels. It also
generates the correct data format and timing control signals for various LCD and
TFT/MD-TFD panels.
4.1.6 Power Save
Power Save contains the power save mode circuitry.
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
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Page 17
5 Pins
5.1 Pinout Diagram
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
COREVDD
DRDY
LCDPWR
TESTEN
CNF4
CNF3
62
CNF2
CNF1
CNF0
VSS
CLKI
IOVDD
AB15
AB14
AB13
AB12
AB11
AB10
AB9
VSS
61
COREVDD
AB8
VSS
FPFRAME
FPLINE
FPDAT0
AB7
AB6
AB5
FPDAT1
AB4
AB3
FPDAT2
AB2
FPDAT4
AB1
AB0
BCLK
FPDAT5
FPDAT6
FPDAT7
FPDAT3
SED1374
VSS
IOVDD
FPSHIFT
RESET#
CS#
BS#
VSS
FPDAT8
FPDAT9
RD#
FPDAT10
FPDAT11
WE0#
WE1#
GPIO0
RD/WR#
COREVDD
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSS
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
IOVDD
DB9
DB10
DB11
DB12
DB13
DB14
DB15
WAIT#
COREVDD
VSS
40
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Figure 5-1: Pinout Diagram
Note
Package type: 80 pin surface mount QFP14
Hardware Functional Specification
Issue Date: 99/04/29
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X26A-A-001-02
Page 18
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5.2 Pin Description
Key:
I
O
I/O
P
C
CD
CS
COx
TSx
TSxD
=
=
=
=
=
=
=
=
=
=
CNx
=
Input
Output
Bi-Directional (Input/Output)
Power pin
CMOS level input
CMOS level input with pull down resistor (typical values of 100KΩ/180ΚΩ at 5V/3.3V respectively)
CMOS level Schmitt input
CMOS output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA)
Tri-state CMOS output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA)
Tri-state CMOS output driver with pull down resistor (typical values of 100KΩ/180ΚΩ at 5V/3.3V
respectively), x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA)
CMOS low-noise output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA)
5.2.1 Host Interface
Pin Names
Type
Pin #
Cell
RESET#
State
Description
This pin has multiple functions.
AB0
I
70
I
53, 54, 55,
56, 57, 58,
59, 62, 63,
64, 65, 66,
67, 68, 69
CS
Input
• For SH-3/SH-4 mode, this pin inputs system address bit
0 (A0).
• For MC68K #1, this pin inputs the lower data strobe
(LDS#).
• For MC68K #2, this pin inputs system address bit 0 (A0).
• For Generic #1, this pin inputs system address bit 0
(A0).
• For Generic #2, this pin inputs system address bit 0
(A0).
See “Host Bus Interface Pin Mapping” for summary.
AB[15:1]
C
Input
These pins input the system address bits 15 through 1
(A[15:1]).
These pins have multiple functions.
DB[15:0]
I/O
3, 4, 5, 6, 7,
8, 9, 11, 12,
13, 14, 15, C/TS2
16, 17, 18,
19
High
Impedance
• For SH-3/SH-4 mode, these pins are connected to
[D15:0].
• For MC68K #1, these pins are connected to D[15:0].
• For MC68K #2, these pins are connected to D[31:16] for
a 32-bit device (e.g. MC68030) or D[15:0] for a 16-bit
device (e.g. MC68340).
• For Generic #1, these pins are connected to D[15:0].
• For Generic #2, these pins are connected to D[15:0].
See “Host Bus Interface Pin Mapping” for summary.
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
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Pin Names
Type
Page 19
Pin #
Cell
RESET#
State
Description
This pin has multiple functions.
WE0#
I
77
CS
Input
• For SH-3/SH-4 mode, this pin inputs the write enable
signal for the lower data byte (WE0#).
• For MC68K #1, this pin must be tied to IO VDD
• For MC68K #2, this pin inputs the bus size bit 0 (SIZ0).
• For Generic #1, this pin inputs the write enable signal for
the lower data byte (WE0#).
• For Generic #2, this pin inputs the write enable signal
(WE#)
See “Host Bus Interface Pin Mapping” for summary.
This pin has multiple functions.
WE1#
I
78
CS
Input
• For SH-3/SH-4 mode, this pin inputs the write enable
signal for the upper data byte (WE1#).
• For MC68K #1, this pin inputs the upper data strobe
(UDS#).
• For MC68K #2, this pin inputs the data strobe (DS#).
• For Generic #1, this pin inputs the write enable signal for
the upper data byte (WE1#).
• For Generic #2, this pin inputs the byte enable signal for
the high data byte (BHE#).
See “Host Bus Interface Pin Mapping” for summary.
CS#
I
74
C
Input
This pin inputs the chip select signal.
BCLK
I
71
C
Input
This pin inputs the system bus clock.
This pin has multiple functions.
BS#
I
75
CS
Input
• For SH-3/SH-4 mode, this pin inputs the bus start signal
(BS#).
• For MC68K #1, this pin inputs the address strobe (AS#).
• For MC68K #2, this pin inputs the address strobe (AS#).
• For Generic #1, this pin must be tied to VSS.
• For Generic #2, this pin must be tied to IO VDD.
See “Host Bus Interface Pin Mapping” for summary.
This pin has multiple functions.
RD/WR#
I
79
CS
Input
• For SH-3/SH-4 mode, this pin inputs the RD/WR# signal.
The SED1374 needs this signal for early decode of the
bus cycle.
• For MC68K #1, this pin inputs the R/W# signal.
• For MC68K #2, this pin inputs the R/W# signal.
• For Generic #1, this pin inputs the read command for the
upper data byte (RD1#).
• For Generic #2, this pin must be tied to IO V DD.
See “Host Bus Interface Pin Mapping” for summary.
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02
Page 20
Pin Names
Epson Research and Development
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Type
Pin #
Cell
RESET#
State
Description
This pin has multiple functions.
RD#
I
76
CS
Input
• For SH-3/SH-4 mode, this pin inputs the read signal
(RD#).
• For MC68K #1, this pin must be tied to IO VDD.
• For MC68K #2, this pin inputs the bus size bit 1 (SIZ1).
• For Generic #1, this pin inputs the read command for the
lower data byte (RD0#).
• For Generic #2, this pin inputs the read command (RD#).
See “Host Bus Interface Pin Mapping” for summary.
This pin has multiple functions.
WAIT#
O
2
TS2
High
Impedance
• For SH-3 mode, this pin outputs the wait request signal
(WAIT#).
• For SH-4 mode, this pin outputs the device ready signal
(RDY#).
• For MC68K #1, this pin outputs the data transfer
acknowledge signal (DTACK#).
• For MC68K #2, this pin outputs the data transfer and
size acknowledge bit 1 (DSACK1#).
• For Generic #1, this pin outputs the wait signal (WAIT#).
• For Generic #2, this pin outputs the wait signal (WAIT#).
See “Host Bus Interface Pin Mapping” for summary.
RESET#
I
73
CS
0
Active low input to set all internal registers to the default state
and to force all signals to their inactive states.
Description
5.2.2 LCD Interface
Pin Name
Type
Pin #
Cell
RESET#
State
FPDAT[7:0]
O
30, 31, 32,
33, 34, 35,
36, 37
CN3
0
Panel Data
These pins have multiple functions.
FPDAT[10:8]
O,
I/O
24, 25, 26
CN3
Input
• Panel Data bits [10:8] for TFT/MD-TFD panels.
• General Purpose Input/Output pins GPIO[3:1].
These pins should be connected to IO VDD when unused.
See “LCD Interface Pin Mapping” for summary.
This pin has multiple functions.
FPDAT11
O,
I/O
23
CN3
Input
• Panel Data bit 11 for TFT/MD-TFD panels.
• General Purpose Input/Output pin GPIO4.
• Inverse Video select pin.
This pin should be connected to IO VDD when unused. See
“LCD Interface Pin Mapping” for summary.
FPFRAME
SED1374
X26A-A-001-02
O
39
CN3
0
Frame Pulse
Hardware Functional Specification
Issue Date: 99/04/29
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Page 21
Pin Name
Type
Pin #
Cell
RESET#
State
Description
FPLINE
O
38
CN3
0
Line Pulse
FPSHIFT
O
28
CN3
0
Shift Clock
LCDPWR
O
43
CO1
0 if CNF4 = 1
LCD Power Control
1 if CNF4 = 0
This pin has multiple functions.
DRDY
O
42
CN3
• TFT/MD-TFD Display Enable (DRDY).
• LCD Backplane Bias (MOD).
• Second Shift Clock (FPSHIFT2).
0
See “LCD Interface Pin Mapping” for summary.
5.2.3 Clock Input
Pin Name
Type
Pin #
Driver
CLKI
I
51
C
Description
Input Clock
5.2.4 Miscellaneous
Pin Name
Type
Pin #
Cell
RESET#
State
CNF[4:0]
I
45, 46, 47,
48, 49
C
As set by
hardware
GPIO0
I/O,
I
22
CS/
TS1
TESTEN
I
44
CD
Description
These inputs are used to configure the SED1374 - see
“Summary of Configuration Options”.
Must be connected directly to IO VDD or VSS.
This pin has multiple functions - see REG[03h] bit 2.
Input
• General Purpose Input/Output pin.
• Hardware Power Save.
High
Test Enable input. This input must be connected to VSS.
Impedance
5.2.5 Power Supply
Pin Name
Type
Pin #
Driver
COREVDD
P
1, 21, 41,
61
P
Core VDD
IOVDD
P
10, 29, 52
P
IO VDD
VSS
P
20, 27, 40,
50, 60, 72,
80
P
Common VSS
Hardware Functional Specification
Issue Date: 99/04/29
Description
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X26A-A-001-02
Page 22
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5.3 Summary of Configuration Options
Table 5-1: Summary of Power On/Reset Options
Power On/Reset State
Configuration
Pin
CNF4
CNF3
1
0
Active high (On) LCDPWR polarity
Active low (On) LCDPWR polarity
Big Endian
Little Endian
Select host bus interface as follows:
CNF2
0
0
0
0
1
1
1
1
1
1
CNF[2:0]
CNF1
0
0
1
1
0
0
1
1
1
1
CNF0
0
1
0
1
0
1
0
0
1
1
BS#
X
X
X
X
X
X
0
1
0
1
Host Bus
SH-4 interface
SH-3 interface
reserved
MC68K #1, 16-bit
reserved
MC68K #2, 16-bit
reserved
reserved
Generic #1, 16-bit
Generic #2, 16-bit
5.4 Host Bus Interface Pin Mapping
Table 5-2: Host Bus Interface Pin Mapping
SED1374
Pin Names
SH-3
SH-4
MC68K #1
MC68K #2
Generic #1
Generic #2
AB[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
AB0
A0
A0
LDS#
A0
A0
A0
DB[15:0]
D[15:0]
D[15:0]
D[15:0]
D[31:16]
D[15:0]
D[15:0]
WE1#
WE1#
WE1#
UDS#
DS#
WE1#
BHE#
CS#
CSn#
CSn#
External Decode
BCLK
CKIO
CKIO
CLK
CLK
BCLK
BCLK
BS#
BS#
BS#
AS#
AS#
connect to VSS
connect to IO VDD
RD/WR#
RD/WR#
RD/WR#
R/W#
R/W#
RD1#
connect to IO VDD
RD#
RD#
RD#
connect to IO VDD
SIZ1
RD0#
RD#
WE0#
WE0#
WE0#
connect to IO VDD
SIZ0
WE0#
WE#
WAIT#
WAIT#
RDY#
DTACK#
DSACK1#
WAIT#
WAIT#
RESET#
RESET#
RESET#
RESET#
RESET#
RESET#
RESET#
SED1374
X26A-A-001-02
External Decode External Decode
External Decode
Hardware Functional Specification
Issue Date: 99/04/29
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Page 23
5.5 LCD Interface Pin Mapping
Table 5-3: LCD Interface Pin Mapping
Monochrome Passive Panel
SED1374
Pin Name
FPFRAME
FPLINE
FPSHIFT
DRDY
FPDAT0
FPDAT1
FPDAT2
FPDAT3
FPDAT4
FPDAT5
FPDAT6
FPDAT7
FPDAT8
FPDAT9
FPDAT10
FPDAT11
4-bit
Single
8-bit
Single
8-bit Dual
MOD
driven 0
driven 0
driven 0
driven 0
D0
D1
D2
D3
GPIO1
GPIO2
GPIO3
GPIO4/
HW Video
Invert
MOD
D0
D1
D2
D3
D4
D5
D6
D7
GPIO1
GPIO2
GPIO3
GPIO4/
HW Video
Invert
MOD
LD0
LD1
LD2
LD3
UD0
UD1
UD2
UD3
GPIO1
GPIO2
GPIO3
GPIO4/
HW Video
Invert
Color Passive Panel
8-bit
8-bit
4-bit
Single
Single
Single
Format 1 Format 2
FPFRAME
FPLINE
FPSHIFT
MOD
FPSHIFT2
MOD
driven 0
D0
D0
driven 0
D1
D1
driven 0
D2
D2
driven 0
D3
D3
D0
D4
D4
D1
D5
D5
D2
D6
D6
D3
D7
D7
GPIO1
GPIO1
GPIO1
GPIO2
GPIO2
GPIO2
GPIO3
GPIO3
GPIO3
GPIO4/
GPIO4/
GPIO4/
HW Video HW Video HW Video
Invert
Invert
Invert
Color TFT/MD-TFD
8-bit Dual
MOD
LD0
LD1
LD2
LD3
UD0
UD1
UD2
UD3
GPIO1
GPIO2
GPIO3
GPIO4/
HW Video
Invert
9-bit
12-bit
DRDY
R2
R1
R0
G2
G1
G0
B2
B1
B0
GPIO2
GPIO3
R3
R2
R1
G3
G2
G1
B3
B2
B1
R0
G0
GPIO4
B0
Note
1. Unused GPIO pins must be connected to IO VDD.
2. Hardware Video Invert is enabled on FPDAT11 by REG[02h] bit 1.
Hardware Functional Specification
Issue Date: 99/04/29
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X26A-A-001-02
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6 D.C. Characteristics
Table 6-1: Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
Core VDD
Supply Voltage
VSS - 0.3 to 4.6
V
IO VDD
Supply Voltage
VSS - 0.3 to 6.0
V
VIN
Input Voltage
VSS - 0.3 to IO VDD + 0.5
V
VOUT
Output Voltage
VSS - 0.3 to IO VDD + 0.5
TSTG
Storage Temperature
-65 to 150
°C
TSOL
Solder Temperature/Time
260 for 10 sec. max at lead
°C
V
Table 6-2: Recommended Operating Conditions
Symbol
Parameter
Condition
Min
Typ
Max
Units
Core VDD
Supply Voltage
VSS = 0 V
3.0
3.3
3.6
V
IO VDD
Supply Voltage
VSS = 0 V
3.0
3.3/5.0
5.5
V
VIN
Input Voltage
VSS
IO VDD
V
TOPR
Operating Temperature
-40
25
85
°C
Table 6-3: Input Specifications
Symbol
Parameter
Condition
Min
Typ
Max
VIL
IO VDD = 3.3
5.0
VIH
High Level Input Voltage
CMOS inputs
IO VDD = 3.3
5.0
2.0
3.5
VT+
Positive-going Threshold
CMOS Schmitt inputs
IO VDD = 3.3
5.0
1.1
2.0
2.4
4.0
V
V
VT-
Negative-going Threshold
CMOS Schmitt inputs
IO VDD = 3.3
5.0
0.6
0.8
1.8
3.1
V
V
IIZ
Input Leakage Current
VDD = Max
VIH = VDD
VIL = VSS
-1
1
µA
CIN
Input Pin Capacitance
HRPD
Pull Down Resistance
VI = VDD
50
SED1374
X26A-A-001-02
0.8
1.0
Units
Low Level Input Voltage
CMOS inputs
V
V
V
V
100
10
pF
300
kΩ
Hardware Functional Specification
Issue Date: 99/04/29
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Page 25
Table 6-4: Output Specifications
Symbol
Parameter
Condition
VOL
Low Level Output Voltage
Type 1 - TS1, CO1
Type 2- TS2, CO2
Type 3 - TS3, CO3
IOL = 3mA
IOL = 6mA
IOL = 12mA
VOH
High Level Output Voltage
Type 1 - TS1, CO1
Type 2- TS2, CO2
Type 3 - TS3, CO3
IOL = -1.5 mA
IOL = -3 mA
IOL = -6 mA
IOZ
Output Leakage Current
COUT
CBID
VDD = MAX
VOH = VDD
VOL = VSS
Min
Typ
Max
0.4
IO VDD - 0.4
Units
V
V
1
µA
Output Pin Capacitance
10
pF
Bidirectional Pin Capacitance
10
pF
Hardware Functional Specification
Issue Date: 99/04/29
-1
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X26A-A-001-02
Page 26
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7 A.C. Characteristics
Conditions: IO VDD = 3.3V ± 10% or IO VDD = 5V ± 10%
TA = -40° C to 85° C
Trise and Tfall for all inputs must be < 5 nsec (10% ~ 90%)
CL = 60pF (Bus/MPU Interface)
CL = 60pF (LCD Panel Interface)
7.1 Bus Interface Timing
7.1.1 SH-4 Interface Timing
TCKIO
t2
t3
CKIO
t4
t5
A[16:0]
RD/WR#
t6
t7
BS#
t8
CSn#
t10
t9
WEn#
RD#
t12
t11
t13
RDY#
t14
t15
D[15:0]
(write)
t16
D[15:0]
(read)
t17
VALID
Figure 7-1: SH-4 Timing
Note
The SH-4 Wait State Control Register for the area in which the SED1374 resides must be set to a
non-zero value. The SH-4 read-to-write cycle transition must be set to a non-zero value (with reference to BUSCLK).
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
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Page 27
Table 7-1: SH-4 Timing
Symbol
Parameter
fCKIO
Bus Clock frequency
TCKIO
Bus Clock period
Min
Max
Units
0
50
MHz
1/fCKIO
t2
Clock pulse width high
17
ns
t3
Clock pulse width low
16
ns
t4
A[15:0], RD/WR# setup to CKIO
0
ns
t5
A[15:0], RD/WR# hold from CS#
0
ns
t6
BS# setup
5
ns
t7
BS# hold
5
ns
t8
CSn# setup
0
ns
t9
Falling edge RD# to DB[15:0] driven
25
ns
t10
Rising edge CSn# to RDY# high impedance
t1
ns
t11
Falling edge CSn# to RDY# driven
20
ns
t12
CKIO to RDY# low
20
ns
t13
Rising edge CSn# to RDY# high
nd
20
ns
0
ns
DB[15:0] hold (write cycle)
0
ns
t16
DB[15:0] valid to RDY# falling edge setup time (read cycle)
0
ns
t17
Rising edge RD# to DB[15:0] high impedance (read cycle)
t14
DB[15:0] setup to 2
t15
CKIO after BS# (write cycle)
10
ns
Note
CKIO may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 86
Hardware Functional Specification
Issue Date: 99/04/29
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X26A-A-001-02
Page 28
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7.1.2 SH-3 Interface Timing
TCKIO
t2
t3
CKIO
t4
t5
A[16:0], M/R#
RD/WR#
t6
t7
BS#
t8
CSn#
t10
t9
WEn#
RD#
t12
t11
WAIT#
Hi-Z
Hi-Z
t14
t13
D[15:0]
(write)
Hi-Z
Hi-Z
t15
D[15:0]
(read)
Hi-Z
t16
VALID
Hi-Z
Figure 7-2: SH-3 Bus Timing
Note
The SH-3 Wait State Control Register for the area in which the SED1374 resides must
be set to a non-zero value.
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
Vancouver Design Center
Page 29
Table 7-2: SH-3 Bus Timing
Symbol
Parameter
fCKIO
Bus Clock frequency
TCKIO
Bus Clock period
Min
Maxa
Units
0
50
MHz
1/fCKIO
t2
Clock pulse width high
17
ns
t3
Clock pulse width low
16
ns
t4
A[15:0], RD/WR# setup to CKIO
0
ns
t5
A[15:0], RD/WR# hold from CS#
0
ns
t6
BS# setup
5
ns
t7
BS# hold
5
ns
t8
CSn# setup
0
ns
t9
Falling edge RD# to DB[15:0] driven
25
ns
t10
Rising edge CSn# to WAIT# high impedance
10
ns
t11
Falling edge CSn# to WAIT# driven
15
ns
t12
CKIO to WAIT# delay
20
ns
t13
DB[15:0] setup to 2nd CKIO after BS# (write cycle)
0
ns
t14
DB[15:0] hold from rising edge of WEn# (write cycle)
0
ns
t15
DB[15:0] valid to RDY# falling edge setup time (read cycle)
0
t16
Rising edge RD# to DB[15:0] high impedance (read cycle)
a
ns
10
ns
One Software WAIT State Required
Note
CKIO may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 86
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02
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7.1.3 Motorola M68K #1 Interface Timing
TCLK
CLK
A[15:1]
CS#
R/W#
VALID
t2
t1
AS#
UDS#, LDS#
INVALID
t3
t6
t4
t5
DTACK#
D[15:0]
(write
Hi-Z
Hi-Z
t8
t7
Hi-Z
Hi-Z
VALID
t9
D[15:0]
(read)
t11
t10
Hi-Z
Hi-Z
VALID
Figure 7-3: M68K #1 Bus Timing (MC68000)
Table 7-3: M68K #1 Bus Timing (MC68000)
Symbol
Parameter
fCLK
Bus Clock Frequency
TCLK
Bus Clock period
Min
Max
Units
0
33
MHz
1/fCLK
t1
A[15:1], CS# valid before AS# falling edge
0
ns
t2
A[15:1], CS# hold from AS# rising edge
0
ns
t3
AS# low to DTACK# driven high
16
ns
t4
CLK to DTACK# low
15
ns
t5
AS# high to DTACK# high
20
ns
t6
AS# high to DTACK# high impedance
TCLK
t7
UDS#, LDS# falling edge to D[15:0] valid (write cycle)
TCLK
t8
D[15:0] hold from AS# rising edge (write cycle)
t9
UDS#, LDS# falling edge to D[15:0] driven (read cycle)
t10
D[15:0] valid to DTACK# falling edge (read cycle)
t11
UDS#, LDS# rising edge to D[15:0] high impedance
0
ns
15
0
ns
ns
10
ns
Note
CLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 86
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
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Page 31
7.1.4 Motorola M68K #2 Interface Timing
TCLK
CLK
A[15:0]
CS#
SIZ0, SIZ1
R/W#
VALID
t2
t1
AS#
DS#
t3
DSACK1#
t6
t4
t5
Hi-Z
t8
t7
D[31:16]
(write)
Hi-Z
D[31:16]
(read)
Hi-Z
Hi-Z
Hi-Z
VALID
t10
t9
Hi-Z
VALID
Figure 7-4: M68K #2 Timing (MC68030)
Table 7-4: M68K #2 Timing (MC68030)
Symbol
Parameter
fCLK
Bus Clock frequency
TCLK
Bus Clock period
t1
Min
Max
Units
0
33
MHz
1/fCLK
A[15:0], CS#, SIZ0, SIZ1 valid before AS# falling edge
0
ns
t2
A[15:0], CS#, SIZ0, SIZ1 hold from AS#, DS# rising edge
0
t3
AS# low to DSACK1# driven high
22
ns
t4
CLK to DSACK1# low
18
ns
t5
AS# high to DSACK1# high
26
ns
t6
AS# high to DSACK1# high impedance
t7
DS# falling edge to D[31:16] valid (write cycle)
t8
AS#, DS# rising edge to D[31:16] invalid (write cycle)
0
ns
t9
D[31:16] valid to DSACK1# low (read cycle)
0
ns
t10
AS#, DS# rising edge to D[31:16] high impedance
ns
TCLK
TCLK / 2
20
ns
Note
CLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 86
Hardware Functional Specification
Issue Date: 99/04/29
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X26A-A-001-02
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7.1.5 Generic #1 Interface Timing
TBCLK
BCLK
A[15:0]
VALID
CS#
t2
t1
WE0#,WE1#
RD0#, RD1#
t3
D[15:0]
(write)
t5
Hi-Z
VALID
t4
D[15:0]
(read)
Hi-Z
Hi-Z
VALID
t8
WAIT#
t7
t6
t9
t10
Hi-Z
Hi-Z
Figure 7-5: Generic #1 Timing
Table 7-5: Generic #1 Timing
Symbol
fBCLK
TBCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Parameter
Bus Clock frequency
Bus Clock period
A[15:0], CS# valid to WE0#, WE1# low (write cycle) or RD0#, RD1# low (read
cycle)
WE0#, WE1# high (write cycle) or RD0#, RD1# high (read cycle) to A[15:0],
CS# invalid
WE0#, WE1# low to D[15:0] valid (write cycle)
RD0#, RD1# low to D[15:0] driven (read cycle)
WE0#, WE1# high to D[15:0] invalid (write cycle)
D[15:0] valid to WAIT# high (read cycle)
RD0#, RD1# high to D[15:0] high impedance (read cycle)
WE0#, WE1# low (write cycle) or RD0#, RD1# low (read cycle) to WAIT#
driven low
BCLK to WAIT# high
WE0#, WE1# high (write cycle) or RD0#, RD1# high (read cycle) to WAIT#
high impedance
Min
0
1/fBCLK
Max
50
Units
MHz
MHz
0
ns
0
ns
TBCLK
17
10
ns
ns
ns
ns
16
ns
16
ns
11
ns
0
0
Note
BCLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 86
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
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7.1.6 Generic #2 Interface Timing
TBCLK
BCLK
A[15:0]
BHE#
VALID
CS#
t2
t1
WE#,RD#
t3
t4
Hi-Z
VALID
D[15:0]
(write)
t5
Hi-Z
VALID
D[15:0]
(read)
t9
t8
WAIT#
t7
t6
Hi-Z
t10
Hi-Z
Hi-Z
Figure 7-6: Generic #2 Timing
Table 7-6: Generic #2 Timing
Symbol
Parameter
fBCLK
Bus Clock frequency
TBCLK
Bus Clock period
Min
Max
Units
0
50
MHz
1/fBCLK
t1
A[15:0], BHE#, CS# valid to WE#, RD# low
0
ns
t2
WE#, RD# high to A[15:0], BHE#, CS# invalid
0
ns
t3
WE# low to D[15:0] valid (write cycle)
t4
WE# high to D[15:0] invalid (write cycle)
t5
RD# low to D[15:0] driven (read cycle)
t6
D[15:0] valid to WAIT# high (read cycle)
t7
RD# high to D[15:0] high impedance (read cycle)
TBCLK
0
ns
16
0
ns
ns
10
ns
t8
WE#, RD# low to WAIT# driven low
14
ns
t9
BCLK to WAIT# high
16
ns
t10
WE#, RD# high to WAIT# high impedance
11
ns
Note
BCLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 86
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02
Page 34
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7.2 Clock Input Requirements
Clock Input Waveform
t
t
PWH
PWL
90%
V
IH
VIL
10%
t
tr
f
TCLKI
Figure 7-7: Clock Input Requirements
Table 7-7: Clock Input Requirements
Symbol
Parameter
Min
Max
Units
0
50
MHz
fCLKI
Input Clock Frequency (CLKI)
TCLKI
Input Clock period (CLKI)
tPWH
Input Clock Pulse Width High (CLKI)
8
ns
tPWL
Input Clock Pulse Width Low (CLKI)
8
ns
1/fCLKI
tf
Input Clock Fall Time (10% - 90%)
5
ns
tr
Input Clock Rise Time (10% - 90%)
5
ns
Note
When CLKI is > 25MHz it must be divided by 2 (REG[02h] bit 4 = 1).
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
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7.3 Display Interface
7.3.1 Power On/Reset Timing
RESET#
00
REG[03h] bits [1:0]
11
LCDPWR
(CNF4 = 1)
LCDPWR
(CNF4 = 0)
FPLINE
FPSHIFT
FPDAT
FPFRAME
DRDY
ACTIVE
t1
t2
Figure 7-8: LCD Panel Power On/Reset Timing
Symbol
t1
t2
Parameter
REG[03h] to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY
active
FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY active to
LCDPWR
Min
Typ
0
Max
Units
TFPFRAME
ns
Frames
Note
Where TFPFRAME is the period of FPFRAME and TPCLK is the period of the pixel clock.
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02
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7.3.2 Power Down/Up Timing
LCDPWR Override
(REG[03h] bit 3)
HW Power Save
or
Software Power Save
REG[03h] bits [1:0]
11
00
11
00
t2
t1
FP Signals
Active
t3
LCDPWR
(polarity set by CNF4)
Active
Inactive
t4
Active
t5
Inactive
11
Inactive
Active
t7
t6
Active
Inactive
Active
Figure 7-9: Power Down/Up Timing
Table 7-8: Power Down/Up Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
Parameter
HW Power Save active to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY
inactive - LCDPWR Override = 1
HW Power Save inactive to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY
active - LCDPWR Override = 1
HW Power Save active to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY
inactive - LCDPWR Override = 0
LCDPWR low to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY inactive
- LCDPWR Override = 0
HW Power Save inactive to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY,
LCDPWR active - LCDPWR Override = 0
LCDPWR Override active (1) to LCDPWR inactive
LCDPWR Override inactive (1) to LCDPWR active
SED1374
X26A-A-001-02
Min
Typ
Max
Units
1
Frame
1
Frame
1
Frame
127
Frame
0
Frame
1
1
Frame
Frame
Hardware Functional Specification
Issue Date: 99/04/29
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Page 37
7.3.3 Single Monochrome 4-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:4]
LINE1
LINE2
LINE3
LINE4
LINE239 LINE240
LINE1
LINE2
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
FPDAT7
1-1
1-5
1-317
FPDAT6
1-2
1-6
1-318
FPDAT5
1-3
1-7
1-319
FPDAT4
1-4
1-8
1-320
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 320x240 panel
For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1
Figure 7-10: Single Monochrome 4-Bit Panel Timing
VDP =
VNDP =
HDP =
HNDP =
Vertical Display Period
Vertical Non-Display Period
Horizontal Display Period
Horizontal Non-Display Period
Hardware Functional Specification
Issue Date: 99/04/29
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= REG[0Ah] bits 5-0 Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= (REG[08h] + 4) x 8Ts
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t2
t1
Sync Timing
Frame Pulse
t3
t4
Line Pulse
t5
DRDY (MOD)
Data Timing
Line Pulse
t6
t8
t7
t9
t14
t11
t10
Shift Pulse
t12
t13
1
FPDAT[7:4]
2
Note: For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1
Figure 7-11: Single Monochrome 4-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
4.
5.
Ts
t1min
t3min
t6min
t7min
Parameter
Frame Pulse setup to Line Pulse falling edge
Frame Pulse hold from Line Pulse falling edge
Line Pulse period
Line Pulse pulse width
MOD delay from Line Pulse rising edge
Shift Pulse falling edge to Line Pulse rising edge
Shift Pulse falling edge to Line Pulse falling edge
Line Pulse falling edge to Shift Pulse falling edge
Shift Pulse period
Shift Pulse pulse width low
Shift Pulse pulse width high
FPDAT[7:4] setup to Shift Pulse falling edge
FPDAT[7:4] hold to Shift Pulse falling edge
Line Pulse falling edge to Shift Pulse rising edge
Min
note 2
9
note 3
9
1
note 4
note 5
t14 + 2
4
2
2
2
2
23
Typ
Max
Units
(note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= t3min - 9Ts
= [((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8]Ts
= [(REG[08h] bits 4-0) x 8 + 2]Ts
= [(REG[08h] bits 4-0) x 8 + 11]Ts
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
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Page 39
7.3.4 Single Monochrome 8-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
LINE1
FPDAT[7:0]
LINE2
LINE3
LINE4
LINE479 LINE480
LINE1
LINE2
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
FPDAT7
1-1
1-9
1-633
FPDAT6
1-2
1-10
1-634
FPDAT5
1-3
1-11
1-635
FPDAT4
1-4
1-12
1-636
FPDAT3
1-5
1-13
1-637
FPDAT2
1-6
1-14
1-638
FPDAT1
1-7
1-15
1-639
FPDAT0
1-8
1-16
1-640
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1
Figure 7-12: Single Monochrome 8-Bit Panel Timing
VDP =
VNDP =
HDP =
HNDP =
Vertical Display Period
Vertical Non-Display Period
Horizontal Display Period
Horizontal Non-Display Period
Hardware Functional Specification
Issue Date: 99/04/29
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= REG[0Ah] bits 5-0 Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= (REG[08h] + 4) x 8Ts
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X26A-A-001-02
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t1
t2
Sync Timing
Frame Pulse
t3
t4
Line Pulse
t5
MOD
Data Timing
Line Pulse
t6
t8
t7
t9
t14
t11
t10
Shift Pulse
t12
t13
1
FPDAT[7:0]
2
Note: For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1
Figure 7-13: Single Monochrome 8-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
4.
5.
Ts
t1min
t3min
t6min
t7min
Parameter
Frame Pulse setup to Line Pulse falling edge
Frame Pulse hold from Line Pulse falling edge
Line Pulse period
Line Pulse pulse width
MOD delay from Line Pulse rising edge
Shift Pulse falling edge to Line Pulse rising edge
Shift Pulse falling edge to Line Pulse falling edge
Line Pulse falling edge to Shift Pulse falling edge
Shift Pulse period
Shift Pulse pulse width low
Shift Pulse pulse width high
FPDAT[7:0] setup to Shift Pulse falling edge
FPDAT[7:0] hold to Shift Pulse falling edge
Line Pulse falling edge to Shift Pulse rising edge
Min
note 2
9
note 3
9
1
note 4
note 5
t14 + 4
8
4
4
4
4
23
Typ
Max
Units
(note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= t3min - 9Ts
= [((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8]Ts
= [(REG[08h] bits 4-0) x 8 + 4]Ts
=[(REG[08h] bits 4-0) x 8 + 13]Ts
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
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7.3.5 Single Color 4-Bit Panel Timing
VNDP
VDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:4]
LINE1
LINE2
LINE3
LINE4
LINE479 LINE480
LINE1
LINE2
FPLINE
DRDY (MOD)
HNDP
HDP
FPSHIFT
FPDAT7
1-R1
1-G2
1-B3
1-B319
FPDAT6
1-G1
1-B2
1-R4
1-R320
FPDAT5
1-B1
1-R3
1-G4
1-G320
FPDAT4
1-R2
1-G3
1-B4
1-B320
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-14: Single Color 4-Bit Panel Timing
VDP =
VNDP =
HDP =
HNDP =
Vertical Display Period
Vertical Non-Display Period
Horizontal Display Period
Horizontal Non-Display Period
Hardware Functional Specification
Issue Date: 99/04/29
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= REG[0Ah] bits 5-0 Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= (REG[08h] + 4) x 8Ts
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X26A-A-001-02
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t1
Sync Timing
t2
Frame Pulse
t3
t4
Line Pulse
t5
DRDY (MOD)
Data Timing
Line Pulse
t6
t8
t7
t9
t14
t11
t10
Shift Pulse
t12
t13
1
FPDAT[7:4]
2
Figure 7-15: Single Color 4-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
4.
5.
Ts
t1min
t3min
t6min
t7min
Parameter
Frame Pulse setup to Line Pulse falling edge
Frame Pulse hold from Line Pulse falling edge
Line Pulse period
Line Pulse pulse width
MOD delay from Line Pulse rising edge
Shift Pulse falling edge to Line Pulse rising edge
Shift Pulse falling edge to Line Pulse falling edge
Line Pulse falling edge to Shift Pulse falling edge
Shift Pulse period
Shift Pulse pulse width low
Shift Pulse pulse width high
FPDAT[7:4] setup to Shift Pulse falling edge
FPDAT[7:4] hold to Shift Pulse falling edge
Line Pulse falling edge to Shift Pulse rising edge
Min
note 2
9
note 3
9
1
note 4
note 5
t14 + 0.5
1
0.5
0.5
0.5
0.5
23
Typ
Max
Units
(note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= t3min - 9Ts
= [((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8]Ts
= [(REG[08h] bits 4-0) x 8 + 0.5]Ts
= [(REG[08h] bits 4-0) x 8 + 9.5]Ts
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
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Page 43
7.3.6 Single Color 8-Bit Panel Timing (Format 1)
VNDP
VDP
FPFRAME
FPLINE
FPDAT[7:0]
LINE1
LINE2
LINE3
LINE4
LINE479 LINE480
LINE1
LINE2
FPLINE
FPSHIFT
HNDP
HDP
FPSHIFT 2
FPDAT7
1-R1
1-G1
1-G6
1-B6
1-B11
1-R12
1-R636
FPDAT6
1-B1
1-R2
1-R7
1-G7
1-G12
1-B12
1-B636
FPDAT5
1-G2
1-B2
1-B7
1-R8
1-R13
1-G13
1-G637
FPDAT4
1-R3
1-G3
1-G8
1-B8
1-B13
1-R14
1-R638
FPDAT3
1-B3
1-R4
1-R9
1-G9
1-G14
1-B14
1-B638
FPDAT2
1-G4
1-B4
1-B9
1-R10
1-R15
1-G15
1-G639
FPDAT1
1-R5
1-G5
1-G10
1-B10
1-B15
1-R16
1-R640
FPDAT0
1-B5
1-R6
1-R11
1-G11 1-G16
1-B16
1-B640
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-16: Single Color 8-Bit Panel Timing (Format 1)
VDP =
VNDP =
HDP =
HNDP =
Vertical Display Period
Vertical Non-Display Period
Horizontal Display Period
Horizontal Non-Display Period
Hardware Functional Specification
Issue Date: 99/04/29
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= REG[0Ah] bits 5-0 Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= (REG[08h] + 4) x 8Ts
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t1
Sync Timing
t2
Frame Pulse
t4
t3
Line Pulse
Data Timing
Line Pulse
t6a
t6b
t8
t9
t14
t7a
t11
t10
Shift Pulse 2
t7b
Shift Pulse
t12 t13 t12 t13
FPDAT[7:0]
1
2
Figure 7-17: Single Color 8-Bit Panel A.C. Timing (Format 1)
Symbol
t1
t2
t3
t4
t6a
t6b
t7a
t7b
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
4.
5.
6.
7.
Ts
t1min
t3min
t6amin
t6bmin
t7amin
t7bmin
Parameter
Frame Pulse setup to Line Pulse falling edge
Frame Pulse hold from Line Pulse falling edge
Line Pulse period
Line Pulse pulse width
Shift Pulse falling edge to Line Pulse rising edge
Shift Pulse 2 falling edge to Line Pulse rising edge
Shift Pulse 2 falling edge to Line Pulse falling edge
Shift Pulse falling edge to Line Pulse falling edge
Line Pulse falling edge to Shift Pulse rising, Shift Pulse 2 falling edge
Shift Pulse 2, Shift Pulse period
Shift Pulse 2, Shift Pulse pulse width low
Shift Pulse 2, Shift Pulse pulse width high
FPDAT[7:0] setup to Shift Pulse 2, Shift Pulse falling edge
FPDAT[7:0] hold to Shift Pulse 2, Shift Pulse falling edge
Line Pulse falling edge to Shift Pulse rising edge
Min
note 2
9
note 3
9
note 4
note 5
note 6
note 7
t14 + 2
4
2
2
1
1
23
Typ
Max
Units
(note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= t3min - 9Ts
= [((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8]Ts
= [(REG[08h] bits 4-0) x 8 + t13 - t10]Ts
= [(REG[08h] bits 4-0) x 8 + t13]Ts
= [(REG[08h] bits 4-0) x 8 + 11]Ts
= [(REG[08h] bits 4-0) x 8 + 11] - t10]Ts
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
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7.3.7 Single Color 8-Bit Panel Timing (Format 2)
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
LINE1
LINE2
LINE3
LINE4
LINE479 LINE480
LINE1
LINE2
FPLINE
DRDY (MOD)
HNDP
HDP
FPSHIFT
FPDAT7
1-R1
1-B3
1-G6
1-G638
FPDAT6
1-G1
1-R4
1-B6
1-B638
FPDAT5
1-B1
1-G4
1-R7
1-R639
FPDAT4
1-R2
1-B4
1-G7
1-G639
FPDAT3
1-G2
1-R5
1-B7
1-B639
FPDAT2
1-B2
1-G5
1-R8
1-R640
FPDAT1
1-R3
1-B5
1-G8
1-G640
FPDAT0
1-G3
1-R6
1-B8
1-B640
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-18: Single Color 8-Bit Panel Timing (Format 2)
VDP =
VNDP =
HDP =
HNDP =
Vertical Display Period
Vertical Non-Display Period
Horizontal Display Period
Horizontal Non-Display Period
Hardware Functional Specification
Issue Date: 99/04/29
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= REG[0Ah] bits 5-0 Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= (REG[08h] + 4) x 8Ts
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t1
Sync Timing
t2
Frame Pulse
t3
t4
Line Pulse
t5
DRDY (MOD)
Data Timing
Line Pulse
t6
t8
t7
t9
t14
t11
t10
Shift Pulse
t12
t13
1
FPDAT[7:0]
2
Figure 7-19: Single Color 8-Bit Panel A.C. Timing (Format 2)
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
4.
5.
Ts
t1min
t3min
t6min
t7min
Parameter
Frame Pulse setup to Line Pulse falling edge
Frame Pulse hold from Line Pulse falling edge
Line Pulse period
Line Pulse pulse width
MOD delay from Line Pulse rising edge
Shift Pulse falling edge to Line Pulse rising edge
Shift Pulse falling edge to Line Pulse falling edge
Line Pulse falling edge to Shift Pulse falling edge
Shift Pulse period
Shift Pulse pulse width low
Shift Pulse pulse width high
FPDAT[7:0] setup to Shift Pulse falling edge
FPDAT[7:0] hold to Shift Pulse falling edge
Line Pulse falling edge to Shift Pulse rising edge
Min
note 2
9
note 3
9
1
note 4
note 5
t14 + 2
2
1
1
1
1
23
Typ
Max
Units
(note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= t3min - 9Ts
= [((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8]Ts
= [(REG[08h] bits 4-0) x 8 + 1]Ts
= [(REG[08h] bits 4-0) x 8 + 10]Ts
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
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Page 47
7.3.8 Dual Monochrome 8-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
LINE 1/241
LINE 2/242
LINE 3/243
LINE 4/244
LINE 239/479 LINE 240/480
LINE 1/241
LINE 2/242
FPLINE
DRDY (MOD)
HNDP
HDP
FPSHIFT
FPDAT7
1-1
1-5
1-637
FPDAT6
1-2
1-6
1-638
FPDAT5
1-3
1-7
1-639
FPDAT4
1-4
1-8
1-640
FPDAT3
241-1
241-5
241-637
FPDAT2
241-2
241-6
241-638
FPDAT1
241-3
241-7
241-639
FPDAT0
241-4
241-8
241-640
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-20: Dual Monochrome 8-Bit Panel Timing
VDP =
VNDP =
HDP =
HNDP =
Vertical Display Period
Vertical Non-Display Period
Horizontal Display Period
Horizontal Non-Display Period
Hardware Functional Specification
Issue Date: 99/04/29
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= REG[0Ah] bits 5-0 Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= (REG[08h] + 4) x 8Ts
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t1
Sync Timing
t2
Frame Pulse
t4
t3
Line Pulse
t5
DRDY (MOD)
Data Timing
Line Pulse
t6
t8
t7
t9
t14
t11
t10
Shift Pulse
t12
t13
1
2
FPDAT[7:0]
Figure 7-21: Dual Monochrome 8-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
5.
6.
Ts
t1min
t3min
t6min
t7min
Parameter
Frame Pulse setup to Line Pulse falling edge
Frame Pulse hold from Line Pulse falling edge
Line Pulse period
Line Pulse pulse width
MOD delay from Line Pulse falling edge
Shift Pulse falling edge to Line Pulse rising edge
Shift Pulse falling edge to Line Pulse falling edge
Line Pulse falling edge to Shift Pulse falling edge
Shift Pulse period
Shift Pulse pulse width low
Shift Pulse pulse width high
FPDAT[7:0] setup to Shift Pulse falling edge
FPDAT[7:0] hold to Shift Pulse falling edge
Line Pulse falling edge to Shift Pulse rising edge
Min
note 2
9
note 3
9
1
note 5
note 6
t14 + 4
8
4
4
4
4
39
Typ
Max
Units
(note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= t3min - 9Ts
= [(((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8) x 2]Ts
= [((REG[08h] bits 4-0) x 2)x 8 + 20]Ts
= [((REG[08h] bits 4-0) x 2)x 8 + 29]Ts
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X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
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7.3.9 Dual Color 8-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
LINE 1/241
LINE 2/242
LINE 239/479 LINE 240/480
LINE 1/241
FPLINE
DRDY (MOD)
HNDP
HDP
FPSHIFT
FPDAT7
1-R1
1-G2
1-B 3
1-R 5
1-G6
1-B7
1-B639
FPDAT6
1-G1
1-B2
1-R4
1-G5
1-B6
1-R8
1-R640
FPDAT5
1-B1
1-R 3
1-G4
1-B5
1-R7
1-G8
1-G640
1-R2
1-G3
1-B4
1-R6
1-G7
1-B8
1-B640
FPDAT4
FPDAT3
241-R 1 241-G2 241-B 3
241-R5 241-G6 241-B7
2 41B639
FPDAT2
241-G1 24 1-B2 241-R 4 241-G 5 241-B6 241-R8
241R640
FPDAT1
241-B1 241-R3 241-G4 241-B5 241-R7 241-G8
241G640
FPDAT0
241-R 2 241-G3 241-B4 241-R 6 241-G7 241-B8
2 41B640
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-22: Dual Color 8-Bit Panel Timing
VDP =
VNDP =
HDP =
HNDP =
Vertical Display Period
Vertical Non-Display Period
Horizontal Display Period
Horizontal Non-Display Period
Hardware Functional Specification
Issue Date: 99/04/29
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= REG[0Ah] bits 5-0 Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= (REG[08h] + 4) x 8Ts
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t1
t2
Sync Timing
Frame Pulse
t4
t3
Line Pulse
t5
DRDY (MOD)
Data Timing
Line Pulse
t6
t8
t7
t9
t14
t11
t10
Shift Pulse
t12
FPDAT[7:0]
t13
1
2
Figure 7-23: Dual Color 8-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.
2.
3.
5.
6.
Ts
t1min
t3min
t6min
t7min
Parameter
Frame Pulse setup to Line Pulse falling edge
Frame Pulse hold from Line Pulse falling edge
Line Pulse period
Line Pulse pulse width
MOD delay from Line Pulse falling edge
Shift Pulse falling edge to Line Pulse rising edge
Shift Pulse falling edge to Line Pulse falling edge
Line Pulse falling edge to Shift Pulse falling edge
Shift Pulse period
Shift Pulse pulse width low
Shift Pulse pulse width high
FPDAT[7:0] setup to Shift Pulse falling edge
FPDAT[7:0] hold to Shift Pulse falling edge
Line Pulse falling edge to Shift Pulse rising edge
Min
note 2
9
note 3
9
1
note 5
note 6
t14 + 1
2
1
1
1
1
39
Typ
Max
Units
(note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= pixel clock period
= t3min - 9Ts
= [(((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8) x 2]Ts
= [((REG[08h] bits 4-0) x 2)x 8 + 17]Ts
= [((REG[08h] bits 4-0) x 2)x 8 + 26]Ts
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Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
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7.3.10 9/12-Bit TFT/MD-TFD Panel Timing
VDP
VNDP2
VNDP1
FPFRAME
FPLINE
FPDAT[11:0]
LINE480
LINE1
LINE480
DRDY
FPLINE
HDP
HNDP2
HNDP1
FPSHIFT
DRDY
FPDAT[9]
FPDAT[2:0]
FPDAT[10]
FPDAT[4:3]
FPDAT[11]
FPDAT[8:6]
1-1
1-2
1-640
1-1
1-2
1-640
1-1
1-2
1-640
Note: DRDY is used to indicate the first pixel
Example Timing for 640x480 panel
Figure 7-24: 12-Bit TFT/MD-TFD Panel Timing
VDP =
VNDP =
VNDP1 =
VNDP2 =
HDP =
HNDP =
HNDP1=
HNDP2=
Vertical Display Period
Vertical Non-Display Period
Vertical Non-Display Period 1
Vertical Non-Display Period 2
Horizontal Display Period
Horizontal Non-Display Period
Horizontal Non-Display Period 1
Horizontal Non-Display Period 2
Hardware Functional Specification
Issue Date: 99/04/29
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= VNDP1 + VNDP2 = (REG[0Ah] bits 5-0) Lines
= REG[09h] bits 5-0 Lines
= (REG[0Ah] bits 5-0) - (REG[09Ah] bits 5-0) Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= HNDP1 + HNDP2 = (REG[08h] + 4) x 8Ts
= ((REG[07h] bits4-0) x 8) +16Ts
= (((REG[08h] bits4-0) - (REG[07h] bits 4-0)) x 8) +16Ts
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t8
t9
Frame Pulse
t12
Line Pulse
t6
Line Pulse
t7
t15
t17
DRDY
t14
t1
t2
t11
t13
t3
t16
Shift Pulse
t5
t4
1
2
639
640
FPDAT[11:0]
t10
Note: DRDY is used to indicate the first pixel
Figure 7-25: TFT/MD-TFD A.C. Timing
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
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Symbol
1.
2.
3.
4.
5.
6.
7.
Page 53
Parameter
Min
Typ
Max
Units
t1
Shift Pulse period
t2
Shift Pulse pulse width high
0.5
Ts
t3
Shift Pulse pulse width low
0.5
Ts
t4
Data setup to Shift Pulse falling edge
0.5
Ts
t5
Data hold from Shift Pulse falling edge
0.5
Ts
t6
Line Pulse cycle time
t7
t8
Line Pulse pulse width low
t9
Frame Pulse pulse width low
t10
Horizontal display period
t11
Line Pulse setup to Shift Pulse falling edge
t12
Frame Pulse falling edge to Line Pulse falling
edge phase difference
t13
DRDY to Shift Pulse falling edge setup time
t14
DRDY pulse width
note 5
t15
DRDY falling edge to Line Pulse falling edge
note 6
t16
DRDY hold from Shift Pulse falling edge
0.5
t17
Line Pulse Falling edge to DRDY active
note 7
Ts
t6min
t8 min
t10min
t14min
t15min
t17min
Frame Pulse cycle time
1
(note 1)
note 2
9
Ts
note 3
2t6
note 4
0.5
Ts
t6 - 18Ts
0.5
Ts
Ts
250
= pixel clock period
= [((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0)+4) x 8] Ts
= [((REG[06h] bits 1-0, REG[05h] bits 7-0)+1) + (REG[0Ah] bits 6-0)] Lines
= [((REG[04h] bits 6-0)+1) x 8] Ts
= [((REG[04h] bits 6-0)+1) x 8] Ts
= [(REG[07h] bits 4-0) x 8 + 16] Ts
= [(REG[08h] bits 4-0) - (REG[07]) x 8 + 16] Ts
Hardware Functional Specification
Issue Date: 99/04/29
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X26A-A-001-02
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8 Registers
8.1 Register Mapping
The SED1374 registers are located in the upper 32 bytes of the 64K byte SED1374 address
range. The registers are accessible when CS# = 0 and AB[15:0] are in the range FFE0h
through FFFFh.
8.2 Register Descriptions
Unless specified otherwise, all register bits are reset to 0 during power up.
REG[00h] Revision Code Register
Address = FFE0h
Read Only
Product Code Product Code Product Code Product Code Product Code Product Code
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Revision
Code Bit 1
Revision
Code Bit 0
bits 7-2
Product Code
This is a read-only register that indicates the product code of the chip. The product code is
000110.
bits 1-0
Revision Code
This is a read-only register that indicates the revision code of the chip. The revision code is
00.
REG[01h] Mode Register 0
Address = FFE1h
TFT/STN
Dual/Single
Read/Write.
Color/Mono
FPLine
Polarity
FPFrame
Polarity
Mask
FPSHIFT
Data Width
Bit 1
Data Width
Bit 0
bit 7
TFT/STN
When this bit = 0, STN (passive) panel mode is selected. When this bit = 1, TFT/MD-TFD
panel mode is selected. If TFT/MD-TFD panel mode is selected, Dual/Single (REG[01h]
bit 6) and Color/Mono (REG[01h] bit5) are ignored. See Table 8-1: “Panel Data Format”
below.
bit 6
Dual/Single
When this bit = 0, Single LCD panel drive is selected. When this bit = 1, Dual LCD panel
drive is selected. See Table 8-1: “Panel Data Format” below.
bit 5
Color/Mono
When this bit = 0, Monochrome LCD panel drive is selected. When this bit = 1, Color
LCD panel drive is selected. See Table 8-1: “Panel Data Format” below.
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
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Page 55
bit 4
FPLINE Polarity
This bit controls the polarity of FPLINE in TFT/MD-TFD mode (no effect in passive
panel mode). When this bit = 0, FPLINE is active low. When this bit = 1, FPLINE is active
high.
bit 3
FPFRAME Polarity
This bit controls the polarity of FPFRAME in TFT/MD-TFD mode (no effect in passive
panel mode). When this bit = 0, FPFRAME is active low. When this bit = 1, FPFRAME is
active high.
bit 2
Mask FPSHIFT
FPSHIFT is masked during non-display periods if either of the following two criteria is
met:
1. Color passive panel is selected (REG[01h] bit 5 = 1)
2. This bit (REG[01h] bit 2) = 1
bits 1-0
Data Width Bits [1:0]
These bits select the display data format. See Table 8-1: “Panel Data Format” below.
Table 8-1: Panel Data Format
TFT/STN
REG[01h] bit 7
Color/Mono Dual/Single
REG[01h] bit 5
REG[01h] bit 6
Data Width
Bit 1
Data Width
Bit 0
REG[01h] bit 1
REG[01h] bit 0
0
0
1
0
0
1
1
0
0
0
1
1
0
1
1
1
X (don’t care)
Hardware Functional Specification
Issue Date: 99/04/29
Function
0
Mono Single 4-bit passive LCD
1
Mono Single 8-bit passive LCD
0
reserved
1
reserved
0
reserved
1
Mono Dual 8-bit passive LCD
0
reserved
1
reserved
0
Color Single 4-bit passive LCD
1
Color Single 8-bit passive LCD format 1
0
reserved
1
Color Single 8-bit passive LCD format 2
0
reserved
1
Color Dual 8-bit passive LCD
0
reserved
1
reserved
0
9-bit TFT/MD-TFD panel
1
12-bit TFT/MD-TFD panel
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REG[02h] Mode Register 1
Address = FFE2h
Bit-Per-Pixel
Bit 1
bits 7-6
Bit-Per-Pixel
Bit 0
Read/Write.
Input Clock
divide
(CLKI/2)
High
Performance
Hardware
Video Invert
Enable
Frame
Repeat
Display Blank
Software
Video Invert
Bit-Per-Pixel Bits [1:0]
These bits select the color or gray-shade depth (Display Mode).
Table 8-2: Gray Shade/Color Mode Selection
Color/Mono
Bit-Per-Pixel Bit 1
Bit-Per-Pixel Bit 0
REG[01h] bit 6
REG[02h] bit 7
REG[02h] bit 6
0
0
0
1
2 Gray shade
4 Gray shade
2 bit-per-pixel
0
16 Gray shade
4 bit-per-pixel
reserved
0
1
1
1 bit-per-pixel
1
1
0
bit 5
Display Mode
2 Colors
1 bit-per-pixel
1
4 Colors
2 bit-per-pixel
0
16 Colors
4 bit-per-pixel
1
256 Colors
8 bit-per-pixel
High Performance (Landscape Modes Only)
When this bit = 0, the internal Memory clock (MCLK) is a divided-down version of the
Pixel clock (PCLK). The denominator is dependent on the bit-per-pixel mode - see the
table below.
Table 8-3: High Performance Selection
High Performance
BPP Bit 1
0
0
1
1
X
BPP Bit 0
Display Modes
0
MClk = PClk/8
1 bit-per-pixel
1
MClk = PClk/4
2 bit-per-pixel
0
MClk = PClk/2
4 bit-per-pixel
1
MClk = PClk
8 bit-per-pixel
X
MClk = PClk
When this bit = 1, MCLK is fixed to the same frequency as PCLK for all bit-per-pixel
modes. This provides a faster screen update performance in 1, 2, 4 bit-per-pixel modes, but
also increases power consumption. This bit can be set to 1 just before a major screen
update, then set back to 0 to save power after the update. This bit has no effect in SwivelView mode. Refer to REG[1Bh] SwivelView Mode Register on page 68 for SwivelView
mode clock selection.
SED1374
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Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
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bit 4
Page 57
Input Clock Divide
When this bit = 0, the operating clock(CLK) is same as the input clock (CLKI). When this
bit = 1, CLK = CLKI/2.
In landscape mode PCLK=CLK and MCLK is selected as per Table 8-3: “High Performance Selection”.
In SwivelView mode MCLK and PCLK are derived from CLK as shown in Table 8-9:
“Selection of PCLK and MCLK in SwivelView Mode,” on page 69.
bit 3
Display Blank
This bit blanks the display image. When this bit = 1, the display is blanked (FPDAT lines
to the panel are driven low). When this bit = 0, the display is enabled.
bit 2
Frame Repeat (EL support)
This feature is used to improve Frame Rate Modulation of EL panels. When this bit = 1,
an internal frame counter runs from 0 to 3FFFFh. When the frame counter rolls over, the
modulated image pattern is repeated (every 1 hour when the frame rate is 72Hz). When
this bit = 0, the modulated image pattern is never repeated.
bit 1
Hardware Video Invert Enable
In passive panel modes (REG[01h] bit 7 = 0) FPDAT11 is available as either GPIO4 or
hardware video invert. When this bit = 1, Hardware Video Invert is enabled via the
FPDAT11 pin. When this bit = 0, FPDAT11 operates as GPIO4. See Table 8-4: “Inverse
Video Mode Select Options” below.
Note
Video data is inverted after the Look-Up Table.
bit 0
Software Video Invert
When this bit = 1, Inverse video mode is selected. When this bit = 0, standard video mode
is selected. See Table 8-4: “Inverse Video Mode Select Options” below.
Note
Video data is inverted after the Look-Up Table.
Table 8-4: Inverse Video Mode Select Options
Hardware Video
Invert Enable
Software Video
Invert
(Passive and
Active Panels)
FPDAT11
(Passive Panels
Only)
Video Data
0
0
X
Normal
0
1
X
Inverse
1
X
0
Normal
1
X
1
Inverse
Hardware Functional Specification
Issue Date: 99/04/29
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REG[03h] Mode Register 2
Address = FFE3h
Look-Up
Table Bypass
bit 7
Read/Write
n/a
n/a
n/a
LCDPWR
Override
Hardware
Power Save
Enable
Software
Power Save
Bit 1
Software
Power Save
Bit 0
Look-Up Table Bypass
When the Look-Up Table Bypass bit = 0, the Green Look-Up Table is used for display
data output in gray shade modes. When this bit = 1, the Look-Up Table is bypassed for display data output in gray shade modes (for power save purposes). See “Look-Up Table
Architecture” on page 72.
There is no effect on changing this bit in color modes. In color display mode the Look-Up
Table cannot be bypassed.
bit 3
LCDPWR Override
This bit is used to override the panel on/off sequencing logic. When this bit = 0, LCDPWR
and the panel interface signals are controlled by the sequencing logic. When this bit 1,
LCDPWR is forced to off and the panel interface signals are forced low immediately upon
entering power save mode. See Section 7.3.2, “Power Down/Up Timing” on page 36 for
further information.
bit 2
Hardware Power Save Enable
When this bit = 1 GPIO0 is used as the Hardware Power Save input pin. When this bit = 0
GPIO0 operates normally.
Table 8-5: Hardware Power Save/GPIO0 Operation
RESET#
State
bits 1-0
Hardware Power
Save Enable
REG[03h] bit 2
GPIO0 Config
REG[18h] bit 0
GPIO0
Status/Control
GPIO0 Operation
REG[19h] bit 0
0
X
X
X
1
0
0
reads pin status
GPIO0 Input
(high impedance)
1
0
1
0
GPIO0 Output = 0
1
0
1
1
GPIO0 Output = 1
1
1
X
X
Hardware Power Save
Input (active high)
Software Power Save Bits [1: 0]
These bits select the Power Save Mode as shown in the following table.
Table 8-6: Software Power Save Mode Selection
SED1374
X26A-A-001-02
Bit 1
Bit 0
Mode
0
0
Software Power Save
0
1
reserved
1
0
reserved
1
1
Normal Operation
Hardware Functional Specification
Issue Date: 99/04/29
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Page 59
Refer to Power Save Modes on page 84 for a complete description.
REG[04h] Horizontal Panel Size Register
Address = FFE4h
n/a
Horizontal
Panel Size
Bit 6
bits 6-0
Horizontal
Panel Size
Bit 5
Read/Write
Horizontal
Panel Size
Bit 4
Horizontal
Panel Size
Bit 3
Horizontal
Panel Size
Bit 2
Horizontal
Panel Size
Bit 1
Horizontal
Panel Size
Bit 0
Horizontal Panel Size Bits [6:0]
This register determines the horizontal resolution of the panel. This register must be programmed with a value calculated as follows:
HorizontalPanelResolution ( pixels )
HorizontalPanelSizeRegister =  ----------------------------------------------------------------------------------------------  – 1
8
This register must not be set to a value less than 03h.
REG[05h] Vertical Panel Size Register (LSB)
Address = FFE5h
Vertical
Panel Size
Bit 7
Vertical
Panel Size
Bit 6
Vertical
Panel Size
Bit 5
Read/Write
Vertical
Panel Size
Bit 4
Vertical
Panel Size
Bit 3
Vertical
Panel Size
Bit 2
Vertical
Panel Size
Bit 1
Vertical
Panel Size
Bit 0
.
REG[06h] Vertical Panel Size Register (MSB)
Address = FFE6h
n/a
n/a
n/a
n/a
Read/Write
n/a
n/a
Vertical
Panel Size
Bit 9
Vertical
Panel Size
Bit 8
REG[05h] bits 7-0
Vertical Panel Size Bits [9:0]
REG[06h] bits 1-0
This 10-bit register determines the vertical resolution of the panel. This register must be
programmed with a value calculated as follows:
VerticalPanelSizeRegister = VerticalPanelResolution ( lines ) – 1
3FFh is the maximum value of this register for a vertical resolution of 1024 lines.
Hardware Functional Specification
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REG[07h] FPLINE Start Position
Address = FFE7h
n/a
n/a
bits 4-0
Read/Write
FPLINE Start
Position Bit 4
n/a
FPLINE Start
Position Bit 3
FPLINE Start
Position Bit 2
FPLINE Start
Position Bit 1
FPLINE Start
Position Bit 0
FPLINE Start Position
These bits are used in TFT/MD-TFD mode to specify the position of the FPLINE pulse.
These bits specify the delay, in 8-pixel resolution, from the end of a line of display data
(FPDAT) to the leading edge of FPLINE. This register is effective in TFT/MD-TFD mode
only (REG[01h] bit 7 = 1). This register is programmed as follows:
FPLINEposition ( pixels ) = ( REG [ 07h ] + 2 ) × 8
The following constraint must be satisfied:
REG [ 07h ] ≤ REG [ 08h ]
REG[08h] Horizontal Non-Display Period
Address = FFE8h
n/a
n/a
bits 4-0
Read/Write
Horizontal
Non-Display
Period Bit 4
n/a
Horizontal
Non-Display
Period Bit 3
Horizontal
Non-Display
Period Bit 2
Horizontal
Non-Display
Period Bit 1
Horizontal
Non-Display
Period Bit 0
Horizontal Non-Display Period
These bits specify the horizontal non-display period in 8-pixel resolution.
HorizontalNonDisplayPeriod ( pixels ) = ( REG [ 08h ] + 4 ) × 8
REG[09h] FPFRAME Start Position
Address = FFE9h
n/a
bits 5-0
n/a
FPFRAME
Start Position
Bit 5
Read/Write
FPFRAME
Start Position
Bit 4
FPFRAME
Start Position
Bit 3
FPFRAME
Start Position
Bit 2
FPFRAME
Start Position
Bit 1
FPFRAME
Start Position
Bit 0
FPFRAME Start Position
These bits are used in TFT/MD-TFD mode to specify the position of the FPFRAME pulse.
These bits specify the number of lines between the last line of display data (FPDAT) and
the leading edge of FPFRAME. This register is effective in TFT/MD-TFD mode only
(REG[01h] bit 7 = 1).
FPFRAMEposition ( lines ) = REG [ 09h ]
The contents of this register must be greater than zero and less than or equal to the Vertical
Non-Display Period Register, i.e.
1 ≤ REG [ 09h ] ≤ REG [ 0Ah ]
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
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Page 61
REG[0Ah] Vertical Non-Display Period
Address = FFEAh
Vertical NonDisplay
Status
Vertical NonDisplay
Period Bit 5
n/a
Read/Write
Vertical NonDisplay
Period Bit 4
Vertical NonDisplay
Period Bit 3
Vertical NonDisplay
Period Bit 2
bit 7
Vertical Non-Display Status
This bit =1 during the Vertical Non-Display period.
bits 5-0
Vertical Non-Display Period
These bits specify the vertical non-display period.
Vertical NonDisplay
Period Bit 1
Vertical NonDisplay
Period Bit 0
VerticalNonDisplayPeriod ( lines ) = REG [ 0Ah ]
Note
This register should be set only once, on power-up during initialization.
.
REG[0Bh] MOD Rate Register
Address = FFEBh
n/a
bits 5-0
MOD Rate
Bit 5
n/a
Read/Write
MOD Rate
Bit 4
MOD Rate
Bit 3
MOD Rate
Bit 2
MOD Rate
Bit 1
MOD Rate
Bit 0
MOD Rate Bits [5:0]
When the value of this register is 0, the MOD output signal toggles every FPFRAME. For
a non-zero value, the value in this register + 1 specifies the number of FPLINEs between
toggles of the MOD output signal. These bits are for passive LCD panels only.
REG[0Ch] Screen 1 Start Address Register (LSB)
Address = FFECh
Read/Write
Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start
Address
Address
Address
Address
Address
Address
Address
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[0Dh] Screen 1 Start Address Register (MSB)
Address = FFEDh
Read/Write
Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start
Address
Address
Address
Address
Address
Address
Address
Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
REG[0Dh] bit 6-0
REG[0Ch] bit 7-0
Screen 1 Start Address Bits [14:0]
These bits determine the word address of the start of Screen 1 in landscape modes or the
byte address of the start of Screen 1 in SwivelView modes.
REG[0Dh] bit 7
Screen 1 Start Address Bit 15
This bit is for SwivelView mode only and has no effect in Landscape mode.
Hardware Functional Specification
Issue Date: 99/04/29
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REG[0Fh] Screen 2 Start Address Register (LSB)
Address = FFEFh
Read/Write
Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start
Address
Address
Address
Address
Address
Address
Address
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[10h] Screen 2 Start Address Register (MSB)
Address = FFF0h
Read/Write
Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start
Address
Address
Address
Address
Address
Address
Address
Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
REG[10h] bit 6-0
REG[0Fh] bit 7-0
Screen 2 Start Address Bits [14:0]
These bits determine the word address of the start of Screen 2 in landscape modes or the
byte address of the start of Screen 2 in SwivelView modes.
REG[10h] bit 7
Screen 2 Start Address Bit 15
This bit is for SwivelView mode only and has no effect in Landscape mode.
REG[12h] Memory Address Offset Register
Address = FFF2h
Memory
Address
Offset Bit 7
bits 7-0
Memory
Address
Offset Bit 6
Memory
Address
Offset Bit 5
Memory
Address
Offset Bit 4
Read/Write
Memory
Address
Offset Bit 3
Memory
Address
Offset Bit 2
Memory
Address
Offset Bit 1
Memory
Address
Offset Bit 0
Memory Address Offset Bits
[7:0] (Landscape Modes Only)
This register is used to create a virtual image by setting a word offset between the last
address of one line and the first address of the following line. If this register is not equal to
zero, then a virtual image is formed. The displayed image is a window into the larger virtual image. See Figure 8-1: “Screen-Register Relationship, Split Screen,” on page 64.
This register has no effect in SwivelView modes. See “REG[1Ch] Line Byte Count Register for SwivelView Mode” on page 69.
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
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Page 63
.
REG[13h] Screen 1 Vertical Size Register (LSB)
Address = FFF3h
Screen 1
Vertical Size
Bit 7
Screen 1
Vertical Size
Bit 6
Screen 1
Vertical Size
Bit 5
Screen 1
Vertical Size
Bit 4
Read/Write
Screen 1
Vertical Size
Bit 3
Screen 1
Vertical Size
Bit 2
Screen 1
Vertical Size
Bit 1
REG[14h] Screen 1 Vertical Size Register (MSB)
Address = FFF4h
n/a
REG[14h] bits 1-0
REG[13h] bits 7-0
n/a
n/a
n/a
Screen 1
Vertical Size
Bit 0
Read/Write
n/a
n/a
Screen 1
Vertical Size
Bit 9
Screen 1
Vertical Size
Bit 8
Screen 1 Vertical Size Bits [9:0]
This register is used to implement the Split Screen feature of the SED1374. These bits
determine the height (in lines) of Screen 1. On reset this register is set to 0h.
In landscape modes, if this register is programmed with a value, n, where n is less than the
Vertical Panel Size (REG[06h], REG[05h]), then lines 0 to n of the panel contain Screen 1
and lines n+1 to REG[06h], REG[05h] of the panel contain Screen 2. See Figure 8-1:
“Screen-Register Relationship, Split Screen,” on page 64. If Split Screen is not desired,
this register must be programmed greater than, or equal to the Vertical Panel Size,
REG[06h] and REG[05h].
In SwivelView modes this register must be programmed greater than, or equal to the Vertical Panel Size, REG[06h] and REG[05h]. See “SwivelView™” on page 79.
Hardware Functional Specification
Issue Date: 99/04/29
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(REG[0Dh], REG[0Ch]) Words
Line 0 Last Pixel Address + REG[12h] Words
Line 0 Last Pixel Address=((REG[0Dh], REG[0Ch]) +
(8(REG[04h]+1) × BPP/16))
Words
Line 0
Line 1
Image 1
((REG[06h], REG[05])+1) Lines
Line=(REG[14h], REG[13h])
Image 2
(REG[10h], REG[0Fh]) Words
8(REG[04h]+1) Pixels
Where:
(REG[0Dh], REG[0Ch]) is the Screen 1 Start Word Address
BPP is Bits-per-Pixel as set by REG[02h] bits 7:6
REG[12h] is the Address Pitch Adjustment in Words
(REG[10h], REG[0Fh]) is the Screen 2 Start Word Address
(REG[14h], REG[13h]) is the Screen 1 Vertical Size
(REG[06h], REG[05h]) is the Vertical Panel Size
REG[12h] Words
Virtual Image
Figure 8-1: Screen-Register Relationship, Split Screen
Consider an example where REG[14h], REG[13h]= 0CEh for a 320x240 display system.
The upper 207 lines (CEh + 1) of the panel show an image from the Screen 1 Start Word
Address. The remaining 33 lines show an image from the Screen 2 Start Word Address.
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
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Page 65
REG[15h] Look-Up Table Address Register
Address = FFF5h
n/a
RGB Index
Bit 1
n/a
Read/Write
RGB Index
Bit 0
Look-Up
Table
Address
Bit 3
Look-Up
Table
Address
Bit 2
Look-Up
Table
Address
Bit 1
Look-Up
Table
Address
Bit 0
The SED1374 has three 16-position, 4-bit wide Look-Up Tables, one each for red, green,
and blue. Refer to “Look-Up Table Architecture” for details. This register selects which
Look-Up Table position is read/write accessible through the Look-Up Table Data Register
(REG[17h]).
bits 5-4
RGB Index Bits [1:0]
These bits select between the Red, Green, and Blue Look-Up Tables, and Auto-Increment
mode. The Green Look-Up Table is used in monochrome mode with these bits set to 10b.
See Note below.
bits 3-0
Look-Up Table Address Bits [3:0]
These 4 bits select one of the 16 positions in the selected Look-Up Table. These bits are
automatically changed as the Look-Up Table Data Register is accessed. See Note below.
Note
Accesses to the Look-Up Table Data Register automatically increment a pointer into the
RGB Look-Up Tables. The pointer sequence varies as shown in the table below.
Table 8-7: Look-Up Table Access
REG[01h]
REG[15h]
Look-Up Table
Selected
Pointer Sequence
bit 5
bit 5
bit 4
0
1
0
Green/Gray LookUp Table
G[n], G[n+1], G[n+2],...
1
0
0
Auto-Increment
R[n], G[n], B[n], R[n+1], G[n+1],...
1
0
1
Red Look-Up Table
R[n], R[n+1], R[n+2],...
G[n], G[n+1], G[n+2],...
B[n], B[n+1], B[n+2],...
1
1
0
Green/Gray LookUp Table
1
1
1
Blue Look-Up Table
In Auto-Increment mode, writing the Look-Up Table Address Register automatically
sets the pointer to the Red Look-Up Table. For example, writing a value 03 into the
Look-Up Table Address Register selects Auto-Increment mode and sets the pointer to
R[3]. Subsequent accesses to the Look-Up Table Data Register move the pointer onto
G[3], B[3], R[4], etc.
Hardware Functional Specification
Issue Date: 99/04/29
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.
REG[16h] Look-Up Table Bank Select Register
Address = FFF6h
n/a
Red Bank
Select
Bit 1
n/a
Red Bank
Select
Bit 0
Read/Write
Green Bank
Select
Bit 1
Green Bank
Select
Bit 0
Blue Bank
Select
Bit 1
Blue Bank
Select
Bit 0
bits 7-6
n/a
bits 5-4
Red Bank Select Bits [1:0]
In 1 bit-per-pixel (bpp) color mode the lower 8 positions of the Red Look-Up Table is
arranged into four banks, each with two positions. These two bits select which bank is
used for display data.
In 2 bpp color mode the 16 position Red Look-Up Table is arranged into four banks, each
with four positions. These two bits select which bank is used for display data.
These bits have no effect in 4 bpp color/gray modes.
In 8 bpp color mode the 16 position, Red Look-Up Table is arranged into two banks, each
with eight positions. Red Bank Select bit 0 selects which bank is used for display data.
bits 3-2
Green Bank Select Bits [1:0]
In 1 bit-per-pixel (bpp) color/gray mode the lower 8 positions of the Green Look-Up Table
is arranged into four banks, each with two positions. These two bits select which bank is
used for display data.
In 2 bpp color/gray mode, the 16 position Green Look-Up Table is arranged into four
banks, each with four positions. These two bits select which bank is used for display data.
These bits have no effect in 4 bpp color/gray modes.
In 8 bpp color mode, the 16 position Green Look-Up Table is arranged into two banks,
each with eight positions. Green Bank Select bit 0 selects which bank is used for display
data.
bit 1-0
Blue Bank Select Bits [1:0]
In 1 bit-per-pixel (bpp) color mode the lower 8 positions of the Blue Look-Up Table is
arranged into four banks, each with two positions. These two bits select which bank is
used for display data.
In 2 bpp color mode, the 16 position Blue Look-Up Table is arranged into four banks, each
with four positions. These two bits select which bank is used for display data.
These bits have no effect in 4 bpp color/gray modes.
In 8 bpp color mode, the 16 position Blue Look-Up Table is arranged into four banks, each
with four positions. These two bits select which bank is used for display data.
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
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Page 67
REG[17h] Look-Up Table Data Register
Address = FFF7h
n/a
n/a
bits 3-0
n/a
Read/Write
n/a
Look-Up
Table Data
Bit 3
Look-Up
Table Data
Bit 2
Look-Up
Table Data
Bit 1
Look-Up Table Data Bits [3:0]
This register is used to read/write the RGB Look-Up Tables. This register is an aperture
into the three 16-position Look-Up Tables. The Look-Up Table Address Register
(REG[16h]) selects which Look-Up Table position is accessible. See REG[16h] Look-Up
Table Bank Select Register on page 66.
REG[18h] GPIO Configuration Control Register
Address = FFF8h
n/a
Look-Up
Table Data
Bit 0
n/a
bits 4-0
n/a
Read/Write
GPIO4 Pin IO GPIO3 Pin IO GPIO2 Pin IO GPIO1 Pin IO GPIO0 Pin IO
Configuration Configuration Configuration Configuration Configuration
GPIO[4:0] Pin IO Configuration
These bits determine the direction of the GPIO[4:0] pins.
When GPIOn Pin IO Configuration bit = 0, the corresponding GPIOn pin is configured as
an input. The input can be read at the GPIOn Status/Control Register bit. See REG[19h]
below.
When GPIOn Pin IO Configuration bit = 1, the corresponding GPIOn pin is configured as
an output. The output can be controlled by writing the GPIOn Status/Control Register bit.
Note
These bits have no effect when the GPIOn pin is configured for a specific function (i.e.
as FPDAT[11:8] for TFT/MD-TFD operation). All unused GPIO pins must be tied to
IO VDD.
REG[19h] GPIO Status/Control Register
Address = FFF9h
n/a
bits 4-0
n/a
n/a
Read/Write
GPIO4 Pin IO
Status
GPIO3 Pin IO
Status
GPIO2 Pin IO
Status
GPIO1 Pin IO
Status
GPIO0 Pin IO
Status
GPIO[4:0] Status
When the GPIOn pin is configured as an input, the corresponding GPIO Status bit is used
to read the pin input. See REG[18h] above.
When the GPIOn pin is configured as an output, the corresponding GPIO Status bit is used
to control the pin output.
Hardware Functional Specification
Issue Date: 99/04/29
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REG[1Ah] Scratch Pad Register
Address = FFFAh
Scratch bit 7
bits 7-0
Scratch bit 6
Read/Write
Scratch bit 5
Scratch bit 4
Scratch bit 3
Scratch bit 2
Scratch bit 1
Scratch Pad Register
This register contains general use read/write bits. These bits have no effect on hardware.
REG[1Bh] SwivelView Mode Register
Address = FFFBh
SwivelView
Mode Enable
Scratch bit 0
SwivelView
Mode Select
Read/Write
n/a
n/a
n/a
reserved
SwivelView
Mode Pixel
Clock Select
Bit 1
SwivelView
Mode Pixel
Clock Select
Bit 0
bit 7
SwivelView Mode Enable
When this bit = 1, SwivelView Mode is enabled. When this bit = 0, Landscape Mode is
enabled.
bit 6
SwivelView Mode Select
When this bit = 0, Default SwivelView Mode is selected. When this bit = 1, Alternate
SwivelView Mode is selected. See Section 12, “SwivelView™” on page 79 for further
information on SwivelView Mode.
The following table shows the selection of SwivelView Mode.
Table 8-8: Selection of SwivelView Mode
SwivelView SwivelView
Mode Enable Mode Select
Mode
(REG[1Bh] bit 7) (REG[1Bh] bit 6)
0
X
Landscape
1
0
Default SwivelView
1
1
Alternate SwivelView
bit 2
reserved
reserved bits must be set to 0.
bits 1-0
SwivelView Mode Pixel Clock Select Bits [1:0]
These two bits select the Pixel Clock (PCLK) source in SwivelView Mode - these bits
have no effect in Landscape Mode. The following table shows the selection of PCLK and
MCLK in SwivelView Mode - see Section 12, “SwivelView™” on page 79 for details.
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
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Page 69
Table 8-9: Selection of PCLK and MCLK in SwivelView Mode
Pixel Clock (PCLK) Select
SwivelView
Mode Enable
SwivelView
Mode Select
(REG[1Bh] bit 7)
(REG[1Bh] bit 6)
Bit 1
Bit 0
0
X
X
1
0
1
(REG[1Bh] bits [1:0]
PCLK =
MCLK =
X
CLK
See Reg[02h] bit 5
0
0
CLK
CLK
0
0
1
CLK/2
CLK/2
1
0
1
0
CLK/4
CLK/4
1
0
1
1
CLK/8
CLK/8
1
1
0
0
CLK/2
CLK
1
1
0
1
CLK/2
CLK
1
1
1
0
CLK/4
CLK/2
1
1
1
1
CLK/8
CLK/4
Where CLK is CLKI (REG[02h] bit 4 = 0) or CLKI/2 (REG[02h] bit 4 = 1)
REG[1Ch] Line Byte Count Register for SwivelView Mode
Address = FFFCh
Line Byte
Count bit 7
bits 7-0
Line Byte
Count bit 6
Line Byte
Count bit 5
Line Byte
Count bit 4
Line Byte
Count bit 3
Read/Write
Line Byte
Count bit 2
Line Byte
Count bit 1
Line Byte
Count bit 0
Line Byte Count Bits [7:0]
This register is the byte count from the beginning of one line to the beginning of the next
consecutive line (commonly called “stride” by programmers). This register may be used to
create a virtual image in SwivelView mode.
REG[1Eh] and REG[1Fh]
REG[1Eh] and REG[1Fh] are reserved for factory SED1374 testing and should not be
written. Any value written to these registers may result in damage to the SED1374 and/or
any panel connected to the SED1374.
Hardware Functional Specification
Issue Date: 99/04/29
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9 Frame Rate Calculation
The following formulae are used to calculate the display frame rate.
TFT/MD-TFD and Passive Single-Panel modes
f PCLK
FrameRate = ----------------------------------------------------------------------------------------( HDP + HNDP ) × ( VDP + VNDP )
Where: fPCLK
HDP
HNDP
VDP
VNDP
= PClk frequency (Hz)
= Horizontal Display Period = ((REG[04h] bits 6-0) + 1) x 8 Pixels
= Horizontal Non-Display Period = ((REG[08h] bits 4-0) + 4) x 8 Pixels
= Vertical Display Period = ((REG[06h] bits 1-0, REG[05h] bits 7-0) + 1) Lines
= Vertical Non-Display Period = (REG[0Ah] bits 5-0) Lines
Passive Dual-Panel mode
f PCLK
FrameRate = -------------------------------------------------------------------------------------------------VDP
2 × ( HDP + HNDP ) × ------------ + VNDP
2
Where:
SED1374
X26A-A-001-02
fPCLK
HDP
HNDP
VDP
VNDP
= PClk frequency (Hz)
= Horizontal Display Period = ((REG[04h] bits 6-0) + 1) x 8 Pixels
= Horizontal Non-Display Period = ((REG[08h] bits 4-0) + 4) x 8 Pixels
= Vertical Display Period = ((REG[06h] bits 1-0, REG[05h] bits 7-0) + 1) Lines
= Vertical Non-Display Period = (REG[0Ah] bits 5-0) Lines
Hardware Functional Specification
Issue Date: 99/04/29
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10 Display Data Formats
1-bpp:
bit 7
A0
Byte 0
bit 0
A1
A2
A3
A4
A5
A6
P0 P1 P2 P3 P4 P5 P6 P7
A7
Pn = (An)
Panel Display
Host Address
Display Memory
2-bpp:
bit 7
bit 0
Byte 0
A0
B0
A1
B1
A2
B2
A3
B3
Byte 1
A4
B4
A5
B5
A6
B6
A7
B7
P0 P1 P2 P3 P4 P5 P6 P7
Pn = (An, Bn)
Panel Display
Host Address
Display Memory
4-bpp:
bit 7
bit 0
Byte 0
A0
B0
C0
D0
A1
B1
C1
D1
Byte 1
A2
B2
C2
D2
A3
B3
C3
D3
Byte 2
A4
B4
C4
D4
A5
B5
C5
D5
P0 P1 P2 P3 P4 P5 P6 P7
Pn = (An, Bn, Cn, Dn)
Panel Display
Host Address
Display Memory
8-bpp:
3-3-2 RGB
bit 7
bit 0
Byte 0
1
R02 R01 R00 G02 G01 G00 B0 B00
Byte 1
1
R12 R11 R10 G12 G11 G10 B1 B10
Byte 2
1
R22 R21 R20 G22 G21 G20 B2 B20
P0 P1 P2 P3 P4 P5 P6 P7
Pn = (Rn2-0, Gn 2-0, Bn1-0)
Panel Display
Host Address
Display Memory
Figure 10-1: 1/2/4/8 Bit-Per-Pixel Display Data Memory Organization
Hardware Functional Specification
Issue Date: 99/04/29
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11 Look-Up Table Architecture
Table 11-1: Look-Up Table Configurations
Display Mode
4-bit wide Look-Up Table
RED
GREEN
2-level gray
4 banks of 2
4-level gray
4 banks of 4
16-level gray
BLUE
1 bank of 16
2 color
4 bank of 2
4 bank of 2
4 bank of 2
4 color
4 banks of 4
4 banks of 4
4 banks of 4
16 color
1 bank of 16
1 bank of 16
1 bank of 16
256 color
2 banks of 8
2 banks of 8
4 banks of 4
Indicates the Look-Up Table is not used for that display mode
The following figures are intended to show the display data output path only. The CPU
R/W access to the individual Look-Up Tables is not affected by the various ‘banking’
configurations.
11.1 Gray Shade Display Modes
2-Level Gray Shade Mode
2 Gray Data Format:
7
Green Look-Up Table
6
5
4
3
2
1
0
A0 A1 A2 A3 A4 A5 A6 A7
1-bit pixel data
0
1
2
3
See Section 10
Bank
Select
Logic
4-bit display data output
4
5
6
7
Green Bank Select
REG[16h] bits [3:2]
Figure 11-1: 2-Level Gray-Shade Mode Look-Up Table Architecture
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Hardware Functional Specification
Issue Date: 99/04/29
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Page 73
4-Level Gray Shade Mode
4 Gray Data Format:
7
6
5
4
3
2
1
0
Green Look-Up Table
A0 B0 A1 B1 A2 B2 A3 B3
See Section 10
Bank 0
0
1
2
3
2-bit pixel data
Bank 1
0
1
2
3
Bank 2
Bank
Select
Logic
4-bit display data output
0
1
2
3
Bank 3
0
1
2
3
Green Bank Select
REG[16h] bits [3:2]
Figure 11-2: 4-Level Gray-Shade Mode Look-Up Table Architecture
16-Level Gray Shade Mode
16 Gray Data Format:
7
6
5
4
3
2
1
0
A0 B0 C0 D0 A1 B1 C1 D1
See Section 10
4-bit pixel data
Green Look-Up Table 16x4
0
1
2
3
4-bit display data output
C
D
E
F
Figure 11-3: 16-Level Gray-Shade Mode Look-Up Table Architecture
Hardware Functional Specification
Issue Date: 99/04/29
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Look-Up Table Bypass Mode
Look-Up Tables
1 bit pixel data (An)
2 bit pixel data (An, Bn)
4 bit pixel data (An, Bn, Cn, Dn)
1 bit display data output (An)
4 bit display data output (An, Bn, An, Bn)
4 bit display data output (An, Bn, Cn, Dn)
Figure 11-4: Look-Up Table Bypass Mode Architecture
Note
In 1 bit-per-pixel display mode, Look-Up Table Bypass mode will turn off the FRM
circuitry and place the SED1374 in Black-and-White mode.
In 2 bit-per-pixel mode the Display Data Output values are 0, 5, A, and F (in hex).
SED1374
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Hardware Functional Specification
Issue Date: 99/04/29
Epson Research and Development
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Page 75
11.2 Color Display Modes
2-Level Color Mode
2 Color Data Format:
7
Red Look-Up Table
1-bit pixel data
0
1
2
3
4
5
6
5
4
3
2
1
0
A0 A1 A2 A3 A4 A5 A6 A7
See Section 10
Bank
Select
Logic
4-bit ‘Red’ display data output
6
7
Red Bank Select
REG[16h] bits [5:4]
Green Look-Up Table
0
1
2
3
4
5
Bank
Select
Logic
4-bit ‘Green’ display data output
6
7
Green Bank Select
REG[16h] bits [3:2]
Blue Look-Up Table
0
1
2
3
4
5
Bank
Select
Logic
4-bit ‘Blue’ display data output
6
7
Blue Bank Select
REG[16h] bits [1:0]
Figure 11-5: 2-Level Color Look-Up Table Architecture
Hardware Functional Specification
Issue Date: 99/04/29
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4-Level Color Mode
4 Color Data Format:
2-bit pixel data
Red Bank Select
REG[16h] bits [5:4]
Green Bank Select
REG[16h] bits [3:2]
Blue Bank Select
REG[16h] bits [1:0]
7
6
5
4
Red Look-Up Table
Bank 0
0
1
2
3
Bank 1
0
1
2
3
Bank 2
0
1
2
3
Bank 3
0
1
2
3
Bank
Select
Logic
4-bit ‘Red’ display data output
Green Look-Up Table
Bank 0
0
1
2
3
Bank 1
0
1
2
3
Bank 2
0
1
2
3
Bank 3
0
1
2
3
Bank
Select
Logic
4-bit ‘Green’ display data output
Bank
Select
Logic
4-bit ‘Blue’ display data output
Blue Look-Up Table
Bank 0
0
1
2
3
Bank 1
0
1
2
3
Bank 2
0
1
2
3
Bank 3
0
1
2
3
3
2
1
0
A0 B0 A1 B1 A2 B2 A3 B3
See Section 10
Figure 11-6: 4-Level Color Mode Look-Up Table Architecture
SED1374
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Hardware Functional Specification
Issue Date: 99/04/29
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16-Level Color Mode
16 Color Data Format:
7
6
5
4
3
2
1
0
A0 B0 C0 D0 A1 B1 C1 D1
See Section 10
4-bit pixel data
Red Look-Up Table 16x4
0
1
2
3
4-bit ‘Red’ display data output
C
D
E
F
Green Look-Up Table 16x4
0
1
2
3
4-bit ‘Green’ display data output
C
D
E
F
Blue Look-Up Table 16x4
0
1
2
3
4-bit ‘Blue’ display data output
C
D
E
F
Figure 11-7: 16-Level Color Mode Look-Up Table Architecture
Hardware Functional Specification
Issue Date: 99/04/29
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256-Level Color Mode
256 Color Data Format:
7
6
5
4
3
2
Red Look-Up Table
1
0
Bank 0
R2 R1 R0 G2 G1 G0 B1 B0
See Section 10
3-bit pixel data
0
1
2
3
4
5
6
7
Bank 1
0
1
2
3
4
5
6
7
Bank
Select
Logic
Red Bank Select
REG[16h] bit 4
3-bit pixel data
Green Look-Up Table
Bank 0
0
1
2
3
4
5
6
7
Bank 1
0
1
2
3
4
5
6
7
Bank
Select
Logic
Green Bank Select
REG[16h] bit 2
2-bit pixel data
Blue Look-Up Table
Bank 0
0
1
2
3
Bank 1
0
1
2
3
Bank 2
0
1
2
3
Bank 3
0
1
2
3
Bank
Select
Logic
Blue Bank Select
REG[16h] bits [1:0]
Figure 11-8: 256-Level Color Mode Look-Up Table Architecture
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
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Page 79
12 SwivelView™
Many of todays applications use the LCD panel in a portrait orientation. In this case it
becomes necessary to “rotate” the displayed image. This rotation can be done by software
at the expense of performance or, as with the SED1374, it can be done by hardware with
no CPU penalty.
There are two SwivelView modes: Default SwivelView and Alternate SwivelView.
12.1 Default SwivelView Mode
Default SwivelView Mode requires the portrait image width be a power of two, e.g. a 240line panel requires a minimum virtual image width of 256. This mode should be used
whenever the required virtual image can be contained within the integrated display buffer
(i.e. virtual image size ≤ 40k bytes), as it consumes less power than the Alternate
SwivelView mode.
For example, the panel size is 320x240 and the display mode is 4 bit-per-pixel. The virtual
image size is 320x256 which can be contained within the 40k Byte display buffer.
Default SwivelView Mode also requires memory clock (MCLK) ≥ pixel clock (PCLK).
The following figure shows how the programmer sees a 240x320 image and how the image
is displayed. The application image is written to the SED1374 in the following sense:
A–B–C–D. The display is refreshed by the SED1374 in the following sense: B-D-A-C.
physical
memory
start
address
256
C
240
256
D
window
display
start
address
SwivelView
SwivelView
window
E
E
B
B
A
320
A
D
C
320
240
image seen by programmer
= image in display buffer
image refreshed by SED1374
Figure 12-1: Relationship Between The Screen Image and the Image Refreshed by SED1374
Hardware Functional Specification
Issue Date: 99/04/29
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X26A-A-001-02
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12.1.1 How to Set Up Default SwivelView Mode
The following describes the register settings needed to set up Default SwivelView Mode
for a 240x320x4 bpp image:
• Select Default SwivelView Mode: REG[1Bh] bit 7 = 1 and bit 6 = 0
• The display refresh circuitry starts at pixel “B”, therefore the Screen 1 Start Address
register must be programmed with the address of pixel “B”, i.e.
REG [ 0Dh ], REG [ 0Ch ] = AddressOfPixelB
= ( AddressOfPixelA + ByteOffset )
240pixels × 4bpp
= AddressOfPixelA +  --------------------------------------------  – 1
8bpb
= AddressOfPixelA + 77h
Where bpp is bits-per-pixel and bpb is bits-per-byte.
• The Line Byte Count Register for SwivelView Mode must be set to the virtual-image
width in bytes, i.e.
256
256
REG [ 1Ch ] = ------------------------------------------ = --------- = 128 = 80h
( 8bpb ) ÷ ( 4bpp )
2
Where bpb is bits-per-byte and bpp is bits-per-pixel.
• Panning is achieved by changing the Screen 1 Start Address register:
• Increment the register by 1 to pan horizontally by one byte, e.g. two pixels in 4 bpp
mode
• Increment the register by twice the value in the Line Byte Count register to pan vertically by two lines, e.g. add 100h to pan by two lines in the example above.
Note
Vertical panning by a single line is not supported in Default SwivelView Mode.
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
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Page 81
12.2 Alternate SwivelView Mode
Alternate SwivelView Mode may be used when the virtual image size of Default
SwivelView Mode cannot be contained in the 40kByte integrated frame buffer. For
example, the panel size is 240x160 and the display mode is 8 bit-per-pixel. The minimum
virtual image size for Default SwivelView Mode would be 240x256 which requires 60K
bytes. Alternate SwivelView Mode requires a panel size of only 240x160 which needs only
38,400 bytes.
Alternate SwivelView Mode requires the memory clock (MCLK) to be at least twice the
frequency of the pixel clock (PCLK), i.e. MCLK ≥ 2 x PCLK. Because of this, the power
consumption in Alternate SwivelView Mode is higher than in Default SwivelView Mode.
The following figure shows how the programmer sees a 240x160 image and how the image
is being displayed. The application image is written to the SED1374 in the following sense:
A–B–C–D. The display is refreshed by the SED1374 in the following sense: B-D-A-C.
C
display
start
address
SwivelView
window
SwivelView
window
160
D
B
A
240
A
B
physical
memory
start
address
D
C
240
160
image seen by programmer
= image in display buffer
image refreshed by SED1374
Figure 12-2: Relationship Between The Screen Image and the Image Refreshed by SED1374
Hardware Functional Specification
Issue Date: 99/04/29
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12.2.1 How to Set Up Alternate SwivelView Mode
The following describes the register settings needed to set up Alternate SwivelView Mode
for a 160x240x8 bpp image.
• Select Alternate SwivelView Mode:
REG[1Bh] bit 7 = 1 and bit 6 = 1
• The display refresh circuitry starts at pixel “B”, therefore the Screen 1 Start Address
register must be programmed with the address of pixel “B”, or
REG [ 0Dh ], REG [ 0Ch ] = AddressOfPixelB
= ( AddressOfPixelA + ByteOffset )
160pixels × 8bpp
= AddressOfPixelA +  --------------------------------------------  – 1
8bpb
= AddressOfPixelA + 9Fh
Where bpp is bits-per-pixel and bpb is bits-per-byte.
• The Line Byte Count Register for SwivelView Mode must be set to the image width in
bytes, i.e.
160
160
REG [ 1Ch ] = ------------------------------------------ = --------- = 160 = A0h
( 8bpb ) ÷ ( 8bpp )
1
Where bpb is bits-per-byte and bpp is bits-per-pixel.
• Panning is achieved by changing the Screen 1 Start Address register:
• Increment the register by 1 to pan horizontally by one byte, e.g. one pixel in 8 bpp
mode
• Increment the register by the value in the Line Byte Count register to pan vertically by
one line, e.g. add A0h to pan by one line in the example above
SED1374
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Hardware Functional Specification
Issue Date: 99/04/29
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Page 83
12.3 Comparison Between Default and Alternate SwivelView Modes
Table 12-1: Default and Alternate SwivelView Mode Comparison
Item
Default SwivelView Mode
Alternate SwivelView Mode
The width of the rotated image must be
a power of 2. In most cases, a virtual
image is required where the right-hand
side of the virtual image is unused and
memory is wasted. For example, a
Memory Requirements 160x240x8bpp image would normally Does not require a virtual image.
require only 38,400 bytes - possible
within the 40K byte address space, but
the virtual image is 256x240x8bpp
which needs 61,440 bytes - not
possible.
CLK need only be as fast as the
required PCLK.
MCLK, and hence CLK, need to be 2x
PCLK. For example, if the panel requires a
3MHz PCLK, then CLK must be 6MHz.
Note that 25MHz is the maximum CLK, so
PCLK cannot be higher than 12.5MHz in
this mode.
Power Consumption
Lowest power consumption.
Higher than Default Mode.
Panning
Vertical panning in 2 line increments.
Vertical panning in 1 line increments.
Performance
Nominal performance.
Higher performance than Default Mode.
Clock Requirements
12.4 SwivelView Mode Limitations
The only limitation to using SwivelView mode on the SED1375 is that split screen
operation is not supported.
Hardware Functional Specification
Issue Date: 99/04/29
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13 Power Save Modes
Two Power Save Modes have been incorporated into the SED1374 to accommodate the
need for power reduction in the hand-held devices market. These modes are enabled as
follows:
Table 13-1: Power Save Mode Selection
Hardware Power
Save
Software Power
Save Bit 1
Software Power
Save Bit 0
Mode
Not Configured or 0
0
0
Software Power Save Mode
Not Configured or 0
0
1
reserved
Not Configured or 0
1
0
reserved
Not Configured or 0
1
1
Normal Operation
Configured and 1
X
X
Hardware Power Save Mode
13.1 Software Power Save Mode
Software Power Save Mode saves power by powering down the panel and stopping display
refresh accesses to the display buffer.
Table 13-2: Software Power Save Mode Summary
• Registers read/write accessible
• Memory read/write accessible
• LCD outputs are forced low
13.2 Hardware Power Save Mode
Hardware Power Save Mode saves power by powering down the panel, stopping accesses
to the display buffer and registers, and disabling the Host Bus Interface.
Table 13-3: Hardware Power Save Mode Summary
• Host Interface not accessible
• Memory read/write not accessible
• LCD outputs are forced low
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
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Page 85
13.3 Power Save Mode Function Summary
Table 13-4: Power Save Mode Function Summary
Hardware
Power Save
Software
Power Save
Normal
IO Access Possible?
No
Yes
Yes
Memory Access Possible?
No
Yes
Yes
Sequence Controller Running?
No
No
Yes
Display Active?
No
No
Yes
LCDPWR
Inactive
Inactive
Active
FPDAT[11:0], FPSHIFT (see note)
Forced Low
Forced Low
Active
FPLINE, FPFRAME, DRDY
Forced Low
Forced Low
Active
Note
When FPDAT[11:8] are designated as GPIO outputs, the output state prior to enabling
the Power Save Mode is maintained. When FPDAT[11:8] are designated as GPIO inputs, unused inputs must be tied to either IO VDD or GND - see Table 5-3: “LCD Interface Pin Mapping,” on page 23.
13.4 Panel Power Up/Down Sequence
After chip reset or when entering/exiting a power save mode, the Panel Interface signals
follow a power on/off sequence shown below. This sequence is essential to prevent damage
to the LCD panel.
Hardware Functional Specification
Issue Date: 99/04/29
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X26A-A-001-02
Page 86
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RESET#
Software Power Save
REG[03h] bits [1:0]
00
11
00
11
or
Hardware Power Save
LCDPWR
Power Save Mode
(CNF4 = Low)
LCDPWR
(CNF4 = Hi)
Panel Interface
Output Signals
(except LCDPWR)
0 frame
power-up
127 frames
power-down
0 frame
power-up
Figure 13-1: Panel On/Off Sequence
After chip reset, LCDPWR is inactive and the rest of the panel interface output signals are
held ‘low’. Software initializes the chip (i.e. programs the registers) and then - as a last step
set - programs REG[03h] bits [1:0] to 11. This starts the power-up sequence as shown. The
power-up/power-down sequence delay is 127 frames.
The power-up/power-down sequence also occurs when exiting/entering Software Power
Save Mode.
13.5 Turning Off BCLK Between Accesses
BCLK may be turned off (held low) between accesses if the following rules are observed:
1. BCLK must be turned off/on in a glitch free manner
2. BCLK must continue for a period equal to [8TBCLK + 12TMCLK] after the end of the
access (RDY# asserted or WAIT# deasserted).
3. BCLK must be present for at least one TBCLK before the start of an access.
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
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Page 87
13.6 Clock Requirements
The following table shows what clock is required for which function in the SED1374.
Table 13-5: SED1374 Internal Clock Requirements
Function
BCLK
CLKI
Register Read/Write
Is required during register accesses. BCLK
can be shut down between accesses: allow
eight BCLK pulses plus 12 MCLK pulses
(8TBCLK + 12TMCLK) after the last access
before shutting BCLK off. Allow one BCLK
pulse after starting up BCLK before the next
access
Not Required
Memory Read/Write
Is required during memory accesses. BCLK
can be shut down between accesses: allow
eight BCLK pulses plus 12 MCLK pulses
(8TBCLK + 12TMCLK) after the last access
before shutting BCLK off. Allow one BCLK
pulse after starting up BCLK before the next
access
Required
Software Power Save
Required
Hardware Power Save
Not Required
Hardware Functional Specification
Issue Date: 99/04/29
Can be stopped after 128 frames from
entering Software Power Save, i.e. after
REG[03h] bits 1-0 = 11
Can be stopped after 128 frames from
entering Hardware Power Save
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14 Mechanical Data
QFP14 - 80 pin
Unit: mm
14.0 ± 0.4
12.0 ± 0.1
60
41
14.0 ± 0.4
40
12.0 ± 0.1
61
Index
80
21
0.125
1.4 ± 0.1
+ 0.05
- 0.025
1
+ 0.1
0.5
20
0.18 - 0.05
0.1
0~10°
0.5 ± 0.2
1.0
Figure 14-1: Mechanical Drawing QFP14
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29
SED1374 Embedded Memory Color LCD Controller
Programming Notes and Examples
Copyright © 1998, 1999 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
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SED1374
X26A-G-002-02
Programming Notes and Examples
Issue Date: 99/04/27
Epson Research and Development
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Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Memory Models . . . . . . . . . . . . . . . . . . .
3.1 Display Buffer Location . . . . . . . . . . .
3.1.1 1 Bit-Per-Pixel (2 Colors/Gray Shades) . . . .
3.1.2 2 Bit-Per-Pixel (4 Colors/Gray Shades) . . . .
3.1.3 4 Bit-Per-Pixel (16 Colors/Gray Shades) . . .
3.1.4 Eight Bit-Per-Pixel (256 Colors) . . . . . . .
4
Look-Up Table (LUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Look-Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Look-Up Table (LUT) Organization . . . . . . . . . . . . . . . . . . . . . . 19
5
Advanced Techniques .
5.1 Virtual Display . . .
5.1.1 Registers . . . .
5.1.2 Examples . . .
5.2 Panning and Scrolling
5.2.1 Registers . . . .
5.2.2 Examples . . .
5.3 Split Screen . . . .
5.3.1 Registers . . . .
5.3.2 Examples . . .
6
LCD Power Sequencing and Power Save Modes
6.1 LCD Power Sequencing . . . . . . . . . .
6.2 Registers . . . . . . . . . . . . . . . .
6.3 LCD Enable/Disable . . . . . . . . . . . .
7
SwivelView™ . . . . . . . . . .
7.1 Introduction To SwivelView .
7.2 Default SwivelView Mode .
7.3 Alternate SwivelView Mode .
7.4 Registers . . . . . . . .
7.5 Limitations . . . . . . .
7.6 Examples . . . . . . . .
8
Identifying the SED1374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9
Hardware Abstraction Layer (HAL) . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Programming Notes and Examples
Issue Date: 99/04/27
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SED1374
X26A-G-002-02
Page 4
Epson Research and Development
Vancouver Design Center
9.2
API for 1374HAL . . . . . . . .
9.2.1 Initialization . . . . . . . . . . .
9.2.2 Miscellaneous HAL Support . .
9.2.3 Advanced HAL Functions . . . .
9.2.4 Register / Memory Access . . . .
9.2.5 Power Save . . . . . . . . . . .
9.2.6 Drawing . . . . . . . . . . . . .
9.2.7 LUT Manipulation . . . . . . . .
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10 Sample Code . . . . . . . . . . . . . . . . . . . . . . . . .
10.1 Introduction . . . . . . . . . . . . . . . . . . . .
10.1.1 Sample code using the SED1374 HAL API . . . . . . .
10.1.2 Sample code without using the SED1374 HAL API . .
10.1.3 Header Files . . . . . . . . . . . . . . . . . . . . . . .
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SED1374
X26A-G-002-02
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Programming Notes and Examples
Issue Date: 99/04/27
Epson Research and Development
Vancouver Design Center
Page 5
List of Tables
Table 2-1: SED1374 Initialization Sequence . . . . . . . . . . . . . . . . . .
Table 4-1: 2 Bpp Banking Scheme . . . . . . . . . . . . . . . . . . . . . . .
Table 4-2: 4 Bpp Banking Scheme . . . . . . . . . . . . . . . . . . . . . . .
Table 4-3: 8 Bpp Banking Scheme . . . . . . . . . . . . . . . . . . . . . . .
Table 4-4: Look-Up Table Configurations . . . . . . . . . . . . . . . . . . .
Table 4-5: Recommended LUT Values for 1 Bpp Color Mode . . . . . . . . .
Table 4-6: LUT Values for 2 Bpp Color Mode . . . . . . . . . . . . . . . . .
Table 4-7: Suggested LUT Values to Simulate VGA Default 16 Color Palette
Table 4-8: Suggested LUT Values to Simulate VGA Default 256 Color Palette
Table 4-9: Recommended LUT Values for 1 Bpp Gray Shade . . . . . . . . .
Table 4-10: Suggested Values for 2 Bpp Gray Shade . . . . . . . . . . . . . .
Table 4-11: Suggested LUT Values for 4 Bpp Gray Shade . . . . . . . . . . .
Table 5-1: Number of Pixels Panned Using Start Address . . . . . . . . . . .
Table 7-1: Default and Alternate SwivelView Mode Comparison . . . . . . .
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41
Pixel Storage for 1 Bpp (2 Colors/Gray Shades) in One Byte of Display Buffer .
Pixel Storage for 2 Bpp (4 Colors/Gray Shades) in One Byte of Display Buffer .
Pixel Storage for 4 Bpp (16 Colors/Gray Shades) in One Byte of Display Buffer
Pixel Storage for 8 Bpp (256 Colors) in One Byte of Display Buffer . . . . . . .
Viewport Inside a Virtual Display . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Address Offset Register . . . . . . . . . . . . . . . . . . . . . . . . .
Screen 1 Start Address Registers . . . . . . . . . . . . . . . . . . . . . . . . .
320x240 Single Panel For Split Screen . . . . . . . . . . . . . . . . . . . . . .
Screen 1 Vertical Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Screen 2 Start Address Registers . . . . . . . . . . . . . . . . . . . . . . . . .
Relationship Between The Screen Image and the Image Refreshed by SED1374
Relationship Between The Screen Image and the Image Refreshed by SED1374
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List of Figures
Figure 3-1:
Figure 3-2:
Figure 3-3:
Figure 3-4:
Figure 5-1:
Figure 5-2:
Figure 5-3:
Figure 5-4:
Figure 5-5:
Figure 5-6:
Figure 7-1:
Figure 7-2:
Programming Notes and Examples
Issue Date: 99/04/27
SED1374
X26A-G-002-02
Page 6
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-G-002-02
Programming Notes and Examples
Issue Date: 99/04/27
Epson Research and Development
Vancouver Design Center
Page 7
1 Introduction
This guide describes how to program various features of the SED1374 Embedded Memory
Color LCD controller. The demonstrations include descriptions of how to calculate register
values and explanations of how or why you might want to do certain procedures.
This guide also introduces the Hardware Abstraction Layer (HAL), which is designed to
simplify the programming of the SED1374. Most SED135x, SED137x, and 138x products
support the HAL allowing OEMs to switch chips with relative ease.
Programming Notes and Examples
Issue Date: 99/04/27
SED1374
X26A-G-002-02
Page 8
Epson Research and Development
Vancouver Design Center
2 Initialization
This section describes the register settings and steps needed to initialize the SED1374. The
first step toward initializing the SED1374 is to set the control registers. The SED1374 then
generates the proper control signals for the display. After setting the control registers, the
Look-up Table must be programmed with meaningful values. This section does not cover
setting Look-Up Table values. See Section 4 on page 14 of this manual for Look-up Table
programming details.
The following initialization, presented in table form, provides the sequences and values to
set the registers. The notes column comments the reason for the particular value being
written.
This example writes to all the control registers. In practice, it may be possible to write to
only a subset of the registers. When the SED1374 is first powered up all registers, unless
noted otherwise in the specification, are set to zero. This example programs these registers
to zero to establish a known state.
The initialization enables the SED1374 to control a panel with the following specifications:
• 320x240 color dual passive panel at 75Hz.
• Color Format 2, 8-bit data interface.
• 4 bit-per-pixel (bpp) - 16 colors.
• 25 MHz input clock (CLKI).
Table 2-1: SED1374 Initialization Sequence
Register
Value (hex)
Notes
[01]
0010 0000 (20)
Select an passive, Single, Color panel with a data width of 4-bits
[02]
1010 0000 (B0)
Select 4-bpp color depth and high performance.
[03]
0000 0011 (03)
Select normal power operation
[04]
0010 0111 (27)
Horizontal display size = (Reg[04]+1)*8 = (39+1) * 8 = 320 pixels
[05]
1110 1111 (EF)
[06]
0000 0000 (00)
Vertical display size = Reg[06][05] + 1
= 0000 0000 1110 1111 + 1 = 239 +1 = 240 lines
[07]
0000 0000 (00)
FPLINE start position (not used by STN)
[08]
0001 1110 (1E)
Horizontal non-display period = (Reg[08] + 4) * 8
= (30 + 4) * 8 = 272 pixels
[09]
0000 0000 (00)
FPFRAME start position (not used by STN)
[0A]
0010 0110 (26)
Vertical non-display period = REG[0A] = 38 lines
[0B]
0000 0000 (00)
MOD rate - not required for this panel
[0C]
0000 0000 (00)
[0D]
0000 0000 (00)
[0F]
0000 0000 (00)
[10]
0000 0000 (00)
SED1374
X26A-G-002-02
Screen 1 Start Address - set to 0 for initialization
See Also
Frame Rate Calculation
Frame Rate Calculation
Split Screen on page 30
Screen 2 Start Address - set to 0 for initialization
Programming Notes and Examples
Issue Date: 99/04/27
Epson Research and Development
Vancouver Design Center
Page 9
Table 2-1: SED1374 Initialization Sequence (Continued)
Register
Value (hex)
[12]
0000 0000 (00)
Notes
[13]
1111 1111 (FF)
[14]
0000 0011 (03)
[15]
0000 0000 (00)
[16]
0000 0000 (00)
[17]
0000 0000 (00)
[18]
0000 0000 (00)
[19]
0000 0000 (00)
[1A]
0000 0000 (00)
Set the scratch pad bits to “0”.
[1B]
0000 0000 (00)
We are not setting up SwivelView mode so set this register to “0”.
[1C]
0000 0000 (00)
Line Byte Count is only required for SwivelView mode.
[1E],[1F]
0000 0000 (00)
These registers are reserved and should not be written to.
See Also
Memory Address offset - not virtual setup so set to 0
Set the vertical size to the maximum value.
Split Screen on page 30
SetLUT control registers to 0 for this example.
Look-Up Table (LUT) on
page 14
GPIO control and status registers - set to “0”
2.1 Frame Rate Calculation
The system the SED1374 is being configured for dictates certain physical constraints such
as the width and height of the panel and the video system input clock.
The following are the formulae for determining the frame rate of a panel. The frame rate
for a single passive or TFT panel is calculated as follows:
PCLK
FrameRate = ----------------------------------------------------------------------------------------( HDP + HNDP ) × ( VDP + VNDP )
for a dual passive panel the formula is:
PCLK
FrameRate = -------------------------------------------------------------------------------------------------VDP
2 × ( HDP + HNDP ) ×  ------------ + VNDP
2
where: PCLK
HDP
HNDP
VDP
VNDP
= Pixel clock (in Hz)
= Horizontal Display Period (in pixels)
= Horizontal Non-Display Period (in pixels)
= Vertical Display Period (in lines)
= Vertical Non-Display Period (in lines)
To achieve the desired frame rate the HNDP and VNDP values can be manipulated. The
example below is a generic routine to calculate HNDP and VNDP from a desired frame
rate.
Programming Notes and Examples
Issue Date: 99/04/27
SED1374
X26A-G-002-02
Page 10
Epson Research and Development
Vancouver Design Center
This routine first performs a formula rearrangement so that HNDP or VNDP can be solved
for. Start with VNDP set to a small value. Loop increasing VNDP and solving the equation
for HNDP until satisfactory HNDP and VNDP values are found. If no satisfactory values
are found then divide CLKI and repeat the process. If a satisfactory frame rate still can’t be
reached - return an error.
In C the code looks like the following snip:
for (int loop = 0; loop < 2; loop++)
{
for (VNDP = 2; VNDP < 0x3F; VNDP += 3)
{
// Solve for HNDP
HNDP = (PCLK / (FrameRate * (VDP + VNDP))) - HDP;
if ((HNDP >= 32) && (HNDP <= 280))
{
// Solve for VNDP.
VNDP = (PCLK / (FrameRate * (HDP + HNDP))) - VDP;
// If we have satisfied VNDP then we're done.
if ((VNDP >= 0) && (VNDP <= 0x3F))
goto DoneCalc;
}
}
// Divide ClkI and try again.
// (Reg[02] allows us to dived CLKI by 2)
PCLK /= 2;
}
// If we still can't hit the frame rate - throw an error.
if ((VNDP < 0) || (VNDP > 0x3F) || (HNDP < 32) || (HNDP > 280))
{
sprintf("ERROR: Unable to set the desired frame rate.\n");
exit(1);
}
SED1374
X26A-G-002-02
Programming Notes and Examples
Issue Date: 99/04/27
Epson Research and Development
Vancouver Design Center
Page 11
3 Memory Models
The SED1374 is capable of operating at four different color depths. The data format for
each color depth is packed pixel. SED1374 packed pixel modes can range from one byte
containing eight adjacent pixels (1-bpp) to one byte containing just one pixel (8-bpp).
Packed pixel data memory may be envisioned as a stream of data. Pixels fill this stream
with one pixel packed in adjacent to the next. If a pixel requires four bits then it will be
located in the four most significant bits of a byte. The pixel to the immediate right on the
display will occupy the lower four bits of the same byte. The next two pixels to the
immediate right are located in the following byte, etc.
3.1 Display Buffer Location
The SED1374 contains 40 kilobytes of internal display memory. External support logic
must be employed to determine the starting address for this display memory in CPU address
space. On the SDU1374B0C PC platform evaluation boards the address is usually fixed at
D0000h.
3.1.1 1 Bit-Per-Pixel (2 Colors/Gray Shades)
1-bit pixels support two color/gray shades. In this memory format each byte of display
buffer contains eight adjacent pixels. Setting or resetting any pixel requires reading the
entire byte, masking out appropriate bits and, if necessary, setting bits to "1".
With color panels the two colors are derived by indexing into positions 0 and 1 of the LookUp Table. For monochrome panels the two gray shades are generated by indexing into the
first two elements of the green component of the Look-Up Table (LUT).
If the first two LUT elements are set to black (RGB = 0 0 0) and white (RGB = F F F) then
each "0" bit of display memory will display as a black pixel and each "1" bit will display as
a white pixel. The two LUT entries can be set to any desired colors, for instance red/green
or cyan/yellow.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pixel 0
Pixel 1
Pixel 2
Pixel 3
Pixel 4
Pixel 5
Pixel 6
Pixel 7
Figure 3-1: Pixel Storage for 1 Bpp (2 Colors/Gray Shades) in One Byte of Display Buffer
Programming Notes and Examples
Issue Date: 99/04/27
SED1374
X26A-G-002-02
Page 12
Epson Research and Development
Vancouver Design Center
3.1.2 2 Bit-Per-Pixel (4 Colors/Gray Shades)
2-bit pixels support four color/gray shades. In this memory format each byte of display
buffer contains four adjacent pixels. Setting or resetting any pixel requires reading the
entire byte, masking out the appropriate bits and, if necessary, setting bits to "1".
For color panels the four colors are derived by indexing into positions 0 through 3 of the
Look-Up Table. For monochrome panels the four gray shades are generated by indexing
into the first four elements of the green component of the Look-Up Table.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pixel 0
Bit 1
Pixel 0
Bit 0
Pixel 1
Bit 1
Pixel 1
Bit 0
Pixel 2
Bit 1
Pixel 2
Bit 0
Pixel 3
Bit 1
Pixel 3
Bit 0
Figure 3-2: Pixel Storage for 2 Bpp (4 Colors/Gray Shades) in One Byte of Display Buffer
3.1.3 4 Bit-Per-Pixel (16 Colors/Gray Shades)
Four bit pixels support 16 color/gray shades. In this memory format each byte of display
buffer contains two adjacent pixels. Setting or resetting any pixel requires reading the entire
byte, masking out the upper or lower nibble (4 bits) and setting the appropriate bits to "1".
For color panels the 16 colors are derived by indexing into the first 16 positions of the
Look-Up Table. For monochrome panels the gray shades are generated by indexing into the
first 16 elements of the green component of the Look-Up Table.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pixel 0
Bit 3
Pixel 0
Bit 2
Pixel 0
Bit 1
Pixel 0
Bit 0
Pixel 1
Bit 3
Pixel 1
Bit 2
Pixel 1
Bit 1
Pixel 1
Bit 0
Figure 3-3: Pixel Storage for 4 Bpp (16 Colors/Gray Shades) in One Byte of Display Buffer
SED1374
X26A-G-002-02
Programming Notes and Examples
Issue Date: 99/04/27
Epson Research and Development
Vancouver Design Center
Page 13
3.1.4 Eight Bit-Per-Pixel (256 Colors)
In eight bit-per-pixel mode one byte of display buffer represents one pixel on the display.
At this color depth the read-modify-write cycles, required by the lessor pixel depths, are
eliminated.
Each byte of display memory consists of three pointers into the Look-Up Table. The three
most significant bits form an index into the first eight red values. The next three bits are an
index into the first eight green values. The last two bits form an index into the first four blue
Look-Up Table entries.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Red bit 2
Red bit 1
Red bit 0
Green bit 2
Green bit 1
Green bit 0
Blue bit 1
Blue bit 0
Figure 3-4: Pixel Storage for 8 Bpp (256 Colors) in One Byte of Display Buffer
Programming Notes and Examples
Issue Date: 99/04/27
SED1374
X26A-G-002-02
Page 14
Epson Research and Development
Vancouver Design Center
4 Look-Up Table (LUT)
This section is supplemental to the description of the Look-Up Table (LUT) architecture
found in the SED1374 Hardware Functional Specification. Covered here is a review of the
LUT registers, recommendations for the color and monochrome LUT values, and
additional programming considerations for the LUT.
The SED1374 Look-Up Table consists of sixteen 4-bit wide entries for each of red, green
and blue. The Look-Up Table is controlled by three registers. REG[15h] forms the index
into the table. REG[16h] determines which bank is active during display. REG[17h] is the
register where the Look-Up Table data is read and written.
The currently configured color depth affects how many indices will be used for image
display. In color modes, pixel values are used as indices to an RGB value stored in the
Look-Up Table. In monochrome modes only the green component of the LUT is used.
4.1 Look-Up Table Registers
REG[15h] Look-Up Table Address Register
n/a
n/a
RGB Index
bit 1
Read/Write
RGB Index
bit 0
LUT Address
Bit 3
LUT Address
Bit 2
LUT Address
Bit 1
LUT Address
Bit 0
RGB Index
The RGB Index bits determine how the SED1374 will handle automatic LUT Address
updates.
When the RGB Index is set to auto-increment (00) then three consecutive accesses of
REG[17h] will read/write the red, green, and then the blue elements at the Look-Up Table
index specified by the LUT Address. After three accesses of REG[17h] the LUT Address
is incremented. The next access of REG[17h] will be the red element from the new LookUp Table address.
By altering the RGB Index the sequence can be changed such that three accesses of
REG[17h] will affect just the reds or just the greens or just the blues at three different LUT
addresses.
When configured for monochrome panels the mechanism in which writes are handled is
slightly different. One to three reads are still required to update the LUT Address depending
on the setting of the RGB Index bits. If the RGB Index bits are set to auto-increment then
three writes to REG[17h] are required to bump the LUT Address. Only the last write will
affect the display appearance; it is copied across all three RGB elements. If the RGB Index
is set to access just red, just green or just blue then a single write to REG[17h] is copied to
the red, green and blue elements of the lookup address and the LUT Address is incremented.
SED1374
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Programming Notes and Examples
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Look-Up Table Address
The Look-Up Table (LUT) consists of 16 indexed entries each consisting three 4-bit
elements (red, green, blue). The LUT Address bits select which of the 16 entries is
accessed. Upon setting the LUT Address an internal pointer is set to the red element.
Dependent on the RGB Index setting one to three accesses of the Look-Up Table Data
register cause the LUT Address to automatically increment to the next index.
REG[16h] Look-Up Table Bank Select Register
n/a
Red Bank
Select bit 1
n/a
Red Bank
Select bit 0
Read/Write
Green Bank
Select bit 1
Green Bank
Select bit 0
Blue Bank
Select bit 1
Blue Bank
Select bit0
Look-Up Table Bank Select
The Look-Up Table Bank Select register affects displayed colors.
Depending on the color mode, not all of the sixteen Look-Up Table (LUT) entries are
required. This register determines which entries will be displayed.
At 1-bpp only the lower eight Look-Up Table addresses are used. These are further divided
into four banks of two colors. The bank selects determine which of the four red, green and
blue banks the displayed colors will come from. For instance: Assume the Look-Up Table
Bank Select register was set to 18h (0001 1000 b). Red pixels would come from the 2nd red
lookup bank (red LUT Addresses 2 and 3). Green would be taken from the 3rd green lookup
bank (green LUT addresses 4 and 5). Blue pixels would be taken from the 1st blue lookup
bank (blue LUT addresses 0 and 1).
Programming Notes and Examples
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At 2-bpp, sixteen Look-Up Table addresses are used. The Look-Up Table is a now arranged
into four banks of four colors each. As with 1-bpp, the bank select bits determine the initial
offset into the Look-Up Table. Incrementing a bank select by one bumps the Look-Up
Table offset by four.
Table 4-1: 2 Bpp Banking Scheme
Bank
Red LUT
Addresses
Green LUT
Addresses
Blue LUT
Addresses
0
0
0
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
6
7
7
7
8
8
8
9
9
9
A
A
A
B
B
B
C
C
C
D
D
D
E
E
E
F
F
F
0
1
2
3
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At 4-bpp the pixel data is a direct index to the color to be displayed. At this color depth the
Look-Up Table Bank Select bits have no effect on the display colors. For instance: If the
data was 7Bh then the first pixel color would be from the RGB values of the 8th Look-Up
Table address. The second pixel would be the colored by the RGB value at the 12th (0Bh)
Look-Up Table address.
Table 4-2: 4 Bpp Banking Scheme
Programming Notes and Examples
Issue Date: 99/04/27
Red LUT
Addresses
Green LUT
Addresses
Blue LUT
Addresses
0
0
0
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
6
7
7
7
8
8
8
9
9
9
A
A
A
B
B
B
C
C
C
D
D
D
E
E
E
F
F
F
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At 8-bpp the lookup scheme gets a little more complicated. Each byte of display data
contains 3 bits of red lookup, 3 bits of green lookup and 2 bits of blue lookup. The 16
addresses of the Look-Up Table are divided into 2 eight-element banks for the red and
green components and 4 four-element banks for the blue component.
Table 4-3: 8 Bpp Banking Scheme
Red/Green
Bank
Red LUT
Addresses
Green LUT
Addresses
0
0
1
1
Blue
Bank
Blue LUT
Addresses
0
1
0
2
2
2
3
3
3
4
4
4
5
5
0
5
1
6
6
6
7
7
7
8
8
8
9
9
9
2
A
A
A
B
B
B
C
C
C
D
D
1
D
3
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E
E
E
F
F
F
Programming Notes and Examples
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REG[17h] Look-Up Table Data Register
n/a
n/a
n/a
Read/Write
LUT Data
Bit 3
n/a
LUT Data
Bit 2
LUT Data
Bit 1
LUT Data
Bit 0
LUT Data
This register is where the 4-bit red/green/blue data value is written/read. With each
successive read or write the internal RGB selector is incremented. Depending on the RGB
Index setting, one to three access of this register will result in the Look-Up Table Address
incrementing.
4.2 Look-Up Table (LUT) Organization
Color and monochrome operation is slightly different. Both Look-Up Table schemes are
described here.
• The Look-Up Table treats the value of a pixel as an index into an array of colors or gray
shades. For example, a pixel value of zero would point to the first LUT entry; a pixel
value of 7 would point to the eighth LUT entry.
• The value inside each LUT entry represents the intensity of the given color or gray
shade. This intensity can range in value between 00 and 0Fh.
The following table shows how many elements from each Look-Up Table index are used
at the different color depths.
Table 4-4: Look-Up Table Configurations
Display Mode
4-Bit Wide Look-Up Table
Red
Green
1 Bpp Gray
4 banks of 2
2 Bpp Gray
4 banks of 4
4 Bpp Gray
1 bank of 16
1 Bpp Color
4 banks of 2
4 banks of 2
Blue
4 banks of 2
2 Bpp Color
4 banks of 4
4 banks of 4
4 banks of 4
4 Bpp Color
1 bank of 16
1 bank of 16
1 bank of 16
8 Bpp Color
2 banks of 8
2 banks of 8
4 banks of 4
Indicates the Look-Up Table is not used for that display mode
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Color Modes
1 Bpp Color
When the SED1374 is configured for 1 bit-per-pixel color mode, only the first two colors
from the active bank are displayed. The two entries can be set to any color but are typically
set to black and white.
Each byte in the display buffer contains 8 bits, each bit represents an individual pixel. A bit
value of "0" results in the Look-Up Table 0 value being displayed. A bit set to "1" results
in the Look-Up Table index 1 value displayed.
The following table shows the recommended values for 1 bpp on a color panel.
Table 4-5: Recommended LUT Values for 1 Bpp Color Mode
Index
Red
Green
Blue
00
00
00
00
01
0F
0F
0F
02
00
00
00
...
00
00
00
0F
00
00
00
Normally unused entries
2 Bpp Color
When the SED1374 is configured for 2 bit-per-pixel color mode, only the first four colors
from the active bank are displayed. The four entries can be set to any color.
Each byte in the display buffer contains 4 adjacent pixels. Each pair of bits in the byte are
used as an index into the LUT. The following table shows example values for 2 bpp color
mode.
Table 4-6: LUT Values for 2 Bpp Color Mode
Index
Red
Green
Blue
00
00
00
0F
01
0F
00
00
02
00
0F
00
03
0F
0F
0F
04
00
00
00
...
00
00
00
0F
00
00
00
Normally unused entries
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4 Bpp Color
When the SED1374 is configured for 4 bit-per-pixel operation all sixteen Look-Up Table
entries are used. Each byte in the display buffer contains two adjacent pixels. The upper and
lower nibbles of the byte are used as indices into the LUT.
The following table shows LUT values that simulate those of a VGA operating in 16 color
mode.
Table 4-7: Suggested LUT Values to Simulate VGA Default 16 Color Palette
Programming Notes and Examples
Issue Date: 99/04/27
Index
Red
Green
Blue
00
00
00
00
01
00
00
0A
02
00
0A
00
03
00
0A
0A
04
0A
00
00
05
0A
00
0A
06
0A
0A
00
07
0A
0A
0A
08
00
00
00
09
00
00
0F
0A
00
0F
00
0B
00
0F
0F
0C
0F
00
00
0D
0F
00
0F
0E
0F
0F
00
0F
0F
0F
0F
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8 Bpp Color
When the SED1374 is configured for 8 bit-per-pixel color mode, 8 colors from red and
green and 4 colors from the blue active banks are displayed. The eight red, eight green and
four blue entries can be set to any color.
The SED1374 LUT has four bits (16 levels) of intensity control per primary color while a
standard VGA RAMDAC has six bits (64 levels). This four to one difference has to be
considered when attempting to match colors between a VGA RAMDAC and the SED1374
LUT. (i.e. VGA levels 0 - 3 map to LUT level 0, VGA levels 4 - 7 map to LUT level 1...
etc.).
The following table shows LUT values that approximate the default 256 color VGA palette.
Table 4-8: Suggested LUT Values to Simulate VGA Default 256 Color Palette
Index
Red
Green
Blue
00
00
00
00
01
02
02
05
02
04
04
0A
03
06
06
0F
04
09
09
00
05
0B
0B
00
06
0D
0D
00
07
0F
0F
00
08
00
00
00
...
00
00
00
0F
00
00
00
Normally unused entries
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Gray Shade Modes
1 Bpp Gray Shade (Black-and-White)
In 1 bpp gray shade mode only the first two entries of the green LUT are used. All other
LUT entries are unused.
Table 4-9: Recommended LUT Values for 1 Bpp Gray Shade
Address
Red
Green
Blue
00
00
00
00
01
0F
0F
0F
02
00
00
00
...
00
00
00
0F
00
00
00
Normally unused entries
2 Bpp Gray Shade
In 2 bpp gray shade mode the first four green elements are used to provide values to the
panel. The remaining indices are unused.
Table 4-10: Suggested Values for 2 Bpp Gray Shade
Index
Red
Green
Blue
0
00
00
00
1
05
05
05
2
0A
0A
0A
3
0F
0F
0F
4
00
00
00
...
00
00
00
F
00
00
00
Normally unused entries
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4 Bpp Gray Shade
The 4 bpp gray shade mode uses all 16 LUT elements.
Table 4-11: Suggested LUT Values for 4 Bpp Gray Shade
Index
Red
Green
Blue
00
00
00
00
01
01
01
01
02
02
02
02
03
03
03
03
04
04
04
04
05
05
05
05
06
06
06
06
07
07
07
07
08
08
08
08
09
09
09
09
0A
0A
0A
0A
0B
0B
0B
0B
0C
0C
0C
0C
0D
0D
0D
0D
0E
0E
0E
0E
0F
0F
0F
0F
Normally unused entries
SED1374
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Programming Notes and Examples
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5 Advanced Techniques
This section contains information on the following:
• virtual display
• panning and scrolling
• split screen display
5.1 Virtual Display
Virtual display refers to the situation where the image to be viewed is larger than the
physical display. The difference can be in the horizontal, vertical or both dimensions. To
view the image, the display is used as a window into the display buffer. At any given time
only a portion of the image is visible. Panning and scrolling are used to view the full image.
The Memory Address Offset register determines the number of horizontal pixels in the
virtual image. The offset register can be used to specify from 0 to 255 additional words for
each scan line. At 1 bpp, 255 words span an additional 4,080 pixels. At 8 bpp, 255 words
span an additional 510 pixels.
The maximum vertical size of the virtual image is the result of dividing 40960 bytes of
display memory by the number of bytes on each line (i.e. at 1 bpp with a 320x240 panel set
for a virtual width of 640x480 there is enough memory for 512 lines).
Figure 5-1: “Viewport Inside a Virtual Display,” depicts a typical use of a virtual display.
The display panel is 320x240 pixels, an image of 640x480 pixels can be viewed by
navigating a 320x240 pixel viewport around the image using panning and scrolling.
320x240
Viewport
640x480
“Virtual” Display
Figure 5-1: Viewport Inside a Virtual Display
Programming Notes and Examples
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5.1.1 Registers
REG[12h] Memory Address Offset Register
Memory
Address
Offset
Bit 7
Memory
Address
Offset
Bit 6
Memory
Address
Offset
Bit 5
Memory
Address
Offset
Bit 4
Memory
Address
Offset
Bit 3
Memory
Address
Offset
Bit 2
Memory
Address
Offset
Bit 1
Memory
Address
Offset
Bit 0
Figure 5-2: Memory Address Offset Register
REG[12h] forms an 8-bit value called the Memory Address Offset. This offset is the
number of additional bytes on each line of the display. If the offset is set to zero there is no
virtual width.
Note
This value does not represent the number of words to be shown on the display. The display width is set in the Horizontal Display Width register.
5.1.2 Examples
Example 1: In this example we go through the calculations to display a 640x480 image on a 320x240 panel at 2 bpp.
Step 1: Calculate the number of pixels per word for this color depth.
At 2 bpp each byte is comprised of 4 pixels, therefore each word contains 8 pixels.
pixels_per_word = 16 / bpp = 16 / 2 = 8
Step 2: Calculate the Memory Address Offset register value
We require a total of 640 pixels. The horizontal display register will account for 320 pixels,
this leaves 320 pixels for the Memory Address Offset register to account for.
offset = pixels / pixels_per_word = 320 / 8 = 40 = 28h
The Memory Address Offset register, REG[12h], will have to be set to 28h to satisfy the
above condition.
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Example 2: From the above, what is the maximum number of lines our image can
contain?
Step 1: Calculate the number of bytes on each line.
bytes_per_line = pixels_per_line / pixels_per_byte = 640 / 4 = 160
Each line of the display requires 160 bytes.
Step 2: Calculate the number of lines the SED1374 is capable of.
total_lines = memory / bytes_per_line = 40960 / 160 = 256
The the maximum number of lines which can be accommodated by our image can contain
is 256. This example will not “fit” in available display memory. We must reduce either the
color depth or the virtual image size.
5.2 Panning and Scrolling
Panning and scrolling describe the actions of appearing to move the image in a virtual
display so that all the image can be viewed. After correctly setting up a virtual display (see
above) and loading an image into display memory, panning and scrolling allow viewing the
entire image a portion at a time.
Panning describes the horizontal (side to side) motion of the viewport. When panning to the
right the image in the viewport appears to slide to the left. When panning to the left the
image to appears to slide to the right. Scrolling describes the vertical (up and down) motion
of the viewport. Scrolling down causes the image to appear to slide up and scrolling up
causes the image to appear to slide down.
Both panning and scrolling are performed by modifying the start address register. Start
address refers to the word offset in the display buffer where the image will start being
displayed from. The start address registers in the SED1374 are an offset to the first word to
be displayed in the top left corner of every frame.
Keep in mind that the start address is a word offset. Changing the start address by one
means a change of one words worth of pixels. The number of pixels in word varies
according to the color depth. At 1 bit-per-pixel a word contains sixteen pixels. At 2 bit-perpixel there are eight pixels, at 4 bit-per-pixel there are four pixels and at 8 bit-per-pixel there
are two pixels. The number of pixels in each word represent the finest panning step the
SED1374 is capable of. (i.e. at 4 bit-per-pixel the display will move sideways by four pixels
for each change to the start address registers)
When SwivelView mode (see SwivelView™ on page 36) is enabled the start address
registers become offsets to bytes. In this mode the step rate for the start address registers if
halved making for smoother panning.
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5.2.1 Registers
REG[0Ch] Screen 1 Display Start Address 0 (LSB)
Start Addr
Bit 7
Start Addr
Bit 6
Start Addr
Bit 5
Start Addr
Bit 4
Start Addr
Bit 3
Start Addr
Bit 2
Start Addr
Bit 1
Start Addr
Bit 0
Start Addr
Bit 11
Start Addr
Bit 10
Start Addr
Bit 9
Start Addr
Bit 8
REG[0Dh] Screen 1 Display Start Address 1 (MSB)
reserved
Start Addr
Bit 14
Start Addr
Bit 13
Start Addr
Bit 12
Figure 5-3: Screen 1 Start Address Registers
In landscape mode these two registers form the offset to the word in display memory to be
displayed in the upper left corner of the screen. Screen 1 is always the top of a display
frame, starting in the upper left corner and descending downward. Changing these registers
by one will shift the display 2 to 16 pixels, depending on the current color depth.
In SwivelView mode these registers form the offset to the byte in display memory from
where screen 1 will start displaying. Changing these registers in SwivelView mode will
result in a shift of 1 to 8 pixels depending on the color depth.
Refer to Table 5-1: “Number of Pixels Panned Using Start Address” to see the minimum
number of pixels affected by a change of one to these registers
Table 5-1: Number of Pixels Panned Using Start Address
Color Depth (bpp)
Pixels per Word
Landscape Mode
Number of Pixels Panned
SwivelView Mode
Number of Pixels Panned
1
16
16
8
2
8
8
4
4
4
4
2
8
2
2
1
5.2.2 Examples
For the following examples assume the display system has been set up to view a 320x240
4 bpp image in a 256x64 viewport. Refer to Section 2, “Initialization” on page 8 and
Section 5.1, “Virtual Display” on page 25 for assistance with these settings. The examples
are shown in a C-like syntax.
Example 3: Panning (Right and Left)
To pan to the right increase the start address value by one. To pan to the left decrease the
start address value. Keep in mind that, with the exception of 8 bit-per-pixel SwivelView
mode, the display will jump by more than one pixel as a result of changing the start address
registers.
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Panning to the right.
StartWord = GetStartAddress();
StartWord ++;
SetStartAddress(StartWord);
Panning to the left.
StartWord = GetStartAddress();
StartWord --;
if (StartWord < 0)
StartWord = 0;
SetStartAddress(StartWord);
Example 4: Scrolling (Up and Down)
To scroll down, increase the value in the Screen 1 Display Start Address Register by the
number of words in one virtual scan line. To scroll up, decrease the value in the Screen 1
Display Start Address Register by the number of words in one virtual scan line.
Step 1: Determine the number of words in one virtual scanline.
bytes_per_line = pixels_per_line / pixels_per_byte = 320 / 2 = 160
words_per_line = bytes_per_line / 2 = 160 /2 = 80
Step 2: Scroll up or down
To scroll up.
StartWord = GetStartAddress();
StartWord -= words_per_line;
if (StartWord < 0)
StartWord = 0;
SetStartAddress(StartWord);
To scroll down.
StartWord = GetStartAddress();
StartWord += words_per_line;
SetStartAddress(StartWord);
long GetStartAddress (void)
{
return (REG[0D] * 256 +REG[0C];
}
void SetStartAddress (long StartWord)
{
REG[0C] = StartWord & 0xFF;
REG[0D] = StartWord / 256;
}
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5.3 Split Screen
Occasionally the need arises to display two different but related images. For example, a
game where the main play area requires rapid updates and game status displayed at the
bottom of the screen. The status area updates far less often than the main play area.
The Split Screen feature of the SED1374 allows a programmer to setup a display for such
an application. The figure below illustrates setting a 320x240 panel to have Image 1
displaying from scan line 0 to scan line 199 and image 2 displaying from scan line 200 to
scan line 239. Although this example picks specific values, the split between image 1 and
image 2 can occur anywhere on the display.
Scan Line 0
...
Scan Line 199
Scan Line 200
...
Scan Line 239
Image 1
Image 2
Screen 1 Vertical Size Registers = 199 lines
Figure 5-4: 320x240 Single Panel For Split Screen
In split screen operation “Image 1" is taken from the display memory location pointed to
by the Screen 1 Start Address registers and always is located at the top of the screen. “Image
2" is taken from the display memory location pointed to by the Screen 2 Start Address
registers and begins after Screen 1 Vertical Size lines.
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5.3.1 Registers
The other registers required for split screen operations, REG[0Ch] through REG[0Dh]
(Screen 1 Start Word Address) and REG[0Fh] through REG[10h] (Screen 2 Start Word
Address) are described in Section 5.2.1 on page 28.
REG[13] Screen 1 Vertical Size (LSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
n/a
n/a
n/a
Bit 9
Bit 8
REG[14] Screen 1 Vertical Size (MSB)
n/a
n/a
n/a
Figure 5-5: Screen 1 Vertical Size
These two registers form a ten bit value which determines the size of screen 1. When the
vertical size is equal to or greater than the physical number of lines being displayed there
is no visible effect on the display. When the vertical size value is less than the number of
physically displayed lines, display operation works like this:
1. From the end of vertical non-display (beginning of a frame) to the number of lines indicated by vertical size the display data will come from the memory pointed to by the
Screen 1 Display Start Address.
2. After vertical size lines have been displayed the system will begin displaying data
from Screen 2 Display Start Address memory.
Screen 1 memory is always displayed at the top of the screen followed by screen 2 memory.
The start address for the screen 2 image may be lower in memory than that of screen 1 (i.e.
screen 2 could be coming from offset 0 in the display buffer while screen 1 was coming
from an offset located several thousand bytes into the display buffer). While not particularly useful, it is even possible to set screen 1 and screen 2 to the same address.
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REG[0Fh] Screen 2 Display Start Address 0 (LSB)
Start Addr Bit
7
Start Addr Bit
6
Start Addr Bit
5
Start Addr Bit
4
Start Addr Bit
3
Start Addr Bit
2
Start Addr Bit
1
Start Addr Bit
0
Start Addr Bit
11
Start Addr Bit
10
Start Addr Bit
9
Start Addr Bit
8
REG[10h] Screen 2 Display Start Address 0 (LSB)
reserved
Start Addr Bit
14
Start Addr Bit
13
Start Addr Bit
12
Figure 5-6: Screen 2 Start Address Registers
In landscape mode these two registers form the offset to the word in display memory to be
displayed immediately after the screen 1 area of display memory. Changing these registers
by one will shift the display 2 to 16 pixels, depending on the current color depth.
Split screen operation is not supported in SwivelView mode, leaving this register un-used.
Refer to Table 5-1:, “Number of Pixels Panned Using Start Address,” on page 28 to see the
minimum number of pixels affected by a change of one to these registers
5.3.2 Examples
Example 5: Display 200 scanlines of image 1 and 40 scanlines of image 2. Image 2 is
located first (offset 0) in the display buffer followed immediately by image 1. Assume a 320x240 display and a color depth of 4 bpp.
1. Calculate the Screen 1Vertical Size register values.
vertical_size = 200 = C8h
Write the Vertical Size LSB, REG[13h], with C8h and Vertical Size MSB, REG[14h],
with a 00h.
2. Calculate the Screen 1 Start Word Address register values.
Screen 2 is located first in display memory, therefore we must calculate the number of
bytes taken up by the screen 2 data.
bytes_per_line = pixels_per_line / pixels_per_byte = 320 / 2 = 160
total bytes = bytes_per_line x lines = 160 x 40 = 6400.
Screen 2 requires 6400 bytes (0 to 6399) therefore the start address offset for screen 1
must be 6400 bytes. (6400 bytes = 3200 words = C80h words)
Set the Screen 1 Start Word Address MSB, REG[0Dh], to 0Ch and the Screen 1 Start
Word Address LSB, REG[0Ch], to 80h.
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3. Calculate the Screen 2 Start Word Address register values.
Screen 2 display data is coming from the very beginning of the display buffer. All there is
to do here is ensure that both the LSB and MSB of the Screen 2 Start Word Address
registers are set to zero.
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6 LCD Power Sequencing and Power Save Modes
6.1 LCD Power Sequencing
LCD Power Sequencing allows the LCD power supply to discharge prior to shutting down
the LCD logic signals. Power sequencing is required to prevent long term damage to the
panel and to avoid unsightly “lines” on power-down and power-up.
The SED1374 performs automatic power sequencing when the LCD is enabled or disabled
through the Power Save bits in REG[03h] or in response to a hardware power save request.
For most applications the internal power sequencing is the appropriate choice.
Proper LCD power sequencing dictates there must be a time delay between the LCD power
being disabled and the LCD signals being shut down. During power-up the LCD signals
must be active prior to or when power is applied to the LCD. The time intervals vary
depending on the power supply design.
One frame after a power save mode has been enabled the SED1374 disables LCD power.
One hundred and twenty seven frames later the LCD logic signals are disabled. There may
be situations where the internal time delay is insufficient to discharge the LCD power
supply before the LCD signals are shut down. This section details the sequences to
manually power-up and power-down the LCD interface.
During the power up sequence the LCD power should not be applied before the LCD logic
signals. Usually the power and logic can begin at the same time. There may be times when
the LCD logic signals must begin before LCD power is applied.
6.2 Registers
REG[03h] Mode Register 2
LCDPWR
Override
Hardware
Power Save
Enable
Software
Power Save
bit 1
Software
Power Save
bit 0
The LCD Power (LCDPWR) Override bit forces LCD power to inactive one frame after
being toggled. The LCD logic signals to the panel are still active and are controlled by
enabling or disabling a power save mode. After enabling a power save mode there are still
128 frames before LCD logic signals are disabled.
The Hardware Power Save Enable bit must be set in order for a hardware power save
request (on GPIO0) to have any affect. Without enabling this bit toggling GPIO0 will have
no power save effect.
The Software Power Save bits are used to set the software power save mode. The two valid
states are "00" for power save and "11" for normal operation.
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6.3 LCD Enable/Disable
The descriptions below cover manually powering the LCD panel up and down. Use them
only if the power supply connected to the panel requires more than 127 frames to discharge
on power-down or if the panel requires starting the LCD logic well in advance of enabling
LCD power.
Power On/Enable Sequence
The following is the recommended sequence for manually powering-up an LCD panel.
These steps would be used if LCD power had to be applied later than LCD logic.
1. Set REG[03h] bit 3, LCDPWR Override, to "1" (ensures that LCD power is disabled).
2. Enable LCD logic. This is done by either setting GPIO0 to 0 for hardware power save
mode and/or by setting REG[03h] bits 1-0, software power save, to "11".
3. Count "x" Vertical Non-Display Periods.
"x" corresponds the length of time LCD logic must be enabled before LCD power-up,
converted to the equivalent vertical non-display periods. For example, at 72 HZ counting 36 non-display periods results in a one half second delay.
4. Set REG[03h] bit 3 to "0" (enable LCD Power).
Power Off/Disable Sequence
The following is the recommended sequence for manually powering-down an LCD panel.
These steps would be used if power supply timing requirements were larger than the
timings built into the SED1374 power disable sequence.
1. Set REG[03h] bit 3, LCDPWR Override, to "1" (disables LCD Power).
2. Count "x" Vertical Non-Display Periods.
"x" corresponds to the power supply discharge time converted to the equivalent vertical non-display periods.
3. Disable the LCD logic by setting the software power save in REG[03h] or setting
hardware power save via GPIO0.
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7 SwivelView™
7.1 Introduction To SwivelView
Many of todays applications use the LCD panel in a portrait orientation. In this case it
becomes necessary to “rotate” the displayed image. This rotation can be done by software
at the expense of performance or, as with the SED1374, it can be done by hardware with
no performance penalty.
There are two hardware rotated modes: Default SwivelView Mode and Alternate
SwivelView Mode.
7.2 Default SwivelView Mode
Default SwivelView Mode requires the portrait image width be a power of two, e.g. a 240line panel requires a minimum virtual image width of 256. This mode should be used
whenever the required virtual image can be contained within the integrated display buffer
(i.e. virtual image size ≤ 40k bytes), as it consumes less power than the Alternate
SwivelView mode.
For example, the panel size is 320x240 and the display mode is 4 bit-per-pixel. The virtual
image size is 320x256 which can be contained within the 40k Byte display buffer.
Default SwivelView Mode also requires memory clock (MCLK) ≥ pixel clock (PCLK).
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The following figures show how the programmer sees a 240x320 image and how the image
is displayed. The application image is written to the SED1374 in the following sense:
A–B–C–D. The display is refreshed by the SED1374 in the following sense: B-D-A-C.
physical
memory
start
address
256
E
240
256
D
C
SwivelView
window
display
start
address
A
320
SwivelView
window
E
B
B
A
D
C
320
240
image seen by programmer
= image in display buffer
image refreshed by SED1374
Figure 7-1: Relationship Between The Screen Image and the Image Refreshed by SED1374
7.3 Alternate SwivelView Mode
Alternate SwivelView Mode may be used when the virtual image size of Default
SwivelView Mode cannot be contained in the 40k Byte integrated frame buffer. For
example, when the panel size is 240x160 and the display mode is 8 bit-per-pixel the
minimum virtual image size for Default SwivelView Mode would be 240x256 which
requires 60K bytes. Alternate SwivelView Mode requires a panel size of only 240x160
which needs only 38,400 bytes.
Alternate SwivelView Mode requires the memory clock (MCLK) to be at least twice the
frequency of the pixel clock (PCLK), i.e. MCLK ≥ 2 x PCLK.
Because of this, the power consumption in Alternate SwivelView Mode is higher than in
Default SwivelView Mode.
The following figure shows how the programmer sees a 240x160 image and how the image
is being displayed. The application image is written to the SED1374 in the following sense:
A–B–C–D. The display is refreshed by the SED1374 in the following sense: B-D-A-C.
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160
C
display
start
address
A
240
SwivelView
window
D
B
SwivelView
window
A
B
physical
memory
start
address
D
C
240
160
image seen by programmer
= image in display buffer
image refreshed by SED1374
Figure 7-2: Relationship Between The Screen Image and the Image Refreshed by SED1374
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7.4 Registers
This section describes the registers used to set SwivelView mode operation.
REG[0Ch] Screen 1 Start Word Address LSB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 11
bit 10
bit 9
bit 8
REG[0Dh] Screen 1 Start Word Address MSB
reserved
bit 14
bit 13
bit 12
The start address registers must be set for SwivelView mode. In SwivelView mode the
offset contained in the start address points to a byte.
REG[1Ch] Line Byte Count Register
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
The line byte count register informs the SED1374 of the stride, in bytes, between two
consecutive lines of display in SwivelView mode. The Line Byte Count register only
affects SwivelView mode operation. The contents of this register are ignored when the
SED1374 is in landscape display mode.
REG[1Bh] SwivelView Mode Register
SwivelView
Mode Enable
SwivelView
Mode Select
n/a
n/a
n/a
reserved
SwivelView
Mode Pixel
Clock Select
Bit 1
SwivelView
Mode Pixel
Clock Select
Bit 0
The SwivelView mode register contains several items for SwivelView mode support.
The first is the SwivelView Mode Enable bit. When this bit is “0” the SED1374 is in
landscape mode and the remainder of the settings in this register as well as the Line Byte
Count in REG[1Ch] are ignored. When this bit is a “1” SwivelView mode is enabled.
There are two SwivelView mode display schemes available. The SwivelView mode select
bit selects between the “Default Mode” and the "Alternate Mode”. The default mode offers
the lowest power consumption with some display mode limitations. The alternate mode
uses more power but offers greater display flexibility.
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In return for using less power the default SwivelView imposes the restriction that the
SwivelView display width must be a power of two (e.g. 64, 128, 256, 512). The physical
display does not need to be a power of two wide. The difference can be treated as a virtual
width. In addition, scrolling in default SwivelView mode is restricted to two lines.
Alternate SwivelView mode requires more power as the internal clocks are run faster. In
return for a higher power consumption the "power of two" width-restriction is removed.
Also, the display can be scrolled one line at a time. One benefit to removing the power of
two width restriction is that panels which might not have been able to be used in
SwivelView mode due to a lack of memory may now be used.
Clocking for the SED1374 works as follows:
An external clock source supplies CLKI, the input clock. CLKI is routed through the Input
Clock Divide from Mode Register 1 (REG[02h] bit 4) and is either divided by two or passed
on. This signal is now the Operating Clock (CLK) from which PCLK and MCLK are
derived. In SwivelView mode the CLK signal may be divided down by 0, 2, 4, or 8 before
PCLK and MCLK are derived.
SwivelView mode offers additional clocking control over landscape mode. One reason for
the additional support is to maintain a register set that was backward compatible with
previous Epson LCD controllers.
When setting SwivelView mode, it is possible that the horizontal and vertical non-display
time must be recalculated as a result of PCLK changing in response to the SwivelView
mode selected or the clock selection method.
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7.5 Limitations
The only limitation to using SwivelView mode on the SED1374 is that split screen
operation is not supported.
A comparison of the two SwivelView modes is as follows:
Table 7-1: Default and Alternate SwivelView Mode Comparison
Item
Default SwivelView Mode
Alternate SwivelView Mode
The width of the rotated image must be a
power of 2. In most cases, a virtual image is
required where the right-hand side of the
virtual image is unused and memory is
wasted. For example, a 160x240x8bpp
Memory Requirements
Does not require a virtual image.
image would normally require only 38,400
bytes - possible within the 40K byte
address space, but the virtual image is
256x240x8bpp which needs 61,440 bytes not possible.
Clock Requirements
CLK need only be as fast as the required
PCLK.
MCLK, and hence CLK, need to be 2x PCLK.
For example, if the panel requires a 3MHz
PCLK, then CLK must be 6MHz. Note that
25MHz is the maximum CLK, so PCLK cannot
be higher than 12.5MHz in this mode.
Power Consumption
Lowest power consumption.
Typically 20% higher than Default Mode.
Panning
Vertical panning in 2-line increments.
Vertical panning in 1-line increments.
Performance
Nominal performance.
Slightly higher performance than Default Mode.
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7.6 Examples
Example 6: Enable default SwivelView mode for a 320x240 panel at 4 bpp.
Before switching to SwivelView mode from landscape mode, display memory should be
cleared to make the user perceived transition smoother. Images in display memory are not
rotated automatically by hardware and the garbled image would be visible for a short period
of time if video memory is not cleared.
In this example we will bypass having to recalculate the horizontal and vertical non-display
times (frame rate) by selecting the default SwivelView mode scheme.
1. Calculate and set the Screen 1 Start Word Address register.
OffsetBytes = (Width x BitsPerPixel / 8) - 1 = (256 x 4 / 8) -1 = 127 = 007Fh
(“Width” is the width of the SwivelView mode display - in this case the next power of
two greater than 240 pixels or 256.)
Set Screen1 Display Start Word Address LSB (REG [0Ch]) to 7Fh and Screen1 Display Start Word Address MSB (REG[0Dh]) to 00h.
2. Calculate the Line Byte Count
The Line Byte Count also must be based on the power of two width.
LineByteCount = Width x BitsPerPixel / 8 = 256 x 4 / 8 = 128 = 80h.
Set the Line Byte Count (REG[1C]) to 80h.
3. Enable SwivelView mode.
This example uses the default SwivelView mode scheme. If we do not change the
SwivelView Mode Pixel Clock Select bits then we will not have to recalculate the nondisplay timings to correct the frame rate.
Write 80h to the SwivelView Mode Register (REG[1Bh]).
The display is now configured for SwivelView mode use. Offset zero into display memory
will corresponds to the upper left corner of the display. The only thing to keep in mind is
that the count from the first pixel of one line to the first pixel of the next line (refered to as
the "stride") is 128 bytes.
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Example 7: Enable alternate SwivelView mode for a 320x240 panel at 4 bpp.
Note
As we have to perform a frame rate calculation for this mode we need to know the following panel characteristics: 320x240 8-bit color to be run at 80 Hz with a 16 MHz input clock.
As in the previous example, before switching to SwivelView mode, display memory should
be cleared. Images in display memory are not rotated automatically by hardware and the
garbled image would be visible for a short period of time if video memory is not cleared.
1. Calculate and set the Screen 1 Start Word Address register.
OffsetBytes = (Width x BitsPerPixel / 8) - 1 = (240 x 4 / 8) - 1 = 119 = 0077h
Set Screen1 Display Start Word Address LSB (REG [0Ch]) to 77h and Screen1 Display Start Word Address MSB (REG[0Dh]) to 00h.
2. Calculate the Line Byte Count.
LineByteCount = Width x BitsPerPixel / 8 = 240 x 4 / 8 = 120 = 78h.
Set the Line Byte Count (REG[1C]) to 78h.
3. Enable SwivelView mode.
This example uses the alternate SwivelView mode scheme. We will not change the
Pixel Clock Select settings.
Write C0h to the SwivelView Mode register (REG[1Bh])
4. Recalculate the frame rate dependents.
This example assumes the alternate SwivelView mode scheme. In this scheme, without
touching the Pixel Clock Select bits the PCLK value will be equal to CLK/2.
Note
These examples don’t use the Pixel Clock Select bits. The ability to divide the PCLK
value down further than the default values was added to the SED1374 to support
SwivelView mode on very small panels.
The Pixel Clock value has changed so we must calculate horizontal and vertical non-display
times to reach the desired frame rate. Rather than perform the frame rate calculations here
I will refer the reader to the frame rate calculations in Frame Rate Calculation on page 9
and simply "arrive" at the following:
Horizontal Non-Display Period = 88h
Vertical Non-Display Period = 03h
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Plugging the values into the frame rate calculations yields:
PCLK
FrameRate = ----------------------------------------------------------------------------------------( HDP + HNDP ) × ( VDP + VNDP )
16, 000, 000
-----------------------------2
FrameRate = ------------------------------------------------------- = 80.69
( 320 + 88 ) × ( 240 + 3 )
For this example the Horizontal Non-Display register [REG[08h]) needs to be set to 07h
and the Vertical Non-Display register (REG[0Ah]) needs to be set to 03h.
The 16,000,000/2 in the formula above represents the input clock being divided by two
when this alternate SwivelView mode is selected. With the values given for this example
we must ensure the Input Clock Divide bit (REG[02h] b4) is reset (with the given values it
was likely set as a result of the frame rate calculations for landscape display mode).
No other registers need to be altered.
The display is now configured for SwivelView mode use. Offset zero of display memory
corresponds to the upper left corner of the display. Display memory is accessed exactly as
it was for landscape mode.
As this is the alternate SwivelView mode the power of two stride issue encountered with
the default SwivelView mode is no longer an issue. The stride is the same as the
SwivelView mode width. In this case 120 bytes.
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Example 8: Pan the above SwivelView mode image to the right by 4 pixels then
scroll it up by 6 pixels.
To pan by four pixels the start address needs to be advanced.
1. Calculate the amount to change start address by.
Bytes = Pixels x BitsPerPixel / 8 = 4 x 4 / 8 = 2 bytes
2. Increment the start address registers by the just calculated value.
In this case the value writen to the start address register will be 81h (7Fh + 2 = 81h)
To scroll by 4 lines we have to change the start address by the offset of four lines of display.
1. Calculate the amount to change start address by.
BytesPerLine = LineByteCount = 128
Bytes = Lines x BytesPerLine = 4 x 128 = 512 = 200h
2. Increment the start address registers by the just calculated value
In this case 281h (81h + 200h) will be written to the Screen 1 Start Word Address register pair.
Set Screen1 Display Start Word Address LSB (REG[0Ch]) to 81h and Screen1 Display
Start Word Address MSB (REG[0Dh]) to 02h.
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8 Identifying the SED1374
As there are several similar products in the 135X and 137X LCD controller families, which
can for the most part share the same code base. It may be important for a program to identify
between products at run time.
Identification of the SED1374 can be performed any time after the system has been
powered up by reading REG[00h], the Revision Code register. The six most significant bits
form the product identification code and the two least significant bits form the product
revision.
From reset (power on) the steps to identifying the SED1374 are as follows:
1. Read REG[00h]. Mask off the lower two bits, the revision code, to obtain the product
code.
2. The product code for the SED1374 is 018h.
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9 Hardware Abstraction Layer (HAL)
9.1 Introduction
The HAL is a processor independent programming library provided by Epson with support
for several different computing platforms. The HAL was developed to aid implementation
of internal test programs and provides an easy, consistent method of programming
SED135x, SED137x, and SED138x products on different processor platforms.
The HAL keeps sample code simpler, although end programmers may find the HAL
functions to be limited in their scope, and may wish to ignore the HAL.
9.2 API for 1374HAL
The following is a description of the HAL library. Updates and revisions to the HAL may
include new functions not included in the following documentation.
The original design philosophy of the HAL was that function return values would be status
of the call. Most functions simple return ERR_OK. If a value had to be returned then a
pointer of the appropriate type was passed to the function.
9.2.1 Initialization
The following section describes the HAL functions dealing with SED1374 initialization.
Typically a programmer has only to concern themselves with calls to seRegisterDevice()
and seSetInit().
int seRegisterDevice(const LPHAL_STRUC lpHalInfo, int * pDevID)
Description:
Registers the SED1374 device parameters with the HAL library. The device parameters have been configured with address range, register values, desired frame rate,
etc., and have been saved in the HAL_STRUCT structure pointed to by lpHalInfo.
Parameters:
lpHalInfo
pDevice
- pointer to HAL_STRUCT information structure
- pointer to the integer to receive the device ID
Return Value: ERR_OK - operation completed with no problems
ERR_UNKNOWN_DEVICE - the HAL was unable to find an SED1374.
Note
No SED1374 registers are changed by calling seRegisterDevice().
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seSetInit(int DevID)
Description:
Configures the SED1374 for operation. This function sets all the SED1374 control
registers to their default values.
Initialization of the SED1374 was made a stand-alone step to accommodate those
programs (e.g. 1374PLAY.EXE) which needed the ability to start and examine the
system before changing register contents.
Parameters:
DevID
Return Value: ERR_OK
- registered device ID
- operation completed with no problems
Note
After this call the Look-Up Table will be set to a default state appropriate to the display
type.
int seInitHal(void)
Description:
This function initializes variables used by the HAL library. Call this function once
when the application starts.
Normally, programmers will never need to call seInitHal(). On PC platforms, seRegisterDevice() automatically calls seInitHal(). Consecutive calls to seRegisterDevice() will not call seInitHal() again. On non-PC platforms the start-up code,
supplied by Seiko, will call seInitHal(). If support code for a new CPU platform is
written the programmer must ensure that seInitHAL() is called prior to calling other
HAL functions.
Parameters:
None
Return Value: ERR_OK
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9.2.2 Miscellaneous HAL Support
Functions in this group do not fit into any specific category of support. They provide a
miscellaneous range of support for working with the SED1374
int seGetId(int DevID, int * pId)
Description:
Reads the SED1374 revision code register to determine the chip product and
revisions. The interpreted value is returned in pID.
Parameters:
DevID
pId
- registered device ID
- pointer to an integer which will receive the controller ID.
SED1374 values returned in pID are:
- ID_SED1374
- ID_SED1374F0A
- ID_UNKNOWN
Other HAL libraries will return their respective controller IDs upon detection of
their controller.
Return Value: ERR_OK - operation completed with no problems
ERR_UNKNOWN_DEVICE - the HAL was unable to identify the display
controller. Returned when pID returns ID_UNKNOWN.
void seGetHalVersion(const char ** pVersion, const char ** pStatus,
const char **pStatusRevision)
Description:
Retrieves the HAL library version information. The return values are ASCII strings.
A typical return would be: “1.01 B 5” - HAL version 1.01, 'B' is the beta designator,
this example would be Beta 5. If pStatus is NULL then pStatusRevision should be
NULL too.
Parameters:
pVersion
- Pointer to string to return the version in.
- must point to an allocated string of size VER_SIZE
pStatus
- Pointer to a string to return the release status in.
- must point to an allocated string of size STATUS_SIZE
pStatusRevision - Pointer to return the current revision of status.
- must point to an allocated string of size STAT_REV_SIZE
Return Value: None
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int seSetBitsPerPixel(int DevID, int BitsPerPixel)
Description:
This routine sets the color depth the SED1374 displays in.
After performing validity checks to ensure the requested video mode can be set the
appropriate registers are changed and the Look-Up table is set its default values
appropriate to the color depth.
This call is similar to a mode set call on a standard VGA.
Parameter:
DevID
- registered device ID
BitsPerPixel - desired color depth in bits per pixel.
- Valid arguments are: 1, 2, 4, and 8.
Return Value: ERR_OK - operation completed with no problems
ERR_FAILED- possible causes for this error include:
1) the desired frame rate may not be attainable with the specified input clock
2) the combination of width, height and color depth may require more memory than
is available on the SED1374.
int seGetBitsPerPixel(int DevID, int * pBitsPerPixel)
Description:
This function reads the SED1374 registers to determine the current color depth and
returns the result in pBitsPerPixel.
Parameters:
DevID
- registered device ID
pBitsPerPixel - pointer to an integer to receive current color depth.
- return values will be: 1, 2, 4, or 8.
Return Value: ERR_OK
- operation completed with no problems
int seGetBytesPerScanline(int DevID, int * pBytes)
Description:
Returns the number of bytes use by each scan line in the integer pointed to by
pBytes. The number of bytes per scanline will include the number of non-displayed
bytes, if applicable.
Prior to calling seGetBytesPerScanline() the SED1374 control registers must have
been correctly initialized.
Parameters:
DevID
pBytes
- registered device ID
- pointer to an integer to receive the number of bytes per scan line
Return Value: ERR_OK - operation completed with no problems
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int seGetScreenSize(int DevID, int * Width, int * Height)
Description:
Retrieves the width and height in pixels of the display surface. The width and height
are derived by reading the horizontal and vertical size registers and calculating the
dimensions. Virtual dimensions are not taken into account for this calculation.
When the display is in SwivelView mode the dimensions will be swapped. (i.e. a
640x480 display in SwivelView mode will return a width and height of 480 and
height of 640.
Parameters:
DevID
Width
Height
Return value: ERR_OK
- registered device ID
- pointer to an integer to receive the display width
- pointer to an integer to receive the display height
- the operation completed successfully
int seDelay(int MilliSeconds)
Description:
This function will delay for the length of time specified in “MilliSeconds” before
returning to the caller.
This function was originally intended for non-PC platforms. Information about how
to access the timers was not always available however we do know frame rate and
can use that for timing calculations.
The SED1374 registers must be initialized for this function to work correctly. On the
PC platform this is simply a call to the C timing functions and is therefore
independent of the register settings.
Parameters:
DevID
- registered device ID
MilliSeconds- time to delay in seconds
Return Value: ERR_OK - operation completed with no problems
ERR_FAILED- returned on non-PC platforms when the SED1374 registers have not
bee initialized
int seGetLastUsableByte(int DevID, long * plLastByte)
Description:
This functions returns a pointer, as a long integer, to the last byte of usable display
memory.
This function is a holdover from 135X products which support different amounts of
memory.
Parameters:
Programming Notes and Examples
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DevID
- registered device ID
plLastByte - pointer to a long integer to receive the offset to the last byte of
display memory
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Return Value: ERR_OK
- operation completed with no problems
int seSetHightPerformance(int DevID, BOOL OnOff)
Description:
This function call enables or disable the high performance bit of the SED1374.
When high performance is enabled then MClk equals PClk for all video display
resolutions. In the high performance state CPU to video memory performance is
improved at the cost of higher power consumption.
When high performance is disabled then MClk ranges from PClk/1 at 8 bit-per-pixel
to PClk/8 at 1 bit-per-pixel. Without high performance CPU to video memory
accessed speeds are slower but the SED1374 uses less power.
Parameters:
DevID
OnOff
Return Value: ERR_OK
- registered device ID
- a boolean value (defined in HAL.H) to indicate whether to
enable of disable high performance.
- operation completed with no problems
9.2.3 Advanced HAL Functions
Advanced HAL functions include the functions to support split, virtual and rotated
displays. While the concept for using these features is advanced the HAL makes actually
using them easy.
int seSetHWRotate(int DevID, int Rotate)
Description:
This function sets the rotation scheme according to the value of 'Rotate'. When
SwivelView mode is selected as the display rotation the scheme selected is the 'nonX2' scheme.
Parameters:
DevID
Rotate
- registered device ID
- the direction to rotate the display
- Valid arguments for Rotate are: LANDSCAPE and PORTRAIT.
Return Value: ERR_OK - operation completed with no problems
ERR_FAILED - the operation failed to complete.
The most likely reason for failing to set a SwivelView mode is an inability to set the
desired frame rate when setting the mode. Other factors which can cause a failure
include having configured for a 0 Hz frame rate or specifying something other than
LANDSCAPE or PORTRAIT for the rotation scheme.
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int seSplitInit(int DevID, WORD Scrn1Addr, WORD Scrn2Addr)
Description:
This function prepares the system for split screen operation. In order for split screen
to function the starting address in display buffer for the upper portion(screen 1) and
the lower portion (screen 2) must be specified. Screen 1 is always displayed above
screen 2 on the display regardless of the location of their start addresses.
Parameters:
DevID
- registered device ID
Scrn1Addr - offset, in bytes, to the start of screen 1
Scrn2Addr - offset, in bytes, to the start of screen 2
Return Value: ERR_OK - operation completed with no problems
Note
It is assumed that the system has been properly initialized prior to calling seSplitInit().
int seSplitScreen(int DevID, int Screen, int VisibleScanlines)
Description:
Changes the relevant registers to adjust the split screen according to the number of
visible lines requested. 'WhichScreen' determines which screen, 1 or 2, to base the
changes on.
The smallest surface screen 1 can display is one line. This is due to the way the
SED1374 operates. Setting Screen 1 Vertical Size to zero results in one line of
screen 1 being displayed. The remainder of the display will be screen 2 image.
Parameters:
DevID
- registered device ID
Screen
- must be set to 1 or 2 (or use the constants SCREEN1 or SCREEN2)
VisibleScanlines- number of lines to display for the selected screen
Return Value: ERR_OK - operation completed with no problems
ERR_HAL_BAD_ARG- argument VisibleScanlines is negative or is greater than
vertical panel size or WhichScreen is not SCREEN1 or SCREEN 2.
Note
seSplitInit() must be called before calling seSplitScreen()
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int seVirtInit(int DevID, DWORD VirtX, DWORD * VirtY)
Description:
This function prepares the system for virtual screen operation. The programmer
passes the desired virtual width, in pixels, as VirtX. When the routine returns VirtY
will contain the maximum number of line that can be displayed at the requested
virtual width.
Parameter:
DevID
VirtX
VirtY
- registered device ID
- horizontal size of virtual display in pixels.
(Must be greater or equal to physical size of display)
- pointer to an integer to receive the maximum number of displayable
lines of 'VirtX' width.
Return Value: ERR_OK - operation completed with no problems
ERR_HAL_BAD_ARG - returned in three situations:
1) the virtual width (VirtX) is greater than the largest possible width
(VirtX varies with color depth and ranges from 4096 pixels wider
than the panel at 1 bit-per-pixel down to 512 pixels wider than the
panel at 8 bit-per-pixel)
2) the virtual width is less than the physical width or
3) the maximum number of lines becomes less than the physical
number of lines
Note
The system must have been properly initialized prior to calling seVirtInit()
int seVirtMove(int DevID, int Screen, int x, int y)
Description:
This routine pans and scrolls the display after a virtual display has bee setup. In the
case where split screen operation is being used the WhichScreen argument specifies
which screen to move. The x and y parameters specify, in pixels, the starting location
in the virtual image for the top left corner of the applicable display.
Parameter:
DevID
Screen
x
y
- registered device ID
- must be set to 1 or 2, or use the constants SCREEN1 or SCREEN2,
to identify which screen to base calculations on
- new starting X position in pixels
- new starting Y position in pixels
Return Value: ERR_OK - operation completed with no problems
ERR_HAL_BAD_ARG- there are several reasons for this return value:
1) WhichScreen is not SCREEN1 or SCREEN2.
2) the y argument is greater than the last available line less the screen height.
Note
seVirtInit() must be been called before calling seVirtMove().
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9.2.4 Register / Memory Access
The Register/Memory Access functions provide access to the SED1374 registers and
display buffer through the HAL.
int seGetReg(int DevID, int Index, BYTE * pValue)
Description:
Reads the value in the register specified by index.
Parameters:
DevID
Index
pValue
Return Value: ERR_OK
- registered device ID
- register index to read
- pointer to a BYTE to receive the register value.
- operation completed with no problems
int seSetReg(int DevID, int Index, BYTE Value)
Description:
Writes value specified in Value to the register specified by Index.
Parameters:
DevID
Index
Value
Return Value: ERR_OK
- registered device ID
- register index to set
- value to write to the register
- operation completed with no problems
int seReadDisplayByte(int DevID, DWORD Offset, BYTE *pByte)
Description:
Reads a byte from the display buffer at the specified offset and returns the value in
pByte.
Parameters:
DevID
Offset
pByte
- registered device ID
- offset, in bytes from start of the display buffer, to read from
- pointer to a BYTE to return the value in
Return Value: ERR_OK - operation completed with no problems
ERR_HAL_BAD_ARG - if the value for Addr is greater 40 kb
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int seReadDisplayWord(int DevID, DWORD Offset, WORD *pWord)
Description:
Reads a word from the display buffer at the specified offset and returns the value in
pWord.
Parameters:
DevID
Offset
pWord
- registered device ID
- offset, in bytes from start of the display buffer, to read from
- pointer to a WORD to return the value in
Return Value: ERR_OK - operation completed with no problems.
ERR_HAL_BAD_ARG - if the value for Addr is greater than 40 kb.
int seReadDisplayDword(int DevID, DWORD Offset, DWORD *pDword)
Description:
Reads a dword from the display buffer at the specified offset and returns the value
in pDword.
Parameters:
DevID
Offset
pDword
- registered device ID
- offset from start of the display buffer to read from
- pointer to a DWORD to return the value in
Return Value: ERR_OK - operation completed with no problems.
ERR_HAL_BAD_ARG - if the value for Addr is greater than 40 kb.
int seWriteDisplayBytes(int DevID, DWORD Offset, BYTE Value,
DWORD Count)
Description:
This routine writes one or more bytes to display buffer at the offset specified by
Addr. If a count greater than one is specified all bytes will have the same value.
Parameters:
DevID
Offset
Value
Count
- registered device ID
- offset from start of the display buffer to start writing at
- BYTE value to write
- number of bytes to write
Return Value: ERR_OK - operation completed with no problems
ERR_HAL_BAD_ARG - if the value for Addr or the value of Addr plus Count is
greater than 40 kb.
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int seWriteDisplayWords(int DevID, DWORD Offset, WORD Value,
DWORD Count)
Description:
Writes one or more WORDS to the display buffer at the offset specified by Addr. If
a count greater than one is specified all WORDS will have the same value.
Parameters:
DevID
Offset
Value
Count
- registered device ID
- offset from start of the display buffer
- WORD value to write
- number of words to write
Return Value: ERR_OK - operation completed with no problems
ERR_HAL_BAD_ARG - if the value for Addr or if Addr plus Count is greater than
40 kb.
int seWriteDisplayDwords(int DevID, DWORD Offset, DWORD Value,
DWORD Count)
Description:
Writes one or more DWORDS to the display buffer at the offset specified by Addr.
If a count greater than one is specified all DWORDSs will have the same value.
Parameters:
DevID
Offset
Value
Count
- registered device ID
- offset from start of the display buffer
- DWORD value to write
- number of dwords to write
Return Value: ERR_OK - operation completed with no problems
ERR_HAL_BAD_ARG - if the value for Addr or if Addr plus Count is greater than
40 kb.
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9.2.5 Power Save
This section covers the HAL functions dealing with the Power Save features of the
SED1374.
int seSetPowerSaveMode(int DevID, int PwrSaveMode)
Description:
This function sets on the SED1374’s software selectable power save modes.
Parameters:
DevID
- a registered device ID
PwrSaveMode - integer value specifying the desired power save mode.
Acceptable values for PwrSaveMode are:
0 - (software power save mode) in this mode registers and memory are
read/writable. LCD output is forced low.
3 - (normal operation) all outputs function normally.
Return Value: ERR_OK
- operation completed with no problems
9.2.6 Drawing
The Drawing routines cover HAL functions that deal with displaying pixels, lines and
shapes.
int seDrawLine(int DevID, int x1, int y1, int x2, int y2, DWORD Color)
Description:
This routine draws a line on the display from the endpoints defined by x1,y1 to the
endpoint x2,y2 in the requested 'Color'.
Currently seDrawLine() only draws horizontal and vertical lines.
Parameters:
Device
(x1, y1)
(x2, y2)
Color
- registered device ID.
- first endpoint of the line in pixels
- second endpoint of the line in pixels (see note below)
- color to draw with. 'Color' is an index into the LUT.
Return Value: ERR_OK - operation completed with no problems
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int seDrawRect(int DevID, long x1, long y1, long x2, long y2,
DWORD Color, BOOL SolidFill)
Description:
This routine draws and optionally fills a rectangular area of display buffer. The
upper right corner is defined by x1,y1 and the lower right corner is defined by x2,y2.
The color, defined by Color, applies both to the border and to the optional fill.
Parameters:
DevID
x1, y1
x2, y2
Color
SolidFill
- registered device ID
- top left corner of the rectangle (in pixels)
- bottom right corner of the rectangle (in pixels)
- The color to draw the rectangle outline and fill with
- Color is an index into the Look-Up Table.
- Flag whether to fill the rectangle or simply draw the border.
- Set to 0 for no fill, set to non-0 to fill the inside of the rectangle
Return Value: ERR_OK - operation completed with no problems.
9.2.7 LUT Manipulation
These functions deal with altering the color values in the Look-Up Table.
int seSetLut(int DevID, BYTE *pLut, int Count)
Description:
This routine writes one or more LUT entries. The writes always start with Look-Up
Table index 0 and continue for 'Count' entries.
A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue.
The color information is stored in the four least significant bits of each byte.
Parameters:
DevID
pLut
Count
- registered device ID
- pointer to an array of BYTE lut[16][3]
lut[x][0] == RED component
lut[x][1] == GREEN component
lut[x][2] == BLUE component
- the number of LUT entries to write.
Return Value: ERR_OK - operation completed with no problems
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int seGetLut(int DevID, BYTE *pLUT, int Count)
Description:
This routine reads one or more LUT entries and puts the result in the byte array
pointed to by pLUT.
A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue.
The color information is stored in the four least significant bits of each byte.
Parameters:
DevID
pLUT
Count
- registered device ID
- pointer to an array of BYTE lut[16][3]
- pLUT must point to enough memory to hold 'Count' x 3 bytes of data.
- the number of LUT elements to read.
Return Value: ERR_OK - operation completed with no problems
int seSetLutEntry(int DevID, int Index, BYTE *pEntry)
Description:
This routine writes one LUT entry. Unlike seSetLut, the LUT entry indicated by
'Index' can be any value from 0 to 15.
A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue.
The color information is stored in the four least significant bits of each byte.
Parameters:
DevID
Index
pLUT
- registered device ID
- index to LUT entry (0 to 15)
- pointer to an array of three bytes.
Return Value: ERR_OK - operation completed with no problems
int seGetLutEntry(int DevID, int index, BYTE *pEntry)
Description:
This routine reads one LUT entry from any index.
A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue.
The color information is stored in the four least significant bits of each byte.
Parameters:
DevID
Index
pEntry
- registered device ID
- index to LUT entry (0 to 15)
- pointer to an array of three bytes
Return Value: ERR_OK - operation completed with no problems
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10 Sample Code
10.1 Introduction
Included in the sample code section are two examples of programing the SED1374. The
first sample uses the HAL to draw a red square, wait for user input then rotates to
SwivelView mode and draws a blue square. The second sample code performs the same
procedures but directly accesses the registers of the SED1374. These code samples are for
example purposes only.
10.1.1 Sample code using the SED1374 HAL API
/*
**===========================================================================
** SAMPLE1.C - Sample code demonstating a program using the SED1374 HAL.
**------------------------------------------------------------------------** Created 1998, Vancouver Design Centre
** Copyright (c) 1998 Epson Research and Development, Inc.
** All Rights Reserved.
**------------------------------------------------------------------------**
** The HAL API code is configured for the following:
**
** 320x240 Single Color 8-bit STN (format 2)
** 4 bpp - 70 Hz Frame Rate (25 MHz CLKi)
** High Performance enabled
**
**===========================================================================
*/
#include <conio.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "hal.h"
/* Structures, constants and prototypes. */
#include "appcfg.h"
/* HAL configuration information. */
/*--------------------------------------------------------------------------*/
void main(void)
{
int ChipId;
int Device;
/*
**
**
**
*/
if
Initialize the HAL.
The call to seRegisterDevice() actually prepares the HAL library
for use. The SED1374 is not accessed.
(ERR_OK != seRegisterDevice(&HalInfo, &Device))
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{
printf("\nERROR: Could not register SED1374 device.");
exit(1);
}
/*
** Get the product code to verify this is an SED1374.
** NOTE: If the SED1374 design is modified then the
**
product identification change. Additional IDs
**
will have to be checked for.
*/
seGetId(Device, &ChipId);
if (ID_SED1374F0A != ChipId)
{
printf("\nERROR: Did not detect an SED1374.");
exit(1);
}
/*
**
**
**
*/
if
{
Initialize the SED1374.
This step programs the registers with values taken from
the HalInfo struct in appcfg.h.
(ERR_OK != seSetInit(Device))
printf("\nERROR: Could not initialize device.");
exit(1);
}
/*
** The default initialization cleared the display.
** Draw a 100x100 red rectangle in the upper left corner (0,0)
** of the display.
*/
seDrawRect(Device, 0, 0, 100, 100, 1, TRUE);
/*
** Pause here.
*/
getch();
/*
** Clear the display. Do this by writing 40960 bytes
*/
seWriteDisplayBytes(Device, 0, 0, FORTY_K);
/*
** Setup SwivelView mode.
*/
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seSetHWRotate(Device, PORTRAIT);
/*
** Draw a solid blue 100x100 rectangle in center of the display.
** This starting co-ordinates, assuming a 320x240 display is
** (320-100)/2 , (240-100)/2 = 110,70.
*/
seDrawRect(Device, 110, 70, 210, 170, 2, TRUE);
/*
** Done!
*/
exit(0);
}
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10.1.2 Sample code without using the SED1374 HAL API
This second sample demonstrates exactly the same sequence as the first howerver the HAL
is not used, all manipulation is done by manually adjusting the registers.
/*
**===========================================================================
** SAMPLE2.C - Sample code demonstating a direct access of the SED1374.
**------------------------------------------------------------------------** Created 1998, Vancouver Design Centre
** Copyright (c) 1998 Epson Research and Development, Inc.
** All Rights Reserved.
**------------------------------------------------------------------------**
** The sample code using direct SED1374 access
** will configure for the following:
**
** 320x240 Single Color 8-bit STN (format 2)
** 4 bpp - 70 Hz Frame Rate (25 MHz CLKi)
** High Performance enabled
**
** Notes:
** 1) This code is pseudo-C code intended to show technique.
**
It is assumed that pointers can access the relevant memory addresses.
** 2) Register setup is done with discreet writes rather than being table
**
driven. This allows for clearer commenting. It is more efficient to
**
loop through the array writing each element to a control register.
** 3) The array of register values as produced by 1374CFG.EXE is included
**
here. I used the values directly rather than refer to the register
**
array in the sample code.
**
**===========================================================================
*/
#include <conio.h>
/*
** Look-up table for 4 bpp color.
*/
unsigned char Color_4BPP[16*3] =
{
0x00, 0x00, 0x00,/* BLACK
0x00, 0x00, 0x0A,/* BLUE
0x00, 0x0A, 0x00,/* GREEN
0x00, 0x0A, 0x0A,/* CYAN
0x0A, 0x00, 0x00,/* RED
0x0A, 0x00, 0x0A,/* PURPLE
0x0A, 0x0A, 0x00,/* YELLOW
0x0A, 0x0A, 0x0A,/* WHITE
0x00, 0x00, 0x00,/* BLACK
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*/
*/
*/
*/
*/
*/
*/
*/
*/
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0x00,
0x00,
0x00,
0x0F,
0x0F,
0x0F,
0x0F,
0x00,
0x0F,
0x0F,
0x00,
0x00,
0x0F,
0x0F,
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0x0F,/* LT BLUE
*/
0x00,/* LT GREEN */
0x0F,/* LT CYAN
*/
0x00,/* LT RED
*/
0x0F,/* LT PURPLE */
0x00,/* LT YELLOW */
0x0F/* LT WHITE */
};
/*
** Register data for the configuratin described above.
** These values were generated using 1374CFG.EXE.
** The sample code uses these values but does not refer to this array.
*/
unsigned char Reg[0x20] = {
0x00, 0x23, 0xB0, 0x03, 0x27, 0xEF, 0x00, 0x00,
0x1E, 0x00, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0xFF, 0x03, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
/*
** Useful definitions, constants and macros to make the sample code
** easier to follow.
*/
#define MEM_OFFSET 0x01374B0B
/* Location is platform dependent */
#define REG_OFFSET MEM_OFFSET + 0xFFE0/* Memory offset + 64K - 0x20
*/
#define MEM_SIZE 0xA000
/* 40 kb display buffer.
*/
typedef unsigned char BYTE;
/* Some usefule typedefs */
typedef BYTE far * LPBYTE;
typedef unsigned short WORD;
#define LOBYTE(w)
((BYTE)(w))
#define HIBYTE(w)
((BYTE)(((WORD)(w) >> 8) & 0xFF))
#define SET_REG(idx, val) (*(LPBYTE)(REG_OFFSET + idx)) = (val)
/*-----------------------------------------------------------------------*/
void main(void)
{
LPBYTE pRegs = (LPBYTE)REG_OFFSET;
LPBYTE pMem = (LPBYTE)MEM_OFFSET;
LPBYTE pLUT;
int
LUTcount, RGBcount;
int x, y, tmp;
int BitsPerPixel = 4;
int Width
= 320;
int Height
= 240;
int OffsetBytes;
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/*
** Check the revision code. Exit if we don't find an SED1374.
*/
if (0x18 != *pRegs)
return;
/*
** Initialize the chip.
** Each register is individually programmed to make comments clearer.
*/
/*
** Register 01h: Mode Register 0 - Color, 8-bit format 2
*/
SET_REG(0x01, 0x23);
/*
** Register 02h: Mode Register 1 - 4BPP,
*/
SET_REG(0x02, 0xB0);
High Performance, CLKi/2
/*
** Register 03h: Mode Register 2 - Normal power mode
*/
SET_REG(0x03, 0x03);
/*
** Register 04h: Horizontal Panel Size - 320 pixels - (320/8)-1 = 39 = 27h
*/
SET_REG(0x04, 0x27);
/*
** Register 05h: Vertical Panel Size LSB - 240 pixels
** Register 06h: Vertical Panel Size MSB - (240 - 1) = 239 = EFh
*/
SET_REG(0x05, 0xEF);
SET_REG(0x06, 0x00);
/*
** Register 07h - FPLINE Start Position - not used by STN
*/
SET_REG(0x07, 0x00);
/*
** Register 08h - Horizontal Non-Display Period
**
- HNDP and VNDP are calculated to achieve the
**
desired frame rate according to:
**
**
PCLK
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**
Frame Rate = --------------------------**
(HDP + HNDP) * (VDP + VNDP)
*/
SET_REG(0x08, 0x1E);
/*
** Register 09h - FPFRAME Start Position - not used by STN
*/
SET_REG(0x09, 0x00);
/*
** Register 0Ah - Vertical Non-Display Register
**
- CAlculated in conjunction with register 08h (HNDP) to
**
achieve the desired frame rate.
*/
SET_REG(0x0A, 0x3B);
/*
** Register 0Bh - MOD Rate - not used by this panel
*/
SET_REG(0x0B, 0x00);
/*
** Register 0Ch - Screen 1 Start Word Address LSB
** Register 0Dh - Screen 1 Start Word Address MSB
**
- Start address should be set to 0
*/
SET_REG(0x0C, 0x00);
SET_REG(0x0D, 0x00);
/*
** Register 0Fh - Screen 2 Start Word Address LSB
** Register 10h - Screen 2 Start Word Address MSB
**
- Set this start address to 0 too
*/
SET_REG(0x0F, 0x00);
SET_REG(0x10, 0x00);
/*
** Register 12h - Memory Address Offset
**
- Used for setting memory to a width greater than the
**
display size. Usually set to 0 during initialization
**
and programmed to desired value later.
*/
SET_REG(0x12, 0x00);
/*
** Register 13h - Screen 1 Vertical Size LSB
** Register 14h - Screen 1 Vertical Size MSB
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**
- Set to maximum (i.e. 0x3FF). This register is used
**
for split screen operation and should be set to 0
**
during initialization.
*/
SET_REG(0x13, 0xFF);
SET_REG(0x14, 0x03);
/*
** Look-Up Table
** In this example the LUT will be programmed in the register sequence.
** In practice the LUT would probably be done after the other registers.
*/
/*
** Register 15h - Look-Up Table Address
**
- Set to 0 to start RGB sequencing at the first LUT entry.
*/
SET_REG(0x15, 0x00);
/*
** Register 16h - Look-Up Table Bank Select
**
- Set all the banks to 0.
**
- At 4BPP this makes no difference however it will affect
**
appearance at other color depths.
*/
SET_REG(0x16, 0x00);
/*
** Register 17h - Look-Up Table Data
**
- Write 16 RGB triplets to setup the LUT for 4BPP operation.
**
- The LUT is 16 elements deep, 4BPP uses all the idices.
*/
pLUT = Color_4BPP;
for (LUTcount = 0; LUTcount < 16; LUTcount++)
{
for (RGBcount = 0; RGBcount < 3; RGBcount++)
{
SET_REG(0x17, *pLUT);
pLUT++;
}
}
/*
** Register 18h - GPIO Configuration - set to 0
**
- '0' configures the GPIO pins for input (power on default)
*/
SET_REG(0x18, 0x00);
/*
** Register 19h - GPIO Status - set to 0
**
- This step has no reason other than it programs the GPIO
SED1374
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**
values low should the pins get configured as outputs.
*/
SET_REG(0x19, 0x00);
/*
** Register 1Ah - Scratch Pad - set to 0
*/
SET_REG(0x1A, 0x00);
/*
** Register 1Bh - SwivelView Mode - set to 0 - disable SwivelView mode
*/
SET_REG(0x1B, 0x00);
/*
** Register 1Ch - Line Byte Count - set to 0 - Not used by landscape mode
*/
SET_REG(0x0C, 0x00);
/*
** Register 1Fh - TestMode - set to 0
*/
SET_REG(0x1F, 0x00);
/*
** Draw a 100x100 red rectangle in the
** of the display.
*/
for (y = 0; y < 100; y++)
{
/*
** Set the memory pointer at the
**
Pointer = MEM_OFFSET + (Y *
*/
pMem = (LPBYTE)MEM_OFFSET + (y *
for (x = 0; x < 100; x+=2)
{
*pMem = 0x44;
/*
pMem++;
}
}
upper left corner (0,0)
start of each line.
Line_Width * BPP / 8) + (X * BPP / 8)
320 * BitsPerPixel / 8) + 0;
Draws 2 pixels with LUT color 4 */
/*
** Pause here.
*/
getch();
/*
** Clear the display, and all of video memory, by writing 40960 bytes of 0.
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** This is done because an image in display memory is not rotated with the
** switch to SwivelView mode we are about to make.
*/
pMem = (LPBYTE)MEM_OFFSET;
do {
*pMem = 0;
pMem++;
} while (pMem < (LPBYTE)(MEM_OFFSET + MEM_SIZE));
/*
** SwivelView mode.
*/
/*
** We will use the default SwivelView mode scheme so we have to adjust
** the ROTATED width to be a power of 2.
** (NOTE: current height will become the rotated width)
*/
tmp = 1;
while (Height > (1 << tmp))
tmp++;
Height = (1 << tmp);
OffsetBytes = Height * BitsPerPixel / 8;
/*
** Set:
** 1) Line Byte Count to size of the ROTATED width (i.e. current height)
** 2) Start Address to the offset of the width of the ROTATED display.
**
(in SwivelView mode the start address registers point to bytes)
*/
SET_REG(0x1C, (BYTE)OffsetBytes);
OffsetBytes--;
SET_REG(0x0C, LOBYTE(OffsetBytes));
SET_REG(0x0D, HIBYTE(OffsetBytes));
/*
** Set SwivelView mode.
** Use the non-X2 (default) scheme so we don't have to re-calc the frame
** rate. MCLK will be <= 25 MHz so we can leave auto-switch enabled.
*/
SET_REG(0x1B, 0x80);
/*
** Draw a solid blue 100x100 rectangle centered on the display.
** Starting co-ordinates, assuming a 320x240 display are:
**
(320-100)/2 , (240-100)/2 = 110,70.
*/
for (y = 70; y < 180; y++)
{
/*
SED1374
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Vancouver Design Center
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** Set the memory pointer at the start of each line.
**
Pointer = MEM_OFFSET + (Y * Line_Width * BPP / 8) + (X * BPP / 8)
** NOTICE that in SwivelView mode we will use a value of 256
** for the line width value (not 240).
*/
x = 110;
pMem = (LPBYTE)MEM_OFFSET + (y * 256 * BitsPerPixel / 8) +
(x * BitsPerPixel / 8);
for (x = 110; x < 210; x+=2)
{
*pMem = 0x11;
/* Draws 2 pixels in LUT color 1 */
pMem++;
}
}
}
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10.1.3 Header Files
The header files included here are the required for the HAL sample to compile correctly.
/*
**===========================================================================
** HAL.H - Typical HAL header file for use with programs written to
**
use the SED1374 HAL.
**--------------------------------------------------------------------------** Created 1998, Vancouver Design Centre
** Copyright (c) 1998 Epson Research and Development, Inc.
** All Rights Reserved.
**===========================================================================
*/
#ifndef _HAL_H_
#define _HAL_H_
#pragma warning(disable:4001)
// Disable the 'single line comment' warning.
#include "hal_regs.h"
/*-------------------------------------------------------------------------*/
typedef unsigned char BYTE;
typedef unsigned short WORD;
typedef unsigned long DWORD;
typedef unsigned int
UINT;
typedef
int
BOOL;
#ifdef INTEL
typedef BYTE far *LPBYTE;
typedef WORD far *LPWORD;
typedef UINT far *LPUINT;
typedef DWORD far *LPDWORD;
#else
typedef BYTE
*LPBYTE;
typedef WORD
*LPWORD;
typedef UINT
*LPUINT;
typedef DWORD
*LPDWORD;
#endif
#ifndef LOBYTE
#define LOBYTE(w)
((BYTE)(w))
#endif
#ifndef HIBYTE
#define HIBYTE(w)
((BYTE)(((UINT)(w) >> 8) & 0xFF))
#endif
#ifndef LOWORD
#define LOWORD(l)
((WORD)(DWORD)(l))
#endif
#ifndef HIWORD
#define HIWORD(l)
((WORD)((((DWORD)(l)) >> 16) & 0xFFFF))
#endif
SED1374
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Programming Notes and Examples
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Epson Research and Development
Vancouver Design Center
#ifndef
#define
#endif
#ifndef
#define
#endif
#ifndef
#define
#endif
#ifndef
#define
#endif
#define
#define
#define
#define
/*
Page 73
MAKEWORD
MAKEWORD(lo, hi) ((WORD)(((WORD)(lo)) | (((WORD)(hi)) << 8)) )
MAKELONG
MAKELONG(lo, hi) ((long)(((WORD)(lo)) | (((DWORD)((WORD)(hi))) << 16)))
TRUE
TRUE
1
FALSE
FALSE
0
OFF 0
ON 1
SCREEN1 1
SCREEN22
** Constants for HW rotate support
*/
#define DEFAULT0
#define LANDSCAPE 1
#define PORTRAIT2
#ifndef NULL
#ifdef __cplusplus
#define NULL
0
#else
#define NULL
((void *)0)
#endif
#endif
/*-------------------------------------------------------------------------*/
/*
** SIZE_VERSION is the size of the version string (eg. "1.00")
** SIZE_STATUS
is the size of the status string (eg. "b" for beta)
** SIZE_REVISION is the size of the status revision string (eg. "00")
*/
#define SIZE_VERSION5
#define SIZE_STATUS 2
#define SIZE_REVISION3
#ifdef ENABLE_DPF
/* Debug_printf() */
#define DPF(exp) printf(#exp "\n")
#define DPF1(exp) printf(#exp " = %d\n", exp)
#define DPF2(exp1, exp2) printf(#exp1 "=%d " #exp2 "=%d\n", exp1, exp2)
#define DPFL(exp) printf(#exp " = %x\n", exp)
#else
#define DPF(exp) ((void)0)
#define DPF1(exp) ((void)0)
#define DPFL(exp) ((void)0)
#endif
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/*-------------------------------------------------------------------------*/
enum
{
ERR_OK = 0,
/* No error, call was successful. */
ERR_FAILED,
/* General purpose failure.
*/
ERR_UNKNOWN_DEVICE,
/* */
ERR_INVALID_PARAMETER, /* Function was called with invalid parameter. */
ERR_HAL_BAD_ARG,
ERR_TOOMANY_DEVS
};
/*******************************************
* Definitions for seGetId()
*******************************************/
#define PRODUCT_ID 0x18
enum
{
ID_UNKNOWN,
ID_SED1374,
ID_SED1374F0A
};
#define
#define
#define
#define
MAX_MEM_ADDR 40960 -1
FORTY_K
MAX_DEVICE
10
SE_RSVD
40960
0
/*
** DetectEndian is used to determine whether the most significant
** and least significant bytes are reversed by the given compiler.
*/
#define ENDIAN
0x1234
#define REV_ENDIAN
0x3412
/*******************************************
* Definitions for Internal calculations.
*******************************************/
#define MIN_NON_DISP_X
32
#define MAX_NON_DISP_X
256
#define MIN_NON_DISP_Y
2
#define MAX_NON_DISP_Y
64
/*******************************************
* Definitions for seSetFont
*******************************************/
enum
{
HAL_STDOUT,
HAL_STDIN,
HAL_DEVICE_ERR
};
#define FONT_NORMAL
0x00
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#define FONT_DOUBLE_WIDTH
0x01
#define FONT_DOUBLE_HEIGHT
0x02
enum
{
RED,
GREEN,
BLUE
};
/*************************************************************************/
typedef struct tagHalStruct
{
char szIdString[16];
WORD wDetectEndian;
WORD wSize;
BYTE Reg[MAX_REG + 1];
DWORD dwClkI;
/* Input Clock Frequency (in kHz) */
DWORD dwDispMem;
/* */
WORD wFrameRate;
/* */
} HAL_STRUCT;
typedef HAL_STRUCT * PHAL_STRUCT;
#ifdef INTEL
typedef HAL_STRUCT far * LPHAL_STRUCT;
#else
typedef HAL_STRUCT
* LPHAL_STRUCT;
#endif
/*=========================================================================*/
/*
FUNCTION PROTO-TYPES
*/
/*=========================================================================*/
/*---------------------------- Initialization -----------------------------*/
int seRegisterDevice( const LPHAL_STRUCT lpHalInfo, int *Device );
int seSetInit( int device );
int
seInitHal( void );
/*----------------------------- Miscellaneous -----------------------------*/
int seGetId( int nDevID, int *pId );
void seGetHalVersion( const char **pVersion, const char **pStatus, const char **pStatusRevision );
int seSetBitsPerPixel( int nDevID, int nBitsPerPixel );
int seGetBitsPerPixel( int nDevID, int *pBitsPerPixel );
int seGetBytesPerScanline( int nDevID, int *pBytes );
int seGetScreenSize( int nDevID, int *width, int *height );
void seDelay( int nMilliSeconds );
int seGetLastUsableByte( int nDevID, long *LastByte );
int seSetHighPerformance( int nDevID, BOOL OnOff );
/*------------------------------- Advanced --------------------------------*/
int seSetHWRotate( int nDevID, int nMode );
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int
int
int
int
Epson Research and Development
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seSplitInit( int nDevID, WORD Scrn1Addr, WORD Scrn2Addr );
seSplitScreen( int nDevID, int WhichScreen, int VisibleScanlines );
seVirtInit( int nDevID, int xVirt, long *yVirt );
seVirtMove( int nDevID, int nWhichScreen, int x, int y );
/*------------------------ Register/Memory Access -------------------------*/
int seGetReg( int nDevID, int index, BYTE *pValue );
int seSetReg( int nDevID, int index, BYTE value );
int seReadDisplayByte( int nDevID, DWORD offset, BYTE *pByte );
int seReadDisplayWord( int nDevID, DWORD offset, WORD *pWord );
int seReadDisplayDword( int nDevID, DWORD offset, DWORD *pDword );
int seWriteDisplayBytes( int nDevID, DWORD addr, BYTE val, DWORD count );
int seWriteDisplayWords( int nDevID, DWORD addr, WORD val, DWORD count );
int seWriteDisplayDwords( int nDevID, DWORD addr, DWORD val, DWORD count );
/*---------------------------------- Power Save ---------------------------*/
int seHWSuspend( int nDevID, BOOL val );
int seSetPowerSaveMode( int nDevID, int PowerSaveMode );
/*----------------------------------- Drawing -----------------------------*/
// int seSetPixel( int nDevID, int x, int y, DWORD color );
// int seGetPixel( int nDevID, int x, int y, DWORD *pVal );
int seDrawLine( int nDevID, int x1, int y1, int x2, int y2, DWORD color );
int seDrawRect( int nDevID, int x1, int y1, int x2, int y2, DWORD color, BOOL Solidfill );
// int seDrawCircle( int nDevID, int xCenter, int yCenter, int radius, DWORD color,
BYTE SolidFill );
/*------------------------------ Text -------------------------------------*/
// int seDrawText( int nDevID, char *fmt, ... );
// int seSetCursor( int row, int col);
// int seSetColor( DWORD foreground, DWORD background);
// int seSetFont( BYTE FontSize, BYTE FontAttr);
/*------------------------------ Color ------------------------------------*/
int seSetLut( int nDevID, BYTE *pLut );
int seGetLut( int nDevID, BYTE *pLut );
int seSetLutEntry( int nDevID, int index, BYTE *pEntry );
int seGetLutEntry( int nDevID, int index, BYTE *pEntry );
#endif
/* _HAL_H_ */
/*--------------------------------------------------------------------------*/
/*
**===========================================================================
** APPCFG.H - Application configuration information.
**--------------------------------------------------------------------------** Created 1998, Vancouver Design Centre
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** Copyright (c) 1998 Epson Research and Development, Inc.
** All Rights Reserved.
**--------------------------------------------------------------------------**
** The data in this file was generated using 1374CFG.EXE.
**
** The configureation parameters chosen were:
**
320x240 Single Color 8-bit STN (format 2)
**
4 bpp - 70 Hz Frame Rate (25 MHz CLKi)
**
High Performance enabled
**
**===========================================================================
*/
/**************************************************************/
/* 1374 HAL HDR
(do not remove)
*/
/* HAL_STRUCT Information generated by 1374CFG.EXE
*/
/* Copyright (c) 1998 Seiko Epson Corp. All rights reserved. */
/*
*/
/* Include this file ONCE in your primary source file
*/
/**************************************************************/
HAL_STRUCT HalInfo =
{
"1374 HAL EXE",
/* ID string
*/
0x1234,
/* Detect Endian */
sizeof(HAL_STRUCT), /* Size
*/
0x00, 0x23, 0xB0, 0x03, 0x27, 0xEF, 0x00, 0x00,
0x1E, 0x00, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0xFF, 0x03, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
25000,
/* ClkI (kHz)
*/
0xD0000,
/* Display Address */
70,
** Panel Frame Rate (Hz) */
};
/*--------------------------------------------------------------------------*/
/*
**===========================================================================
** HAL_REGS.H
**--------------------------------------------------------------------------** Created 1998, Epson Research & Development
**
Vancouver Design Center.
** Copyright(c) Seiko Epson Corp. 1998. All rights reserved.
**===========================================================================
*/
#ifndef __HAL_REGS_H__
#define __HAL_REGS_H__
/*
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**
1374 register names
*/
#define REG_REVISION_CODE
0x00
#define REG_MODE_REGISTER_0
0x01
#define REG_MODE_REGISTER_1
0x02
#define REG_MODE_REGISTER_2
0x03
#define REG_HORZ_PANEL_SIZE
0x04
#define REG_VERT_PANEL_SIZE_LSB
0x05
#define REG_VERT_PANEL_SIZE_MSB
0x06
#define REG_FPLINE_START_POS
0x07
#define REG_HORZ_NONDISP_PERIOD
0x08
#define REG_FPFRAME_START_POS
0x09
#define REG_VERT_NONDISP_PERIOD
0x0A
#define REG_MOD_RATE
0x0B
#define REG_SCRN1_START_ADDR_LSB
0x0C
#define REG_SCRN1_START_ADDR_MSB
0x0D
#define REG_RESERVED_1
0x0E
#define REG_SCRN2_START_ADDR_LSB
0x0F
#define REG_SCRN2_START_ADDR_MSB
0x10
#define REG_RESERVED_2
0x11
#define REG_PITCH_ADJUST
0x12
#define REG_SCRN1_VERT_SIZE_LSB
0x13
#define REG_SCRN1_VERT_SIZE_MSB
0x14
#define REG_LUT_ADDR
0x15
#define REG_LUT_BANK_SELECT
0x16
#define REG_LUT_DATA
0x17
#define REG_GPIO_CONFIG
0x18
#define REG_GPIO_STATUS
0x19
#define REG_SCRATCHPAD
0x1A
#define REG_PORTRAIT_MODE
0x1B
#define REG_LINE_BYTE_COUNT
0x1C
#define REG_NOT_PRESENT_1
0x1D
#define REG_FRAMING
0x1E
#define REG_TEST_MODE
0x1F
/*
** WARNING!!! MAX_REG must be the last available register!!!
*/
#define MAX_REG
0x1F
#endif
/* __HAL_REGS_H__ */
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Appendix A Supported Panel Values
A.1 Introduction
Future versions of this document will supply example tables for programming the
SED1374 for different panels.
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SED1374
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SED1374 Register Summary
X26A-R-001-02
4 Panel Data Format
REG[00h] REVISION CODE REGISTER 1 IO address = FFE0h 2, RO
REG[13h] SCREEN 1 VERTICAL SIZE REGISTER (LSB) IO address = FFF3h, RW
Product Code = 000110
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FPFrame
Polarity
Mask
FPSHIFT
Bit 1
Bit 0
REG[01h] MODE REGISTER 0 IO address = FFE1h, RW
TFT/STN
Dual/Single Color/Mono3
Screen 1 Vertical Size = (REG[13h], REG[14h])
Revision Code = 00
FPLine
Polarity
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Color/
Mono
REG[01]
bit 5
TFT/STN
REG[01]
bit 7
Data
Width
Bit 1
REG[01]
bit 1
Dual/
Single
REG[01]
bit 6
Data
Width
Bit 0
REG[01]
bit 0
REG[14h] SCREEN 1 VERTICAL SIZE REGISTER (MSB) IO address = FFF4h, RW
Data Width 4
Bit 1
Bit 0
n/a
n/a
n/a
n/a
n/a
0
Screen 1 Vertical Size
n/a
Bit 9
0
Bit 8
1
REG[15h] LOOK-UP TABLE ADDRESS REGISTER 7 IO address = FFF5h, RW
REG[02h] MODE REGISTER 1 IO address = FFE2h, RW
Bit-Per-Pixel 3
Bit 1
Bit 0
5
High
Input Clock
Performance Div (CLKI/2)
Display
Blank
Frame
Repeat
Hw Video
Invert
Enable
Software
Video Invert
n/a
n/a
n/a
n/a
Bit 1
Look-Up Table Address
Bit 0
Bit 3
Bit 2
Bit 1
0
Bit 0
1
1
REG[16h] LOOK-UP TABLE BANK SELECT REGISTER IO address = FFF6h, RW
REG[03h] MODE REGISTER 2 IO address = FFE3h, RW
Look-Up
Table Bypass
n/a
RGB Index
0
LCDPWR
Override
Hardware
PS Enable
Sw Power Save 6
Bit 1
n/a
Red Bank Select
n/a
Bit 1
Bit 0
Bit 0
Green Bank Select
Blue Bank Select
Bit 1
Bit 1
Bit 0
0
0
Bit 0
0
REG[17h] LOOK-UP TABLE DATA REGISTER IO address = FFF7h, RW
REG[04h] HORIZONTAL PANEL SIZE R EGISTER IO address = FFE4h, RW
n/a
Horizontal Panel Size = 8(REG + 1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
n/a
Bit 1
Bit 5
Bit 4
Bit 3
Bit 2
Look-Up Table Data
n/a
Bit 3
Bit 2
Bit 1
Bit 0
0
n/a
Bit 1
n/a
n/a
GPIO4 Pin
IO Config
GPIO3 Pin
IO Config
1
GPIO2 Pin
IO Config
GPIO1 Pin
IO Config
1
REG[19h] GPIO STATUS / CONTROL REGISTER IO address = FFF9h, RW
n/a
n/a
n/a
n/a
n/a
Vertical Panel Size
Bit 9
n/a
n/a
n/a
GPIO4 Pin
IO Status
GPIO3 Pin
IO Status
GPIO2 Pin
IO Status
GPIO1 Pin
IO Status
GPIO0 Pin
IO Status
REG[1Ah] SCRATCH PAD REGISTER IO address = FFFAh, RW
n/a
n/a
Bit 3
Bit 2
Bit 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
n/a
SwivelView
Mode En.
Horizontal Non-Display Period = 8(REG + 4)
Bit 4
Bit 3
Bit 2
Bit 1
n/a
n/a
Bit 4
Bit 3
Bit 2
Bit 4
Bit 3
n/a
Bit 0
Bit 2
Bit 1
Bit 0
Bit 7
Bit 4
Bit 2
Bit 1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 12
Bit 11
Bit 10
Bit 9
Color Single 4-bit LCD
1
Color Single 8-bit LCD Format 1
0
reserved
1
Color Single 8-bit LCD Format 2
0
reserved
1
Color Dual 8-bit LCD
0
reserved
1
reserved
0
9 bit TFT Panel
1
12 bit TFT Panel
reserved
Bit 4
Bit 3
1
Bit 0
1
X
Display Modes
0
MClk = PClk/8
1 bit-per-pixel
1
MClk = PClk/4
2 bit-per-pixel
0
MClk = PClk/2
4 bit-per-pixel
1
MClk = PClk
8 bit-per-pixel
X
MClk = PClk
6 Power Save Mode Selection
Bit 2
Bit 1
Bit 0
Power Save Bit 1
Power Save Bit 0
Mode
1
reserved
0
reserved
3 Gray Shade/Color Mode Selection
1
1
Normal Operation
Bit-Per-Pixel Bit 1
REG[02] bit 7
0
1
Bit 0
0
1
Screen 1 Start Word Address
Bit 13
reserved
0
1
0
Bit 14
reserved
1
0
Bit 0
REG[0Dh] SCREEN 1 START W ORD ADDRESS REGISTER (MSB) IO address = FFEDh, RW
reserved
0
2 IO addresses are relative to the beginning of display memory.
Screen 1 Start Word Address = (REG[0Ch], REG[0Dh])
Bit 5
Mono Dual 8-bit LCD
Notes
1 These bits are used to identify the SED1373 at power on / reset.
REG[0Ch] SCREEN 1 START W ORD ADDRESS REGISTER (LSB) IO address = FFECh, RW
Bit 6
reserved
1
Software Power Save Mode
1
Bit 7
reserved
0
0
Color/Mono
REG[01] bit 5
Bit 3
reserved
1
0
MOD Rate
Bit 5
n/a
Line Byte Count
Bit 1
Vertical Non-Display Period
Bit 5
n/a
Bit 1
FPFrame Start Position
Bit 5
REG[0Bh] MOD RATE REGISTER IO address = FFEBh, RW
n/a
n/a
SwivelView Mode PCLK
Select
REG[1Ch] LINE BYTE COUNT REGISTER IO address = FFFCh, RW
REG[0Ah] VERTICAL NON-DISPLAY PERIOD REGISTER IO address = FFEAh, RW
Vert NonDisp Status
SwivelView
Mode Sel.
0
Bit 0
REG[09h] FPFRAME START POSITION IO address = FFE9h, RW
n/a
Mono Single 8-bit LCD
0
Bit-Per-Pixel
Bit 0
REG[02] bit 6
0
Bit 0
REG[08h] HORIZONTAL NON-DISPLAY PERIOD IO address = FFE8h, RW
n/a
Bit-Per-Pixel
Bit 1
REG[02] bit 7
Bit 0
REG[1Bh] SWIVELVIEW MODE REGISTER IO address = FFFBh, RW
n/a
Mono Single 4-bit LCD
1
5 High Performance Selection
High Performance
Scratch Pad Register
FPLine Start Position = 8(REG[07h] + 2)
Bit 4
don’t care
0
Bit 8
REG[07h] FPLINE START POSITION IO address = FFE7h, RW
n/a
1
GPIO0 Pin
IO Config
Bit 0
REG[06h] VERTICAL PANEL SIZE REGISTER (MSB) IO address = FFE6h, RW
n/a
1
REG[18h] GPIO CONFIGURATION CONTROL REGISTER IO address = FFF8h, RW
Vertical Panel Size = (REG[05h], REG[06h]) + 1
Bit 6
n/a
Bit 0
REG[05h] VERTICAL PANEL SIZE REGISTER (LSB) IO address = FFE5h, RW
Bit 7
n/a
1
Function
Bit-Per-Pixel Bit 0
REG[02] bit 6
Display Mode
7 Look-Up Table Access
0
2 Colors
1 Bit-Per-Pixel
1
4 Colors
2 Bit-Per-Pixel
0
16 Colors
4 Bit-Per-Pixel
0
X
X
Green/Gray Look-Up Table
1
256 Colors
8 Bit-Per-Pixel
1
0
0
Auto-Increment
0
2 Gray Shade
1 Bit-Per-Pixel
1
0
1
Red Look-Up Table
R[n], R[n+1], R[n+2]...
1
4 Gray Shade
2 Bit-Per-Pixel
1
1
0
Green/Gray Look-Up Table
G[n], G[n+1], G[n+2]...
0
16 Gray Shade
4 Bit-Per-Pixel
1
1
1
Blue Look-Up Table
B[n], B[n+1], B[n+2]...
1
Color/Mono
REG[01h]
bit 5
REG[15h]
Look-Up Table Selected
bit 5
Pointer Sequence
bit 4
G[n], G[n+1], G[n+2]...
R[n], G[n], B[n] R[n+1], G[n+1],...
reserved
Bit 8
REG[0Fh] SCREEN 2 START WORD ADDRESS REGISTER (LSB) IO address = FFEFh, RW
Screen 2 Start Word Address = (REG[0F], REG[10h])
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[10h] SCREEN 2 START W ORD ADDRESS REGISTER (MSB) IO address = FFF0h, RW
Screen 2 Start Word Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 1
Bit 0
REG[12h] M EMORY ADDRESS OFFSET REGISTER IO address = FFF2h, RW
Memory Address Offset
Bit 7
Page 1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
99/04/23
SED1374 Register Summary
Page 2
X26A-R-001-02
99/04/23
SED1374 Embedded Memory Color LCD Controller
1374CFG.EXE Configuration Program
Document No. X26A-B-001-01
Copyright © 1998 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-B-001-01
1374CFG.EXE Configuration Program
Issue Date: 98/10/27
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Program Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Installation . . . . .
Usage . . . . . . .
1374CFG . . . . . .
Panel Information . .
Miscellaneous Options
System . . . . . . .
LUT Control . . . .
Open . . . . . . .
Save . . . . . . . .
Help . . . . . . . .
Exit . . . . . . . .
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.6
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10
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15
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Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
1374CFG Window. . . . . . .
Panel Information . . . . . . .
Miscellaneous Options. . . . .
System Options . . . . . . . .
ERROR: Frame Rate . . . . .
ERROR: Zero Frame Rate. . .
LUT Control . . . . . . . . . .
1374CFG File Open Dialog . .
ERROR: Unable to read HAL .
1374CFG Save As Dialog . . .
ERROR: Unable to read HAL .
1374CFG.EXE Configuration Program
Issue Date: 98/10/27
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. 7
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SED1374
X26A-B-001-01
Page 4
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-B-001-01
1374CFG.EXE Configuration Program
Issue Date: 98/10/27
Epson Research and Development
Vancouver Design Center
Page 5
Introduction
1374CFG is a Win 32 program which gives developers an easy means to modify panel
types, clock rates, color depths, etc. for SED1374 demonstration programs.
1374CFG can:
• Read programs, based on the 1374 Hardware Abstraction Layer (HAL), modify the
settings and write the changes back to the file. The ability to read, modify and write
bypasses having to recompile after every change.
• Write C header files containing register settings which can be used to initialize the 1374
registers in programs which do not use the HAL.
1374CFG.EXE Configuration Program
Issue Date: 98/10/27
SED1374
X26A-B-001-01
Page 6
Epson Research and Development
Vancouver Design Center
Program Requirements
This program is designed to run under Windows 95/98 or Windows NT 4.0
Installation
There is no installation program for 1374CFG. Installation to a local drive is done by
copying 1374CFG.EXE and 1374CFG.HLP to your hard drive and optionally creating a
link on the Windows desktop for easy access to the program.
Usage
Open the drive and folder where you copied 1374CFG.EXE and double click the icon to
start the program. Optionally, if you created a link to the program on your desktop, double
click the link icon.
SED1374
X26A-B-001-01
1374CFG.EXE Configuration Program
Issue Date: 98/10/27
Epson Research and Development
Vancouver Design Center
Page 7
1374CFG
The 1374CFG window has four main sections: Panel information (includes Dimensions),
LookUp Table, Miscellaneous Options, and System settings.
Figure 1: 1374CFG Window
The following sections describe each of the main sections of the configuration dialog box.
1374CFG.EXE Configuration Program
Issue Date: 98/10/27
SED1374
X26A-B-001-01
Page 8
Epson Research and Development
Vancouver Design Center
Panel Information
Figure 2: Panel Information
This section of the 1374CFG dialog describes the panel connected to the SED1374. Each
of the settings are described briefly below.
• Mono / Color – select mono for monochrome panels or color for color panels.
This option is STN specific and is disabled if TFT is selected.
• Single / Dual – select single when connected to a single panel or dual for connection to
a dual panel.
This option is STN specific and is disabled if TFT is selected.
• STN / TFT – select STN for passive panels or TFT for active panels. Switching
between these two panel types causes visible changes to take place to the configuration
dialog box.
• 4 Bit / 8 Bit – here the panel data width is selected. When STN panel types are selected
the options are 4-bit and 8-bit. When TFT panels are selected the options will be 9-bit
and 12-bit.
• Dimensions – in the left selection box horizontal pixels can be chosen from the list or
typed in; in the right selection box, vertical lines, in pixels, can be selected from the list
or typed in.
• Mask FPSHIFT – when selected the panel clocking signal FPSHIFT is masked off.
This option is required for most newer monochrome panels. When color panel type is
selected this option is disabled.
This option is STN specific and is disabled if TFT is selected.
SED1374
X26A-B-001-01
1374CFG.EXE Configuration Program
Issue Date: 98/10/27
Epson Research and Development
Vancouver Design Center
Page 9
• Format 2 – There are two data clocking formats in use by 8-bit color panels. The original clocking scheme was designated to be format 1 and the newer scheme was designated format 2. Select this option for most 8 bit color panels. To date all color panels
smaller than 640x480 have been found to be format 2.
Setting this attribute incorrectly will result in a garbled display but will not damage the
panel. The display may appear “cut in half” or possibly horizontally skewed.
This option is STN specific and is disabled if TFT is selected. It is also disabled if the
panel type is selected to be 4-bit or monochrome.
• Frame Repeat – is a feature for EL panel support. EL panels use a frame of repeated
data as the cue to change their polarization. Without this change in polarization panel
quality deteriorates.
When Frame Repeat is selected an internal counter causes the periodic repeat of one
frame of modulated panel. At a frame rate of 72 Hz the repeat period is roughly one
hour. When not selected the modulated image is never consecutively repeated.
This option is STN specific and is disabled if TFT is selected.
• MOD Count – the mod count value specifies the number of FPLINEs between toggles
of the MOD output signal. When set to “0” (default) the MOD output signal toggles
every FPFRAME.
This field is for passive panels only and is generally only required for older monochrome panels.
• FPLINE Start – this field specifies the delay, in an 8 pixel resolution, from the end of a
line of display data (FPDAT) to the leading edge of FPLINE.
This field is a TFT specific setting and is disabled if an STN panel is chosen.
• FPFRAME Start - this field specifies the number of lines between the last line of
display data (FPDAT) and the leading edge of FPFRAME.
This field is a TFT specific setting and is disabled if an STN panel is chosen.
• FPLINE / FPFRAME Polarity - these settings control the sync pulse direction of the
FPLINE and FPFRAME pulses in TFT modes.
Select the appropriate pulse direction for the panel being connected. Selecting 'Lo'
results in an active low sync pulse while 'Hi' results in an active high pulse.
These settings are TFT specific and are disabled when STN panel is selected. When
STN panel type is selected the pulse directions are preset to +ve, +ve.
1374CFG.EXE Configuration Program
Issue Date: 98/10/27
SED1374
X26A-B-001-01
Page 10
Epson Research and Development
Vancouver Design Center
Miscellaneous Options
Figure 3: Miscellaneous Options
Miscellaneous options are several items which do not fit into any other category.
• HW Video Invert Enable - the SED1374 supports inverted color output. The color
inversion can be toggled by software or in response to a signal applied to pin FPDAT11.
In order for the hardware color inversion to succeed this option must be selected.
- The color inversion is performed on the output from the LUT.
- HW Video Invert is not availlable for TFT operation.
• HW Power Save Enable - the SED1374 supports two power save modes. One is initiated by software, the second in response to input on the GPIO0 pin. In order for the
hardware power save mode to function this option must be selected.
• High Performance - improves chip throughput at the expense of power consumption.
When not selected the internal MCLK signal is divided down version of the internal
PCLK signal. Table 1 depicts the ratios when high performance is not selected. The
slower MCLKs result in lower power use.
Table 1: MCLK to PCLK ratios
Color Depth (bpp)
Ratio
1
MCLK = PCLK / 8
2
MCLK = PCLK / 4
4
MCLK = PCLK / 2
8
MCLK = PCLK
When this option is selected MCLK == PCLCK at all pixel depths. Running MCLK at
higher frequencies results in greater power use.
SED1374
X26A-B-001-01
1374CFG.EXE Configuration Program
Issue Date: 98/10/27
Epson Research and Development
Vancouver Design Center
Page 11
• Portrait Mode - selecting Portrait Mode causes register settings and timings to be saved
for portrait mode operation.
The HAL is capable of performing rotations “on the fly”. Most programs written for the
HAL will ignore this setting and set Portrait or Landscape display modes as desired.
This setting is useful when the configuration is saved into a C header file to be used by
non-HAL programs.
System
The options in the System section describe the items which are required for frame rate
calculations and where in CPU address space the SED1374 will be located.
Figure 4: System Options
• Memory Location - this describes where in CPU address space the SED1374 will be
located. This setting is required by the HAL to locate the SED1374. If the settings from
1374CFG will be saved to a C header file for use in a non-HAL program this value does
not have to be filled in.
• Frame Rate - indicate the desired frame rate here. 1374CFG will attempt to write
register settings which result in the requested frame rate. If the frame rate cannot be
reached then the following dialog inform the user of the problem
Figure 5: ERROR: Frame Rate
1374CFG.EXE Configuration Program
Issue Date: 98/10/27
SED1374
X26A-B-001-01
Page 12
Epson Research and Development
Vancouver Design Center
A Frame rate must be entered in order for 1374CFG to complete the frame rate calculations. If no frame rate is entered or the frame rate is set to 0 then the following dialog box
will inform the user when they try to save the configuration.
Figure 6: ERROR: Zero Frame Rate
• Input Clock - this field specifies the clock rate being applied to the SED1374 in kHz.
LUT Control
The items in this section control the color depth for the SED1374 after initialization.
Figure 7: LUT Control
The color depth selections in this section will become enabled or disabled in response to
the panel dimensions entered. (i.e. there is only enough memory to operate a 640x480 panel
at 1 bit per pixel so the selections for 2 BPP, 4 BPP and 8 BPP would be disabled if this size
pane was selected)
• 1 BPP – sets the color depth to 1 bit per pixel.
• 2 BPP – sets the color depth to 2 bit per pixel.
• 4 BPP – sets the color depth to 4 bit per pixel.
• 8 BPP – sets the color depth to 8 bit per pixel.
SED1374
X26A-B-001-01
1374CFG.EXE Configuration Program
Issue Date: 98/10/27
Epson Research and Development
Vancouver Design Center
Page 13
• Bypass LUT – when selected this option causes the lookup table to be bypassed.
Selecting to bypass the lookup table results in a power saving as the lookup table section
of the SED1374 is powered down when this option is selected.
This option is only applicable for monochrome displays. If a color panel is selected this
option is disabled.
When the lookup table is not enabled then display intensities are dependent on the
values in the lookup table. A smaller numerical value in display memory may be
displayed with a greater intensity than a larger value.
When the lookup table is bypassed the colors displayed on the panel are directly proportional to their memory value. (i.e. at 4 bit per pixel; 00h will display as black and 0Fh
will display as full intensity)
Open
Click on the Open button to read the settings saved in an executable program based on the
SED1374 hardware abstraction layer.
Clicking the Open button brings up the standard Windows file open dialog.
Figure 8: 1374CFG File Open Dialog
From here the user selects the file to be opened. 1374CFG is capable of opening executable
files based on the SED1374 HAL. Typically the file extension for these file are .EXE for
intel platform executables and .S9 for 68k and SH3 platform executables.
1374CFG.EXE Configuration Program
Issue Date: 98/10/27
SED1374
X26A-B-001-01
Page 14
Epson Research and Development
Vancouver Design Center
Opening a file reads that files HAL configuration information. Use the data read as a
starting point in configuring this or other files or to check on the current configuration.
If 1374CFG is unable locate the HAL information in the selected file the following dialog
box is displayed.
Figure 9: ERROR: Unable to read HAL
Save
Click on the Close button to save the current configuration settings. When clicked the
standard Windows file “Save As” dialog box is displayed.
Figure 10: 1374CFG Save As Dialog
From the save as dialog box first select the type of file to save to in the “Save as type:” edit
field. 1374CFG currently saves in three file formats.
• .EXE files - are binary images containing a HAL structure for execution on Intel platforms
• .S9 files - are ASCII binary format files used by several embedded systems. The .S9 file
is a variation of .S19 files.
• .H files - are ASCII C header files which can be included in other programs.
SED1374
X26A-B-001-01
1374CFG.EXE Configuration Program
Issue Date: 98/10/27
Epson Research and Development
Vancouver Design Center
Page 15
If an executable file (.EXE or .S9) is selected as the type of file to save to the file being
saved to must already exist and be an SED1374 HAL based program. 1374CFG is cannot
save to a non-existent program. If 1374CFG is unable to locate the HAL information in the
file being saved to the following dialog box is displayed.
Figure 11: ERROR: Unable to read HAL
Help
Clicking on the Help button will start the help file for SED1374CFG.
Exit
Clicking on the Exit button exits 1374CFG immediately. The user is not prompted to save
any changes they may have made.
1374CFG.EXE Configuration Program
Issue Date: 98/10/27
SED1374
X26A-B-001-01
Page 16
Epson Research and Development
Vancouver Design Center
Comments
It is assumed that the 1374CFG user is familiar with SED1374 hardware and software.
Refer to the SED1374 “Functional Hardware Specification,” drawing office number
X22A-A-001-xx, and the SED1374 “Programming Notes and Examples” manual, drawing
office number X22A-G-002-xx for information.
SED1374
X26A-B-001-01
1374CFG.EXE Configuration Program
Issue Date: 98/10/27
SED1374 Embedded Memory Color LCD Controller
1374SHOW Demonstration Program
Document No. X26A-B-002-01
Copyright © 1998 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-B-002-01
1374SHOW Demonstration Program
Issue Date: 98/10/20
Epson Research and Development
Vancouver Design Center
Page 3
1374SHOW
1374SHOW demonstrates SED1374 display capabilities by drawing a pattern image at
different pixel depths (1, 2, 4, and 8 bits-per-pixel) on the display.
1374SHOW must be configured to work with each different hardware platform. Consult
documentation for the program 1374CFG.EXE which can be used to configure
1374SHOW.
This software is designed to work in a variety of embedded and personal computer (PC)
environments. For embedded environments the model employed is that of host-target. It is
assumed that the system has a means of downloading software from the host to the target
platform. Typically this is done by a serial communication link. Alternative methods
include EPROM, parallel port connection or network connection. It is beyond the scope of
this document to provide support for target/host configurations.
SED1374 Supported Evaluation Platforms
1374SHOW has been tested with the following SED1374 supported evaluation platforms:
• PC system with an Intel 80x86 processor.
• M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332
processor.
• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola
M68EC000 processor.
• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.
If the platform you are using is different from the above, please see the SED1374
Programming Notes and Examples manual, document number X26A-G-002-xx.
Installation
PC platform: copy the file 1374SHOW.EXE to a directory that is in the DOS path on your
hard drive.
Embedded platform: download the program 1374SHOW to the system.
1374SHOW Demonstration Program
Issue Date: 98/10/20
SED1374
X26A-B-002-01
Page 4
Epson Research and Development
Vancouver Design Center
Usage
PC platform: at the prompt, type:
1374show [/a][b=n][/l][/p][/vertical][/noinit][/?]
Embedded platform: execute 1374show and at the prompt, type the command line
argument(s).
Where:
/a
automatically cycle through all video modes.
b=?
starts 1374SHOW at a user specified
bit-per-pixel (bpp) level, where ? can be:
1, 2, 4, 8.
/l
set landscape mode.
/p
set portrait mode.
/vertical
displays vertical line pattern.
/noinit
bypass register initialization and use
values which are currently in the registers.
/?
displays the help screen.
Program Messages
ERROR: Too many devices registered.
There are too many display devices attached to the HAL. The HAL currently can manage only one
device.
ERROR: Could not register 1374 device.
A 1374 device was not found at the configured addresses. Check the configuration address using the
1374CFG configuration program.
ERROR: Did not find a 1374 device.
The HAL was unable to read the revision code register on the SED1374. Ensure that the SED1374
hardware is installed and that the hardware platform has been set up correctly.
ERROR: Could not initialize device.
The HAL failed to initialize the registers.
SED1374
X26A-B-002-01
1374SHOW Demonstration Program
Issue Date: 98/10/20
SED1374 Embedded Memory Color LCD Controller
1374SPLT Display Utility
Document No. X26A-B-003-01
Copyright © 1998 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-B-003-01
1374SPLT Display Utility
Issue Date: 98/10/20
Epson Research and Development
Vancouver Design Center
Page 3
1374SPLT
1374SPLT demonstrates SED1374 split screen capability by showing two different areas
of display memory on the screen simultaneously.
Screen 1 memory is located at the start of the display buffer and is filled with horizontal
bars. Screen 2 memory is located immediately after Screen 1 in the display buffer and is
filled with vertical bars. On either user input or elapsed time, the line compare register value
is changed to adjust the amount of display area taken up by each screen.
1374SPLT must be configured to work with each different hardware platform. Consult
documentation for the program 1374CFG.EXE which can be used to configure 1374SPLT.
This software is designed to work with a variety of embedded and personal computer (PC)
environments. For embedded environments the model employed is that of host-target. It is
assumed that the system has a means of downloading software from the host to the target
platform. Typically this is done by a serial communication link. Alternative methods
include EPROM, parallel port connection or network connection. It is beyond the scope of
this document to provide support for target/host configurations.
SED1374 Supported Evaluation Platforms
1374SPLT has been tested with the following SED1374 supported evaluation platforms:
• PC system with an Intel 80x86 processor.
• M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332
processor.
• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola
M68EC000 processor.
• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.
If the platform you are using is different from the above, please see the SED1374
Programming Notes and Examples manual, document number X26A-G-002-xx.
Installation
PC platform: Copy the file 1374SPLT.EXE to a directory that is in the DOS path on your
hard drive.
Embedded platform: Download the program 1374SPLT to the system.
1374SPLT Display Utility
Issue Date: 98/10/20
SED1374
X26A-B-003-01
Page 4
Epson Research and Development
Vancouver Design Center
Usage
PC platform: at the prompt, type 1374SPLT [/a] [/l] [/p] [/?]
Embedded platform: execute 1374splt and at the prompt, type the command line
argument.
Where:
no argument enables manual split screen operation
/a
enables automatic split screen operation
(a timer is used to move screen 2)
/?
display the help screen
After starting 1374SPLT the following keyboard commands are available.
Manual mode:
↑, u
move Screen 2 up
↓, d
move Screen 2 down
HOME
covers Screen 1 with Screen 2
END
displays only Screen 1
Automatic mode: any key
change the direction of split screen movement
(for PC only)
Both modes:
b
changes the color depth (bits-per-pixel)
ESC
exits 1374SPLT
1374SPLT Example
1. Type “1374splt /a” to automatically move the split screen.
2. Press “b” to change the color depth from 1 bit-per-pixel to 2 bit-per-pixel.
3. Repeat step 2 for the remaining color depths (4 and 8 bit-per-pixel).
4. Press <ESC> to exit the program.
SED1374
X26A-B-003-01
1374SPLT Display Utility
Issue Date: 98/10/20
Epson Research and Development
Vancouver Design Center
Page 5
Program Messages
ERROR: Too many devices registered.
There are too many display devices attached to the HAL. The HAL currently can manage only one
device.
ERROR: Could not register 1374 device.
A 1374 device was not found at the configured addresses. Check the configuration address using the
1374CFG configuration program.
ERROR: Did not detect 1374.
The HAL was unable to read the revision code register on the SED1374. Ensure that the SED1374
hardware is installed and that the hardware platform has been set up correctly.
1374SPLT Display Utility
Issue Date: 98/10/20
SED1374
X26A-B-003-01
Page 6
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Vancouver Design Center
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SED1374
X26A-B-003-01
1374SPLT Display Utility
Issue Date: 98/10/20
SED1374 Embedded Memory Color LCD Controller
1374VIRT Display Utility
Document No. X26A-B-004-01
Copyright © 1998 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-B-004-01
1374VIRT Display Utility
Issue Date: 98/10/20
Epson Research and Development
Vancouver Design Center
Page 3
1374VIRT
1374VIRT demonstrates the virtual display capability of the SED1374. A virtual display is
where the image to be displayed is larger than the physical display device. The display
surface is used a viewing window. The entire image can be seen only by panning and
scrolling.
1374VIRT must be configured to work with each different hardware platform. Consult
documentation for the program 1374CFG.EXE which can be used to configure 1374VIRT.
This software is designed to work with a variety of embedded and personal computer (PC)
environments. For embedded environments the model employed is that of host/target. It is
assumed that the system has a means of downloading software from the host to the target
platform. Typically this is done by a serial communication link. Alternative methods
include EPROM, parallel port connection or network connection. It is beyond the scope of
this document to provide support for target/host configurations.
SED1374 Supported Evaluation Platforms
1374VIRT has been tested with the following SED1374 supported evaluation platforms:
• PC system with an Intel 80x86 processor.
• M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332
processor.
• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola
M68EC000 processor.
• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.
If the platform you are using is different from the above, please see the SED1374
Programming Notes and Examples manual, document number X26A-G-002-xx.
Installation
PC platform: copy the file 1374VIRT.EXE to a directory that is in the DOS path on your
hard drive.
Embedded platform: download the program 1374VIRT to the system.
1374VIRT Display Utility
Issue Date: 98/10/20
SED1374
X26A-B-004-01
Page 4
Epson Research and Development
Vancouver Design Center
Usage
PC platform: at the prompt, type 1374virt [/a] [/w=???].
Embedded platform: execute 1374virt and at the prompt, type the command line
argument.
Where:
no argument
panning and scrolling is performed manually
(defaults to virtual width = = physical width x 2
and maximum virtual height)
/a
panning and scrolling is performed automatically
/w=???
specifies the virtual display width which includes
both on-screen and off-screen size
the maximum virtual display width for each
display mode is:
1 bpp – 4096 pixels
2 bpp – 2048 pixels
4 bpp – 1024 pixels
8 bpp – 512 pixels
The following keyboard commands are for navigation within the program.
Manual mode:
SED1374
X26A-B-004-01
↑
scrolls up
↓
scrolls down
←
pans to the left
→
pans to the right
HOME
moves the display screen so that the upper right of
the virtual screen shows in the upper right of the
display
END
moves the display screen so that the lower left of
the virtual screen shows in the lower left of the
display
Automatic mode: any key
changes the direction of screen
Both modes:
b
changes the color depth (bits-per-pixel)
ESC
exits 1374VIRT
1374VIRT Display Utility
Issue Date: 98/10/20
Epson Research and Development
Vancouver Design Center
Page 5
1374VIRT Example
1. Type “1374virt /a” to automatically pan and scroll.
2. Press "b" to change the bits-per-pixel from 1 bit-per-pixel to 2 bits-per-pixel.
3. Repeat steps 1 and 2 for the remaining color depths (4 and 8 bit-per-pixel).
4. Press <ESC> to exit the program.
Program Messages
ERROR: Too many devices registered.
There are too many display devices attached to the HAL. The HAL currently can manage only one
device.
ERROR: Could not register 1374 device.
A 1374 device was not found at the configured addresses. Check the configuration address using the
1374CFG configuration program.
ERROR: Did not detect 1374.
The HAL was unable to read the revision code register on the SED1374. Ensure that the SED1374
hardware is installed and that the hardware platform has been set up correctly.
1374VIRT Display Utility
Issue Date: 98/10/20
SED1374
X26A-B-004-01
Page 6
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-B-004-01
1374VIRT Display Utility
Issue Date: 98/10/20
SED1374 Embedded Memory Color LCD Controller
1374PLAY Diagnostic Utility
Document No. X26A-B-005-02
Copyright © 1998 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-B-005-02
1374PLAY Diagnostic Utility
Issue Date: 99/11/29
Epson Research and Development
Vancouver Design Center
Page 3
1374PLAY
1374PLAY is a utility which allows the user to easily read/write the SED1374 registers,
Look-up Table and display memory.
The user interface for 1374PLAY is similar to the DOS DEBUG program; commands are
received from the standard input device, and output is sent to the standard output device
(console for Intel and terminal for embedded platforms). This utility requires the target
platform to support standard I/O.
1374PLAY commands can be entered interactively using a keyboard/monitor or they can
be executed from a script file. Scripting is a powerful feature which allows command
sequences played back from a file thus avoiding having to retype lengthy sequences.
1374PLAY must be configured to work with each different hardware platform. Consult
documentation for the program 1374CFG.EXE which can be used to configure 1374PLAY.
This software is designed to work with a variety of embedded and personal computer (PC)
environments. For embedded environments the model employed is that of host.target. It is
assumed that the system has a means of downloading software from the host to the target
platform. Typically this is done by a serial communication link. Alternative methods
include EPROM, parallel port connection or network connection. It is beyond the scope of
this document to provide support for target/host configurations.
SED1374 Supported Evaluation Platforms
1374PLAY has been tested with the following SED1374 supported evaluation platforms:
• PC system with an Intel 80x86 processor.
• M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332
processor.
• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola
M68EC000 processor.
• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.
If the platform you are using is different from the above, please see the SED1374
Programming Notes and Examples manual, document number X26A-G-002-xx.
1374PLAY Diagnostic Utility
Issue Date: 99/11/29
SED1374
X26A-B-005-02
Page 4
Epson Research and Development
Vancouver Design Center
Installation
PC platform: copy the file 1374PLAY.EXE to a directory that is in the DOS path on your
hard drive.
Embedded platform: download the program 1374PLAY to the system.
Usage
PC platform: at the prompt, type 1374play [/?].
Embedded platform: execute 1374play and at the prompt, type the command line
argument.
Where: /? displays program revision information.
The following commands are valid within the 1374PLAY program.
X index [data]
Reads/writes the registers.
Writes data to the register specified by the index
when “data” is specified; otherwise the register is
read.
SED1374
X26A-B-005-02
XA
Reads all registers.
L index [data1 data2 data3]
Reads/writes Look-Up Table (LUT) values.
Writes data to the LUT index when “data” is
specified; otherwise the LUT index is read.
Data must consist of 3 bytes: 1 red, 1 green, 1
blue. and range in value from 0x00 to 0x0F.
LA
Reads all LUT values.
F[W] addr1 addr2 data . . .
Fills bytes or words from address 1 to address 2
with data. Data can be multiple values
(e.g. F 0 20 1 2 3 4 fills address 0 to 0x20
with a repeating pattern of 1 2 3 4).
R[W] addr [count]
Reads “count” of bytes or words from the address
specified by “addr”. If “count” is not specified,
then 16 bytes/words are read.
W[W] addr data . . .
Writes bytes or words of data to address specified
by “addr”. Data can be multiple values
e.g. W 0 1 2 3 4 writes the byte values
1 2 3 4 starting at address 0).
I
Initializes the chip with user specified
configuration.
1374PLAY Diagnostic Utility
Issue Date: 99/11/29
Epson Research and Development
Vancouver Design Center
Page 5
M [bpp]
Returns information about the current mode.
If “bpp” is specified then set the requested
color depth.
P 0|1|2
Sets software power save mode 0-2.
Power save mode 0 is normal operation.
H [lines]
Halts after specified lines of display.
This feature halts the display during long
read operations to prevent
data from scrolling off the display.
Set 0 to disable.
Q
Quits this utility.
?
Displays Help information.
1374PLAY Example
1. Type “1374PLAY” to start the program.
2. Type "?" for help.
3. Type "i" to initialize the registers.
4. Type "xa" to display the contents of the registers.
5. Type "x 5" to read register 5.
6. Type "x 3 10" to write 10 hex to register 3.
7. Type "f 0 400 aa" to fill the first 400 hex bytes of display memory with AA hex.
8. Type "f 0 a000 aa" to fill 40k bytes of display memory.
9. Type "r 0 ff" to read the first 100 hex bytes of display memory.
10. Type "q" to exit the program.
1374PLAY Diagnostic Utility
Issue Date: 99/11/29
SED1374
X26A-B-005-02
Page 6
Epson Research and Development
Vancouver Design Center
Scripting
1374PLAY can be driven by a script file. This is useful when:
• there is no standard display output to monitor command entry and results.
• various registers must be quickly changed faster than can achieved by typing.
• The same series of keystrokes is being entered time and again.
A script file is an ASCII text file with one 1374PLAY command per line. All scripts must
end with a “q” (quit) command in order to return control to the operating system. The semicolon is used as a comment delimitor. Everything on a line after the semi-colon will be
ignored.
On a PC platform, a typical script command line is: “1374PLAY < dumpregs.scr > results”.
This causes the script file “dumpregs.scr” to be interpreted and the results to be sent to the
file “results.”
Example 1: The script file “dumpregs.scr” can be created with and text editor and will look
like the following:
; This file initializes the SED1374 and reads the registers
i
; Initialize the registers.
xa
; Dump all the registers
la
; And the LUT
q
; Exit
Comments
• All numeric values are considered to be hexadecimal unless identified otherwise. For
example, 10 = 10h = 16 decimal; 10t = 10 decimal; 010b = 2 decimal.
• Redirecting commands from a script file (PC platform) allows those commands to be
executed as though they were typed.
SED1374
X26A-B-005-02
1374PLAY Diagnostic Utility
Issue Date: 99/11/29
Epson Research and Development
Vancouver Design Center
Page 7
Program Messages
ERROR: Too many devices registered.
There are too many display devices attached to the HAL. The HAL currently can manage only one
device.
ERROR: Could not register 1374 device.
A 1374 device was not found at the configured addresses. Check the configuration address using the
1374CFG configuration program.
WARNING: Did not detect 1374.
The HAL did not detect an SED1374, however 1374PLAY will continue to function.
1374PLAY Diagnostic Utility
Issue Date: 99/11/29
SED1374
X26A-B-005-02
Page 8
Epson Research and Development
Vancouver Design Center
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SED1374
X26A-B-005-02
1374PLAY Diagnostic Utility
Issue Date: 99/11/29
SED1374 Embedded Memory Color LCD Controller
1374BMP Demonstration Program
Document No. X26A-B-006-01
Copyright © 1998 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-B-006-01
1374BMP Demonstration Program
Issue Date: 98/10/20
Epson Research and Development
Vancouver Design Center
Page 3
1374BMP
1374BMP demonstrates SED1374 display capabilities by rendering bitmap images on the
display.
The 1374BMP display utility is designed to operate in a personal computer DOS
environment and must be configured to work with your display hardware. Consult
documentation for the program 1374CFG.EXE which can be used to configure 1374BMP.
1374BMP is not supported on non-PC platforms.
Installation
Copy the file 1374BMP.EXE to a directory that is in the DOS path on your hard drive.
Usage
At the prompt, type:
1374bmp bmp_file [/a[time]] [/l] [/p] [/?].
Where:
bmp_file
the name of the file to display
/a[time]
automatic mode returns to the operating system after “time” seconds.
If time is not specified the default is 5 seconds. This option is intended
for use with batch files to automate displaying a series of images.
/l
override default configuration settings and set landscape display mode.
/p
override default configuration settings and set portrait display mode.
/?
displays the Help screen
Comments
• 1374BMP currently views only Windows BMP format images.
1374BMP Demonstration Program
Issue Date: 98/10/20
SED1374
X26A-B-006-01
Page 4
Epson Research and Development
Vancouver Design Center
Program Messages
ERROR: Too many devices registered.
There are too many display devices attached to the HAL. The HAL currently can manage only one
device.
ERROR: Could not register 1374 device.
A 1374 device was not found at the configured addresses. Check the configuration address using the
1374CFG configuration program.
ERROR: Did not detect 1374.
The HAL was unable to read the revision code register on the SED1374. Ensure that the SED1374
hardware is installed and that the hardware platform has been set up correctly.
SED1374
X26A-B-006-01
1374BMP Demonstration Program
Issue Date: 98/10/20
SED1374 Embedded Memory Color LCD Controller
1374PWR Power Save Utility
Document Number: X26A-B-007-01
Copyright © 1998 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-B-007-01
1374PWR Power Save Utility
Issue Date: 98/10/27
Epson Research and Development
Vancouver Design Center
Page 3
1374PWR
The 1374PWR Power Save Utility is a tool to assist in the testing of the software and
hardware power save modes.
Refer to the section titled “Power Save Modes” in the SED1374 Programming Notes and
Examples manual, document number X26A-G-002-xx, and the SED1374 Functional
Hardware Specification, document number X26A-A-001-xx for further information.
The 1374PWR utility must be configured and/or compiled to work with your hardware
platform. Consult documentation for the program 1374CFG.EXE which can be used to
configure 1374PWR.
This software is designed to work in both embedded and personal computer (PC) environments. For the embedded environment, it is assumed that the system has a means of
downloading software from the PC to the target platform. Typically this is done by serial
communications, where the PC uses a terminal program to send control commands and
information to the target processor. Alternatively, the PC can program an EPROM, which
is then placed in the target platform. Some target platforms can also communicate with the
PC via a parallel port connection, or an Ethernet connection.
SED1374 Supported Evaluation Platforms
1374PWR has been designed to work with the following SED1374 supported evaluation
platforms:
• PC system with an Intel 80x86 processor.
• M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332
processor.
• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola
M68EC000 processor.
• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.
If the platform you are using is different from the above, please see the SED1374
“Programming Notes and Examples” manual, document number X26A-G-002-xx.
Installation
PC platform: copy the file 1374PWR.EXE to a directory that is in the DOS path on your
hard drive.
Embedded platform: download the program 1374PWR to the system.
1374PWR Power Save Utility
Issue Date: 98/10/27
SED1374
X26A-B-007-01
Page 4
Epson Research and Development
Vancouver Design Center
Usage
PC platform: at the prompt, type 1374pwr [s0] [s1] [h0] [h1].
Embedded platform: execute 1374pwr and at the prompt, type the command line
argument.
Where:
s0
resets software power save mode
s1
sets software power save mode
h0
resets (disables) hardware power save mode (REG[03h] bit 2)
h1
sets (enables) hardware power save mode (REG[03h] bit 2)
/?
displays this usage message
Program Messages
ERROR: Unknown command line argument.
An invalid command line argument was entered. Enter a valid command line argument.
ERROR: Too many devices registered.
There are too many display devices attached to the HAL. The HAL currently can manage only one
device.
ERROR: Could not register 1374 device.
A 1374 device was not found at the configured addresses. Check the configuration address using the
1374CFG configuration program.
ERROR: Did not detect 1374.
The HAL was unable to read the revision code register on the SED1374. Ensure that the SED1374
hardware is installed and that the hardware platform has been set up correctly.
SED1374
X26A-B-007-01
1374PWR Power Save Utility
Issue Date: 98/10/27
SED1374 Embedded Memory Color LCD Controller
Windows® CE Display Drivers
Document Number: X26A-E-001-01
Copyright © 1998 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows is a registered trademark of Microsoft Corporation. All
other Trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-E-001-01
Windows® CE Display Drivers
Issue Date: 98/11/11
Epson Research and Development
Vancouver Design Center
Page 3
1 WINDOWS® CE DISPLAY DRIVERS
The Windows CE display drivers are designed to support the SED1374 Embedded Memory
LCD Controller running under the Microsoft Windows CE operating system. Available
drivers include: 4 bit-per-pixel landscape mode, and 4 bit-per-pixel portrait mode.
For updated source code, visit Epson Research and Development on the World Wide Web
at www.erd.epson.com, or contact your Seiko Epson sales representative.
1.1 Program Requirements
Video Controller
: SED1374
Display Type
: LCD
Windows Version
: CE Version 2.0/2.1
1.2 Example Driver Build
Build For CEPC (X86) Version 2.0/2.1
To build a Windows CE v2.0/2.1 display driver for the CEPC (X86) platform using a
SDU1374B0C evaluation board, follow the instructions below:
1. Install Microsoft Windows NT v4.0.
2. Install Microsoft Visual C/C++ v5.0.
3. Install the Microsoft Windows CE Embedded Toolkit (ETK) by running SETUP.EXE
from the ETK compact disc #1.
4. Create a new project by following the procedure documented in “Creating a New
Project Directory” from the Windows CE ETK. Alternately, use the current
“DEMO7” project included with the ETK. Follow the steps below to create a “X86
DEMO7” shortcut on the Windows NT v4.0 desktop which uses the current
“DEMO7” project:
a. Right click on the “Start” menu on the taskbar.
b. Click on the item “Open All Users” and the “Start Menu” window will come up.
c. Click on the icon “Programs”.
d. Click on the icon “Windows CE Embedded Development Kit”.
e. Drag the icon “X86 DEMO1” onto the desktop using the right mouse button.
f.
Click on “Copy Here”.
g. Rename the icon “X86 DEMO1” on the desktop to “X86 DEMO7” by right clicking on the icon and choosing “rename”.
Windows® CE Display Drivers
Issue Date: 98/11/11
SED1374
X26A-E-001-01
Page 4
Epson Research and Development
Vancouver Design Center
h. Right click on the icon “X86 DEMO7” and click on “Properties” to bring up the
“X86 DEMO7 Properties” window.
i.
Replace the string “DEMO1” under the entry “Target” with “DEMO7”.
j.
Click on “OK” to finish.
1. Create a sub-directory named 4BPP1374 under \wince\platform\cepc\drivers\display.
2. Copy the source code to the 4BPP1374 subdirectory.
3. Add an entry for the 4BPP1374 in the file \wince\platform\cepc\drivers\display\dirs.
4. Modify the file CONFIG.BIB (using any text editor such as NOTEPAD) to set the
system RAM size, the SED1374 IO port and display buffer address mapping. Note
that CONFIG.BIB is located in X:\wince\platform\cepc\files (where X: is the drive
letter). Since the SDU1374B0C maps the 64K byte region from D0000h to DFFFFh,
make sure no other devices occupy this area. The following lines should be in CONFIG.BIB:
NK 80200000 00500000 RAMIMGE
RAM 80700000 00500000 RAM
Note
DISPDRVR.C should include the following:
#define PhysicalPortAddr 0x000DF000L
#define PhysicalVmemAddr 0x000D0000L
5. Edit the file PLATFORM.BIB (located in X:\wince\platform\cepc\files) to set the default display driver to the file 4BPP1374.DLL. 4BPP1374.DLL will be created during
the build in step 13.
You may replace the following lines in PLATFORM.BIB:
IF CEPC_DDI_VGA2BPP
ddi.dll
$(_FLATRELEASEDIR)\ddi_vga2.dll
ENDIF
IF CEPC_DDI_VGA8BPP
ddi.dll
$(_FLATRELEASEDIR)\ddi_vga8.dll
ENDIF
IF CEPC_DDI_VGA2BPP !
IF CEPC_DDI_VGA8BPP !
ddi.dll
$(_FLATRELEASEDIR)\ddi_s364.dll
ENDIF
ENDIF
NK SH
NK SH
NK SH
with this line:
ddi.dll
SED1374
X26A-E-001-01
$(_FLATRELEASEDIR)\4BPP1374.dll
NK SH
Windows® CE Display Drivers
Issue Date: 98/11/11
Epson Research and Development
Vancouver Design Center
Page 5
6. Edit the file DISPDRVR.C (located in X:\wince\platform\odo\drivers\display\
4BPP1374) to set the desired screen resolution, color depth (bpp) and panel type. The
sample code defaults to a 320x240 color single passive 4-bit LCD panel. To support
one of the other listed panels, change the #define statement.
7. Generate the proper building environment by double-clicking on the sample project
icon (i.e. X86 DEMO7).
8. Type BLDDEMO <ENTER> at the DOS prompt of the X86 DEMO7 window to generate a Windows CE image file (NK.BIN).
1.3 Example Installation
Installation for CEPC Environment
Windows CE v2.0 can be loaded on a PC using a floppy drive or a hard drive. The two
methods are described below:
To load CEPC from a floppy drive:
1. Create a DOS bootable floppy disk.
2. Edit CONFIG.SYS on the floppy disk to contain the following line only.
device=a:\himem.sys
3. Edit AUTOEXEC.BAT on the floppy disk to contain the following lines.
mode com1:9600,n,8,1
loadcepc /B:9600 /C:1 c:\wince\release\nk.bin
4. Copy LOADCEPC.EXE from c:\wince\public\common\oak\bin to the bootable
floppy disk.
5. Confirm that NK.BIN is located in c:\wince\release.
6. Reboot the system from the bootable floppy disk.
To load CEPC from a hard drive:
1. Copy LOADCEPC.EXE to the root directory of the hard drive.
2. Edit CONFIG.SYS on the hard drive to contain the following line only.
device=c:\himem.sys
3. Edit AUTOEXEC.BAT on the hard drive to contain the following lines.
mode com1:9600,n,8,1
loadcepc /B:9600 /C:1 c:\wince\release\nk.bin
4. Confirm that NK.BIN is located in c:\wince\release.
5. Reboot the system from the hard drive.
Windows® CE Display Drivers
Issue Date: 98/11/11
SED1374
X26A-E-001-01
Page 6
Epson Research and Development
Vancouver Design Center
1.4 Comments
• At the time of this printing, the drivers have been tested on the x86 CPUs and have only
been run with version 2.0 of the ETK. We are constantly updating the drivers so please
check our website at www.erd.epson.com, or contact your Seiko Epson or Epson
Electronics America sales representative.
SED1374
X26A-E-001-01
Windows® CE Display Drivers
Issue Date: 98/11/11
SED1374 Embedded Memory Color LCD Controller
SDU1374B0C Rev. 1.0 ISA Bus
Evaluation Board User Manual
Document Number: X26A-G-005-01
Copyright © 1998 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
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Vancouver Design Center
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SED1374
X26A-G-005-01
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
LCD Interface Pin Mapping
4
CPU/Bus Interface Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . 11
5
Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
Technical Description . . . . . . . . . . . . . . .
6.1 ISA Bus Support . . . . . . . . . . . . . .
6.1.1 Display Adapter Card Support . . . . . . . .
6.1.2 Expanded Memory Manager . . . . . . . . .
6.2 Non-ISA Bus Support . . . . . . . . . . . .
6.3 Embedded Memory Support . . . . . . . . . .
6.4 Decode Logic . . . . . . . . . . . . . . .
6.5 Clock Input Support . . . . . . . . . . . . .
6.6 LCD Panel Voltage Setting . . . . . . . . . .
6.7 Monochrome LCD Panel Support . . . . . . . .
6.8 Color Passive LCD Panel Support . . . . . . .
6.9 Color TFT/D-TFD LCD Panel Support . . . . .
6.10 Power Save Modes . . . . . . . . . . . . .
6.11 Adjustable LCD Panel Negative Power Supply . .
6.12 Adjustable LCD Panel Positive Power Supply . . .
6.13 CPU/Bus Interface Header Strips . . . . . . . .
7
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8
Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
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SED1374
X26A-G-005-01
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Vancouver Design Center
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SED1374
X26A-G-005-01
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
Epson Research and Development
Vancouver Design Center
Page 5
List of Tables
Table 2-1:
Table 2-2:
Table 2-3:
Table 3-1:
Table 4-1:
Table 4-2:
Table 5-1:
Configuration DIP Switch Settings
Host Bus Selection . . . . . . . . .
Jumper Settings . . . . . . . . . .
LCD Signal Connector (J5) Pinout
CPU/BUS Connector (H1) Pinout .
CPU/BUS Connector (H2) Pinout .
Host Bus Interface Pin Mapping . .
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List of Figures
Figure 8-1:
Figure 8-2:
Figure 8-3:
Figure 8-4:
SED1374B0C Schematic Diagram (1 of 4)
SED1374B0C Schematic Diagram (2 of 4)
SED1374B0C Schematic Diagram (3 of 4)
SED1374B0C Schematic Diagram (4 of 4)
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
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SED1374
X26A-G-005-01
Page 6
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-G-005-01
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
Epson Research and Development
Vancouver Design Center
Page 7
1 Introduction
This manual describes the setup and operation of the SDU1374B0C Rev. 1.0 Evaluation
Board. Implemented using the SED1374 Embedded Memory Color LCD Controller, the
SDU1374B0C board is designed for the 16-bit ISA bus environment. To accommodate
other bus architectures, the SDU1374B0C board also provides CPU/Bus interface
connectors.
For more information regarding the SED1374, refer to the SED1374 Hardware Functional
Specification, document number X26A-A-001-xx.
1.1 Features
• 80-pin QFP14 package.
• SMT technology for all appropriate devices.
• 4/8-bit monochrome and color passive LCD panel support.
• 9/12-bit LCD TFT/D-TFD panel support.
• Selectable 3.3V or 5.0V LCD panel support.
• Oscillator support for CLKI (up to 50MHz with internal clock divide or 25MHz with no
internal clock divide).
• Embedded 40K byte SRAM display buffer for 1/2/4 bit-per-pixel (bpp), 2/4/16 level
gray shade display and 1/2/4/8 bpp, 2/4/16/256 level color display.
• Support for software and hardware power save modes.
• On-board adjustable LCD bias positive power supply (+23V to 40V).
• On-board adjustable LCD bias negative power supply (-14V to -24V).
• 16-bit ISA bus support.
• CPU/Bus interface header strips for non-ISA bus support.
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
SED1374
X26A-G-005-01
Page 8
Epson Research and Development
Vancouver Design Center
2 Installation and Configuration
The SED1374 has five configuration inputs, CNF[4:0], which are read on the rising edge
of RESET# and are fully configurable on this evaluation board. One six-position DIP
switch is provided on the board to configure these five configuration inputs and to
enable/disable hardware power save mode.
The following settings are recommended when using the SDU1374B0C with the ISA bus.
Table 2-1: Configuration DIP Switch Settings
Switch
Signal
Closed (0 or low)
Open (1 or high)
SW1-1
CNF0
SW1-2
CNF1
SW1-3
CNF2
SW1-4
CNF3
Little Endian
Big Endian
SW1-5
CNF4
Active low LCDPWR signal
Active high LCDPWR signal
SW1-6
GPIO0
Hardware Suspend Disable
Hardware Suspend Enable
See “Host Bus Selection” table below See “Host Bus Selection” table below
= recommended settings (configured for ISA bus support)
Table 2-2: Host Bus Selection
S1-3
S1-2
S1-1
BS#
Host Bus Interface
0
0
0
X
SH-4 bus interface
0
0
1
X
SH-3 bus interface
0
1
0
X
reserved
0
1
1
X
MC68K bus interface #1, 16-bit
1
0
0
X
reserved
1
0
1
X
MC68K bus interface #2, 16-bit
1
1
0
0
reserved
1
1
0
1
reserved
1
1
1
0
Generic #1, 16-bit
1
1
1
1
Generic #2, 16-bit
= recommended settings (configured for ISA bus support)
SED1374
X26A-G-005-01
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
Epson Research and Development
Vancouver Design Center
Page 9
Table 2-3: Jumper Settings
Description
1-2
2-3
JP1
IOVDD Selection
5.0V IOVDD
3.3V IOVDD
JP2
BS# Signal Selection
Pulled up to IOVDD
No Connection
JP3
RD/WR# Signal Selection
Pulled up to IOVDD
No Connection
JP4
LCD Panel Voltage Selection
5.0V LCD Panel
3.3V LCD Panel
= recommended settings (configured for ISA bus support)
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
SED1374
X26A-G-005-01
Page 10
Epson Research and Development
Vancouver Design Center
3 LCD Interface Pin Mapping
Table 3-1: LCD Signal Connector (J5) Pinout
Connector
Pin Name
BFPDAT0
BFPDAT1
BFPDAT2
BFPDAT3
BFPDAT4
BFPDAT5
BFPDAT6
BFPDAT7
BFPDAT8
BFPDAT9
BFPDAT10
BFPDAT11
BFPSHIFT
Pin #
4-bit
Single Passive Panel
Color
Mono
8-bit
8-bit
Alternate
4-bit
8-bit
Format
D0
D0
D0
D1
D1
D1
D2
D2
D2
D3
D3
D3
D4
D4
D0
D4
D5
D5
D1
D5
D6
D6
D2
D6
D7
D7
D3
D7
Dual Passive Panel
Color
Mono
8-bit
8-bit
Color TFT/D-TFD
9-bit
12-bit
1
LD0
LD0
R2
R3
3
LD1
LD1
R1
R2
5
LD2
LD2
R0
R1
7
LD3
LD3
G2
G3
9
D0
UD0
UD0
G1
G2
11
D1
UD1
UD1
G0
G1
13
D2
UD2
UD2
B2
B3
15
D3
UD3
UD3
B1
B2
17
B0
B1
19
R0
21
G0
23
B0
33
FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT
BFPSHIFT2
FPSHIFT2
35
BFPLINE
37
FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE
BFPFRAME
FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME
39
2-26
GND
(Even
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pins)
N/C
28
VLCD
30
LCD panel negative bias voltage (-18V to -23V)
LCDVCC
32
+3.3V or +5V (selectable with JP4)
+12V
34
+12V
+12V
+12V
+12V
+12V
+12V
+12V
+12V
+12V
VDDH
36
LCD panel positive bias voltage (+24V to +38V)
BDRDY
38
MOD
MOD
MOD
MOD
MOD
MOD
DRDY
DRDY
BLCDPWR
LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR
40
SED1374
X26A-G-005-01
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
Epson Research and Development
Vancouver Design Center
Page 11
4 CPU/Bus Interface Connector Pinouts
Table 4-1: CPU/BUS Connector (H1) Pinout
Connector
Pin No.
CPU/BUS
Pin Name
1
SD0
Connected to DB0 of the SED1374
2
SD1
Connected to DB1 of the SED1374
3
SD2
Connected to DB2 of the SED1374
4
SD3
Connected to DB3 of the SED1374
5
GND
Ground
6
GND
Ground
7
SD4
Connected to DB4 of the SED1374
8
SD5
Connected to DB5 of the SED1374
9
SD6
Connected to DB6 of the SED1374
Comments
10
SD7
Connected to DB7 of the SED1374
11
GND
Ground
12
GND
Ground
13
SD8
Connected to DB8 of the SED1374
14
SD9
Connected to DB9 of the SED1374
15
SD10
Connected to DB10 of the SED1374
16
SD11
Connected to DB11 of the SED1374
17
GND
Ground
18
GND
Ground
19
SD12
Connected to DB12 of the SED1374
20
SD13
Connected to DB13 of the SED1374
21
SD14
Connected to DB14 of the SED1374
22
SD15
Connected to DB15 of the SED1374
23
RESET#
24
GND
Ground
25
GND
Ground
26
GND
Ground
27
+12V
12 volt supply
28
+12V
12 volt supply
29
WE0#
Connected to the WE0# signal of the SED1374
30
WAIT#
31
CS#
Connected to the CS# signal of the SED1374
32
NC
Not connected
33
WE1#
34
NC
Connected to the RESET# signal of the SED1374
Connected to the WAIT# signal of the SED1374
Connected to the WE1# signal of the SED1374
Not connected
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
SED1374
X26A-G-005-01
Page 12
Epson Research and Development
Vancouver Design Center
Table 4-2: CPU/BUS Connector (H2) Pinout
SED1374
X26A-G-005-01
Connector
Pin No.
CPU/BUS
Pin Name
1
SA0
Connected to AB0 of the SED1374
2
SA1
Connected to AB1 of the SED1374
3
SA2
Connected to AB2 of the SED1374
4
SA3
Connected to AB3 of the SED1374
5
SA4
Connected to AB4 of the SED1374
6
SA5
Connected to AB5 of the SED1374
7
SA6
Connected to AB6 of the SED1374
8
SA7
Connected to AB7 of the SED1374
Comments
9
GND
Ground
10
GND
Ground
11
SA8
Connected to AB8 of the SED1374
12
SA9
Connected to AB9 of the SED1374
13
SA10
Connected to AB10 of the SED1374
14
SA11
Connected to AB11 of the SED1374
15
SA12
Connected to AB12 of the SED1374
16
SA13
Connected to AB13 of the SED1374
17
GND
Ground
18
GND
Ground
19
SA14
Connected to AB14 of the SED1374
20
SA15
Connected to AB14 of the SED1374
21
SA16
Connected to AB16 of the SED1374
22
SA17
Connected to AB17 of the SED1374
23
SA18
Connected to AB18 of the SED1374
24
SA19
Connected to AB19 of the SED1374
25
GND
Ground
26
GND
Ground
27
VCC
5 volt supply
28
VCC
5 volt supply
29
RD/WR#
Connected to the R/W# signal of the SED1374
30
BS#
Connected to the BS# signal of the SED1374
31
BUSCLK
32
RD#
Connected to the RD# signal of the SED1374
33
NC
Not connected
34
NC
Not connected
Connected to the BCLK signal of the SED1374
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
Epson Research and Development
Vancouver Design Center
Page 13
5 Host Bus Interface Pin Mapping
Table 5-1: Host Bus Interface Pin Mapping
SED1374
Pin Names
SH-3
SH-4
MC68K #1
MC68K #2
AB[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
Generic Bus #1 Generic Bus #2
A[15:1]
A[15:1]
AB0
A0
A0
LDS#
A0
A0
A0
DB[15:0]
D[15:0]
D[15:0]
D[15:0]
D[15:0]
D[15:0]
D[15:0]
WE1#
WE1#
WE1#
UDS#
DS#
WE1#
BHE#
CS#
CSn#
CSn#
BCLK
CKIO
CKIO
External Decode External Decode External Decode External Decode
BCLK
BCLK
BCLK
BCLK
BS#
BS#
BS#
AS#
AS#
Connect to VSS
Connect to IO
VDD
RD/WR#
RD/WR#
RD/WR#
R/W#
R/W#
RD1#
Connect to IO
VDD
RD#
RD#
RD#
Connect to IO
VDD
SIZ1
RD0#
RD#
WE0#
WE0#
WE0#
Connect to IO
VDD
SIZ0
WE0#
WE#
WAIT#
WAIT#
RDY#
DTACK#
DSACK1#
WAIT#
WAIT#
RESET#
RESET#
RESET#
RESET#
RESET#
RESET#
RESET#
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
SED1374
X26A-G-005-01
Page 14
Epson Research and Development
Vancouver Design Center
6 Technical Description
6.1 ISA Bus Support
This board has been designed to support the 16-bit ISA bus environment and can be used
in conjunction with either a VGA or a monochrome display adapter card.
There are 5 configuration inputs associated with the Host Interface (CNF[3:0] and BS#).
Refer to Table 2-3: “Jumper Settings” and Table 5-1: “Host Bus Interface Pin Mapping”
for complete details.
6.1.1 Display Adapter Card Support
When using the SDU1374B0B in conjunction with another primary Display Adapter (VGA
or Monochrome) the following applies:
ISA or VL Bus VGA Display Adapter
When the SDU1374B0B board is used with an ISA or VL Bus VGA display adapter, the
VGA card must have a 16-bit BIOS to prevent conflicts during 16-bit accesses
(MEMCS16#). If an 8-bit VGA adapter card is installed in the system being used, it must
be removed and the screen display routed through a COM port to a terminal display device.
PCI Bus VGA Display Adapter
All PCI based VGA display adapters can be used in conjunction with the SDU1374B0C
board.
Monochrome Display Adapter
All monochrome display adapters can be used in conjunction with the SDU1374B0C
board.
6.1.2 Expanded Memory Manager
If a memory manager is being used for system memory, the address range D0000h to
DFFFFh must be excluded from use as this range is used by the SDU1374B0C.
SED1374
X26A-G-005-01
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
Epson Research and Development
Vancouver Design Center
Page 15
6.2 Non-ISA Bus Support
The SDU1374B0C board is specifically designed to support the standard 16-bit ISA bus;
however, the SED1374 directly supports many other host bus interfaces. Header strips H1
and H2 are provided and contain all the necessary IO pins to interface to these host buses.
See CPU/Bus Interface Connector Pinouts on page 11; Table 2-1: “Configuration DIP
Switch Settings,” on page 8; and Table 2-3: “Jumper Settings,” on page 9 for details.
When using the header strips to provide the bus interface observe the following:
• All IO signals on the ISA bus card edge must be isolated from the ISA bus (do not plug
the card into a computer). Voltage lines are provided on the header strips.
• U7, a TIBPAL16L8-15 PAL, is currently used to provide the SED1374 CS# (pin 74),
RESET# (pin 73) and other decode logic signals for ISA bus use. This functionality
must now be provided externally; remove the PAL from its socket to eliminate conflicts
resulting from two different outputs driving the same input. Refer to Table 5-1: “Host
Bus Interface Pin Mapping” for connection details.
Note
When using a 3.3V host bus interface, IOVDD must be set to 3.3V by setting jumper
(JP1) to the 2-3 position. Refer to Table 2-3: “Jumper Settings,” on page 9.
6.3 Embedded Memory Support
The SED1374 contains 40K bytes of 16-bit SRAM used for the display buffer. The SRAM
starting address is set at D0000h. Starting at this address, the board design decodes a 64K
byte segment accommodating both the 40K byte display buffer and the SED1374 internal
register set.
The SED1374 registers are mapped into the upper 32 bytes of the 64K byte segment
(DFFE0h to DFFFFh).
6.4 Decode Logic
All the required decode logic is provided through a TIBPAL16L8-15 PAL (U7, socketed).
This PAL contains the following equations.
!CS = (Address >= ^hD0000) & (Address <= ^hDFFFF) & REFRESH & !RESET;
!MEMCS16= (Address1 >= ^h0C0000) & (Address1 <= ^h0DFFFF);
RESET_ = !RESET;
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
SED1374
X26A-G-005-01
Page 16
Epson Research and Development
Vancouver Design Center
6.5 Clock Input Support
The input clock (CLKI) frequency can be up to 50.0MHz for the SED1374 if the internal
clock divide by 2 is set. If the clock divide is not used, the maximum CLKI frequency is
25MHz.
A 25.0MHz oscillator (U2, socketed) is provided as the default clock source.
6.6 LCD Panel Voltage Setting
The SDU1374B0C board supports both 3.3V and 5.0V LCD panels through the single LCD
connector J5. The voltage level is selected by setting jumper J4 to the appropriate position.
Refer to Table 2-3: “Jumper Settings,” on page 9 for setting this jumper.
6.7 Monochrome LCD Panel Support
The SED1374 directly supports 4 and 8-bit, dual and single, monochrome passive LCD
panels. All necessary signals are provided on the 40-pin ribbon cable header J5. The
interface signals on the cable are alternated with grounds to reduce crosstalk and noise.
Refer to Table 3-1: “LCD Signal Connector (J5) Pinout,” on page 10 for specific
connection information.
6.8 Color Passive LCD Panel Support
The SED1374 directly supports 4 and 8, dual and single, color passive LCD panels. All the
necessary signals are provided on the 40-pin ribbon cable header J5. The interface signals
on the cable are alternated with grounds to reduce crosstalk and noise.
Refer to Table 3-1: “LCD Signal Connector (J5) Pinout,” on page 10 for specific
connection information.
6.9 Color TFT/D-TFD LCD Panel Support
The SED1374 directly supports 9 and 12-bit active matrix color TFT/D-TFD panels. All
the necessary signals can also be found on the 40-pin LCD connector J5. The interface
signals on the cable are alternated with grounds to reduce crosstalk and noise.
Refer to Table 3-1: “LCD Signal Connector (J5) Pinout,” on page 10 for connection information.
SED1374
X26A-G-005-01
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
Epson Research and Development
Vancouver Design Center
Page 17
6.10 Power Save Modes
The SED1374 supports one hardware and one software power save mode. These modes are
controlled by the utility 1374PWR. The hardware power save mode needs to be enabled by
1374PWR and then activated by DIP switch SW1-6. See Table 2-1: “Configuration DIP
Switch Settings,” on page 8 for details on setting this switch.
6.11 Adjustable LCD Panel Negative Power Supply
Most monochrome passive LCD panels require a negative power supply to provide
between -18V and -23V (Iout=45mA). For ease of implementation, such a power supply has
been provided as an integral part of this design. The VLCD power supply can be adjusted
by R21 to give an output voltage from -14V to -23V, and is enabled/disabled by the
SED1374 control signal LCDPWR.
LCDPWR is an SED1374 output signal which is configurable as active high or active low
by the CNF4 signal status on the rising edge of the RESET# signal. For the proper operation
of the VLCD power supply, LCDPWR must be configured as active low.
Determine the panel’s specific power requirements and set the potentiometer accordingly
before connecting the panel.
6.12 Adjustable LCD Panel Positive Power Supply
Most color passive LCD panels and most single monochrome 640x480 passive LCD panels
require a positive power supply to provide between +23V and +40V (Iout=45mA). For ease
of implementation, such a power supply has been provided as an integral part of this design.
The VDDH power supply can be adjusted by R15 to provide an output voltage from +23V
to +40V and is enabled/disabled by the SED1374 control signal LCDPWR.
LCDPWR is an SED1374 output signal which is configurable as active high or active low
by the CNF4 signal status on the rising edge of the RESET# signal. For the proper operation
of the VDDH power supply, LCDPWR must be configured as active low.
Determine the panel’s specific power requirements and set the potentiometer accordingly
before connecting the panel.
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
SED1374
X26A-G-005-01
Page 18
Epson Research and Development
Vancouver Design Center
6.13 CPU/Bus Interface Header Strips
All of the CPU/Bus interface pins of the SED1374 are connected to the header strips H1
and H2 for easy interface to a CPU/Bus other than ISA.
Refer to Table 4-1: “CPU/BUS Connector (H1) Pinout,” on page 11 and Table 4-2:
“CPU/BUS Connector (H2) Pinout,” on page 12 for specific settings.
Note
These headers only provide the CPU/Bus interface signals from the SED1374. When
another host bus interface is selected by CNF[3:0] and BS#, appropriate external decode
logic MUST be used to access the SED1374. Refer to Table 5-1: “Host Bus Interface
Pin Mapping,” on page 13 for connection details.
SED1374
X26A-G-005-01
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
Epson Research and Development
Vancouver Design Center
Page 19
7 Parts List
Item # Qty/board
Designation
Part Value
Description
1
13
C1-C11, C15,C16
0.1uF, 5%, 50V
0805 ceramic capacitor
2
1
C12
1uF, 10%, 16V
Tantalum capacitor size A
3
2
C13, C14
10uF, 10%, 25V
Tantalum capacitor size D
4
2
C17, C21
47uF, 10%, 16V
Tantalum capacitor size D
5
3
C18-C20
4.7uF, 10%, 50V
Tantalum capacitor size D
6
1
C22
56uF, 20%, 63V
Electrolytic, radial, low ESR
7
2
H1,H2
CON34A Header
0.1” 17x2 header, PTH
8
4
JP1-JP4
HEADER 3
0.1” 1x3 header, PTH
9
1
J1
AT CON-A
ISA Bus gold-fingers
10
1
J2
AT CON-B
ISA Bus gold-fingers
11
1
J3
AT CON-C
ISA Bus gold-fingers
12
1
J4
AT CON-D
ISA Bus gold-fingers
13
1
J5
CON40A
Shrouded header 2x20, PTH, center key
14
1
L1
1µH
MCI-1812 inductor
15
3
L2-L4
Ferrite bead
Philips BDS3/3/8.9-4S2
16
1
Q1
2N3906
PNP signal transistor, SOT23
17
1
Q2
2N3903
NPN signal transistor, SOT23
18
6
R1-R6
15K, 5%
0805 resistor
19
7
R7-R13
10K, 5%
0805 resistor
20
1
R14
470K, 5%
0805 resistor
21
1
R15
200K
200K Trim POT Spectrol 63S204T607 (or equivalent)
22
1
R16
14K, 1%
0805 resistor
23
2
R17, R18
1K, 5%
0805 resistor
24
2
R19, R20
100K, 5%
0805 resistor
25
1
R21
100K
100K Trim POT Spectrol 63S104T607 (or equivalent)
26
1
S1
SW DIP-6
6 position DIP switch
27
1
U1
SED1374F0A
QFP14-80, 80 pin, SMT
28
1
U2
25.0 MHz oscillator
FOX 25MHz oscillator or equiv., 14 pin DIP socketed
29
3
U3-U5
74AHC244
SO-22, TI74AHC244
30
1
U6
LT1117CM-3.3
Linear Technology 5V to 3.3V regulator, 800mA
31
1
U7
TIBPAL16L8-15
TI PAL, 20 Pin DIP, socketed.
32
1
U8
74ALS125
SO-20, TI74ALS125
33
1
U9
RD-0412
Xentek RD-0412, positive PS
34
1
U10
EPN001
Xentek EPN001 negative PS
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
SED1374
X26A-G-005-01
SED1374
X26A-G-005-01
D
C
B
A
3
2
1
1
2
2
3
1
3.3V
IOVDD
VCC
3
2
1
2
R/W#
WE1#
WE0#
RD#
BS#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
U1
74 CS#
73 RESET#
79
78
77
76
75
19
18
17
16
15
14
13
12
11
9
8
7
6
5
4
3
70
69
68
67
66
65
64
63
62
59
58
57
56
55
54
53
IOVDD
IOVDD
3.3V
WAIT#
3
2
1
HEADER 3
JP3
C7
0.1uF
IOVDD
RD/WR#
C6
0.1uF
3
COREVDD
COREVDD
COREVDD
COREVDD
20
27
40
50
60
72
80
SED1374F0A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
10 IOVDD
29 IOVDD
52 IOVDD
By-pass Capacitors (1 per power pin)
1
21
C1
C2
C3
C4
41
0.1uF
0.1uF
0.1uF
0.1uF
61
C5
0.1uF
WAIT#
44 TESTEN
2
51 CLKI
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
CLKI
SD[0..15]
SA[0..19]
3
71 BCLK
BS#
2
BUSCLK
CS#
RESET#
RD/WR#
WE1#
WE0#
RD#
BS#
SD[0..15]
SA[0..19]
HEADER 3
JP2
5.0V IOVDD
3.3V IOVDD
HEADER 3
JP1
1
4
4
LCDPWR
37
36
35
34
33
32
31
30
39
38
28
42
43
49
48
47
46
45
GPIO0 22
CNF0
CNF1
CNF2
CNF3
CNF4
FPDAT8/GPIO1 26
FPDAT9GPIO2 25
FPDAT10/GPIO3 24
FPDAT11/GPIO4 23
FPDAT0
FPDAT1
FPDAT2
FPDAT3
FPDAT4
FPDAT5
FPDAT6
FPDAT7
FPFRAME
FPLINE
FPSHIFT
DRDY
CNF0
CNF1
CNF2
CNF3
CNF4
FPDAT0
FPDAT1
FPDAT2
FPDAT3
FPDAT4
FPDAT5
FPDAT6
FPDAT7
5
5
12
11
10
9
8
7
SW DIP-6
S1
CNF[0..4]
6
FPDAT[0..7]
1
2
3
4
5
6
6
R1
15K
R3
15K
R4
15K
R5
15K
CNF0
CNF1
CNF2
CNF3
CNF4
SUSPEND
R6
15K
8
CNF[0..4]
Document Number
Date: Friday, October 09, 1998
7
Size
B
Sheet
1
8
of
4
Rev
1.0
SDU1374B0C ISA-Bus Rev.Evaluation
1.0
Board : 1374FOA Chip
Epson Re
search & Development, Inc.
SUSPEND
CNF[0..4]
FPDAT8
FPDAT9
FPDAT10
FPDAT11
FPDAT[0..7]
FPFRAME
FPLINE
FPSHIFT
DRDY
LCDPWR
R2
15K
7
IOVDD
D
C
B
A
Page 20
Epson Research and Development
Vancouver Design Center
8 Schematic Diagrams
Figure 8-1: SED1374B0C Schematic Diagram (1 of 4)
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
D
C
B
1
SD[0..15]
SD[0..15]
VCC
C11
0.1uF
BCLKI
SD8
SD10
SD4
SD6
SD0
SD2
VIN
2
VCC
VOUT
7
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
14
+
HEADER 17X2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
H1
2
OUT
GND
25.0Mhz
U2
NC
U6
LT1117CM-3.3
SD12
SD14
RESET#
+12V
WE0#
CS#
WE1#
3
8
1
2
ADJ
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
1
A
1
LCDVCC
4
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
U4
U5
74AHC244
1 1G
19 2G
2
4
6
8
11
13
15
17
74AHC244
SA[0..19]
74AHC244
1 1G
19 2G
20
10
18
16
14
12
9
7
5
3
20
10
18
16
14
12
9
7
5
3
20
10
SA8
SA10
SA12
SA0
SA2
SA4
SA6
VCC
GND
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCC
GND
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCC
GND
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
18
16
14
12
9
7
5
3
3
RD/WR#
BUSCLK
VCC
SA[0..19]
5.0V LCD Panels
3.3V LCD Panels
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
U3
1 1G
19 2G
2
4
6
8
11
13
15
17
FPSHIFT 2
1A1
DRDY
4 1A2
FPLINE
6
FPFRAME 8 1A3
1A4
LCDPWR
11 2A1
BCLKI
13 2A2
15 2A3
17 2A4
FPDAT8
FPDAT9
FPDAT10
FPDAT11
FPDAT0
FPDAT1
FPDAT2
FPDAT3
FPDAT4
FPDAT5
FPDAT6
FPDAT7
+12V
WAIT#
2
3
VCC
JP4
HEADER 3
FPSHIFT
DRDY
FPLINE
FPFRAME
LCDPWR
BCLKI
FPDAT8
FPDAT9
FPDAT10
FPDAT11
FPDAT[0..7]
4
SA14
SA16
SA18
1
2
3
2
1
SD13
SD15
SD9
SD11
SD5
SD7
SD1
SD3
C12
1uF 16V
3.3V
VCC
FPDAT[0..7]
3
5
5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
CLKI
HEADER 17X2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
H2
C10
0.1uF
C9
0.1uF
C8
0.1uF
VCC
SA15
SA17
SA19
SA9
SA11
SA13
SA1
SA3
SA5
SA7
6
BS#
RD#
BFPLINE
BFPFRAME
BFPSHIFT
BFPDAT0
BFPDAT1
BFPDAT2
BFPDAT3
BFPDAT4
BFPDAT5
BFPDAT6
BFPDAT7
BFPDAT8
BFPDAT9
BFPDAT10
BFPDAT11
SELECTABLE 3.3
V /
6
J5
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
CON40A
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
+12V
VDDH
VLCD
8
Document Number
Date: Friday, October 09, 1998
7
Size
B
Sheet
2
8
of
4
Rev
1.0
SDU1374B0C ISA-Bus Rev. 1.0 Evaluation Connector
Card : LCD& Headers
Epson Re
search & Development, Inc.
BDRDY
BLCDPWR
LCDVCC
5.0V COLOR/MONO LCD CONNECTOR
7
D
C
B
A
Epson Research and Development
Vancouver Design Center
Page 21
Figure 8-2: SED1374B0C Schematic Diagram (2 of 4)
SED1374
X26A-G-005-01
SED1374
X26A-G-005-01
D
C
B
A
1
SA[0..19]
LA[17..23]
WE1#
LA[17..23]
SA[0..19]
WAIT#
SD[0..15]
SA[0..19]
2
R9
10K
IOVDD
LA[17..23]
SD[0..15]
2
LA23
LA22
LA21
LA20
LA19
LA18
LA17
SA19
SA18
IOVDD
LA[17..23]
SA[0..19]
1
2
3
4
5
6
7
8
9
10
10K
R10
O2
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
O1
I10
VCC
19
18
17
16
15
14
13
12
11
20
3
TIBPAL16L8-15
I1
I2
I3
I4
I5
I6
I7
I8
I9
GND
U7
3
C15
0.1uF
SA17
VCC
SA16
MEMCS16
LA23
LA22
LA21
LA20
LA19
LA18
LA17
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
4
AT CON-C
/SBHE
LA23
LA22
LA21
LA20
LA19
LA18
LA17
/MEMR
/MEMW
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
J3
/IOCHCK
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
IOCHRDY
AEN
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
AT CON-A
J1
R12
10K
IOVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R11
10K
IOVDD
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
4
5
/MEMCS16
/IOCS16
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
/DACK0
DRQ0
/DACK5
DRQ5
/DACK6
DRQ6
/DACK7
DRQ7
+5V
MASTER
GND
AT CON-D
J4
GND
RESET
+5V
IRQ9
-5V
DRQ2
-12V
OWS
+12V
GND
/SMEMW
/SMEMR
/IOW
/IOR
/DACK3
DRQ3
/DACK1
DRQ1
/REFRESH
CLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
/DACK2
T/C
BALE
+5V
OSC
GND
AT CON-B
J2
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VCC
RESET#
REFRESH#
RESET
CS#
VCC
+12V
+ C13
10uF
6
6
+ C14
10uF
14
2
7
U8A
74ALS125
3
C16
0.1uF
R8
10K
IOVDD
7
VCC
R13
10K
MEMCS16#
MEMCS16#
BUSCLK
REFRESH#
RD#
WE0#
RESET
8
D
C
B
A
Document Number
Date: Thursday, October 08, 1998 Sheet
7
Size
B
3
8
of
4
Rev
1.0
SDU1374B0B ISA-Bus Rev. 1.0
ation
Evalu
Board : ISA-Bus and PAL Decode
Epson Research & Development, Inc.
VCC
R7
10K
IOVDD
1
1
Page 22
Epson Research and Development
Vancouver Design Center
Figure 8-3: SED1374B0C Schematic Diagram (3 of 4)
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
D
C
B
1
VCC
IOVDD
LCDPWR
1
1
1
L4
L3
L2
2
2
2
PSGND
PSVCC
PSIOVDD
2
3
PSVCC
+
+
U10
EPN001
4
C21
47uF / 16V
C17
47uF/16V
PSVCC
DC_IN
2
REMOTE
U9
RD-0412
2
R21
100K
2
VOUT_ADJ
4
GND
GND
6
3
VOUT_ADJ
5
4
3
DC_IN
DC_IN
11
10
GND
GND
GND
GND
GND
GND
GND
4
5
6
7
8
10
11
NC
9
NC
NC
NC
NC
1
5
3
5
1
DC_OUT
9
8
7
3
1
DC_OUT
12
DC_OUT
2
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
1
3
R16
14K
R15
200K
R14
470K
PSGND
6
100K
R20
1K
R17
C18
4.7uF/50V
C22
56uF/35V
Low ESR
+
6
2
+
2
5
1
Q2
2N3903
3
R18
1K
1
Q1
2N3906
3
PSIOVDD
C19
4.7uF/50V
1uH
L1
2
A
2
+
1
VLCD
8
Document Number
Date: Friday, October 09, 1998
7
Size
B
Sheet
4
8
of
4
Rev
1.0
SDU1374B0C ISA-Bus Rev. 1.0 on
Evaluati
Board : LCD Power Supply
Epson Re
search & Development, Inc.
R19
100K
PSVCC
VDDH
PSGND
+ C20
4.7uF/50V
7
D
C
B
A
Epson Research and Development
Vancouver Design Center
Page 23
Figure 8-4: SED1374B0C Schematic Diagram (4 of 4)
SED1374
X26A-G-005-01
Page 24
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-G-005-01
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
SED1374 Embedded Memory Color LCD Controller
Interfacing to the Toshiba MIPS
TX3912 Processor
Document Number: X26A-G-004-01
Copyright © 1998 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
EPSON Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-G-004-01
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 98/11/09
EPSON Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
2
3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Direct Connection to the Toshiba TX3912 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2
Memory Mapping and Aliasing
2.3
SED1374 Configuration and Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . .9
. . . . . . . . . . . . . . . . . . . . . . . . . . . .9
System Design Using the ITE IT8368E PC Card Buffer . . . . . . . . . . . . . . . . . . . . 10
3.1
Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2
IT8368E Configuration
3.3
Memory Mapping and Aliasing
3.4
SED1374 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
EPSON LCD Controllers (SED1374) . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2
Toshiba MIPS TX3912 Processor
5.3
ITE IT8368E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 98/11/09
. . . . . . . . . . . . . . . . . . . . . . . . . . 15
SED1374
X26A-G-004-01
Page 4
EPSON Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-G-004-01
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 98/11/09
EPSON Research and Development
Vancouver Design Center
Page 5
List of Tables
Table 2-1:
SED1374 Configuration for Direct Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 2-2:
SED1374 Generic #2 Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 3-1:
TX3912 to Unbuffered PC Card Slots System Address Mapping . . . . . . . . . . . . . . . . . . 12
Table 3-2:
TX3912 to PC Card Slots Address Remapping Using the IT8368E . . . . . . . . . . . . . . . . . 12
Table 3-3:
SED1374 Configuration Using the IT8368E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3-4:
SED1374 Generic #1 Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
List of Figures
Figure 2-1:
SED1374 to TX3912 Direct Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3-1:
SED1374 to TX3912 Connection Using an IT8368E . . . . . . . . . . . . . . . . . . . . . . . . 10
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 98/11/09
SED1374
X26A-G-004-01
Page 6
EPSON Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-G-004-01
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 98/11/09
EPSON Research and Development
Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware and software environment required to provide an
interface between the SED1374 Embedded Memory Color Graphics LCD Controller and the
Toshiba MIPS TX3912 Processor.
For further information on the SED1374, refer to the SED1374 Hardware Functional Specification,
document number X26A-A-001-xx.
For further information on the TX3912, contact Toshiba or refer to the Toshiba website under
semiconductors at http://www.toshiba.com/taec/nonflash/indexproducts.html.
For further information on the ITE IT8368E, refer to the IT8368E PC Card / GPIO Buffer Chip
Specification.
1.1 General Description
The Toshiba MIPS TX3912 processor supports up to two PC Card (PCMCIA) slots. It is through
this host bus interface that the SED1374 connects to the TX3912 processor.
The SED1374 can be successfully interfaced using one of two configurations:
• Direct connection to TX3912 (see Section 2, “Direct Connection to the Toshiba TX3912” on
page 8).
• System design using one ITE IT8368E PC Card/GPIO buffer chip (see Section 3, “System
Design Using the ITE IT8368E PC Card Buffer” on page 10).
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 98/11/09
SED1374
X26A-G-004-01
Page 8
EPSON Research and Development
Vancouver Design Center
2 Direct Connection to the Toshiba TX3912
2.1 General Description
In this example implementation, the SED1374 occupies the TX3912 PC Card slot #1.
The SED1374 is easily interfaced to the TX3912 with minimal additional logic. The address bus of
the TX3912 PC Card interface is multiplexed and can be demultiplexed using an advanced CMOS
latch (e.g., 74ACT373). The direct connection approach makes use of the SED1374 in its “Generic
Interface #2” configuration.
The following diagram demonstrates a typical implementation of the interface.
SED1374
+3.3V
TX3912
IO VDD, CORE VDD
RD*
RD#
WE*
WE#
CARD1CSL*
CARD1CSH*
BHE#
IO VDD
BS#
IO VDD
RD/WR#
System RESET
ENDIAN
RESET#
Latch
CS#
ALE
AB[15:13]
AB[12:0]
A[12:0]
D[31:24]
D[23:16]
DB[7:0]
DB[15:8]
VDD
pull-up
CARD1WAIT*
WAIT#
DCLKOUT
See text
Clock divider
...or...
Oscillator
CLKI
BCLK
Figure 2-1: SED1374 to TX3912 Direct Connection
The “Generic #2” host interface control signals of the SED1374 are asynchronous with respect to
the SED1374 bus clock. This gives the system designer full flexibility to choose the appropriate
source (or sources) for CLKI and BCLK. The choice of whether both clocks should be the same, and
whether to use DCLKOUT (divided) as clock source, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum SED1374 clock frequencies.
The SED1374 also has internal clock dividers providing additional flexibility.
SED1374
X26A-G-004-01
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 98/11/09
EPSON Research and Development
Vancouver Design Center
Page 9
2.2 Memory Mapping and Aliasing
The SED1374 requires an addressing space of 64K bytes. The on-chip display memory occupies the
range 0 through 9FFFh. The registers occupy the range FFE0h through FFFFh. The TX3912
demultiplexed address lines A16 and above are ignored, thus the SED1374 is aliased 1024 times at
64K byte intervals over the 64M byte PC Card slot #1 memory space. In this example
implementation, the TX3912 control signal CARDREG* is ignored, the SED1374 also takes up the
entire PC Card slot 1 configuration space.
Note
If aliasing is undesirable, additional decoding circuitry must be added.
2.3 SED1374 Configuration and Pin Mapping
The SED1374 is configured at power up by latching the state of the CNF[4:0] pins. Pin BS# also
plays a role in host bus interface configuration. For details on configuration, refer to the SED1374
Hardware Functional Specification, document number X26A-A-001-xx.
The table below shows those configuration settings relevant to the direct connection approach.
Table 2-1: SED1374 Configuration for Direct Connection
Value hard wired on this pin is used to configure:
SED1374
Configuration
Pin
1 (IO VDD)
0 (VSS)
BS#
Generic #2
Generic #1
CNF3
Big Endian
Little Endian
111: Generic #1 or #2
CNF[2:0]
= configuration for Toshiba TX3912 host bus interface
When the SED1374 is configured for “Generic #2” interface, the host interface pins are mapped as
in the table below.
Table 2-2: SED1374 Generic #2 Interface Pin Mapping
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 98/11/09
Pin Name
Pin Function
WE1#
BHE#
BS#
Connect to IO VDD
RD/WR#
Connect to IO VDD
RD#
RD#
WE0#
WE#
SED1374
X26A-G-004-01
Page 10
EPSON Research and Development
Vancouver Design Center
3 System Design Using the ITE IT8368E PC Card Buffer
If the system designer uses the ITE IT8368E PC Card and multiple-function I/O buffer, the
SED1374 can be interfaced so that it ’shares’ a PC Card slot. The SED1374 is mapped to a rarelyused 16M byte portion of the PC Card slot buffered by the IT8368E. This makes the SED1374
virtually transparent to PC Card devices that use the same slot.
3.1 Hardware Description
The ITE8368E has been specially designed to support EPSON LCD controllers. The ITE IT8368E
provides eleven Multi-Function IO pins (MFIO). Configuration registers may be used to allow these
MFIO pins to provide the control signals required to implement the SED1374 CPU interface.
The TX3912 processor only provides addresses A[12:0], therefore devices requiring more address
space must use an external device to latch A[25:13]. The IT8368E’s MFIO pins can be configured
to provide this latched address.
SED1374
+3.3V
IO VDD, CORE VDD
TX3912
HA[12:0]
AB[12:0]
ENDIAN
AB[15:13]
HD[31:24]
DB[7:0]
HD[23:16]
DB[15:8]
VDD
System RESET
CARDxWAIT*
WAIT#
DCLKOUT
See text
...or...
IT8368E
RESET#
pull-up
Clock divider
Oscillator
CLKI
BCLK
LHA[23]/MFIO[10]
WE1#
LHA[22]/MFIO[9]
WE0#
LHA[21]/MFIO[8]
RD1#
LHA[20]/MFIO[7]
RD0#
LHA[19]/MFIO[6]
LHA[15:13]/
MFIO[2:0]
CS#
BS#
Figure 3-1: SED1374 to TX3912 Connection Using an IT8368E
SED1374
X26A-G-004-01
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 98/11/09
EPSON Research and Development
Vancouver Design Center
Page 11
The “Generic #1” host interface control signals of the SED1374 are asynchronous with respect to
the SED1374 bus clock. This gives the system designer full flexibility to choose the appropriate
source (or sources) for CLKI and BCLK. The choice of whether both clocks should be the same, and
whether to use DCLKOUT (divided) as clock source, should be based on pixel and frame rates,
power budget, part count and maximum SED1374 respective clock frequencies. Also, internal
SED1374 clock dividers provide additional flexibility.
3.2 IT8368E Configuration
The IT8368E provides eleven multi-function IO pins (MFIO). The IT8368E must have both “Fix
Attribute/IO” and “VGA” modes on. When both these modes are enabled, the MFIO pins provide
control signals needed by the SED1374 host bus interface, and a 16M byte portion of the system PC
Card attribute and IO space is allocated to address the SED1374. When accessing the SED1374 the
associated card-side signals are disabled in order to avoid any conflicts.
For mapping details, refer to section 3.3: “Memory Mapping and Aliasing.” For connection details
see Figure 3-1: “SED1374 to TX3912 Connection Using an IT8368E,” on page 10. For further information on the IT8368E, refer to the IT8368E PC Card/GPIO Buffer Chip Specification.
Note
When a second IT8368E is used, that circuit should not be set in VGA mode.
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 98/11/09
SED1374
X26A-G-004-01
Page 12
EPSON Research and Development
Vancouver Design Center
3.3 Memory Mapping and Aliasing
When the TX3912 accesses the PC Card slots without the ITE IT8368E, its system memory is
mapped as in Table 3-1:, “TX3912 to Unbuffered PC Card Slots System Address Mapping”.
Note
Bits CARD1IOEN and CARD2IOEN need to be set in TX3912 Memory Configuration
Register 3.
Table 3-1: TX3912 to Unbuffered PC Card Slots System Address Mapping
TX3912 Address
Function
(CARDnIOEN=0)
Size
Function
(CARDnIOEN=1)
0800 0000h
64M byte
Card 1 Attribute
Card 1 IO
0C00 0000h
64M byte
Card 2 Attribute
Card 2 IO
6400 0000h
64M byte
Card 1 Memory
6400 0000h
64M byte
Card 2 Memory
When the TX3912 accesses the PC Card slots buffered through the ITE IT8368E, bits CARD1IOEN
and CARD2IOEN are ignored and the attribute/IO space of the TX3912 is divided into Attribute,
I/O and SED1374 access. Table 3-2:, “TX3912 to PC Card Slots Address Remapping Using the
IT8368E” provides all details of the Attribute/IO address reallocation by the IT8368E.
Table 3-2: TX3912 to PC Card Slots Address Remapping Using the IT8368E
IT8368E Uses PC Card Slot #
1
2
SED1374
X26A-G-004-01
TX3912 Address
Size
Function
0800 0000h
16M byte
Card 1 IO
0900 0000h
16M byte
SED1374 (aliased 256 times at 64K byte intervals)
0A00 0000h
32M byte
Card 1 Attribute
6400 0000h
64M byte
Card 1 Memory
0C00 0000h
16M byte
Card 2 IO
0D00 0000h
16M byte
SED1374 (aliased 256 times at 64K byte intervals)
0E00 0000h
32M byte
Card 2 Attribute
6800 0000h
64M byte
Card 2 Memory
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 98/11/09
EPSON Research and Development
Vancouver Design Center
Page 13
3.4 SED1374 Configuration
The SED1374 is configured at power up by latching the state of the CNF[4:0] pins. Pin BS# also
plays a role in host bus interface configuration. For details on configuration, refer to the SED1374
Hardware Functional Specification, document number X26A-A-001-xx.
The table below shows those configuration settings relevant to this specific interface.
Table 3-3: SED1374 Configuration Using the IT8368E
Value hard wired on this pin is used to configure:
SED1374
Configuration
Pin
1 (IO VDD)
0 (VSS)
BS#
Generic #2
Generic #1
CNF3
Big Endian
Little Endian
111: Generic #1 or #2
CNF[2:0]
= configuration for connection using ITE IT8368E
When the SED1374 is configured for “Generic #1” interface, the host interface pins are mapped as
in the table below.
Table 3-4: SED1374 Generic #1 Interface Pin Mapping
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 98/11/09
Pin Name
Pin Function
WE1#
WE1#
BS#
connect to VSS
RD/WR#
RD1#
RD#
RD0#
WE0#
WE0#
SED1374
X26A-G-004-01
Page 14
EPSON Research and Development
Vancouver Design Center
4 Software
Test utilities and Windows® CE v2.0 display drivers are available for the SED1374. Full source
code is available for both the test utilities and the drivers.
The test utilities are configurable for different panel types using a program called 1357CFG, or by
directly modifying the source. The Windows CE v2.0 display drivers can be customized by the OEM
for different panel types, resolutions and color depths only by modifying the source.
The SED1374 test utilities and Windows CE v2.0 display drivers are available from your sales
support contact or www.erd.epson.com.
SED1374
X26A-G-004-01
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 98/11/09
EPSON Research and Development
Vancouver Design Center
Page 15
5 Technical Support
5.1 EPSON LCD Controllers (SED1374)
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
5.2 Toshiba MIPS TX3912 Processor
http://www.toshiba.com/taec/nonflash/indexproducts.html
5.3 ITE IT8368E
Integrated Technology Express, Inc.
Sales & Marketing Division
2710 Walsh Avenue
Santa Clara, CA 95051, USA
Tel: (408) 980-8168
Fax: (408) 980-9232
http://www.iteusa.com
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 98/11/09
SED1374
X26A-G-004-01
Page 16
EPSON Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-G-004-01
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 98/11/09
SED1374 Embedded Memory Color LCD Controller
SED1374
Power Consumption
Document Number: X26A-G-006-01
Copyright © 1998 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-G-006-01
Power Consumption
Issue Date: 98/10/27
Epson Research and Development
Vancouver Design Center
Page 3
1 SED1374 Power Consumption
SED1374 power consumption is affected by many system design variables.
• Input clock frequency (CLKI): the CLKI frequency and the internal clock divide register determine the operating clock (CLK) frequency of the SED1374. The higher CLK is, the higher the
frame fate, performance, and power consumption.
• CPU interface: the SED1374 current consumption depends on the BUSCLK frequency, data
width, number of toggling pins, and other factors – the higher the BUSCLK, the higher the CPU
performance and power consumption.
• VDD voltage levels (Core and IO): the voltage level of the Core and IO sections in the SED1374
affects power consumption – the higher the voltage, the higher the consumption.
• Display mode: the resolution, panel type, and color depth affect power consumption. The higher
the resolution/color depth and number of LCD panel signals, the higher the power consumption.
Note
If the High Performance option is turned on, the power consumption increases to that of
8 bit-per-pixel mode for all color depths.
There are two power save modes in the SED1374: Software and Hardware Power Save. The power
consumption of these modes is affected by various system design variables.
• CPU bus state during Power Save: the state of the CPU bus signals during Power Save has a
substantial effect on power consumption. An inactive bus (e.g. BUSCLK = low, Addr = low etc.)
reduces overall system power consumption.
• CLKI state during Power Save: disabling the CLKI during Power Save has substantial power
savings.
Power Consumption
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1.1 Conditions
Table 1-1: “SED1374 Total Power Consumption” below gives an example of a specific environment
and its effects on power consumption.
Table 1-1: SED1374 Total Power Consumption
Test Condition
Core VDD = 3.3V, IO VDD = 3.3V
BUSCLK = 8.33MHz
Power Consumption
Gray Shades /
Colors
Active
Power Save Mode
Core
IO
Total
Software
Hardware
5.29mW
6.86mW
8.15mW
0.3mW
0.43mW
0.55mW
5.59mW
7.29mW
8.70mW
1.58mW1
1.19mW2
Input Clock = 6MHz
2 Colors
2 LCD Panel = 320x240 4-bit Single Color 4 Colors
16 Colors
6.82mW
7.58mW
8.98mW
1.13mW
2.29mW
2.25mW
7.95mW
9.86mW
11.23mW
1.58mW1
1.19mW2
Input Clock = 25MHz
3 LCD Panel = 640x480 8-bit Single
Monochrome
21.38mW
0.92mW
22.30mW
3.09mW1
2.71mW2
23.66mW
2.40mW
26.07mW
3.09mW1
2.71mW2
Black-and-White
20.93mW
0.88mW
21.81mW
3.09mW1
2.71mW2
Input Clock = 25MHz
6 LCD Panel = 640x480 8-bit Dual Color
2 Colors
23.78mW
1.93mW
25.72mW
3.09mW1
2.71mW2
Input Clock = 25MHz
7 LCD Panel = 640x480 9-bit TFT
2 Colors
16.48mW
8.07mW
24.55mW
3.09mW1
2.71mW2
Input Clock = 6MHz
1 LCD Panel = 320x240 4-bit Single
Monochrome
4
Black-and-White
4 Gray Shades
16 Gray Shades
Black-and-White
Input Clock = 25MHz
2 Colors
LCD Panel = 640x480 8-bit Single Color
Input Clock = 25MHz
5 LCD Panel = 640x480 8-bit Dual
Monochrome
Note
1. Conditions for Software Power Save:
• CPU interface active (signals toggling)
• CLKI active
2. Conditions for Hardware Power Save:
• CPU interface inactive (high impedance)
• CLKI active
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Power Consumption
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2 Summary
The system design variables in Section 1, “SED1374 Power Consumption” and in Table 1-1:
“SED1374 Total Power Consumption” show that SED1374 power consumption depends on the
specific implementation. Active Mode power consumption depends on the desired CPU performance and LCD frame-rate, whereas Power Save Mode consumption depends on the CPU Interface
and Input Clock state.
In a typical design environment, the SED1374 can be configured to be an extremely power-efficient
LCD Controller with high performance and flexibility.
Power Consumption
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SED1374
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Power Consumption
Issue Date: 98/10/27
SED1374 Embedded Memory Color LCD Controller
Interfacing to the Motorola MC68328
‘Dragonball’ Microprocessor
Document Number: X26A-G-007-02
Copyright © 1998, 1999 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.
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SED1374
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Interfacing to the Motorola MC68328 ‘Dragonball’ Microprocessor
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Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Interfacing to the MC68328 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 The MC68328 System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Chip-Select Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
SED1374 Host Bus Interface
3.1 Bus Interface Modes . . .
3.2 Generic #1 Interface Mode
3.3 MC68K #1 Interface Mode
4
MC68328 To SED1374 Interface . . . . . . . .
4.1 Hardware Description . . . . . . . . . .
4.1.1 Using The MC68K #1 Host Bus Interface
4.1.2 Using The Generic #1 Host Bus Interface
4.2 SED1374 Hardware Configuration . . . . .
4.3 MC68328 Chip Select Configuration . . . .
5
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1 EPSON LCD Controllers (SED1374) . . . . . . . . . . . . . . . . . . . . . 17
7.2 Motorola MC68328 Processor . . . . . . . . . . . . . . . . . . . . . . . . 17
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List of Tables
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4-1: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4-2: Host Bus Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
List of Figures
Figure 4-1: Typical Implementation of MC68328 to SED1374 Interface - MC68K #1 . . . . . . . . 12
Figure 4-2: Typical Implementation of MC68328 to SED1374 Interface - Generic #1 . . . . . . . . 13
Interfacing to the Motorola MC68328 ‘Dragonball’ Microprocessor
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1 Introduction
This application note describes the hardware required to provide an interface between the
SED1374 Embedded Memory LCD Controller and the Motorola MC68328 “Dragonball”
Microprocessor. By implementing a dedicated display refresh memory, the SED1374 can
reduce system power consumption, improve image quality, and increase system performance as compared to the Dragonball’s on-chip LCD controller.
The designs described in this document are presented only as examples of how such
interfaces might be implemented. This application note will be updated as appropriate.
Please check the Epson Research and Development Website at http://www.erd.epson.com
for the latest revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
Interfacing to the Motorola MC68328 ‘Dragonball’ Microprocessor
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2 Interfacing to the MC68328
2.1 The MC68328 System Bus
The MC68328 is an integrated controller for handheld products, based upon the
MC68EC000 microprocessor core. It implements a 16-bit data bus and a 32-bit address bus.
The bus interface consists of all the standard MC68000 bus interface signals, plus some
new signals intended to simplify the task of interfacing to typical memory and peripheral
devices.
The MC68000 bus control signals are well documented in Motorola’s user manuals, and
will not be described here. A brief summary of the new signals appears below:
• Output Enable (OE) is asserted when a read cycle is in process; it is intended to connect
to the output enable control of a typical static RAM, EPROM, or Flash EPROM device.
• Upper Write Enable and Lower Write Enable (UWE/LWE) are asserted during memory
write cycles for the upper and lower bytes of the 16-bit data bus; they may be directly
connected to the write enable inputs of a typical memory device.
The SED1374 implements the MC68000 bus interface using its “MC68K #1” mode, so this
mode may be used to connect the MC68328 directly to the SED1374 with no glue logic.
However, several of the MC68000 bus control signals are multiplexed with IO and interrupt
signals on the MC68328, and in many applications it may be desirable to make these pins
available for these alternate functions. This requirement may be accommodated through
use of the Generic #1 interface mode on the SED1374.
2.2 Chip-Select Module
The MC68328 can generate up to 16 chip select outputs, organized into four groups “A”
through “D”.
Each chip select group has a common base address register and address mask register, to
set the base address and block size of the entire group. In addition, each chip select within
a group has its own address compare and address mask register, to activate the chip select
for a subset of the group’s address block. Finally, each chip select may be individually
programmed to control an 8 or 16-bit device, and each may be individually programmed to
generate from 0 through 6 wait states internally, or allow the memory or peripheral device
to terminate the cycle externally through use of the standard MC68000 DTACK signal.
Groups A and B can have a minimum block size of 64K bytes, so these are typically used
to control memory devices. Chip select A0 is active immediately after reset, so it is
typically used to control a boot EPROM device. Groups C and D have a minimum block
size of 4K bytes, so they are well-suited to controlling peripheral devices. Chip select D3
is associated with the MC68328 on-chip PCMCIA control logic.
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3 SED1374 Host Bus Interface
This section is a summary of the host bus interface modes available on the SED1374 and
offers some detail on the Generic #1 and MC68K #1 host bus interfaces that may be used
to implement the interface to the MC68328.
3.1 Bus Interface Modes
The SED1374 implements a 16-bit interface to the host microprocessor which may operate
in one of several modes compatible with most of the popular embedded microprocessor
families. Six bus interface modes are supported:
• Hitachi SH-4.
• Hitachi SH-3
• Motorola MC68000 (using Upper Data Strobe/Lower Data Strobe).
• Motorola MC68020/MC68030/MC683xx (using Data Strobe/DSACKx).
• Generic #1 (Chip Select, plus individual Read Enable/Write Enable for each byte).
• Generic #2 (External Chip Select, shared Read/Write Enable for high byte, individual
Read/Write Enable for low byte).
The SED1374 latches CNF[2:0] and BS# to allow selection of the host bus interface on the
rising edge of RESET#. After releasing reset, the bus interface signals assume their selected
configuration. The following table shows the functions of each host bus interface signal.
Table 3-1: Host Bus Interface Pin Mapping
SED1374
Pin Names
SH-3
SH-4
MC68K #1
MC68K #2
Generic #1
Generic #2
AB[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
AB0
A0
A0
LDS#
A0
A0
A0
DB[15:0]
D[15:0]
D[15:0]
D[15:0]
D[31:16]
D[15:0]
D[15:0]
WE1#
WE1#
WE1#
UDS#
DS#
WE1#
BHE#
CS#
CSn#
CSn#
External Decode
BCLK
CKIO
CKIO
CLK
CLK
BCLK
BCLK
BS#
BS#
BS#
AS#
AS#
connect to VSS
connect to IO VDD
RD/WR#
RD/WR#
RD/WR#
R/W#
R/W#
RD1#
connect to IO VDD
RD#
RD#
RD#
connect to IO VDD
SIZ1
RD0#
RD#
WE0#
WE0#
WE0#
connect to IO VDD
SIZ0
WE0#
WE#
WAIT#
WAIT#
RDY#
DTACK#
DSACK1#
WAIT#
WAIT#
RESET#
RESET#
RESET#
RESET#
RESET#
RESET#
RESET#
Interfacing to the Motorola MC68328 ‘Dragonball’ Microprocessor
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External Decode External Decode
External Decode
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Two other configuration options (CNF[4:3]) are also made at time of hardware reset:
• endian mode setting (big endian or little endian).
• polarity of the LCDPWR signal.
The capability to select the endian mode independent of the host bus interface offers more
flexibility in configuring the SED1374 with other CPUs.
For details on configuration, refer to the SED1374 Hardware Functional Specification,
document number X26A-A-001-xx.
3.2 Generic #1 Interface Mode
Generic #1 interface mode is the most general and least processor-specific interface mode
on the SED1374. The Generic # 1 interface mode was chosen for this interface due to the
simplicity of its timing.
The interface requires the following signals:
• BUSCLK is a clock input which is required by the SED1374 host interface. It is separate
from the input clock (CLKI) and is typically driven by the host CPU system clock.
• The address inputs AB0 through AB15, and the data bus DB0 through DB15, connect
directly to the CPU address and data bus, respectively. On 32-bit big endian architectures such as the Power PC, the data bus would connect to the high-order data lines; on
little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data
lines. The hardware engineer must ensure that CNF3 selects the proper endian mode
upon reset.
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper
IO or memory address space.
• WE0# and WE1# are write enables for the low-order and high-order bytes, respectively,
to be driven low when the host CPU is writing data to the SED1374. These signals must
be generated by external hardware based on the control outputs from the host CPU.
• RD# and RD/WR# are read enables for the low-order and high-order bytes, respectively,
to be driven low when the host CPU is reading data from the SED1374. These signals
must be generated by external hardware based on the control outputs from the host CPU.
• WAIT# is a signal output from the SED1374 that indicates the host CPU must wait until
data is ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU
accesses to the SED1374 may occur asynchronously to the display update, it is possible
that contention may occur in accessing the SED1374 internal registers and/or refresh
memory. The WAIT# line resolves these contentions by forcing the host to wait until the
resource arbitration is complete. This signal is active low and may need to be inverted if
the host CPU wait state signal is active high.
• The Bus Status (BS#) signal is not used in the bus interface for Generic #1 mode.
However, BS# is used to configure the SED1374 for Generic #1 mode and should be
tied low (connected to GND).
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3.3 MC68K #1 Interface Mode
The MC68K #1 Interface Mode can be used to interface to the MC68328 microprocessor
if the previously mentioned, multiplexed, bus signals will not be used for other purposes.
The interface requires the following signals:
• BUSCLK is a clock input which synchronizes transfers between the host CPU and the
SED1374. It is separate from the input clock (CLKI) and is typically driven by the host
CPU system clock.
• The address inputs AB1 through AB15, and the data bus DB0 through DB15, connect
directly to the CPU address and data bus, respectively. On 32-bit big endian architectures such as the Power PC, the data bus would connect to the high-order data lines; on
little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data
lines. The hardware engineer must ensure that CNF3 selects the proper endian mode
upon reset.
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper
IO or memory address space.
• A0 and WE1# are the enables for the low-order and high-order bytes, respectively, to be
driven low when the host CPU is reading or writing data to the SED1374. These must be
generated by external decode hardware based upon the control outputs from the host
CPU.
• RD/WR# is the read/write signal that is driven low when the CPU writes to the
SED1374 and is driven high when the CPU is doing a read from the SED1374. This
signal must be generated by external decode hardware based upon the control output
from the host CPU.
• WAIT# is a signal which is output from the SED1374 to the host CPU that indicates
when data is ready (read cycle) or accepted (write cycle) on the host bus. Since host
CPU accesses to the SED1374 may occur asynchronously to the display update, it is
possible that contention may occur in accessing the SED1374 internal registers and/or
refresh memory. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete.
• The Bus Status (BS#) signal indicates that the address on the address bus is valid. This
signal must be generated by external decode hardware based upon the control outputs
from the host CPU.
• The WE0# signal is not used in the bus interface for MC68K #1 and must be tied high
(tied to IO VDD).
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4 MC68328 To SED1374 Interface
4.1 Hardware Description
The interface between the MC68328 and the SED1374 can be implemented using either the
MC68K #1 or Generic #1 host bus interface of the SED1374.
4.1.1 Using The MC68K #1 Host Bus Interface
The MC68328 multiplexes dual functions on some of its bus control pins (specifically
UDS, LDS, and DTACK). In implementations where all of these pins are available for use
as bus control pins, then the SED1374 interface is a straightforward implementation of the
“MC68K #1” host bus interface. For further information on this host bus interface, refer to
the SED1374 Hardware Functional Specification, document number
X26A-A-001-xx.
The following diagram shows a typical implementation of the MC68328 to SED1374 using
the MC68K #1 host bus interface.
MC68328
SED1374
A[15:0]
AB[15:1]
D[15:0]
DB[15:0]
CSB3
CS#
Vcc
470
DTACK
WAIT#
AS
BS#
UDS
WE1#
LDS
AB0
R/W
RD/WR#
Vcc
RD#
CLK0
BUSCLK
RESET
RESET#
Figure 4-1: Typical Implementation of MC68328 to SED1374 Interface - MC68K #1
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4.1.2 Using The Generic #1 Host Bus Interface
If UDS and/or LDS are required for their alternate IO functions, then the MC68328 to
SED1374 interface may be implemented using the SED1374 Generic #1 host bus interface.
Note that in either case, the DTACK signal must be made available for the SED1374, since
it inserts a variable number of wait states depending upon CPU/LCD synchronization and
the LCD panel display mode. WAIT# must be inverted (using an inverter enabled by CS#)
to make it an active high signal and thus compatible with the MC68328 architecture. A
single resistor is used to speed up the rise time of the WAIT# (DTACK) signal when
terminating the bus cycle.
The following diagram shows a typical implementation of the MC68328 to SED1374 using
the Generic #1 host bus interface.
SED1374
MC68328
A[15:0]
AB[15:0]
D[15:0]
DB[15:0]
CS#
CSB3
Vcc
470
DTACK
WAIT#
UWE
WE1#
LWE
WE0#
OE
RD/WR#
RD#
CLK0
BUSCLK
RESET
RESET#
Figure 4-2: Typical Implementation of MC68328 to SED1374 Interface - Generic #1
Interfacing to the Motorola MC68328 ‘Dragonball’ Microprocessor
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4.2 SED1374 Hardware Configuration
The SED1374 uses CNF4 through CNF0 and BS# to allow selection of the bus mode and
other configuration data on the rising edge of RESET#. Refer to the SED1374 Hardware
Functional Specification, document number X26A-A-001-xx for details.
The tables below show those configuration settings important to the MC68K #1 and
Generic #1 host bus interfaces.
Table 4-1: Summary of Power-On/Reset Options
SED1374
Pin Name
CNF0
CNF1
CNF2
CNF3
CNF4
value on this pin at the rising edge of RESET# is used to configure: (1/0)
0
1
See “Host Bus Selection” table below See “Host Bus Selection” table below
Little Endian
Active low LCDPWR signal
Big Endian
Active high LCDPWR signal
= configuration for MC68328 support
Table 4-2: Host Bus Interface Selection
CNF2
0
0
0
0
1
1
1
1
1
1
CNF1
0
0
1
1
0
0
1
1
1
1
CNF0
0
1
0
1
0
1
0
0
1
1
BS#
X
X
X
X
X
X
0
1
0
1
Host Bus Interface
SH-4 interface
SH-3 interface
reserved
MC68K #1, 16-bit
reserved
MC68K #2, 16-bit
reserved
reserved
Generic #1, 16-bit
Generic #2, 16-bit
= configuration for MC68328 using Generic #1 host bus interface
= configuration for MC68328 using MC68K #1 host bus interface
4.3 MC68328 Chip Select Configuration
The SED1374 requires a 64K byte address space for the display buffer and its internal
registers. To accommodate this block size, it is preferable (but not required) to use one of
the chip selects from groups A or B. Virtually any chip select other than CSA0 or CSD3
would be suitable for the SED1374 interface.
In the example interface, chip select CSB3 is used to control the SED1374. A 64K byte
address space is used with the SED1374 control registers mapped into the top 32 bytes of
the 64K byte block and the 40K bytes of display buffer mapped to the starting address of
the block. The chip select should have its RO (Read Only) bit set to 0, and the WAIT field
(Wait states) should be set to 111b to allow the SED1374 to terminate bus cycles externally.
SED1374
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5 Software
Test utilities and Windows® CE v2.0 display drivers are available for the SED1374. Full
source code is available for both the test utilities and the drivers.
The test utilities are configurable for different panel types using a program called
1374CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can
be customized by the OEM for different panel types, resolutions and color depths only by
modifying the source.
The SED1374 test utilities and Windows CE v2.0 display drivers are available from your
sales support contact or on the internet at http://www.erd.epson.com.
Interfacing to the Motorola MC68328 ‘Dragonball’ Microprocessor
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6 References
6.1 Documents
• Motorola Inc., MC68328 DragonBall® Integrated Microprocessor User’s Manual,
Motorola Publication no. MC68328UM/AD; available on the Internet at
http://www.mot.com/SPS/WIRELESS/products/MC68328.html.
• Epson Research and Development, Inc., SED1374 Hardware Functional Specification;
Document Number X26A-A-001-xx.
• Epson Research and Development, Inc., SDU1374B0C Rev. 1.0 ISA Bus Evaluation
Board User Manual; Document Number X26A-G-005-xx.
• Epson Research and Development, Inc., SED1374 Programming Notes and Examples;
Document Number X26A-G-002-xx.
6.2 Document Sources
• Motorola Inc.: Motorola Literature Distribution Center, (800) 441-2447.
• Motorola Website: http://www.mot.com.
• Epson Research and Development Website: http://www.erd.epson.com.
SED1374
X26A-G-007-02
Interfacing to the Motorola MC68328 ‘Dragonball’ Microprocessor
Issue Date: 99/01/05
Epson Research and Development
Vancouver Design Center
Page 17
7 Technical Support
7.1 EPSON LCD Controllers (SED1374)
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
7.2 Motorola MC68328 Processor
• Motorola Design Line, (800) 521-6274.
• Local Motorola sales office or authorized distributor.
Interfacing to the Motorola MC68328 ‘Dragonball’ Microprocessor
Issue Date: 99/01/05
SED1374
X26A-G-007-02
Page 18
Epson Research and Development
Vancouver Design Center
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SED1374
X26A-G-007-02
Interfacing to the Motorola MC68328 ‘Dragonball’ Microprocessor
Issue Date: 99/01/05
SED1374 Embedded Memory Color LCD Controller
Interfacing to the NEC VR4102™
Microprocessor
Document Number: X26A-G-008-04
Copyright © 1998, 1999 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-G-008-04
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/01/05
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Interfacing to the NEC VR4102 . .
2.1 The NEC VR4102 System Bus . .
2.1.1 Overview . . . . . . . . . .
2.1.2 LCD Memory Access Cycles
3
SED1374 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Bus Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Generic #2 Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
VR4102 to SED1374 Interface . . .
4.1 Hardware Description . . . . .
4.2 SED1374 Hardware Configuration
4.3 NEC VR4102 Configuration . . .
5
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1 Epson LCD Controllers (SED1374) . . . . . . . . . . . . . . . . . . . . . . 18
7.2 NEC Electronics Inc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/01/05
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SED1374
X26A-G-008-04
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Epson Research and Development
Vancouver Design Center
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SED1374
X26A-G-008-04
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/01/05
Epson Research and Development
Vancouver Design Center
Page 5
List of Tables
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4-1: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4-2: Host Bus Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
List of Figures
Figure 2-1: NEC VR4102 Read/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4-1: Typical Implementation of VR4102 to SED1374 Interface . . . . . . . . . . . . . . . . 13
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/01/05
SED1374
X26A-G-008-04
Page 6
Epson Research and Development
Vancouver Design Center
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SED1374
X26A-G-008-04
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/01/05
Epson Research and Development
Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware required to provide an interface between the
SED1374 Embedded Memory LCD Controller and the NEC VR4102 Microprocessor
(uPD30102). The NEC VR4102 Microprocessor is specifically designed to support an
external LCD controller and the pairing of these two devices results in an embedded system
offering impressive display capability with very low power consumption.
The designs described in this document are presented only as examples of how such
interfaces might be implemented. This application note will be updated as appropriate.
Please check the Epson Research and Development Website at http://www.erd.epson.com
for the latest revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/01/05
SED1374
X26A-G-008-04
Page 8
Epson Research and Development
Vancouver Design Center
2 Interfacing to the NEC VR4102
2.1 The NEC VR4102 System Bus
The VR-Series family of microprocessors features a high-speed synchronous system bus
typical of modern microprocessors. Designed with external LCD controller support and
Windows CE-based embedded consumer applications in mind, the VR4102 offers a highly
integrated solution for portable systems. This section is an overview of the operation of the
CPU bus to establish interface requirements.
2.1.1 Overview
The NEC VR4102 is designed around the RISC architecture developed by MIPS. This
microprocessor is designed around the 66MHz VR4100 CPU core which supports 64-bit
processing. The CPU communicates with the Bus Control Unit (BCU) with its internal
SysAD bus. The BCU in turn communicates with external devices with its ADD and DAT
buses that can be dynamically sized to 16 or 32-bit operation.
The NEC VR4102 has direct support for an external LCD controller. Specific control
signals are assigned for an external LCD controller that provide an easy interface to the
CPU. A 16M byte block of memory is assigned for the LCD controller with its own chip
select and ready signals available. Word or byte accesses are controlled by the system high
byte signal, SHB#.
SED1374
X26A-G-008-04
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/01/05
Epson Research and Development
Vancouver Design Center
Page 9
2.1.2 LCD Memory Access Cycles
Figure 2-1: “NEC VR4102 Read/Write Cycles,” on page 9 shows the read and write cycles
to the LCD Controller Interface.
Once an address in the LCD block of memory is placed on the external address bus,
ADD[25:0], the LCD chip select, LCDCS#, is driven low. The read or write enable signals,
RD# and WR#, are driven low for the appropriate cycle and LCDRDY is driven low to
insert wait states into the cycle. The high byte enable is driven low for 16-bit transfers and
high for 8-bit transfers.
TCLK
ADD[25:0]
VALID
SHB#
LCDCS#
WR#,RD#
D[15:0]
(write)
VALID
Hi-Z
D[15:0]
(read)
VALID
Hi-Z
LCDRDY
Figure 2-1: NEC VR4102 Read/Write Cycles
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/01/05
SED1374
X26A-G-008-04
Page 10
Epson Research and Development
Vancouver Design Center
3 SED1374 Host Bus Interface
This section is a summary of the host bus interface modes available on the SED1374 and
offers some detail on the Generic #2 host bus interface used to implement the interface to
the VR4102.
3.1 Bus Interface Modes
The SED1374 implements a 16-bit interface to the host microprocessor which may operate
in one of several modes compatible with most of the popular embedded microprocessor
families. Six bus interface modes are supported:
• Hitachi SH-4.
• Hitachi SH-3
• Motorola MC68000 (using Upper Data Strobe/Lower Data Strobe).
• Motorola MC68020/MC68030/MC683xx (using Data Strobe/DSACKx).
• Generic #1 (Chip Select, plus individual Read Enable/Write Enable for each byte).
• Generic #2 (External Chip Select, shared Read/Write Enable for high byte, individual
Read/Write Enable for low byte).
The SED1374 latches CNF[2:0] and BS# to allow selection of the host bus interface on the
rising edge of RESET#. After releasing reset, the bus interface signals assume their selected
configuration. The following table shows the functions of each host bus interface signal.
Table 3-1: Host Bus Interface Pin Mapping
SED1374
Pin Names
SH-3
SH-4
MC68K #1
MC68K #2
Generic #1
Generic #2
AB[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
AB0
A0
A0
LDS#
A0
A0
A0
DB[15:0]
D[15:0]
D[15:0]
D[15:0]
D[31:16]
D[15:0]
D[15:0]
WE1#
WE1#
WE1#
UDS#
DS#
WE1#
BHE#
CS#
CSn#
CSn#
External Decode
BCLK
CKIO
CKIO
CLK
CLK
BCLK
BCLK
BS#
BS#
BS#
AS#
AS#
connect to VSS
connect to IO VDD
RD/WR#
RD/WR#
RD/WR#
R/W#
R/W#
RD1#
connect to IO VDD
RD#
RD#
RD#
connect to IO VDD
SIZ1
RD0#
RD#
WE0#
WE0#
WE0#
connect to IO VDD
SIZ0
WE0#
WE#
WAIT#
WAIT#
RDY#
DTACK#
DSACK1#
WAIT#
WAIT#
RESET#
RESET#
RESET#
RESET#
RESET#
RESET#
RESET#
SED1374
X26A-G-008-04
External Decode External Decode
External Decode
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/01/05
Epson Research and Development
Vancouver Design Center
Page 11
Two other configuration options (CNF[4:3]) are also made at time of hardware reset:
• endian mode setting (big endian or little endian).
• polarity of the LCDPWR signal.
The capability to select the endian mode independent of the host bus interface offers more
flexibility in configuring the SED1374 with other CPUs.
For details on configuration, refer to the SED1374 Hardware Functional Specification,
document number X26A-A-001-xx.
3.2 Generic #2 Interface Mode
Generic #2 interface mode is a general and non-processor-specific interface mode on the
SED1374. The Generic # 2 interface mode was chosen for this interface due to the
simplicity of its timing and compatibility with the VR4102 control signals.
The interface requires the following signals:
• BUSCLK is a clock input which synchronizes transfers between the host CPU and the
SED1374. It is separate from the input clock (CLKI) and is typically driven by the host
CPU system clock.
• The address inputs AB0 through AB15, and the data bus DB0 through DB15, connect
directly to the CPU address and data bus, respectively. On 32-bit big endian architectures such as the Power PC, the data bus would connect to the high-order data lines; on
little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data
lines. The hardware engineer must ensure that CNF3 selects the proper endian mode
upon reset.
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper
IO or memory address space.
• WE1# is the high byte enable for both read and write cycles and WE0# is the enable
signal for a write access. These must be generated by external decode hardware based
upon the control outputs from the host CPU.
• RD# is the read enable for the SED1374, to be driven low when the host CPU is reading
data from the SED1374. RD# must be generated by external decode hardware based
upon the control outputs from the host CPU.
• WAIT# is a signal which is output from the SED1374 to the host CPU that indicates
when data is ready (read cycle) or accepted (write cycle) on the host bus. Since host
CPU accesses to the SED1374 may occur asynchronously to the display update, it is
possible that contention may occur in accessing the 1374 internal registers and/or
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/01/05
SED1374
X26A-G-008-04
Page 12
Epson Research and Development
Vancouver Design Center
refresh memory. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete. This signal is active low and may need to be
inverted if the host CPU wait state signal is active high.
• The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in the bus interface for Generic #2 mode. However, BS# is used to configure the SED1374 for
Generic #2 mode and should be tied high (connected to IO VDD). RD/WR# should also
be tied high.
SED1374
X26A-G-008-04
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/01/05
Epson Research and Development
Vancouver Design Center
Page 13
4 VR4102 to SED1374 Interface
4.1 Hardware Description
The NEC VR4102 Microprocessor is specifically designed to support an external LCD
controller by providing the internal address decoding and control signals necessary. By
using the Generic # 2 interface, only one inverter is required to change the polarity of the
system reset signal to active low. A pull-up resistor is attached to WAIT# to speed up its
rise time when terminating a cycle.
The following diagram shows a typical implementation of the VR4102 to SED1374
interface.
NEC VR4102
SED1374
WR#
WE0#
SHB#
WE1#
RD#
RD#
LCDCS#
CS#
Pull-up
LCDRDY
WAIT#
RSTOUT
RESET#
ADD[15:0]
AB[15:0]
DATA[15:0]
DB[15:0]
BUSCLK
BUSCLK
Vcc
BS#
Vcc
RD/WR#
Figure 4-1: Typical Implementation of VR4102 to SED1374 Interface
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/01/05
SED1374
X26A-G-008-04
Page 14
Epson Research and Development
Vancouver Design Center
4.2 SED1374 Hardware Configuration
The SED1374 uses CNF4 through CNF0 and BS# to allow selection of the bus mode and
other configuration data on the rising edge of RESET#. Refer to the SED1374 Hardware
Functional Specification, document number X26A-A-001-xx for details.
The tables below show those configuration settings important to the Generic #2 host bus
interface.
Table 4-1: Summary of Power-On/Reset Options
Signal
value on this pin at the rising edge of RESET# is used to configure: (0/1)
0
1
CNF0
CNF1
See “Host Bus Selection” table below See “Host Bus Selection” table below
CNF2
CNF3
Little Endian
Big Endian
CNF4
Active low LCDPWR signal
Active high LCDPWR signal
= configuration for NEC VR4102 support
Table 4-2: Host Bus Selection
CNF2
CNF1
CNF0
BS#
0
0
0
X
SH-4 interface
Host Bus Interface
0
0
1
X
SH-3 interface
0
1
0
X
reserved
0
1
1
X
MC68K #1, 16-bit
1
0
0
X
reserved
1
0
1
X
MC68K #2, 16-bit
1
1
0
0
reserved
1
1
0
1
reserved
1
1
1
0
Generic #1, 16-bit
1
1
1
1
Generic #2, 16-bit
= configuration for NEC VR4102 support
SED1374
X26A-G-008-04
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/01/05
Epson Research and Development
Vancouver Design Center
Page 15
4.3 NEC VR4102 Configuration
The NEC VR4102 provides the internal address decoding necessary to map to an external
LCD controller. Physical address 0A000000h to 0AFFFFFFh (16M bytes) is reserved for
an external LCD controller.
The SED1374 supports up to 40K bytes of display buffer memory and 32 bytes for internal
registers. Therefore, the SED1374 will be shadowed over the entire 16M byte memory
range at 64K byte segments. The starting address of the display buffer is 0A000000h and
register 0 of the SED1374 (REG[00h]) resides at 0A00FFE0h.
The NEC VR4102 has a 16-bit internal register named BCUCNTREG2 located at address
0B000002h. It must be set to the value of 0001h to indicate that LCD controller accesses
use a non-inverting data bus.
The 16-bit internal register named BCUCNTREG1, located at address 0B000000h, must
have bit D[13] (ISA/LCD bit) set to 0 to reserve the 16M bytes space, 0A000000h to
0AFFFFFFh, for LCD use and not as ISA bus memory space.
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/01/05
SED1374
X26A-G-008-04
Page 16
Epson Research and Development
Vancouver Design Center
5 Software
Test utilities and Windows® CE v2.0 display drivers are available for the SED1374. Full
source code is available for both the test utilities and the drivers.
The test utilities are configurable for different panel types using a program called
1374CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can
be customized by the OEM for different panel types, resolutions and color depths only by
modifying the source.
The SED1374 test utilities and Windows CE v2.0 display drivers are available from your
sales support contact or on the internet at http://www.erd.epson.com.
SED1374
X26A-G-008-04
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/01/05
Epson Research and Development
Vancouver Design Center
Page 17
6 References
6.1 Documents
• NEC VR4102 64/32-bit Microprocessor Preliminary User’s Manual.
• Epson Research and Development, Inc., SED1374 Embedded Memory Color LCD
Controller Hardware Functional Specification; Document Number X26A-A-001-xx.
• Epson Research and Development, Inc., SDU1374B0C Rev. 1.0 ISA Bus Evaluation
Board User Manual; Document Number X26A-G-005-xx.
• Epson Research and Development, Inc., SED1374 Programming Notes and Examples;
Document Number X26A-G-002-xx.
6.2 Document Sources
• NEC web page : http://www.nec.com.
• Epson Research and Development web page: http://www.erd.epson.com
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/01/05
SED1374
X26A-G-008-04
Page 18
Epson Research and Development
Vancouver Design Center
7 Technical Support
7.1 Epson LCD Controllers (SED1374)
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
7.2 NEC Electronics Inc.
NEC Electronics Inc. (U.S.A.)
Santa Clara
California
Tel: (800) 366-9782
Fax: (800) 729-9288
http://www.nec.com
SED1374
X26A-G-008-04
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/01/05
SED1374 Embedded Memory Color LCD Controller
Interfacing to the PC Card Bus
Document Number: X26A-G-009-02
Copyright © 1998 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-G-009-02
Interfacing to the PC Card Bus
Issue Date: 98/12/10
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Interfacing to the PC Card Bus
2.1 The PC Card System Bus . .
2.1.1 PC Card Overview . .
2.1.2 Memory Access Cycles
3
SED1374 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Bus Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Generic #1 Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
PC Card to SED1374 Interface . . .
4.1 Hardware Connections . . . . .
4.2 SED1374 Hardware Configuration
4.3 PAL Equations . . . . . . . .
4.4 Register/Memory Mapping . . .
5
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1 EPSON LCD Controllers (SED1374) . . . . . . . . . . . . . . . . . . . . . 17
7.2 PC Card Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Interfacing to the PC Card Bus
Issue Date: 98/12/10
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X26A-G-009-02
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SED1374
X26A-G-009-02
Interfacing to the PC Card Bus
Issue Date: 98/12/10
Epson Research and Development
Vancouver Design Center
Page 5
List of Tables
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4-1: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4-2: Host Bus Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
List of Figures
Figure 2-1: PC Card Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2-2: PC Card Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4-1: Typical Implementation of PC Card to SED1374 Interface . . . . . . . . . . . . . . . . 12
Interfacing to the PC Card Bus
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X26A-G-009-02
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SED1374
X26A-G-009-02
Interfacing to the PC Card Bus
Issue Date: 98/12/10
Epson Research and Development
Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware and software environment required to provide
an interface between the SED1374 Embedded Memory LCD Controller and the PC Card
(PCMCIA) bus.
The designs described in this document are presented only as examples of how such
interfaces might be implemented. This application note will be updated as appropriate.
Please check the Epson Research and Development Website at http://www.erd.epson.com
for the latest revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
Interfacing to the PC Card Bus
Issue Date: 98/12/10
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X26A-G-009-02
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Epson Research and Development
Vancouver Design Center
2 Interfacing to the PC Card Bus
2.1 The PC Card System Bus
PC Card technology has gained wide acceptance in the mobile computing field as well as
in other markets due to its portability and ruggedness. This section is an overview of the
operation of the 16-bit PC Card interface conforming to the PCMCIA 2.0/JEIDA 4.1
Standard (or later).
2.1.1 PC Card Overview
The 16-bit PC Card provides a 26-bit address bus and additional control lines which allow
access to three 64M byte address ranges. These ranges are used for common memory space,
IO space, and attribute memory space. Common memory may be accessed by a host system
for memory read and write operations. Attribute memory is used for defining card specific
information such as configuration registers, card capabilities, and card use. IO space
maintains software and hardware compatibility with hosts such as the Intel x86
architecture, which address peripherals independently from memory space.
Bit notation follows the convention used by most micro-processors, the high bit is the most
significant. Therefore, signals A25 and D15 are the most significant bits for the address and
data bus respectively.
Support is provided for on-chip DMA controllers. To find further information on these
topics, refer to Section 6, “References” on page 16.
PC Card bus signals are asynchronous to the host CPU bus signals. Bus cycles are started
with the assertion of either the CE1# and/or the CE2# card enable signals. The cycle ends
once these signals are de-asserted. Bus cycles can be lengthened using the WAIT# signal.
Note
The PCMCIA 2.0/JEIDA 4.1 (and later) PC Card Standard support the two signals
WAIT# and RESET which are not supported in earlier versions of the standard. The
WAIT# signal allows for asynchronous data transfers for memory, attribute, and IO access cycles. The RESET signal allows resetting of the card configuration by the reset
line of the host CPU.
2.1.2 Memory Access Cycles
A data transfer is initiated when the memory address is placed on the PC Card bus and one,
or both, of the card enable signals (CE1# and CE2#) are driven low. REG# must be kept
inactive. If only CE1# is driven low, 8-bit data transfers are enabled and A0 specifies
whether the even or odd data byte appears on data bus lines D[7:0]. If both CE1# and CE2#
are driven low, a 16-bit word transfer takes place. If only CE2# is driven low, an odd byte
transfer occurs on data lines D[15:8].
SED1374
X26A-G-009-02
Interfacing to the PC Card Bus
Issue Date: 98/12/10
Epson Research and Development
Vancouver Design Center
Page 9
During a read cycle, OE# (output enable) is driven low. A write cycle is specified by
driving OE# high and driving the write enable signal (WE#) low. The cycle can be
lengthened by driving WAIT# low for the time needed to complete the cycle.
Figure 2-1: and Figure 2-2: illustrate typical memory access cycles on the PC Card bus.
A[25:0]
REG#
ADDRESS VALID
CE1#
CE2#
OE#
WAIT#
Hi-Z
D[15:0]
Hi-Z
DATA VALID
Transfer Start
Transfer Complete
Figure 2-1: PC Card Read Cycle
A[25:0]
REG#
ADDRESS VALID
CE1#
CE2#
OE#
WE#
WAIT#
Hi-Z
D[15:0]
DATA VALID
Transfer Start
Hi-Z
Transfer Complete
Figure 2-2: PC Card Write Cycle
Interfacing to the PC Card Bus
Issue Date: 98/12/10
SED1374
X26A-G-009-02
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Epson Research and Development
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3 SED1374 Bus Interface
This section is a summary of the host bus interface modes available on the SED1374 and
offers some detail on the Generic #1 host bus interface used to implement the interface to
the PC Card bus.
3.1 Bus Interface Modes
The SED1374 implements a 16-bit interface to the host microprocessor which may operate
in one of several modes compatible with most of the popular embedded microprocessor
families. Six bus interface modes are supported:
• Hitachi SH-4.
• Hitachi SH-3
• Motorola MC68000 (using Upper Data Strobe/Lower Data Strobe).
• Motorola MC68020/MC68030/MC683xx (using Data Strobe/DSACKx).
• Generic #1 (Chip Select, plus individual Read Enable/Write Enable for each byte).
• Generic #2 (External Chip Select, shared Read/Write Enable for high byte, individual
Read/Write Enable for low byte).
The SED1374 latches CNF[2:0] and BS# to allow selection of the host bus interface on the
rising edge of RESET#. After releasing reset, the bus interface signals assume their selected
configuration. The following table shows the functions of each host bus interface signal.
Table 3-1: Host Bus Interface Pin Mapping
SED1374
Pin Names
SH-3
SH-4
MC68K #1
MC68K #2
Generic #1
Generic #2
AB[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
AB0
A0
A0
LDS#
A0
A0
A0
DB[15:0]
D[15:0]
D[15:0]
D[15:0]
D[31:16]
D[15:0]
D[15:0]
WE1#
WE1#
WE1#
UDS#
DS#
WE1#
BHE#
CS#
CSn#
CSn#
External Decode
BCLK
CKIO
CKIO
CLK
CLK
BCLK
BCLK
BS#
BS#
BS#
AS#
AS#
connect to VSS
connect to IO VDD
RD/WR#
RD/WR#
RD/WR#
R/W#
R/W#
RD1#
connect to IO VDD
RD#
RD#
RD#
connect to IO VDD
SIZ1
RD0#
RD#
WE0#
WE0#
WE0#
connect to IO VDD
SIZ0
WE0#
WE#
WAIT#
WAIT#
RDY#
DTACK#
DSACK1#
WAIT#
WAIT#
RESET#
RESET#
RESET#
RESET#
RESET#
RESET#
RESET#
SED1374
X26A-G-009-02
External Decode External Decode
External Decode
Interfacing to the PC Card Bus
Issue Date: 98/12/10
Epson Research and Development
Vancouver Design Center
Page 11
Two other configuration options (CNF[4:3]) are also made at time of hardware reset:
• endian mode setting (big endian or little endian).
• polarity of the LCDPWR signal.
The capability to select the endian mode independent of the host bus interface offers more
flexibility in configuring the SED1374 with other CPUs.
For details on configuration, refer to the SED1374 Hardware Functional Specification,
document number X26A-A-001-xx.
3.2 Generic #1 Interface Mode
Generic #1 interface mode is the most general and least processor-specific interface mode
on the SED1374. The Generic # 1 interface mode was chosen for this interface due to the
simplicity of its timing.
The interface requires the following signals:
• BUSCLK is a clock input which is required by the SED1374 host interface. It is separate
from the input clock (CLKI) and is typically driven by the host CPU system clock.
• The address inputs AB0 through AB15, and the data bus DB0 through DB15, connect
directly to the CPU address and data bus, respectively. On 32-bit big endian architectures such as the Power PC, the data bus would connect to the high-order data lines; on
little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data
lines. The hardware engineer must ensure that CNF3 selects the proper endian mode
upon reset.
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper
IO or memory address space.
• WE0# and WE1# are write enables for the low-order and high-order bytes, respectively,
to be driven low when the host CPU is writing data to the SED1374. These signals must
be generated by external hardware based on the control outputs from the host CPU.
• RD# and RD/WR# are read enables for the low-order and high-order bytes, respectively,
to be driven low when the host CPU is reading data from the SED1374. These signals
must be generated by external hardware based on the control outputs from the host CPU.
• WAIT# is a signal output from the SED1374 that indicates the host CPU must wait until
data is ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU
accesses to the SED1374 may occur asynchronously to the display update, it is possible
that contention may occur in accessing the SED1374 internal registers and/or refresh
memory. The WAIT# line resolves these contentions by forcing the host to wait until the
resource arbitration is complete. This signal is active low and may need to be inverted if
the host CPU wait state signal is active high.
• The Bus Status (BS#) signal is not used in the bus interface for Generic #1 mode.
However, BS# is used to configure the SED1374 for Generic #1 mode and should be
tied low (connected to GND).
Interfacing to the PC Card Bus
Issue Date: 98/12/10
SED1374
X26A-G-009-02
Page 12
Epson Research and Development
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4 PC Card to SED1374 Interface
4.1 Hardware Connections
The SED1374 is interfaced to the PC Card interface with a minimal amount of glue logic.
A PAL is used to decode the write and read signals of the PC Card bus to generate RD#,
RD/WR#, WE0#, WE1#, and CS# for the SED1374. The PAL also inverts the reset signal
of the PC card since it is active high and the SED1374 uses an active low reset. For PAL
equations for this implementation refer to Section 4.3, “PAL Equations” on page 14.
In this implementation, the address inputs (AB[15:0]) and data bus (DB[15:0] connect
directly to the CPU address (A[15:0]) and data bus (D[15:0]).
The PC Card interface does not provide a bus clock, so one must be supplied for the
SED1374. Since the bus clock frequency is not critical, nor does it have to be synchronous
to the bus signals, it may be the same as CLKI.
BS# (bus start) is not used by Generic #1 mode but is used to configure the SED1374 for
Generic #1 and should be tied low (connected to GND).
The following diagram shows a typical implementation of the PC Card to SED1374
interface.
PC Card socket
SED1374
PAL16L8-15
RD#
OE#
WE#
RD/WR#
CE1#
CE2#
WE0#
REG#
CS#
WE1#
RESET
RESET#
AB[15:0]
A[15:0]
D[15:0]
DB[15:0]
15K pull-up
WAIT#
WAIT#
BUSCLK
Oscillator
CLKI
Figure 4-1: Typical Implementation of PC Card to SED1374 Interface
SED1374
X26A-G-009-02
Interfacing to the PC Card Bus
Issue Date: 98/12/10
Epson Research and Development
Vancouver Design Center
Page 13
4.2 SED1374 Hardware Configuration
The SED1374 uses CNF4 through CNF0 and BS# to allow selection of the bus mode and
other configuration data on the rising edge of RESET#. Refer to the SED1374 Hardware
Functional Specification, document number X26A-A-001-xx for details.
The tables below show only those configuration settings important to the PC Card host bus
interface.
Table 4-1: Summary of Power-On/Reset Options
Signal
Low
High
CNF0
CNF1
See “Host Bus Selection” table below See “Host Bus Selection” table below
CNF2
CNF3
Little Endian
Big Endian
CNF4
Active low LCDPWR signal
Active high LCDPWR signal
= configuration for PC Card host bus interface
Table 4-2: Host Bus Interface Selection
CNF2
CNF1
CNF0
BS#
Host Bus Interface
0
0
0
X
SH-4 bus interface
0
0
1
X
SH-3 bus interface
0
1
0
X
reserved
0
1
1
X
MC68K bus interface #1, 16-bit
1
0
0
X
reserved
1
0
1
X
MC68K bus interface #2, 16-bit
1
1
0
0
reserved
1
1
0
1
reserved
1
1
1
0
Generic #1, 16-bit
1
1
1
1
Generic #2, 16-bit
= configuration for PC Card host bus interface
Interfacing to the PC Card Bus
Issue Date: 98/12/10
SED1374
X26A-G-009-02
Page 14
Epson Research and Development
Vancouver Design Center
4.3 PAL Equations
The PAL equations for the implementation presented in this document are as follows.
PAL
device
‘16L8’;
OE
WE
CE1
CE2
REG
PCRESET
RESET
WE0
WE1
RD
RDWR
CS
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
1;
2;
3;
4;
5;
6;
14;
15;
16;
17;
18;
19;
equations
!WE0 = !WE & !CE1 & REG;
!WE1 = !WE & !CE2 & REG;
!CS = REG & (!RD # !RDWR # !WE0 # !WE1);
!RD = !OE & !CE1 & REG;
!RDWR = !OE & !CE2 & REG;
!RESET = PCRESET;
4.4 Register/Memory Mapping
The SED1374 is a memory mapped device. The SED1374 memory may be addressed
starting at 0000h, or on consecutive 64K byte blocks, and its internal registers are located
in the upper 32 bytes of the 64K byte block (i.e. REG[0] = FFE0h).
While the PC Card socket provides 64M bytes of address space, the SED1374 only needs
a 64K byte block of memory to accommodate its 40K byte display buffer and its 32 byte
register set. For this reason only address bits A[15:0] are used while A[25:16] are ignored.
Because the entire 64M bytes of memory is available, the SED1374’s memory and registers
will be aliased every 64K bytes for a total of 1024 times.
Note
If aliasing is not desirable, the upper addresses must be fully decoded.
SED1374
X26A-G-009-02
Interfacing to the PC Card Bus
Issue Date: 98/12/10
Epson Research and Development
Vancouver Design Center
Page 15
5 Software
Test utilities and Windows® CE v2.0 display drivers are available for the SED1374. Full source
code is available for both the test utilities and the drivers.
The test utilities are configurable for different panel types using a program called 1374CFG, or by
directly modifying the source. The Windows CE v2.0 display drivers can be customized by the OEM
for different panel types, resolutions and color depths only by modifying the source.
The SED1374 test utilities and Windows CE v2.0 display drivers are available from your sales
support contact or on the internet at http://www.erd.epson.com.
Interfacing to the PC Card Bus
Issue Date: 98/12/10
SED1374
X26A-G-009-02
Page 16
Epson Research and Development
Vancouver Design Center
6 References
6.1 Documents
• PC Card (PCMCIA) Standard March 1997
• Epson Research and Development, Inc., SED1374 Embedded Memory Color LCD
Controller Hardware Functional Specification; Document Number X26A-A-001-xx.
• Epson Research and Development, Inc., SDU1374B0C Rev. 1.0 ISA Bus Evaluation
Board User Manual; Document Number X26A-G-005-xx.
• Epson Research and Development, Inc., SED1374 Programming Notes and Examples;
Document Number X26A-G-002-xx.
6.2 Document Sources
• PC Card web page: http://www.pc-card.com.
• EPSON Research and Development web page: http://www.erd.epson.com
SED1374
X26A-G-009-02
Interfacing to the PC Card Bus
Issue Date: 98/12/10
Epson Research and Development
Vancouver Design Center
Page 17
7 Technical Support
7.1 EPSON LCD Controllers (SED1374)
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
7.2 PC Card Standard
PCMCIA
(Personal Computer Memory Card International Association)
2635 North First Street, Suite 209
San Jose, CA 95134
Tel: (408) 433-2273
Fax: (408) 433-9558
http://www.pc-card.com
Interfacing to the PC Card Bus
Issue Date: 98/12/10
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X26A-G-009-02
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SED1374
X26A-G-009-02
Interfacing to the PC Card Bus
Issue Date: 98/12/10
SED1374 Embedded Memory Color LCD Controller
Interfacing to the Motorola MPC821
Microprocessor
Document Number: X26A-G-010-02
Copyright © 1998, 1999 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.
Page 2
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SED1374
X26A-G-010-02
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 99/01/05
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Interfacing to the MPC821 . . . . . . . . . . . . . . . .
2.1 The MPC8xx System Bus . . . . . . . . . . . . .
2.2 MPC821 Bus Overview . . . . . . . . . . . . .
2.2.1 Normal (Non-Burst) Bus Transactions . . . . . . .
2.2.2 Burst Cycles . . . . . . . . . . . . . . . . . . . . .
2.3 Memory Controller Module . . . . . . . . . . . .
2.3.1 General-Purpose Chip Select Module (GPCM) . . .
2.3.2 User-Programmable Machine (UPM) . . . . . . . .
3
SED1374 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Host Bus Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Generic #1 Host Bus Interface Mode . . . . . . . . . . . . . . . . . . . . . 14
4
MPC821 to SED1374 Interface . . .
4.1 Hardware Description . . . . .
4.2 Hardware Connections . . . . .
4.3 SED1374 Hardware Configuration
4.4 MPC821 Chip Select Configuration
4.5 Test Software . . . . . . . .
5
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1 EPSON LCD/CRT Controllers (SED1374) . . . . . . . . . . . . . . . . . . . 24
7.2 Motorola MPC821 Processor . . . . . . . . . . . . . . . . . . . . . . . . 24
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 99/01/05
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X26A-G-010-02
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SED1374
X26A-G-010-02
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 99/01/05
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Vancouver Design Center
Page 5
List of Tables
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . .
Table 4-1: List of Connections from MPC821ADS to SED1374
Table 4-2: Configuration Settings . . . . . . . . . . . . . . . . .
Table 4-3: Host Bus Selection . . . . . . . . . . . . . . . . . . .
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List of Figures
Figure 2-1: Power PC Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2-2: Power PC Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4-1: Typical Implementation of MPC821 to SED1374 Interface . . . . . . . . . . . . . . . . 15
Interfacing to the Motorola MPC821 Microprocessor
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SED1374
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Interfacing to the Motorola MPC821 Microprocessor
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1 Introduction
This application note describes the hardware and software environment required to provide
an interface between the SED1374 Embedded Memory LCD Controller and the Motorola
MPC821 Processor.
The designs described in this document are presented only as examples of how such
interfaces might be implemented. This application note will be updated as appropriate.
Please check the Epson Research and Development Website at http://www.erd.epson.com
for the latest revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
Interfacing to the Motorola MPC821 Microprocessor
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2 Interfacing to the MPC821
2.1 The MPC8xx System Bus
The MPC8xx family of processors feature a high-speed synchronous system bus typical of
modern RISC microprocessors. This section provides an overview of the operation of the
CPU bus in order to establish interface requirements.
2.2 MPC821 Bus Overview
The MPC8xx microprocessor family uses a synchronous address and data bus. All IO is
synchronous to a square-wave reference clock called MCLK (Master Clock). This clock
runs at the machine cycle speed of the CPU core (typically 25 to 50 MHz). Most outputs
from the processor change state on the rising edge of this clock. Similarly, most inputs to
the processor are sampled on the rising edge.
Note
The external bus can run at one-half the CPU core speed using the clock control register.
This is typically used when the CPU core is operated above 50 MHz.
The MPC821 can generate up to eight independent chip select outputs, each of which may
be controlled by one of two types of timing generators: the General Purpose Chip Select
Module (GPCM) or the User-Programmable Machine (UPM). Examples are given using
the GPCM.
It should be noted that all Power PC microprocessors, including the MPC8xx family, use
bit notation opposite from the convention used by most other microprocessor systems. Bit
numbering for the MPC8xx always starts with zero as the most significant bit, and increments in value to the least-significant bit. For example, the most significant bits of the
address bus and data bus are A0 and D0, while the least significant bits are A31 and D31.
The MPC8xx uses both a 32-bit address and data bus. A parity bit is supported for each of
the four byte lanes on the data bus. Parity checking is done when data is read from external
memory or peripherals, and generated by the MPC8xx bus controller on write cycles. All
IO accesses are memory-mapped meaning there is no separate IO space in the Power PC
architecture.
Support is provided for both on-chip (DMA controllers) and off-chip (other processors and
peripheral controllers) bus masters. For further information on this topic, refer to Section
6, “References” on page 23.
The bus can support both normal and burst cycles. Burst memory cycles are used to fill
on-chip cache memory, and for certain on-chip DMA operations. Normal cycles are used
for all other data transfers.
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2.2.1 Normal (Non-Burst) Bus Transactions
A data transfer is initiated by the bus master by placing the memory address on address
lines A0 through A31 and driving TS (Transfer Start) low for one clock cycle. Several
control signals are also provided with the memory address:
• TSIZ[0:1] (Transfer Size) -- indicates whether the bus cycle is 8, 16, or 32-bit.
• RD/WR -- set high for read cycles and low for write cycles.
• AT[0:3] (Address Type Signals) -- provides more detail on the type of transfer being
attempted.
When the peripheral device being accessed has completed the bus transfer, it asserts TA
(Transfer Acknowledge) for one clock cycle to complete the bus transaction. Once TA has
been asserted, the MPC821 will not start another bus cycle until TA has been de-asserted.
The minimum length of a bus transaction is two bus clocks.
Figure 2-1: “Power PC Memory Read Cycle” illustrates a typical memory read cycle on
the Power PC system bus.
SYSCLK
TS
TA
A[0:31]
RD/WR
TSIZ[0:1], AT[0:3]
D[0:31]
Sampled when TA low
Transfer Start
Wait States
Transfer
Complete
Next Transfer
Starts
Figure 2-1: Power PC Memory Read Cycle
Interfacing to the Motorola MPC821 Microprocessor
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Figure 2-2: “Power PC Memory Write Cycle” illustrates a typical memory write cycle on
the Power PC system bus.
SYSCLK
TS
TA
A[0:31]
RD/WR
TSIZ[0:1], AT[0:3]
D[0:31]
Transfer Start
Valid
Wait States
Transfer
Complete
Next Transfer
Starts
Figure 2-2: Power PC Memory Write Cycle
If an error occurs, TEA (Transfer Error Acknowledge) is asserted and the bus cycle is
aborted. For example, a peripheral device may assert TEA if a parity error is detected, or
the MPC821 bus controller may assert TEA if no peripheral device responds at the
addressed memory location within a bus time-out period.
For 32-bit transfers, all data lines (D[0:31]) are used and the two low-order address lines
A30 and A31 are ignored. For 16-bit transfers, data lines D0 through D15 are used and
address line A30 is ignored. For 8-bit transfers, data lines D0 through D7 are used and all
address lines (A[0:31]) are used.
Note
This assumes that the Power PC core is operating in big endian mode (typically the case
for embedded systems).
2.2.2 Burst Cycles
Burst memory cycles are used to fill on-chip cache memory and to carry out certain on-chip
DMA operations. They are very similar to normal bus cycles with the following exceptions:
• Always 32-bit.
• Always attempt to transfer four 32-bit words sequentially.
• Always address longword-aligned memory (i.e. A30 and A31 are always 0:0).
• Do not increment address bits A28 and A29 between successive transfers; the addressed
device must increment these address bits internally.
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If a peripheral is not capable of supporting burst cycles, it can assert Burst Inhibit (BI)
simultaneously with TA, and the processor will revert to normal bus cycles for the
remaining data transfers.
Burst cycles are mainly intended to facilitate cache line fills from program or data memory.
They are normally not used for transfers to/from IO peripheral devices such as the
SED1354, therefore the interfaces described in this document do not attempt to support
burst cycles. However, the example interfaces include circuitry to detect the assertion of
BDIP and respond with BI if caching is accidently enabled for the SED1354 address space.
2.3 Memory Controller Module
2.3.1 General-Purpose Chip Select Module (GPCM)
The General-Purpose Chip Select Module (GPCM) is used to control memory and
peripheral devices which do not require special timing or address multiplexing. In addition
to the chip select output, it can generate active-low Output Enable (OE) and Write Enable
(WE) signals compatible with most memory and x86-style peripherals. The MPC821 bus
controller also provides a Read/Write (RD/WR) signal which is compatible with most 68K
peripherals.
The GPCM is controlled by the values programmed into the Base Register (BR) and Option
Register (OR) of the respective chip select. The Option Register sets the base address, the
block size of the chip select, and controls the following timing parameters:
• The ACS bit field allows the chip select assertion to be delayed with respect to the
address bus valid, by 0, ¼, or ½ clock cycle.
• The CSNT bit causes chip select and WE to be negated ½ clock cycle earlier than
normal.
• The TRLX (relaxed timing) bit will insert an additional one clock delay between assertion of the address bus and chip select. This accommodates memory and peripherals
with long setup times.
• The EHTR (Extended hold time) bit will insert an additional 1-clock delay on the first
access to a chip select.
• Up to 15 wait states may be inserted, or the peripheral can terminate the bus cycle itself
by asserting TA (Transfer Acknowledge).
• Any chip select may be programmed to assert BI (Burst Inhibit) automatically when its
memory space is addressed by the processor core.
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2.3.2 User-Programmable Machine (UPM)
The UPM is typically used to control memory types, such as Dynamic RAMs, which have
complex control or address multiplexing requirements. The UPM is a general purpose
RAM-based pattern generator which can control address multiplexing, wait state generation, and five general-purpose output lines on the MPC821. Up to 64 pattern locations are
available, each 32 bits wide. Separate patterns may be programmed for normal accesses,
burst accesses, refresh (timer) events, and exception conditions. This flexibility allows
almost any type of memory or peripheral device to be accommodated by the MPC821.
In this application note, the GPCM is used instead of the UPM, since the GPCM has enough
flexibility to accommodate the SED1354 and it is desirable to leave the UPM free to handle
other interfacing duties, such as EDO DRAM.
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3 SED1374 Host Bus Interface
This section is a summary of the host bus interface modes available on the SED1374 and
offers some detail on the Generic #1 host bus interface used to implement the interface to
the MPC821 bus.
3.1 Host Bus Interface Modes
The SED1374 implements a 16-bit interface to the host microprocessor which may operate
in one of several modes compatible with most of the popular embedded microprocessor
families. Six host bus interface modes are supported:
• Hitachi SH-4.
• Hitachi SH-3
• Motorola MC68000 (using Upper Data Strobe/Lower Data Strobe).
• Motorola MC68020/MC68030/MC683xx (using Data Strobe/DSACKx).
• Generic #1 (Chip Select, plus individual Read Enable/Write Enable for each byte).
• Generic #2 (External Chip Select, shared Read/Write Enable for high byte, individual
Read/Write Enable for low byte).
The SED1374 latches CNF[2:0] and BS# to allow selection of the host bus interface on the
rising edge of RESET#. After releasing reset, the host bus interface signals assume their
selected configuration. The following table shows the functions of each host bus interface
signal.
Table 3-1: Host Bus Interface Pin Mapping
SED1374
Pin Names
SH-3
SH-4
MC68K #1
MC68K #2
Generic #1
Generic #2
AB[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
AB0
A0
A0
LDS#
A0
A0
A0
DB[15:0]
D[15:0]
D[15:0]
D[15:0]
D[31:16]
D[15:0]
D[15:0]
WE1#
WE1#
WE1#
UDS#
DS#
WE1#
BHE#
CS#
CSn#
CSn#
External Decode
BCLK
CKIO
CKIO
CLK
CLK
BCLK
BCLK
BS#
BS#
BS#
AS#
AS#
connect to VSS
connect to IO VDD
RD/WR#
RD/WR#
RD/WR#
R/W#
R/W#
RD1#
connect to IO VDD
RD#
RD#
RD#
connect to IO VDD
SIZ1
RD0#
RD#
WE0#
WE0#
WE0#
connect to IO VDD
SIZ0
WE0#
WE#
WAIT#
WAIT#
RDY#
DTACK#
DSACK1#
WAIT#
WAIT#
RESET#
RESET#
RESET#
RESET#
RESET#
RESET#
RESET#
Interfacing to the Motorola MPC821 Microprocessor
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External Decode External Decode
External Decode
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Two other configuration options (CNF[4:3]) are also made at time of hardware reset:
• endian mode setting (big endian or little endian).
• polarity of the LCDPWR signal.
The capability to select the endian mode independent of the host bus interface offers more
flexibility in configuring the SED1374 with other CPUs.
For details on configuration, refer to the SED1374 Hardware Functional Specification,
document number X26A-A-001-xx.
3.2 Generic #1 Host Bus Interface Mode
Generic #1 host bus interface mode is the most general and least processor-specific host bus
interface mode on the SED1374. The Generic # 1 host bus interface mode was chosen for
this interface due to the simplicity of its timing.
The host bus interface requires the following signals:
• BUSCLK is a clock input which is required by the SED1374 host interface. It is separate
from the input clock (CLKI) and is typically driven by the host CPU system clock.
• The address inputs AB0 through AB15, and the data bus DB0 through DB15, connect
directly to the CPU address and data bus, respectively. On 32-bit big endian architectures such as the Power PC, the data bus would connect to the high-order data lines; on
little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data
lines. The hardware engineer must ensure that CNF3 selects the proper endian mode
upon reset.
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper
IO or memory address space.
• WE0# and WE1# are write enables for the low-order and high-order bytes, respectively,
to be driven low when the host CPU is writing data to the SED1374. These signals must
be generated by external hardware based on the control outputs from the host CPU.
• RD# and RD/WR# are read enables for the low-order and high-order bytes, respectively,
to be driven low when the host CPU is reading data from the SED1374. These signals
must be generated by external hardware based on the control outputs from the host CPU.
• WAIT# is a signal output from the SED1374 that indicates the host CPU must wait until
data is ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU
accesses to the SED1374 may occur asynchronously to the display update, it is possible
that contention may occur in accessing the SED1374 internal registers and/or refresh
memory. The WAIT# line resolves these contentions by forcing the host to wait until the
resource arbitration is complete. This signal is active low and may need to be inverted if
the host CPU wait state signal is active high.
• The Bus Status (BS#) signal is not used in the bus interface for Generic #1 mode.
However, BS# is used to configure the SED1374 for Generic #1 mode and should be
tied low (connected to GND).
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4 MPC821 to SED1374 Interface
4.1 Hardware Description
The interface between the SED1374 and the MPC821 requires minimal glue logic. One
inverter is required to change the polarity of the WAIT# signal (an active low signal) to
insert wait states in the bus cycle. The MPC821 Transfer Acknowledge signal (TA) is an
active low signal which ends the current bus cycle. The inverter is enabled using CS# so
that TA is not driven by the SED1374 during non-SED1374 bus cycles. A single resistor is
used to speed up the rise time of the WAIT# (TA) signal when terminating the bus cycle.
BS# (bus start) is not used in this implementation and should be tied low (connected to
GND).
The following diagram shows a typical implementation of the MPC821 to SED1374
interface.
SED1374
MPC821
A[16:31]
AB15-AB0
D[0:15]
DB[15:D0]
CS#
CS4
Vcc
470
TA
WAIT#
WE0
WE1#
WE1
WE0#
OE
RD/WR#
RD#
SYSCLK
BUSCLK
RESET
RESET#
Figure 4-1: Typical Implementation of MPC821 to SED1374 Interface
Interfacing to the Motorola MPC821 Microprocessor
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4.2 Hardware Connections
The following table details the connections between the pins and signals of the MPC821
and the SED1374.
Table 4-1: List of Connections from MPC821ADS to SED1374
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MPC821 Signal Name
MPC821ADS Connector and Pin Name
SED1374 Signal Name
Vcc
P6-A1, P6-B1
Vcc
A16
P6-B24
SA15
A17
P6-C24
SA14
A18
P6-D23
SA13
A19
P6-D22
SA12
A20
P6-D19
SA11
A21
P6-A19
SA10
A22
P6-D28
SA9
A23
P6-A28
SA8
A24
P6-C27
SA7
A25
P6-A26
SA6
A26
P6-C26
SA5
A27
P6-A25
SA4
A28
P6-D26
SA3
A29
P6-B25
SA2
A30
P6-B19
SA1
A31
P6-D17
SA0
D0
P12-A9
SD15
D1
P12-C9
SD14
D2
P12-D9
SD13
D3
P12-A8
SD12
D4
P12-B8
SD11
D5
P12-D8
SD10
D6
P12-B7
SD9
D7
P12-C7
SD8
D8
P12-A15
SD7
D9
P12-C15
SD6
D10
P12-D15
SD5
D11
P12-A14
SD4
D12
P12-B14
SD3
D13
P12-D14
SD2
D14
P12-B13
SD1
D15
P12-C13
SD0
SRESET
P9-D15
RESET#
SYSCLK
P9-C2
BUSCLK
CS4
P6-D13
CS#
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Table 4-1: List of Connections from MPC821ADS to SED1374 (Continued)
MPC821 Signal Name
MPC821ADS Connector and Pin Name
SED1374 Signal Name
TA
P6-B6 to inverter enabled by CS#
WAIT#
WE0
P6-B15
WE1#
WE1
P6-A14
WE0#
OE
P6-B16
RD/WR#, RD#
GND
P12-A1, P12-B1, P12-A2, P12-B2,
P12-A3, P12-B3, P12-A4, P12-B4,
P12-A5, P12-B5, P12-A6, P12-B6,
P12-A7
Vss
Note
The bit numbering of the Power PC bus signals is reversed from the normal convention,
e.g.: the most significant address bit is A0, the next is A1, A2, etc.
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4.3 SED1374 Hardware Configuration
The SED1374 uses CNF4 through CNF0 and BS# to allow selection of the bus mode and
other configuration data on the rising edge of RESET#. Refer to the SED1374 Hardware
Functional Specification, document number X26A-A-001-xx for details.
The tables below show only those configuration settings important to the MPC821
interface. The settings are very similar to the ISA bus with the following exceptions:
• the WAIT# signal is active high rather than active low.
• the Power PC is big endian rather than little endian.
Table 4-2: Configuration Settings
Signal
CNF0
CNF1
CNF2
CNF3
CNF4
Low
High
See “Host Bus Selection” table below See “Host Bus Selection” table below
Little Endian
Active low LCDPWR signal
Big Endian
Active high LCDPWR signal
= configuration for MPC821 host bus interface
Table 4-3: Host Bus Selection
CNF2
0
0
0
0
1
1
1
1
1
1
CNF1
0
0
1
1
0
0
1
1
1
1
CNF0
0
1
0
1
0
1
0
0
1
1
BS#
X
X
X
X
X
X
0
1
0
1
Host Bus Interface
SH-4 interface
SH-3 interface
reserved
MC68K #1, 16-bit
reserved
MC68K #2, 16-bit
reserved
reserved
Generic #1, 16-bit
Generic #2, 16-bit
= configuration for MPC821 host bus interface
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4.4 MPC821 Chip Select Configuration
The DRAM on the MPC821 ADS board extends from address 0 through 3F FFFFh, so the
SED1374 is addressed starting at 40 0000h. The SED1374 uses a 64K byte segment of
memory starting at this address, with the first 40K bytes used for the display buffer and the
upper 32 bytes of this memory block used for the SED1374 internal registers.
Chip select 4 is used to control the SED1374. The following options are selected in the base
address register (BR4):
• BA (0:16) = 0000 0000 0100 0000 0 – set starting address of SED1374 to 40 0000h
• AT (0:2) = 0 – ignore address type bits
• PS (0:1) = 1:0 – memory port size is 16 bits
• PARE = 0 – disable parity checking
• WP = 0 – disable write protect
• MS (0:1) = 0:0 – select General Purpose Chip Select module to control this chip select
• V = 1 – set valid bit to enable chip select
The following options were selected in the option register (OR4):
• AM (0:16) = 1111 1111 1100 0000 0 – mask all but upper 10 address bits; SED1374
consumes 4M byte of address space
• ATM (0:2) = 0 – ignore address type bits
• CSNT = 0 – normal CS/WE negation
• ACS (0:1) = 1:1 – delay CS assertion by ½ clock cycle from address lines
• BI = 1 – assert Burst Inhibit
• SCY (0:3) = 0 – wait state selection; this field is ignored since external transfer
acknowledge is used; see SETA below
• SETA = 1 – the SED1374 generates an external transfer acknowledge using the WAIT#
line
• TRLX = 0 – normal timing
• EHTR = 0 – normal timing
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4.5 Test Software
The test software to exercise this interface is very simple. It configures chip select 4 on the
MPC821 to map the SED1374 to an unused 64k byte block of address space and loads the
appropriate values into the option register for CS4. At that point the software runs in a tight
loop reading the 1374 Revision Code Register REG[00h], which allows monitoring of the
bus timing on a logic analyzer.
The source code for this test routine is as follows:
BR4
OR4
MemStart
address
RevCodeReg
ter
Start
registers
equ
equ
equ
$120
$124
$40
; CS4 base register
; CS4 option register
; upper word of SED1374 start
equ
FFE0
; address of Revision Code Regis-
mfspr
r1,IMMR
; get base address of internal
andis.
andis.
oris
ori
r1,r1,$ffff
r2,r0,0
r2,r2,MemStart
r2,r2,$0801
;
;
;
;
stw
andis.
oris
r2,BR4(r1)
r2,r0,0
r2,r2,$ffc0
; write value to base register
; clear r2
; address mask – use upper 10
ori
r2,r2,$0708
; normal CS negation; delay CS ½
stw
andis.
oris
r2,OR4(r1)
r1,r0,0
r1,r1,MemStart
;
;
;
;
lbz
b
r0,RevCodeReg(r1) ; read revision code into r1
Loop
; branch forever
clear lower 16 bits to 0
clear r2
write base address
port size 16 bits; select GPCM;
enable
bits
clock;
mem space
Loop
inhibit burst
write to option register
clear r1
point r1 to start of SED1374
end
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This code was entered into the memory of the MPC821ADS using the line-by-line
assembler in MPC8BUG, the debugger provided with the ADS board. It was executed on
the ADS and a logic analyzer was used to verify operation of the interface hardware.
Note
MPC8BUG does not support comments or symbolic equates; these have been added for
clarity.
It is important to note that when the MPC821 comes out of reset, its on-chip caches and
MMU are disabled. If the data cache is enabled, then the MMU must be set up so that the
SED1374 memory block is tagged as non-cacheable, to ensure that accesses to the
SED1374 will occur in proper order, and also to ensure that the MPC821 does not attempt
to cache any data read from or written to the SED1374 or its display buffer.
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5 Software
Test utilities and Windows® CE v2.0 display drivers are available for the SED1374. Full
source code is available for both the test utilities and the drivers.
The test utilities are configurable for different panel types using a program called
1374CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can
be customized by the OEM for different panel types, resolutions and color depths only by
modifying the source.
The SED1374 test utilities and Windows CE v2.0 display drivers are available from your
sales support contact or on the internet at http://www.erd.epson.com.
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6 References
6.1 Documents
• Motorola Inc., Power PC MPC821 Portable Systems Microprocessor User’s Manual,
Motorola Publication no. MPC821UM/AD; available on the Internet at
http://www.mot.com/SPS/ADC/pps/_subpgs/_documentation/821/821UM.html.
• Epson Research and Development, Inc., SED1374 Embedded Memory LCD Controller
Hardware Functional Specification; Document Number X126A-A-002-xx.
• Epson Research and Development, Inc., SDU1374B0C Rev. 1.0 ISA Bus Evaluation
Board User Manual; Document Number X26A-G-005-xx.
• Epson Research and Development, Inc., Programming Notes and Examples; Document
Number X26A-G-002-xx.
6.2 Document Sources
• Motorola Inc. Literature Distribution Center: (800) 441-2447.
• Motorola Inc. Website: http://www.mot.com.
• Epson Research and Development Website: http://www.erd.epson.com.
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 99/01/05
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X26A-G-010-02
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7 Technical Support
7.1 EPSON LCD/CRT Controllers (SED1374)
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
7.2 Motorola MPC821 Processor
• Motorola Design Line, (800) 521-6274.
• Local Motorola sales office or authorized distributor.
SED1374
X26A-G-010-02
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 99/01/05
SED1374 Embedded Memory Color LCD Controller
Interfacing to the Motorola MCF5307
"ColdFire" Microprocessor
Document Number: X26A-G-011-02
Copyright © 1998, 1999 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.
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SED1374
X26A-G-011-02
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
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Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Interfacing to the MCF5307 . . . . . . . . . . . .
2.1 The MCF5307 System Bus . . . . . . . . . .
2.1.1 Overview . . . . . . . . . . . . . . . . . . .
2.1.2 Normal (Non-Burst) Bus Transactions . . . .
2.1.3 Burst Cycles . . . . . . . . . . . . . . . . . .
2.2 Chip-Select Module . . . . . . . . . . . . .
3
SED1374 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Bus Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Generic #1 Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
MCF5307 To SED1374 Interface . . .
4.1 Hardware Description . . . . . .
4.2 SED1374 Hardware Configuration .
4.3 MCF5307 Chip Select Configuration
5
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1 EPSON LCD Controllers (SED1374) . . . . . . . . . . . . . . . . . . . . . 18
7.2 Motorola MCF5307 Processor . . . . . . . . . . . . . . . . . . . . . . . . 18
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 99/01/05
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Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 99/01/05
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Vancouver Design Center
Page 5
List of Tables
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4-1: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4-2: Host Bus Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
List of Figures
Figure 2-1: MCF5307 Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2-2: MCF5307 Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4-1: Typical Implementation of MCF5307 to SED1374 Interface . . . . . . . . . . . . . . . 13
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 99/01/05
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SED1374
X26A-G-011-02
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 99/01/05
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Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware required to provide an interface between the
SED1374 Embedded Memory LCD Controller and the Motorola MCF5307 Processor. The
pairing of these two devices results in an embedded system offering impressive display
capability with very low power consumption.
The designs described in this document are presented only as examples of how such
interfaces might be implemented. This application note will be updated as appropriate.
Please check the Epson Research and Development Website at http://www.erd.epson.com
for the latest revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 99/01/05
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2 Interfacing to the MCF5307
2.1 The MCF5307 System Bus
The MCF5200/5300 family of processors feature a high-speed synchronous system bus
typical of modern microprocessors. This section is an overview of the operation of the CPU
bus to establish interface requirements.
2.1.1 Overview
The MCF5307 microprocessor family uses a synchronous address and data bus, very
similar in architecture to the MC68040 and MPC8xx. All outputs and inputs are timed with
respect to a square-wave reference clock called BCLK0 (Master Clock). This clock runs at
a software-selectable divisor rate from the machine cycle speed of the CPU core, typically
20 to 33 MHz. Both the address and the data bus are 32 bits in width. All IO accesses are
memory-mapped; there is no separate IO space in the Coldfire architecture.
The bus can support two types of cycles, normal and burst. Burst memory cycles are used
to fill on-chip cache memories, and for certain on-chip DMA operations. Normal cycles are
used for all other data transfers.
2.1.2 Normal (Non-Burst) Bus Transactions
A data transfer is initiated by the bus master by placing the memory address on address
lines A31 through A0 and driving TS (Transfer Start) low for one clock cycle. Several
control signals are also provided with the memory address:
• SIZ[1:0] (Transfer Size), which indicate whether the bus cycle is 8, 16, or 32 bits in
width.
• R/W, which is high for read cycles and low for write cycles.
• A set of transfer type signals (TT[1:0]) which provide more detail on the type of transfer
being attempted.
• TIP (Transfer In Progress), which is asserted whenever a bus cycle is active.
When the peripheral device being accessed has completed the bus transfer, it asserts TA
(Transfer Acknowledge) for one clock cycle, completing the bus transaction. Once TA has
been asserted, the MCF5307 will not start another bus cycle until TA has been de-asserted.
The minimum length of a bus transaction is two bus clocks.
Figure 2-1 illustrates a typical memory read cycle on the MCF5307 system bus, and Figure
2-2 illustrates a memory write cycle.
SED1374
X26A-G-011-02
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 99/01/05
Epson Research and Development
Vancouver Design Center
Page 9
BCLK0
TS
TA
TIP
A[31:0]
R/W
SIZ[1:0], TT[1:0]
Sampled when TA low
D[31:0]
Transfer Start
Wait States
Transfer
Next Transfer
Complete
Starts
Figure 2-1: MCF5307 Memory Read Cycle
BCLK0
TS
TA
TIP
A[31:0]
R/W
SIZ[1:0], TT[1:0]
D[31:0]
Valid
Transfer Start
Wait States
Transfer
Next Transfer
Complete
Starts
Figure 2-2: MCF5307 Memory Write Cycle
2.1.3 Burst Cycles
Burst cycles are very similar to normal cycles, except that they occur as a series of four
back-to-back, 32-bit memory reads or writes, with the TIP (Transfer In Progress) output
asserted continuously through the burst. Burst memory cycles are mainly intended to facilitate cache line fill from program or data memory; they are typically not used for transfers
to or from IO peripheral devices such as the SED1374. The MCF5307 chip selects provide
a mechanism to disable burst accesses for peripheral devices which are not able to support
them.
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
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2.2 Chip-Select Module
In addition to generating eight independent chip-select outputs, the MCF5307 Chip Select
Module can generate active-low Output Enable (OE) and Write Enable (WE) signals
compatible with most memory and x86-style peripherals. The MCF5307 bus controller also
provides a Read/Write (R/W) signal which is compatible with most 68K peripherals.
Chip selects 0 and 1 can be programmed independently to respond to any base address and
block size. Chip select 0 can be active immediately after reset, and is typically used to
control a boot ROM. Chip select 1 is likewise typically used to control a large static or
dynamic RAM block.
Chip selects 2 through 7 have fixed block sizes of 2M bytes each. Each has a unique, fixed
offset from a common, programmable starting address. These chip selects are well-suited
to typical IO addressing requirements.
Each chip select may be individually programmed for port size (8/16/32 bits), 0-15 wait
states or external acknowledge, address space type, burst or non-burst cycle support, and
write protect.
SED1374
X26A-G-011-02
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 99/01/05
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Vancouver Design Center
Page 11
3 SED1374 Bus Interface
This section is a summary of the host bus interface modes available on the SED1374 and
offers some detail on the Generic #1 host bus interface used to implement the interface to
the MCF5307.
3.1 Bus Interface Modes
The SED1374 implements a 16-bit interface to the host microprocessor which may operate
in one of several modes compatible with most of the popular embedded microprocessor
families. Six bus interface modes are supported:
• Hitachi SH-4.
• Hitachi SH-3
• Motorola MC68000 (using Upper Data Strobe/Lower Data Strobe).
• Motorola MC68020/MC68030/MC683xx (using Data Strobe/DSACKx).
• Generic #1 (Chip Select, plus individual Read Enable/Write Enable for each byte).
• Generic #2 (External Chip Select, shared Read/Write Enable for high byte, individual
Read/Write Enable for low byte).
The SED1374 latches CNF[2:0] and BS# to allow selection of the host bus interface on the
rising edge of RESET#. After releasing reset, the bus interface signals assume their selected
configuration. The following table shows the functions of each host bus interface signal.
Table 3-1: Host Bus Interface Pin Mapping
SED1374
Pin Names
SH-3
SH-4
MC68K #1
MC68K #2
Generic #1
Generic #2
AB[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
A[15:1]
AB0
A0
A0
LDS#
A0
A0
A0
DB[15:0]
D[15:0]
D[15:0]
D[15:0]
D[31:16]
D[15:0]
D[15:0]
WE1#
WE1#
WE1#
UDS#
DS#
WE1#
BHE#
CS#
CSn#
CSn#
External Decode
BCLK
CKIO
CKIO
CLK
CLK
BCLK
BCLK
BS#
BS#
BS#
AS#
AS#
connect to VSS
connect to IO VDD
RD/WR#
RD/WR#
RD/WR#
R/W#
R/W#
RD1#
connect to IO VDD
RD#
RD#
RD#
connect to IO VDD
SIZ1
RD0#
RD#
WE0#
WE0#
WE0#
connect to IO VDD
SIZ0
WE0#
WE#
WAIT#
WAIT#
RDY#
DTACK#
DSACK1#
WAIT#
WAIT#
RESET#
RESET#
RESET#
RESET#
RESET#
RESET#
RESET#
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 99/01/05
External Decode External Decode
External Decode
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Two other configuration options (CNF[4:3]) are also made at time of hardware reset:
• endian mode setting (big endian or little endian).
• polarity of the LCDPWR signal.
The capability to select the endian mode independent of the host bus interface offers more
flexibility in configuring the SED1374 with other CPUs.
For details on configuration, refer to the SED1374 Hardware Functional Specification,
document number X26A-A-001-xx.
3.2 Generic #1 Interface Mode
Generic #1 interface mode is the most general and least processor-specific interface mode
on the SED1374. The Generic # 1 interface mode was chosen for this interface due to the
simplicity of its timing.
The interface requires the following signals:
• BUSCLK is a clock input which is required by the SED1374 host interface. It is separate
from the input clock (CLKI) and is typically driven by the host CPU system clock.
• The address inputs AB0 through AB15, and the data bus DB0 through DB15, connect
directly to the CPU address and data bus, respectively. On 32-bit big endian architectures such as the Power PC, the data bus would connect to the high-order data lines; on
little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data
lines. The hardware engineer must ensure that CNF3 selects the proper endian mode
upon reset.
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper
IO or memory address space.
• WE0# and WE1# are write enables for the low-order and high-order bytes, respectively,
to be driven low when the host CPU is writing data to the SED1374. These signals must
be generated by external hardware based on the control outputs from the host CPU.
• RD# and RD/WR# are read enables for the low-order and high-order bytes, respectively,
to be driven low when the host CPU is reading data from the SED1374. These signals
must be generated by external hardware based on the control outputs from the host CPU.
• WAIT# is a signal output from the SED1374 that indicates the host CPU must wait until
data is ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU
accesses to the SED1374 may occur asynchronously to the display update, it is possible
that contention may occur in accessing the SED1374 internal registers and/or refresh
memory. The WAIT# line resolves these contentions by forcing the host to wait until the
resource arbitration is complete. This signal is active low and may need to be inverted if
the host CPU wait state signal is active high.
• The Bus Status (BS#) signal is not used in the bus interface for Generic #1 mode.
However, BS# is used to configure the SED1374 for Generic #1 mode and should be
tied low (connected to GND).
SED1374
X26A-G-011-02
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 99/01/05
Epson Research and Development
Vancouver Design Center
Page 13
4 MCF5307 To SED1374 Interface
4.1 Hardware Description
The SED1374 is interfaced to the MCF5307 with a minimal amount of glue logic. One
inverter is required to change the polarity of the WAIT# signal, which is an active low
signal to insert wait states in the bus cycle, while the MCF5307’s Transfer Acknowledge
signal (TA) is an active low signal to end the current bus cycle. The inverter is enabled by
CS# so that TA is not driven by the SED1374 during non-SED1374 bus cycles. A single
resistor is used to speed up the rise time of the WAIT# (TA) signal when terminating the
bus cycle.
The following diagram shows a typical implementation of the MCF5307 to SED1374
interface.
SED1374
MCF5307
A[16:31]
AB[15:0]
D[0:15]
DB[15:0]
CS4
CS#
Vcc
470
TA
WAIT#
WE3
WE1#
WE2
WE0#
OE
RD/WR#
RD#
BCLK0
BUSCLK
RESET
RESET#
Figure 4-1: Typical Implementation of MCF5307 to SED1374 Interface
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 99/01/05
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4.2 SED1374 Hardware Configuration
The SED1374 uses CNF0 through CNF4 and BS# to allow selection of the bus mode and
other configuration data on the rising edge of RESET#. Table 4-1: “Summary of PowerOn/Reset Options” and Table 4-2: “Host Bus Interface Selection” shows the settings used
for the SED1374 in this interface.
Table 4-1: Summary of Power-On/Reset Options
SED1374 value on this pin at the rising edge of RESET# is used to configure: (0/1)
Pin Name
0
1
CNF0
CNF1
See “Host Bus Selection” table below See “Host Bus Selection” table below
CNF2
CNF3
Little Endian
Big Endian
CNF4
Active low LCDPWR signal
Active high LCDPWR signal
= configuration for MFC5307 support
Table 4-2: Host Bus Interface Selection
CNF2
0
0
0
0
1
1
1
1
1
1
CNF1
0
0
1
1
0
0
1
1
1
1
CNF0
0
1
0
1
0
1
0
0
1
1
BS#
X
X
X
X
X
X
0
1
0
1
Host Bus Interface
SH-4 bus interface
SH-3 bus interface
reserved
MC68K bus interface #1, 16-bit
reserved
MC68K bus interface #2, 16-bit
reserved
reserved
Generic #1, 16-bit
Generic #2, 16-bit
= configuration for MFC5307 support
SED1374
X26A-G-011-02
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 99/01/05
Epson Research and Development
Vancouver Design Center
Page 15
4.3 MCF5307 Chip Select Configuration
Chip Selects 0 and 1 have programmable block sizes from 64K bytes through 2G bytes.
However, these chip selects would normally be needed to control system RAM and ROM.
Therefore, one of the IO chip selects, CS2 through CS7, is required to address the entire
address space of the SED1374. These IO chip selects have a fixed, 2M byte block size. In
the example interface, chip select 4 is used to control the SED1374. The SED1374 only
uses a 64K byte block with its 40K byte display buffer residing at the start of this 64K byte
block and its internal registers occupying the last 32 bytes of this block. This 64K byte
block of memory will be shadowed over the entire 2M byte space. The CSBAR register
should be set to the upper 8 bits of the desired base address.
The following options should be selected in the chip select mask registers (CSMR4/5):
• WP = 0 – disable write protect
• AM = 0 - enable alternate bus master access to the SED1374
• C/I = 1 - disable CPU space access to the SED1374
• SC = 1 - disable Supervisor Code space access to the SED1374
• SD = 0 - enable Supervisor Data space access to the SED1374
• UC = 1 - disable User Code space access to the SED1374
• UD = 0 - enable User Data space access to the SED1374
• V = 1 - global enable (“Valid”) for the chip select
The following options should be selected in the chip select control registers (CSCR4/5):
• WS0-3 = 0 - no internal wait state setting
• AA = 0 - no automatic acknowledgment
• PS (1:0) = 1:0 – memory port size is 16 bits
• BEM = 0 – Byte enable/write enable active on writes only
• BSTR = 0 – disable burst reads
• BSTW = 0 – disable burst writes
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 99/01/05
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Epson Research and Development
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5 Software
Test utilities and Windows® CE v2.0 display drivers are available for the SED1374. Full
source code is available for both the test utilities and the drivers.
The test utilities are configurable for different panel types using a program called
1374CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can
be customized by the OEM for different panel types, resolutions and color depths only by
modifying the source.
The SED1374 test utilities and Windows CE v2.0 display drivers are available from your
sales support contact or on the internet at http://www.erd.epson.com.
SED1374
X26A-G-011-02
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 99/01/05
Epson Research and Development
Vancouver Design Center
Page 17
6 References
6.1 Documents
• Motorola Inc., MCF5307 ColdFire® Integrated Microprocessor User’s Manual,
Motorola Publication no. MCF5307UM/AD; available on the Internet at
http://www.mot.com/SPS/HPESD/prod/coldfire/5307UM.html.
• Epson Research and Development, Inc., SED1374 Hardware Functional Specification;
Document Number X26A-A-002-xx.
• Epson Research and Development, Inc., SDU1374B0C Rev. 1.0 ISA Bus Evaluation
Board User Manual; Document Number X26A-G-005-xx.
• Epson Research and Development, Inc., SED1374 Programming Notes and Examples;
Document Number X26A-G-002-xx.
6.2 Document Sources
• Motorola Inc.: Motorola Literature Distribution Center, (800) 441-2447.
• Motorola Website: http://www.mot.com.
• Epson Research and Development Website: http://www.erd.epson.com
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 99/01/05
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X26A-G-011-02
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7 Technical Support
7.1 EPSON LCD Controllers (SED1374)
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
7.2 Motorola MCF5307 Processor
• Motorola Design Line, (800) 521-6274.
• Local Motorola sales office or authorized distributor.
SED1374
X26A-G-011-02
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 99/01/05
SED1374 Embedded Memory Color LCD Controller
Interfacing to the Philips MIPS
PR31500/PR31700 Processor
Document Number: X26A-G-012-01
Copyright © 1998 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
EPSON Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
SED1374
X26A-G-012-01
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 98/11/09
EPSON Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
2
3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Direct Connection to the Philips PR31500/PR31700 . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2
Memory Mapping and Aliasing
2.3
SED1374 Configuration and Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . .9
. . . . . . . . . . . . . . . . . . . . . . . . . . . .9
System Design Using the ITE IT8368E PC Card Buffer . . . . . . . . . . . . . . . . . . . . 10
3.1
Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2
IT8368E Configuration
3.3
Memory Mapping and Aliasing
3.4
SED1374 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
EPSON LCD Controllers (SED1374) . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2
Philips MIPS PR31500/PR31700 Processor
5.3
ITE IT8368E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 98/11/09
. . . . . . . . . . . . . . . . . . . . . . 15
SED1374
X26A-G-012-01
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SED1374
X26A-G-012-01
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 98/11/09
EPSON Research and Development
Vancouver Design Center
Page 5
List of Tables
Table 2-1:
SED1374 Configuration for Direct Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 2-2:
SED1374 Generic #2 Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 3-1:
PR31500/PR31700 to Unbuffered PC Card Slots System Address Mapping . . . . . . . . . . . . 12
Table 3-2:
PR31500/PR31700 to PC Card Slots Address Remapping Using the IT8368E . . . . . . . . . . . 12
Table 3-3:
SED1374 Configuration Using the IT8368E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3-4:
SED1374 Generic #1 Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
List of Figures
Figure 2-1:
SED1374 to PR31500/PR31700 Direct Connection . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3-1:
SED1374 to PR31500/PR31700 Connection Using an IT8368E . . . . . . . . . . . . . . . . . . 10
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 98/11/09
SED1374
X26A-G-012-01
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Vancouver Design Center
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SED1374
X26A-G-012-01
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 98/11/09
EPSON Research and Development
Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware and software environment required to provide an
interface between the SED1374 Embedded Memory Color Graphics LCD Controller and the Philips
MIPS PR31500/PR31700 Processor.
For further information on the SED1374, refer to the SED1374 Hardware Functional Specification,
document number X26A-A-001-xx.
For further information on the PR31500/PR31700, contact Philips or refer to the Philips website at
http://www.philips.com.
For further information on the ITE IT8368E, refer to the IT8368E PC Card / GPIO Buffer Chip
Specification.
1.1 General Description
The Philips MIPS PR31500/PR31700 processor supports up to two PC Card (PCMCIA) slots. It is
through this host bus interface that the SED1374 connects to the PR31500/PR31700 processor.
The SED1374 can be successfully interfaced using one of two configurations:
• Direct connection to PR31500/PR31700 (see Section 2, “Direct Connection to the Philips
PR31500/PR31700” on page 8).
• System design using one ITE IT8368E PC Card/GPIO buffer chip (see Section 3, “System
Design Using the ITE IT8368E PC Card Buffer” on page 10).
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 98/11/09
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X26A-G-012-01
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EPSON Research and Development
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2 Direct Connection to the Philips PR31500/PR31700
2.1 General Description
In this example implementation the SED1374 occupies the PR31500/PR31700 PC Card slot #1.
The SED1374 is easily interfaced to the PR31500/PR31700 with minimal additional logic. The
address bus of the PR31500/PR31700 PC Card interface is multiplexed and can be demultiplexed
using an advanced CMOS latch (e.g., 74ACT373). The direct connection approach makes use of the
SED1374 in its “Generic Interface #2” configuration.
The following diagram demonstrates a typical implementation of the interface.
SED1374
+3.3V
PR31500/PR31700
IO VDD, CORE VDD
/RD
RD#
/WE
WE#
/CARD1CSL
/CARD1CSH
BHE#
IO VDD
BS#
IO VDD
RD/WR#
System RESET
ENDIAN
RESET#
Latch
CS#
ALE
AB[15:13]
AB[12:0]
A[12:0]
D[31:24]
D[23:16]
DB[7:0]
DB[15:8]
VDD
pull-up
/CARD1WAIT
WAIT#
DCLKOUT
See text
Clock divider
...or...
Oscillator
CLKI
BCLK
Figure 2-1: SED1374 to PR31500/PR31700 Direct Connection
The “Generic #2” host interface control signals of the SED1374 are asynchronous with respect to
the SED1374 bus clock. This gives the system designer full flexibility to choose the appropriate
source (or sources) for CLKI and BCLK. The choice of whether both clocks should be the same, and
whether to use DCLKOUT (divided) as clock source, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum SED1374 clock frequencies.
The SED1374 also has internal clock dividers providing additional flexibility.
SED1374
X26A-G-012-01
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 98/11/09
EPSON Research and Development
Vancouver Design Center
Page 9
2.2 Memory Mapping and Aliasing
The SED1374 requires an addressing space of 64K bytes. The on-chip display memory occupies the
range 0 through 9FFFh. The registers occupy the range FFE0h through FFFFh. The
PR31500/PR31700 demultiplexed address lines A16 and above are ignored, thus the SED1374 is
aliased 1024 times at 64K byte intervals over the 64M byte PC Card slot #1 memory space. In this
example implementation, the PR31500/PR31700 control signal /CARDREG is ignored, the
SED1374 also takes up the entire PC Card slot 1 configuration space.
Note
If aliasing is undesirable, additional decoding circuitry must be added.
2.3 SED1374 Configuration and Pin Mapping
The SED1374 is configured at power up by latching the state of the CNF[4:0] pins. Pin BS# also
plays a role in host bus interface configuration. For details on configuration, refer to the SED1374
Hardware Functional Specification, document number X26A-A-001-xx.
The table below shows those configuration settings relevant to the direct connection approach.
Table 2-1: SED1374 Configuration for Direct Connection
Value hard wired on this pin is used to configure:
SED1374
Configuration
Pin
1 (IO VDD)
0 (VSS)
BS#
Generic #2
Generic #1
CNF3
Big Endian
Little Endian
111: Generic #1 or #2
CNF[2:0]
= configuration for Philips PR31500/PR31700 host bus interface
When the SED1374 is configured for “Generic #2” interface, the host interface pins are mapped as
in the table below.
Table 2-2: SED1374 Generic #2 Interface Pin Mapping
Pin Name
Pin Function
WE1#
BHE#
BS#
Connect to IO VDD
RD/WR#
Connect to IO VDD
RD#
RD#
WE0#
WE#
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 98/11/09
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X26A-G-012-01
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3 System Design Using the ITE IT8368E PC Card Buffer
If the system designer uses the ITE IT8368E PC Card and multiple-function I/O buffer, the
SED1374 can be interfaced so that it ’shares’ a PC Card slot. The SED1374 is mapped to a rarelyused 16M byte portion of the PC Card slot buffered by the IT8368E. This makes the SED1374
virtually transparent to PC Card devices that use the same slot.
3.1 Hardware Description
The ITE8368E has been specially designed to support EPSON LCD controllers. The ITE IT8368E
provides eleven Multi-Function IO pins (MFIO). Configuration registers may be used to allow these
MFIO pins to provide the control signals required to implement the SED1374 CPU interface.
The PR31500/PR31700 processor only provides addresses A[12:0], therefore devices requiring
more address space must use an external device to latch A[25:13]. The IT8368E’s MFIO pins can
be configured to provide this latched address.
SED1374
+3.3V
IO VDD, CORE VDD
PR31500/PR31700
HA[12:0]
AB[12:0]
ENDIAN
AB[15:13]
HD[31:24]
DB[7:0]
HD[23:16]
DB[15:8]
VDD
System RESET
/CARDxWAIT
WAIT#
DCLKOUT
See text
...or...
IT8368E
RESET#
pull-up
Clock divider
Oscillator
CLKI
BCLK
LHA[23]/MFIO[10]
WE1#
LHA[22]/MFIO[9]
WE0#
LHA[21]/MFIO[8]
RD1#
LHA[20]/MFIO[7]
RD0#
LHA[19]/MFIO[6]
LHA[15:13]/
MFIO[2:0]
CS#
BS#
Figure 3-1: SED1374 to PR31500/PR31700 Connection Using an IT8368E
SED1374
X26A-G-012-01
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 98/11/09
EPSON Research and Development
Vancouver Design Center
Page 11
The “Generic #1” host interface control signals of the SED1374 are asynchronous with respect to
the SED1374 bus clock. This gives the system designer full flexibility to choose the appropriate
source (or sources) for CLKI and BCLK. The choice of whether both clocks should be the same, and
whether to use DCLKOUT (divided) as clock source, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum SED1374 clock frequencies.
The SED1374 also has internal clock dividers providing additional flexibility.
3.2 IT8368E Configuration
The IT8368E provides eleven multi-function IO pins (MFIO). The IT8368E must have both “Fix
Attribute/IO” and “VGA” modes on. When both these modes are enabled, the MFIO pins provide
control signals needed by the SED1374 host bus interface, and a 16M byte portion of the system PC
Card attribute and IO space is allocated to address the SED1374. When accessing the SED1374 the
associated card-side signals are disabled in order to avoid any conflicts.
For mapping details, refer to section 3.3: “Memory Mapping and Aliasing.” For connection details
see Figure 3-1: “SED1374 to PR31500/PR31700 Connection Using an IT8368E,” on page 10. For
further information on the IT8368E, refer to the IT8368E PC Card/GPIO Buffer Chip Specification.
Note
When a second IT8368E is used, that circuit should not be set in VGA mode.
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 98/11/09
SED1374
X26A-G-012-01
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3.3 Memory Mapping and Aliasing
When the PR31500/PR31700 accesses the PC Card slots without the ITE IT8368E, its system
memory is mapped as in Table 3-1:, “PR31500/PR31700 to Unbuffered PC Card Slots System
Address Mapping”.
Note
Bits CARD1IOEN and CARD2IOEN need to be set in PR31500/PR31700 Memory
Configuration Register 3.
Table 3-1: PR31500/PR31700 to Unbuffered PC Card Slots System Address Mapping
Philips Address
Function
(CARDnIOEN=0)
Size
Function
(CARDnIOEN=1)
0800 0000h
64M byte
Card 1 Attribute
Card 1 IO
0C00 0000h
64M byte
Card 2 Attribute
Card 2 IO
6400 0000h
64M byte
Card 1 Memory
6400 0000h
64M byte
Card 2 Memory
When the PR31500/PR31700 accesses the PC Card slots buffered through the ITE IT8368E, bits
CARD1IOEN and CARD2IOEN are ignored and the attribute/IO space of the PR31500/PR31700 is
divided into Attribute, I/O and SED1374 access. Table 3-2:, “PR31500/PR31700 to PC Card Slots
Address Remapping Using the IT8368E” provides all details of the Attribute/IO address reallocation
by the IT8368E.
Table 3-2: PR31500/PR31700 to PC Card Slots Address Remapping Using the IT8368E
IT8368E Uses PC Card Slot #
1
2
SED1374
X26A-G-012-01
Philips Address
Size
Function
0800 0000h
16M byte
Card 1 IO
0900 0000h
16M byte
SED1374 (aliased 256 times at 64K byte intervals)
0A00 0000h
32M byte
Card 1 Attribute
6400 0000h
64M byte
Card 1 Memory
0C00 0000h
16M byte
Card 2 IO
0D00 0000h
16M byte
SED1374 (aliased 256 times at 64K byte intervals)
0E00 0000h
32M byte
Card 2 Attribute
6800 0000h
64M byte
Card 2 Memory
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 98/11/09
EPSON Research and Development
Vancouver Design Center
Page 13
3.4 SED1374 Configuration
The SED1374 is configured at power up by latching the state of the CNF[4:0] pins. Pin BS# also
plays a role in host bus interface configuration. For details on configuration, refer to the SED1374
Hardware Functional Specification, document number X26A-A-001-xx.
The table below shows those configuration settings relevant to this specific interface.
Table 3-3: SED1374 Configuration Using the IT8368E
Value hard wired on this pin is used to configure:
SED1374
Configuration
Pin
1 (IO VDD)
0 (VSS)
BS#
Generic #2
Generic #1
CNF3
Big Endian
Little Endian
111: Generic #1 or #2
CNF[2:0]
= configuration for connection using ITE IT8368E
When the SED1374 is configured for “Generic #1” interface, the host interface pins are mapped as
in the table below.
Table 3-4: SED1374 Generic #1 Interface Pin Mapping
Pin Name
Pin Function
WE1#
WE1#
BS#
connect to VSS
RD/WR#
RD1#
RD#
RD0#
WE0#
WE0#
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 98/11/09
SED1374
X26A-G-012-01
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EPSON Research and Development
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4 Software
Test utilities and Windows® CE v2.0 display drivers are available for the SED1374. Full source
code is available for both the test utilities and the drivers.
The test utilities are configurable for different panel types using a program called 1357CFG, or by
directly modifying the source. The Windows CE v2.0 display drivers can be customized by the OEM
for different panel types, resolutions and color depths only by modifying the source.
The SED1374 test utilities and Windows CE v2.0 display drivers are available from your sales
support contact or www.erd.epson.com.
SED1374
X26A-G-012-01
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 98/11/09
EPSON Research and Development
Vancouver Design Center
Page 15
5 Technical Support
5.1 EPSON LCD Controllers (SED1374)
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
5.2 Philips MIPS PR31500/PR31700 Processor
Philips Semiconductors
Handheld Computing Group
4811 E. Arques Avenue
M/S 42, P.O. Box 3409
Sunnyvale, CA 94088-3409
Tel: (408) 991-2313
http://www.philips.com
5.3 ITE IT8368E
Integrated Technology Express, Inc.
Sales & Marketing Division
2710 Walsh Avenue
Santa Clara, CA 95051, USA
Tel: (408) 980-8168
Fax: (408) 980-9232
http://www.iteusa.com
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 98/11/09
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X26A-G-012-01
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SED1374
X26A-G-012-01
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 98/11/09
SED1374/75 Embedded Memory Color LCD Controller
SDU1374/75-TMPR3912/22U CPU
Module
Document Number: X00A-G-004-01
Copyright © 1998 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
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THIS PAGE LEFT BLANK
X00A-G-004-01
SDU1374/75-TMPR3912/22U CPU Module
Issue Date: 98/12/23
EPSON Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
2
3
4
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
SED1374/75 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Bus Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2
Generic #2 Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
TMPR3912/22U and SED1374/75 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
Hardware Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2
Memory Mapping and Aliasing
3.3
SED1374/75 Configuration and Pin Mapping . . . . . . . . . . . . . . . . . . . . . . 11
. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CPU Module Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
4.2
4.3
Clock Signals
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.1
BUSCLK
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.2
CLKI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
LCD Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.1
50-pin LCD Module Connector, J3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.2
Standard Epson LCD Connector, J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
LCD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3.1
SED1374 vs. SED1375 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3.2
LCDPWR Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3.3
SED1374\75 Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SDU1374/75-TMPR3912/22U CPU Module
Issue Date: 98/12/23
X00A-G-004-01
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X00A-G-004-01
SDU1374/75-TMPR3912/22U CPU Module
Issue Date: 98/12/23
EPSON Research and Development
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Page 5
List of Tables
Table 3-1:
SED1374/75 Configuration for Generic #2 Bus Interface . . . . . . . . . . . . . . . . . . . . . . 11
Table 3-2:
SED1374/75 Generic #2 Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
List of Figures
Figure 3-1:
SED1374 to TMPR3912/22U Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SDU1374/75-TMPR3912/22U CPU Module
Issue Date: 98/12/23
X00A-G-004-01
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X00A-G-004-01
SDU1374/75-TMPR3912/22U CPU Module
Issue Date: 98/12/23
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Vancouver Design Center
Page 7
1 Introduction
This manual describes the interface between the SED1374/75 LCD Controller (LCDC) and
the TMPR3912/22U microprocessor as implemented on the Toshiba 3912/22 and
SED1374/75 CPU Module. This module is used in conjunction with the Toshiba TX RISC
Reference Platform.
For more information regarding the SED1374 or SED1375 refer to their respective
Hardware Functional Specification, document number X26A-A-001-xx and
X27A-A-001-xx respectively.
For more information regarding the TMPR3912/22U, refer to the TMPR3912/22U 32-Bit
MIPS RISC Processor User’s Manual. See the Toshiba website under semiconductors at
http://toshiba.com/taec/nonflash/indexproducts.html.
1.1 General Description
The Toshiba TX RISC Reference Kit consists of 6 boards which include : a main board, a
CPU board, a EPROM board, a FMEM board, a debug board, and an analog board. The
main board acts as the motherboard for all the other add-on boards. In addition to these
boards, there is an LCD module that connects to the CPU board. In order to support the
add-on LCD panel that connects to the LCD module, the CPU board microprocessor must
have an internal LCD controller or the CPU board must have an LCD controller on it that
interfaces to the microprocessor.
For the TMPR3912/22U microprocessor, the SED1374 or SED1375 LCDC is used to
provide support for LCD panels. The LCDC is socketed so that it can be interchanged
between the SED1374 and the SED1375. These controllers are very similar, with the main
differences being the amount of embedded display memory and the lookup-table architecture (LUT). The SED1374 has 40K bytes of display memory and the SED1375 has 80K
bytes.
The Toshiba TMPR3912/22U processor supports two PC Card (PCMCIA) slots on the TX
RISC Reference Platform. The SED1374 or SED1375 LCD controller uses the PC Card
slot 1 to interface to the TMPR3912/22U, therefore, this slot is unavailable for use on the
TX RISC Reference Platform.
SDU1374/75-TMPR3912/22U CPU Module
Issue Date: 98/12/23
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2 SED1374/75 Bus Interface
This section is summary of the bus interface modes available on the SED1374 and
SED1375 LCDCs, and offers some detail on the Generic #2 bus mode used to implement
the interface to the TMPR3912/22U.
2.1 Bus Interface Modes
The SED1374/75 implements a general-purpose 16-bit interface to the host microprocessor, which may operate in one of several modes compatible with most of the popular
embedded microprocessor families.
Bus interface mode selections are made during reset by sampling the state of the configuration pins CNF[2:0] and the BS# line. Table 5-1 in the SED1374 or SED1375 Hardware
Functional Specification details the values needed for the configuration pins and BS# to
select the desired mode.
X00A-G-004-01
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2.2 Generic #2 Interface Mode
Generic #2 interface mode is a general and non-processor-specific interface mode on the
SED1374/75. The Generic # 2 interface mode was chosen for this interface due to its
compatibility with the PC Card interface.
The interface requires the following signals:
• BUSCLK is a clock input which synchronizes transfers between the host CPU and the
SED1374/75. BUSCLK is separate from the input clock (CLKI) and is typically driven
by the host CPU system clock.
• The address inputs AB0 through AB15, and the data bus DB0 through DB15, connect
directly to the CPU address and data bus, respectively. On 32-bit big endian architectures such as the Power PC, the data bus would connect to the high-order data lines; on
little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data
lines. The hardware engineer must ensure that CNF3 selects the proper endian mode
upon reset.
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper
memory address space.
• WE1# is the high byte enable for both read and write cycles and WE0# is the enable
signal for a write access. These must be generated by external decode hardware based
upon the control outputs from the host CPU.
• RD# is the read enable for the SED1374/75, to be driven low when the host CPU is
reading data from the SED1374/75. RD# must be generated by external decode hardware based upon the control outputs from the host CPU.
• WAIT# is a signal which is output from the SED1374/75 to the host CPU that indicates
when data is ready (read cycle) or accepted (write cycle) on the host bus. Since host
CPU accesses to the SED1374/75 may occur asynchronously to the display update, it is
possible that contention may occur in accessing the 1374/75 internal registers and/or
refresh memory. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete. This signal is active low and may need to be
inverted if the host CPU wait state signal is active high.
• The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in the bus interface for Generic #2 mode. However, BS# is used to configure the SED1374/75 for
Generic #2 mode and must be tied high (connected to IOVDD = 3.3V). RD/WR# must
also be tied high.
SDU1374/75-TMPR3912/22U CPU Module
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3 TMPR3912/22U and SED1374/75 Interface
3.1 Hardware Connections
The SED1374/75 occupies the TMPR3912/22U’s PC Card slot #1. Therefore, this slot
cannot be used for other devices on the main board. The Generic # 2 bus mode of the
SED1374/75 is used to interface to this PC Card slot #1.
The SED1374/75 is interfaced to the TMPR3912/22U with minimal glue logic. Since the
address bus of the TMPR3912/22U is multiplexed, it is demultiplexed using an advanced
CMOS latch (74ACT373) to obtain the higher address bits needed for the SED1374/75.
The following diagram demonstrates the implementation of the interface.
SED1374
+3.3V
TMPR3912/22U
IO VDD, CORE VDD
RD*
RD#
WE*
WE10#
CARD1CSL*
CARD1CSH*
WE1#
ENDIAN
3.3V
BS#
3.3V
RD/WR#
System RESET
RESET#
Latch
CS#
ALE
AB[15:13]
AB[12:0]
A[12:0]
D[31:24]
D[23:16]
DB[7:0]
DB[15:8]
3.3V
10K pull-up
CARD1WAIT*
WAIT#
DCLKOUT
Clock divider
/2
or...
Oscillator
Clock divider
/2
CLKI
BUSCLK
Figure 3-1: SED1374 to TMPR3912/22U Interface
X00A-G-004-01
SDU1374/75-TMPR3912/22U CPU Module
Issue Date: 98/12/23
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Page 11
3.2 Memory Mapping and Aliasing
The SED1374 requires an addressing space of 64K bytes while the SED1375 requires
128K. The on-chip display memory occupies the range 0 through 9FFFh. The registers
occupy the range FFE0h through FFFFh. The TMPR3912/22U demultiplexed address lines
A16 and above are ignored if the SED1374 is used, thus it is aliased 1024 times at 64K byte
intervals over the 64M byte PC Card slot #1 memory space. If the SED1375 is used, address
lines A17 and above are ignored; therefore the SED1375 is aliased 512 times at 128K byte
intervals. The TMPR3912/22U control signal CARDREG# is ignored; therefore the
SED1374 also takes up the entire PC Card slot #1 configuration space.
Note
If aliasing is undesirable, additional decoding circuitry must be added.
3.3 SED1374/75 Configuration and Pin Mapping
The SED1374/75 host bus interface is configured at power up by latching the state of the
CNF[3:0] pins. Pin BS# also plays a role in host bus interface configuration. One additional
configuration pin for the SED1374, CNF4, is also used to set the polarity of the LCDPWR
signal.
The table below shows the configuration pin connections to configure the SED1374/75 for
use with the TMPR3912/22U microprocessor.
Table 3-1: SED1374/75 Configuration for Generic #2 Bus Interface
Value hard wired on this pin is used to configure:
SED1374
Configuration
Pin
1 (IO VDD)
0 (VSS)
BS#
Generic #2
Generic #1
CNF3
Big Endian
Little Endian
111: Generic #1 or #2
CNF[2:0]
= configuration for Toshiba TMPR3912/22U host bus interface
When the SED1374/75 is configured for Generic #2 bus interface mode, the host interface
pins are mapped as in the table below.
Table 3-2: SED1374/75 Generic #2 Interface Pin Mapping
SDU1374/75-TMPR3912/22U CPU Module
Issue Date: 98/12/23
Pin Name
Pin Function
WE1#
BHE#
BS#
Connect to IO VDD
RD/WR#
Connect to IO VDD
RD#
RD#
WE0#
WE#
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4 CPU Module Description
This section will describe the various parts of the CPU module that pertain to the
SED1374/75 LCD Controller.
4.1 Clock Signals
4.1.1 BUSCLK
Because the bus clock for the SED1374/75 does not need to be synchronous with the bus
interface control signals, a lot of flexibility is available in the choice for BUSCLK. In this
CPU module, BUSCLK is a divided by two version of the SDRAM clock signal,
DCLKOUT. Since DCLKOUT equals 73.728MHz, BUSCLK = 36.864MHz.
4.1.2 CLKI
The pixel clock for the SED1374/75, CLKI, is also asynchronous with respect to the
interface control signals. This clock is selected based upon panel frame rates, power vs
performance budget, and maximum input frequencies. The maximum CLKI input is
25MHz if the internal CLKI/2 isn’t used, and if it is used the maximum input is 50MHz.
On the CPU module, CLKI’s default input is a divided by four version of DCLKOUT,
which gives a CLKI = 18.432MHZ. This frequency gives good performance for 320x240
resolution panels for both portrait and landscape modes. If power saving is desired, the
CLKI can be reduced by using the internal CLKI/2 and the various PCLK and MCLK
dividers for portrait mode.
A socket for an external oscillator is also provided if a different frequency is required. This
option is selected by positioning jumper JP8 in the 2 3 position and adding a standard 14DIP type oscillator in the socket U10.
4.2 LCD Connectors
4.2.1 50-pin LCD Module Connector, J3
The standard connector used on Toshiba’s CPU Modules to connect to the LCD module is
included in this CPU module. All twelve LCD data lines, FPDAT[11:0], from the
SED1374/75, as well as the five video control signals, FPFRAME, FPSHIFT, FPLINE,
DRDY, LCDPWR, are passed through this connector. Through this connector, the
SED1374/75 supports monochrome and color STN panels up to a resolution of 640x480 as
well as color TFT/D-TFT up to a resolution of 640x480. All touch panel signals from the
main board have also been routed through this connector.
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SDU1374/75-TMPR3912/22U CPU Module
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Page 13
4.2.2 Standard Epson LCD Connector, J4
A shrouded 40-pin header, J4, is also added to the CPU module to connect to LCD panels.
This header is the standard LCD connector used on Epson Research and Development
evaluation boards and can be used to directly connect LCD panels to the SED1374/75
controller. All LCD signals are buffered to allow 3.3V or 5.0V logic LCD panels to be
connected. Jumper, JP9, selects between these two types of panels.
A positive power supply for panels requiring a positive bias voltage is supplied to header
J4, by the LCD module through the 50-pin LCD module connector, J3. No negative power
supply is available on the LCD module, therefore only panels which have their own bias
voltage supply, or those that use a positive supply, can be connected to J4. The LCD
module can only support these panels as well.
Header, J4, and its associated buffers and components have been left unpopulated on the
CPU module. These parts can be added by the user if desired.
4.3 LCD Controller
4.3.1 SED1374 vs. SED1375
The LCD controller used in conjunction with the TMPR3912/22U microprocessor can
either be a SED1374 or a SED1375. If a SED1374 is used, jumper JP7 must be set to
position 1 2. This setting allows CNF4 to be configured for the SED1374. CNF4 controls
the polarity of the LCDPWR signal and can be set either high or low with jumper, JP11. If
a SED1375 is used, jumper JP7 must be set to position 2 3. This setting allows pin 45 of
the LCDC to be used as address bit, AB16, which is needed on the SED1375 to accommodate the larger display memory.
4.3.2 LCDPWR Polarity
The power supply on the LCD module used LCDON, an active low signal to turn on the
supply. This signal is connected to LCDPWR. Since LCDPWR is configurable on the
SED1374 and is set active high on the SED1375, a facility must be provided to invert this
signal if it is active high so that LCDON will be the right polarity to turn on the LCD power
supply. Jumper, JP10 must be set to position 1 2 if LCDPWR is active low and to position
2 3 if LCDPWR is active high.
4.3.3 SED1374\75 Chip Select
Minimal glue logic is used on the CPU module to provide the chip select signal, CS#, for
the LCDC. A simple AND gate activates the SED1374/75 whenever the PC Card slot #1
is accessed, whether it be memory space or attribute space.
SDU1374/75-TMPR3912/22U CPU Module
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X00A-G-004-01
SDU1374/75-TMPR3912/22U CPU Module
Issue Date: 98/12/23
SED1374 Embedded Memory Color LCD Controller
Interfacing to an 8-bit Processor
Document Number: X26A-G-013-01
Copyright © 1999 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.
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SED1374
X26A-G-013-01
Interfacing to an 8-bit Processor
Issue Date: 99/05/04
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Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Interfacing to an 8-bit Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 The Generic 8-bit Processor System Bus . . . . . . . . . . . . . . . . . . . . . 8
3
SED1374 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Host Bus Pin Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Generic #2 Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
8-Bit Processor to SED1374 Interface
4.1 Hardware Description . . . . . .
4.2 SED1374 Hardware Configuration .
4.3 Register/Memory Mapping . . . .
5
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1 Epson LCD/CRT Controllers (SED1374) . . . . . . . . . . . . . . . . . . . . 15
Interfacing to an 8-bit Processor
Issue Date: 99/05/04
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Page 5
List of Tables
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4-1: Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4-2: Host Bus Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
List of Figures
Figure 4-1: Typical Implementation of an 8-bit Processor to the SED1374 Generic #2 Interface . . . 11
Interfacing to an 8-bit Processor
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X26A-G-013-01
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SED1374
X26A-G-013-01
Interfacing to an 8-bit Processor
Issue Date: 99/05/04
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Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware environment required to provide an interface
between the SED1374 Embedded Memory LCD Controller and a generic 8-bit microprocessor.
The designs described in this document are presented only as examples of how such
interfaces might be implemented. This application note will be updated as appropriate.
Please check the Epson Electronics America Website at http://www.eea.epson.com for the
latest revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
Interfacing to an 8-bit Processor
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2 Interfacing to an 8-bit Processor
2.1 The Generic 8-bit Processor System Bus
Although the SED1374 does not directly support an 8-bit CPU, with minimal external
logic, an 8-bit interface can be achieved.
Typically, the bus of an 8-bit microprocessor is straight forward with minimal CPU and
system control signals. To connect a memory mapped device such as the SED1374, only
the write, read, and wait control signals, as well as the data and address lines, need to be
interfaced. Since the SED1374 is a 16-bit device, some external logic is required.
SED1374
X26A-G-013-01
Interfacing to an 8-bit Processor
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Vancouver Design Center
Page 9
3 SED1374 Bus Interface
This section is a summary of the host bus interface modes available on the SED1374 and
offers some detail on the Generic #2 Host Bus Interface used to implement the interface to
an 8-bit processor.
The SED1374 provides a 16-bit interface to the host microprocessor which may operate in
one of several modes compatible with most of the popular embedded microprocessor
families. The bus interface mode used in this example is:
• Generic #2 (this bus interface is ISA-like and can easily be modified to support an 8-bit
CPU).
3.1 Host Bus Pin Connection
The following table shows the functions of each host bus interface signal.
Table 3-1: Host Bus Interface Pin Mapping
SED1374
Pin Names
Generic #2
AB[15:1]
A[15:1]
AB0
A0
DB[15:0]
D[15:0]
WE1#
BHE#
CS#
External Decode
Chip Select
BCLK
BCLK
Bus Clock
BS#
n/c
Must be tied to IO VDD
RD/WR#
n/c
Must be tied to IO VDD
RD#
RD#
Read
WE0#
WE#
Write
WAIT#
WAIT#
RESET#
RESET#
Description
Address [15:1]
Address A0
Data
Byte High Enable
For details on configuration, refer to the SED1374 Hardware Functional Specification,
document number X26A-A-001-xx.
Interfacing to an 8-bit Processor
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3.2 Generic #2 Interface Mode
Generic #2 Host Bus Interface is a general, non-processor specific interface mode on the
SED1374 that is ideally suited to interface to an 8-bit processor bus.
The interface requires the following signals:
• BUSCLK is a clock input which synchronizes transfers between the host CPU and the
SED1374. It is separate from the input clock (CLKI) and is typically driven by the host
CPU system clock. If the host CPU bus does not provide this clock, an asynchronous
clock can be provided.
• The address inputs AB0 through AB15, and the data bus DB0 through DB15, connect
directly to the CPU address and data bus, respectively. On 32-bit big endian architectures such as the Power PC, the data bus would connect to the high-order data lines; on
little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data
lines. The hardware engineer must ensure that CNF3 selects the proper endian mode
upon reset.
Note
In an 8-bit environment D[7:0] must also be connected to D[15:8] respectively
(see Figure 4-1: “Typical Implementation of an 8-bit Processor to the SED1374 Generic
#2 Interface” )
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper
memory address space.
• BHE# (WE1#) is the high byte enable for both read and write cycles.
Note
In an 8-bit environment, this signal is driven by inverting address line A0 thus indicating
that odd addresses are to be R/W on the high byte of the data bus.
• WE0# is the enable signal for a write access, to be driven low when the host CPU is
writing the 1374 memory or registers.
• RD# is the read enable for the SED1374, to be driven low when the host CPU is reading
data from the SED1374.
• WAIT# is a signal which is output from the SED1374 to the host CPU that indicates
when data is ready (read cycle) or accepted (write cycle) on the host bus. Since host
CPU accesses to the SED1374 may occur asynchronously to the display update, it is
possible that contention may occur in accessing the 1374 internal registers and/or
refresh memory. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete. This signal is active low and may need to be
inverted if the host CPU wait state signal is active high.
• The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in the bus interface for Generic #2 mode. However, BS# is used to configure the SED1374 for
Generic #2 mode and should be tied high (connected to IO VDD). RD/WR# should also
be tied high.
SED1374
X26A-G-013-01
Interfacing to an 8-bit Processor
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Vancouver Design Center
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4 8-Bit Processor to SED1374 Interface
4.1 Hardware Description
The interface between the SED1374 and an 8-bit processor requires minimal glue logic. A
decoder is used to generate the chip select for the SED1374 based on where the SED1374
is mapped into memory. Alternatively, if the processor supports a chip select module, it can
be programmed to generate a chip select for the SED1374 without the need of an address
decoder.
An inverter inverts A0 to generate the Byte High Enable signal for the SED1374. If the
8-bit host interface has an active high WAIT signal, it must be inverted as well.
In order to support an 8-bit microprocessor with a 16-bit peripheral, the low and high order
bytes of the data bus must be connected together. The following diagram shows a typical
implementation of an 8-bit processor to SED1374 interface.
Generic 8-bit Bus
SED1374
A[15:0]
AB[15:0]
D[7:0]
DB[7:0]
DB[15:8]
Decoder
CS#
WAIT#
WAIT#
WE#
WE0#
RD#
RD#
A0
BHE# (WE1#)
IO VDD
RD/WR#
BS#
BUSCLK
BUSCLK
System RESET
RESET#
Note:
When connecting the SED1374 RESET# pin, the system designer should be aware of all
conditions that may reset the SED1374 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of an 8-bit Processor to the SED1374 Generic #2 Interface
Interfacing to an 8-bit Processor
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4.2 SED1374 Hardware Configuration
The SED1374 uses CNF4 through CNF0 and BS# to allow selection of the bus mode and
other configuration data on the rising edge of RESET#. Refer to the SED1374 Hardware
Functional Specification, document number X26A-A-001-xx for details.
The tables below show only those configuration settings important to the 8-bit processor
interface. The endian must be selected based on the 8-bit processor used.
Table 4-1: Configuration Settings
Signal
CNF0
CNF1
CNF2
CNF3
CNF4
Low
High
See “Host Bus Selection” table below See “Host Bus Selection” table below
Little Endian
Active low LCDPWR signal
Big Endian
Active high LCDPWR signal
= configuration for 8-bit processor host bus interface
Table 4-2: Host Bus Selection
CNF2
1
CNF1
1
CNF0
1
BS#
1
Host Bus Interface
Generic #2, 16-bit
= required configuration for this application.
4.3 Register/Memory Mapping
The SED1374 needs a 64K byte block of memory to accommodate its 40K byte display
buffer and its 32 byte register set. The starting memory address is located at 0000h of the
64K byte memory block while the internal registers are located in the upper 32 bytes of this
memory block. (i.e. REG[0]= FFE0h).
An external decoder can be used to decode the address lines and generate a chip select for
the SED1374 whenever the selected 64K byte memory block is accessed. If the processor
supports a general chip select module, its internal registers can be programmed to generate
a chip select for the SED1374 whenever the SED1374 memory block is accessed.
SED1374
X26A-G-013-01
Interfacing to an 8-bit Processor
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Vancouver Design Center
Page 13
5 Software
Test utilities and Windows® CE v2.0 display drivers are available for the SED1374. Full
source code is available for both the test utilities and the drivers.
The test utilities are configurable for different panel types using a program called
1374CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can
be customized by the OEM for different panel types, resolutions and color depths only by
modifying the source.
The SED1374 test utilities and Windows CE v2.0 display drivers are available from your
sales support contact or on the internet at http://www.eea.epson.com.
Interfacing to an 8-bit Processor
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6 References
6.1 Documents
• Epson Research and Development, Inc., SED1374 Embedded Memory LCD Controller
Hardware Functional Specification; Document Number X26A-A-002-xx.
• Epson Research and Development, Inc., SDU1374B0C Rev. 1.0 ISA Bus Evaluation
Board User Manual; Document Number X26A-G-005-xx.
• Epson Research and Development, Inc., Programming Notes and Examples; Document
Number X26A-G-002-xx.
6.2 Document Sources
• Epson Electronics America Website: http://www.eea.epson.com.
SED1374
X26A-G-013-01
Interfacing to an 8-bit Processor
Issue Date: 99/05/04
Epson Research and Development
Vancouver Design Center
Page 15
7 Technical Support
7.1 Epson LCD/CRT Controllers (SED1374)
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
Interfacing to an 8-bit Processor
Issue Date: 99/05/04
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
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Epson Research and Development
Vancouver Design Center
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Interfacing to an 8-bit Processor
Issue Date: 99/05/04