Serial RTC with Alarm and Timer
RTC - 4573
· Built-in frequency adjusted 32.768KHz crystal oscillator
· Serial interface that can be controlled through three signal lines
· Week , Day , hour , and minute alarm interrupt functions
· Interval timer interrupt function that can be set with an interval ranging from 1/4096th of a second to 255minutes
· Dual dedicated interrupt outputs for software maskable alarms and for timers
· Functions that detect halting of crystal oscillation, and when the time is being updated
· Automatic leap year compensation function
· Wide interface voltage range, from 1.6 to 5.5V
· Wide timing voltage range, from 1.6 to 5.5V
· Low current consumption : 0.5mA/3V (typ.)
· Small SOP package suited for high-density mounting
n Overview
This module is a serial interface-type real-time clock with a crystal oscillator on chip. This module includes clock
and calendar circuitry (from seconds to years) with automatic leap year compensation, alarms, and timer interrupt
functions, as well as functions that detect when oscillation is halted, the time is being updated. The serial
interface permits control through three signal lines, keeping the number of ports required on the system side to a
minimum. Because the small SOP package can be used in high-density mounting, this module is ideal for
portable telephones, hand-held terminals, and other compact electronic equipment.
n
Block Diagram
CONTROL LINE
32.768KHz
DIVIDER
OSC
FOUT
CLOCK and
CALENDAR
OUTPUT
TIMER
REGISTER
CONTROLLER
/ TIRQ
/ AIRQ
DATA
CLK
C E1
INTERRUPTS
ALARM
REGISTER
CONTROLLER
CONTROL
REGISTER
BUS
INTERFACE
CIRCUIT
C E0
SHIFT REGISTER
Page-1
Aug. 1998
n
Pin Connection
1. N.C
18 N.C
#1
#18
2. N.C
17 N.C
3 N.C
16 N.C
4 N.C
15 N.C
5 CE1
14 V DD
6 DATA
13 FOUT
7. CLK
12 CE0
11. / AIRQ
8. N.C
#9
#10
9 GND
Symbol
Pin-No.
I/O
10 / TIRQ
Function
Chip enable 1 input pin.
This terminal has pull-down resistor built-in. Access to this RTC is possible in
Input
"H" level both CE0,CE1 terminal. FOUT terminal can output frequency when
inputs "H" level into this terminal regardless of state of CE0 terminal. FOUT
terminal is high impedance state in input "L" level.
This I/O pin is used to for setting write mode/read mode, for writing an
Biaddress, and for reading and writing data. This pin functions either as an
directional input pin or an output pin, according to the write mode/read mode setting
made in the first 8 bits of input data following the rising edge of the CE input.
Shift clock input pin. In write mode, the data is read from the DATA pin at
Input
the rising edge of the CLK signal; in read mode, the data is output from the
DATA pin at the rising edge of the CLK signal.
Connect to the negative (ground) line of the power supply.
CE1
5
DATA
6
CLK
7
GND
9
/ TIRQ
10
Output
Open drain interrupt output pin for the interval timer.
/ AIRQ
11
Output
Output Open drain interrupt output pin for alarms.
CE0
12
Input
FOUT
13
Output
VDD
14
-
Chip enable 0 input pin.
When high, access to the internal registers is enabled. While low, the
DATA pin goes to high impedance. When the CE pin is set low, the fr, TEST,
and RESET bits are forcibly cleared to "0".Set this pin low when turning the
power on, when the device is not to be accessed, and when using the
backup power supply. This pin does not affect FOUT terminal.
Frequency output terminal. Frequency is selectable by software.
Connect to the positive line of the power supply.
Access is possible between 1.6 and 5.5V
1,2,3,
4,8,
Although these pins are not connected internally, they should always be left
15,16,
open in order to obtain the most stable oscillation possible.
17,18
* Always connect a passthrough capacitor of at least 0.1mF as close as possible between VDD and GND.
N.C.
Page-2
Aug.1998
Electrical Characteristics
n
1. Absolute Maximum Ratings
Description
Power supply Voltage
Input Voltage
Output Voltage
Temperature
Symbol
VDD
VIN1
VOUT1
VOUT2
TSTG
Conditions
input pins
/ TIRQ,/ AIRQ
FOUT,DATA
-
Symbol
VDD
VCLK
TOPR
Conditions
-
Rated values
-0.3 to +7.0
GND-0.3 to VDD+0.3
-0.3 to +8.0
GND-0.3 to VDD+0.3
-55 to +125
Unit
V
V
V
MIN.
1.6
1.6
Unit
V
V
°C
°C
2. Operating Condition
Item
Supply Voltage
Data Holding Voltage
Operating Temperature Range
MAX.
5.5
5.5
+85
3. Frequency Characteristics
Item
Frequency accuracy
Oscillator start up time
Temperature characteristics
Voltage characteristics
* Monthly error of about 1 minute
Symbol
Conditions
Specifications
Unit
f / fo
tSTA
Ta=25 °C,VDD=3V
Ta=25°C,VDD=1.6V
-10 to 70 °C 25 °C(Typ)
Ta=25°C,VDD=1.6 to 5.5V
5 ± 23 *
3 (MAX)
+10 / -120
± 2.0
ppm
sec
ppm
ppm / V
4. DC Characteristics
Description
Standby current 1
Standby current 2
Input Voltage
Input leakage current
PulIdown R 1
PulIdown R 2
Output voltage 1
Symbol
IDD1
IDD2
VIH
VIL
ILK
RDWN1
RDWN2
VOH1
VOH2
VOH3
VOL1
VOL2
VOL3
Output voltage 2
Leakage current
VOL4
VOL5
IOZ
Conditions
VDD=5V
CE0,CE1=GND
VDD=3V
CE0,CE1=GND
CE0,CE1
CLK,DATA pins
VI=VDD or GND
CLK pins
VDD=5V
VDD=3V
CE0,CE1 pins
VDD=5V
IOH=-1mA
VDD=3V
DATA,FOUT pins
VDD=3V
IOH=-100mA
DATA,FOUT pins
VDD=5V
IOL=1mA
VDD=3V
DATA,FOUT pins
VDD=3V
IOL=100 mA
DATA,FOUT pins
VDD=5V
IOL=1mA
VDD=3V
/ AIRQ,/ TIRQ pins
VO=GND or VDD
DATA,/ AIRQ,/ TIRQ pins
Page-3
MIN.
0.8VDD
0
(VDD =1.6 to 5.5V,Ta=-40 to 85°C )
TYP.
MAX.
Unit
1.0
2.0
mA
0.5
1.0
mA
VDD
V
0.2VDD
V
-0.5
-
0.5
mA
75
150
4.5
2.0
2.9
150
300
300
600
5.0
3.0
3.0
kW
kW
V
V
V
GND+0.5
GND+0.8
GND+0.1
V
V
V
GND+0.25
GND+0.4
V
V
0.5
mA
-0.5
Aug.1998
5. AC Characteristics
Description
CLK clock cycle
CLK H Pulse Width
CLK L Pulse Width
CE setup time
CE hold time
CE recovery time
CLK hold time
Write DATA in setup time
Write DATA in hold time
Read DATA in delay time
Output disable delay time
rise and fall time
FOUT duty ratio
( 32.768kHz output )
Symbol
t CLK
t WH
t WL
t CS
t CH
t CR
t CKH
t DS
t DH
t RD
t RZ
t RF
Duty
tCS
CLK
( CL=50pF,Ta=-40 to 85 °C )
VDD=5.0V±10%
MIN.
TYP.
MAX.
Unit
600
ns
300
ns
300
ns
150
ns
200
ns
300
ns
50
ns
50
ns
50
ns
0
200
ns
100
ns
20
ns
VDD=3.0V±10%
MIN.
TYP.
MAX.
1200
600
600
300
400
600
100
50
50
0
400
200
40
35
-
tWL
65
40
tWH
-
60
%
tCH tCKH
50%
CE
50%
tCR
Write Mode
ReadMode
t DS t DH
t RF
t RF
90%
CLK
CLK
50%
50%
10%
t RD
90%
DATA
DATA
50%
Hi-Z
50%
10%
t RZ
CE
CE
50%
50%
t CS
Page-4
Aug.1998
n
Register Table
Address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Function
Sec
Min
Hour
Week
Day
Month
Year
Minutes Alarm
Hours Alarm
Week Alarm
Day Alarm
FOUT control
Timer interrupt control
Count Down Timer
Control 1
Control 2
bit7
fos
fr
fr
fr
fr
fr
80
AE
AE
AE
AE
FE
TE
128
*
*
bit6
40
40
*
6
*
*
40
40
*
6
*
*
*
64
*
TEST
bit5
bit4
bit3
20
10
8
20
10
8
20
10
8
5
4
3
20
10
8
*
10
8
20
10
8
20
10
8
20
10
8
5
4
3
20
10
8
FD4
FD3
*
TD1
TD0
*
32
16
8
*
TI/TP
AF
STOP RESET HOLD
bit2
4
4
4
2
4
4
4
4
4
2
4
FD2
*
4
TF
*
bit1
2
2
2
1
2
2
2
2
2
1
2
FD1
*
2
AIE
*
bit0
1
1
1
0
1
1
1
1
1
0
1
FD0
*
1
TIE
*
1.1 Timekeeping/calendar registers (register 0 to register 6)
· The data in these registers is BCD format. For example, "0101 1001" represents 59 seconds. In addition, the
"*" mark in the register table means that the register is readable and writable, and can be used as RAM. Time is
kept in the 24-hour format.
· Writing to a bit marked with an asterisk ("*") is permitted; such bits can be used as RAM. When the alarm and
timer functions are not used, registers 7 to A can be used as 8-bit memory registers, and registers C and D can
be used as 7-bit memory registers.
· Year register and leap years
A leap year is detected by dividing the two BCD digits of the year register by four; if the remainder is zero, the
year is a leap year. Therefore, leap years can be automatically determined whether the year is numbered
according to the western calendar or the Japanese calendar (year of Heisei).
· Day of the week
The day of the week register uses 7 bits, from 0 to 6; the meanings of the bits are shown in the table below.
not set more than one bit to "1" at any one time.
bit 6
0
0
0
0
0
0
1
bit 5
0
0
0
0
0
1
0
bit 4
0
0
0
0
1
0
0
bit 3
0
0
0
1
0
0
0
bit 2
0
0
1
0
0
0
0
bit 1
0
1
0
0
0
0
0
bit 0
1
0
0
0
0
0
0
Do
day of week
Sunday
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
· fos ( OSC Flag )
This flag uses it for a monitor of battery listing degradation with the binary digit which that oscillation stopped is
set at. Oscillation stopping shows "1", and it is cleared by writing in "0". But fo flag can't write in "0" when
oscillation stopped. And fo can write in "1", but don't write in it. Other binary digit (HOLD,STOP,RESET) doesn't
receive affect even in case of "1".
· fr ( READ Flag )
It is the binary digit that turn into "1" when CE was input, and carry occurred during "H" for 1 second. The distinction
that carry to a figure rose during (CE input ="H" during readout of register in an indicator by this for 1 second is
possible. When fr was "1", I need to read register in all indicators once again.
Page-5
Aug.1998
1.2 Alarm registers (register 7 to register A)
Alarms can be set for days of the week, hours, and minutes. Bit 7 of each alarm register is an AE bit that can be
used to set an hourly alarm or a daily alarm. An alarm can also be set for multiple days of the week.However, when
using the day of the week alarm, also set either or both the hour and minute alarms. If the day of the week alarm is
set by itself, the alarm may not be output properly.When the AE bit is "0", the register in question and the timekeeping
register is compared; when the AE bit is "1", this indicates "don't care", and the registers are assumed to match,
regardless of the data.
1.3. Frequency output control register ( Reg-B )
FE bit is Frequency output enable bit. Source clock is selectable by FD4 and FD3 bits. And Count down rate is
selectable by FD0 , FD1 and FD2 bits. This frequency is output from FOUT terminal.
FOUT control ( Reg.B )
FD4
0
0
1
1
FD3
0
1
0
1
FD2
0
0
0
0
1
1
1
1
Source Clk.
32768Hz
1024Hz
32Hz
1Hz
FD1
0
0
1
1
0
0
1
1
FD0
0
1
0
1
0
1
0
1
Div.
1/1
1/2
1/3
1/6
1/5
1 / 10
1 / 15
1 / 30
FOUT Duty
50%
50%
33%
50%
20%
50%
33%
50%
1.4. Timer register( Reg-C to Reg-D )
Register-D is presetable binary down counter of 8 bits.
Source clock of this counter does setup by TD bit of Register-C.
Register-D does countdown by a period of selected source clock.
When data of register-D becomes 0, /TIRQ terminal changes to Low level.
In that time, register-D does written data reloads again if TI/TP bit is 1.
And counter does countdown repeatedly.
As a result, by a same period, interrupt occurs repeatedly.
When TIE bit of Register-E is "0", /TIRQ terminal keep high impedance.
When TI/TP bit is 0, Register-D does never reload the data.
Set TI/TP.TD,TIE and TE bits carefully, for perfect function of timer.
Source clock control for Timer ( Reg.C )
TD1
0
0
1
1
TD0
0
1
0 sec.
1 min.
Source Clk.
4096Hz
64Hz
update
update
When TEbit is 0, Register-D loads preset data, and keeps stop. Note:There isn't pause.
When TE bit is cleared, Register-D starts countdown from preset data.
Timer interrupt doesn't occur when set 0 in Register-D.
Therefore pay attention because 1 period error of source clock occurs as for timer time.
Timing of Timer start
Address C
DATA LOAD
CLK
DATA
TD0
TD1
*
TE
ZERO
TIMER COUNT DOWN
TIRQ-PIN
COUNT DOWN
Page-6
Aug.1998
1.5. Control register1 ( Reg-E )
Address
E
bit 7
*
bit 6
*
bit 5
*
bit 4
TI/TP
bit 3
AF
bit 2
TF
bit 1
AIE
bit 0
TIE
TI / TPbits: ( Interrupt Signal Output Mode Select. Timer-Interrupt / Timer-Periodic )
output mode of timer signaling.
bit
TI / TP
0
1
TIRQ terminal is maintained by "L" till it is
written in "0" at TF bit when turn into interrupt
mode, and timer interrupt occurs, and, but,
timer interrupt signal does it with TIE=1
Timer interrupt signaling is set in a mode
repeatedly. When timer interrupt occurs,
TIRQ terminal is set at "L" immediately and,
but, does it with TIE=1. TF bit is set in "1",
and TIRQ terminal is set in Hi-Z after
approximately 3.9 m s, and TF bit holds "1" till
it is write clear by "0".
AF / TF bits: ( Alarm Flag / Timer Flag )
When alarm occurs, AF bit is set in "1", and a timer is set in "1" at 0 o?clock, and TF bit can?t write in "1" at both bit.
AIE,TIE bits: ( Alarm / Timer Interrupt Enable )
It is decided whether IRQ terminal drives it when alarm, timer interrupt occurred, and AIE corresponds in alarm, and
TIE corresponds to a timer, and AIRQ terminal is set in case of "0" AIE bit by Hi-Z, and TIRQ terminal is set in case of
"0" TIE bit by Hi-Z.
1.6
Control register 2 (register F )
Address
F
bit 7
*
bit 6
TEST
bit 5
STOP
bit 4
RESET
bit 3
HOLD
bit 2
*
bit 1
*
bit 0
*
· TEST bit : This is a test bit for Seiko-Epson?s use.
Always set this bit to "0". When writing to the other bits in the CF register, be careful not to accidentally write a "1" to
this bit. This bit is cleared by setting CE low.
· STOP bit
If this bit is set to "1", timekeeping stops (after 4KHz).
If this bit is set back to "0", timekeeping resumes.
· RESET bit
Setting this bit to "1" resets the counter below the seconds counter, stopping timekeeping. If a "1" is written to this bit,
it is cleared either by writing a "0" to this bit again with the auto increment function, or by setting CE low.
The only effect on timekeeping precision is a maximum error 61 [micro]s. This bit is unaffected by the status of other
bits.
· HOLD bit
This bit stops carries to the ones digit of the seconds counter. Timekeeping continues below the seconds counter,
and if there was a carry to the seconds counter while HOLD = 1, compensation (by means of adding one second) is
made immediately (within 0 to 122 [micro]s) after HOLD is released.This bit is cleared by writing a "0" to it.
Page-7
Aug.1998
n
Usage
Functional Overview
The basic sequence for reads and writes is the same: after the CE input goes high, the 4-bit mode is set, the 4-bit
address is specified, and then the data is read or written in 8-bit units.If the input of an 8-bit unit of data is not yet
complete when the CE input is set low, the 8-bit data that was being written when the CE input went low is ignored.
(Prior data is valid. Also, in these circumstances, the WF bit is set to "1", indicating that the write operation was not
completed normally.)Writes and reads are both LSB first.
[ Writes ]
1) After the CE input goes high, set the value of the first four write bits is to "3", indicating write mode, and then set
the address to be written in the next four bits.
2) The 8 bits of write data that follow are written to the address that was set; the address is then automatically
incremented, and the next 8 bits of data are written to the new address.
3) The automatic address incrementation is cyclic, with address 0 following address F.
CE
---
CLK
DATA
D0
D1
D2 D3
Write mode
CODE=3 (0011)
D0 D1
D2 D3
D0
D1 D2 D3
Write to address (N)
D4
D5 D6
D7 D0
D1
Write DATA to (N)
D2
D3
D4 D5
---
D6 D7
Write DATA
(to address N + 1)
[ Reads ]
1) After the CE input goes high, set the value of the first four write bits to "C", indicating read mode, and then set the
address to be written in the next four bits.
2) The 8 bits of data that follow are read from the address that was set; the address is then automatically
incremented, and the next 8 bits of data are read from the new address.
3) The automatic address incrementation is cyclic, with address 0 following address F.
CE
----
CLK
DATA
D0 D1 D2
D3 D0
Set readout mode
CODE=C (1100)
D2
READ address (N)
D0
D2
D4
READ DATA
(address N)
D6
D0
D2
D4
D6
---
READ DATA
( address N + 1)
If the mode setting code was set to a value other than "C" or "3", the subsequent data is ignored and the DATA pin
remains in the input state.
Page-8
Aug.1998
n
Examples of External Connections
D1
Note
4.7uF
VDD
SCI7701
or SCI7721
VDD
Schottky
Barrier
Diode
+
RTC4573
VO
VSS
Voltage
Detector
VDD
CE1
CE0
0.1uF
DATA
CLK
/ TIRQ
/ AIRQ
FOUT
GND
D 1 : 1SS108 or Equivalent
n
Vf = 0.1V
Package Outline
11.4 0.2
5.4
7.8 0.2
0.15
1.8 2.0
MAX.
0.4
1.27
0 MIN.
0 - 10
0.12
0.6
0.2
0.1
Page-9
Aug.1998
Reference data
( 1 ) Frequency temperature characteristics
( typical )
Finding the frequency stability (clock error)
1. The frequency temperature characteristics can be
approximated by using the following expression:
qT = 25°C TYP.
a = -0.035ppm/°C² TYP.
DfT(ppm)=a(qT-qX) 2
D f T(ppm)
: Frequency deviation at target temperature
2
a (ppm/ °C ) : Secondary temperature coefficient
2
(-0.035 0.005ppm/ °C )
: Peak temperature (25°C ± 5°C)
q T (°C)
: Target temperature
q X (°C)
10
0
-10
-20
Frequency dft[ppm]
n
-30
-40
2. To determine the overall clock accuracy, add the
frequency tolerance and the voltage characteristics:
-50
-60
Df/f(ppm) = Df/f0 + DfT + DfV
-70
-80
-90
-100
-110
-120
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
D f /f (ppm)
: Clock accuracy at a given temperature
and voltage
D f /f 0 (ppm)
D f T (ppm)
: Frequency tolerance
: Temperature dependent frequency
deviation
: Voltage dependent frequency deviation
D f V (ppm)
Temperature [°C]
3. Finding the daily deviation:
Daily deviation (seconds) = Df/f x 10-6 x 86400
The clock error is one second per day at 11.574 ppm.
( 2 ) Frequency voltage characteristics
( typical )
( 3 ) Current consumption voltage characteristics
( typical )
Frequency[ppm]
Current consumption [µA]
Conditions
+ 10
3V reference , Ta=+25°C
4
Conditions
CE0,CE1=0V,No load
+5
Ta=+25 °C
3
0
2
Supply voltage VDD[V]
-5
1
Supply voltage VDD[V]
- 10
2
3
4
5
2
3
4
5
Note : This data shows average values for a sample lot.
For rated values, see the spacifications on page 3.
Page-10
Aug.1998
n
Notes on Use
( 1 ) Notes on handling
In order to attain low power consumption, this module incorporates a CMOS IC.
should be kept in mind when using this module.
Therefore, the following points
1. Static electricity
While this module does have built-in circuitry designed to protect it against damage from electrostatic discharge, the
module could still be damaged by an extremely large electrostatic discharge. Therefore, packing materials and
shipping containers should be made of conductive materials.Furthermore, use soldering equipment, test circuits, etc.,
that do not have high-voltage leakage, and ground such equipment when working with it.
2. Electronic noise
If excessive external noise is applied to the power supply and
I/O pins, the module may operate incorrectly or may even be
damaged as a result of the latch-up phenomenon.
In order to assure stable operation, connect a passthrough
capacitor (ceramic is recommended) of at least 0.1mF located as
closely as possible to the power supply pins on this module
(between VDD and GND). Furthermore, do not place a device
that generates high noise levels near this module.Keep signal
lines away from the shaded areas shown in the figure at right,
and fill the area with a GND pattern, if possible.
3. Electric potential of I/O pins
Because having the electric potential of the input pins at an intermediate level contributes to increased power
consumption, reduced noise margin, and degradation of the device, keep the electric potential as close as possible
to the electric potential of VDD or GND.
4. Treatment of unused input pins
Because the input impedance of the input pins is extremely high and using the module with these pins open can
result in unstable electric potential and misoperation due to noise, unused input pins must always be connected to a
pull-up or pull-down resistor.
Page-11
Aug.1998
( 2 ) Notes on mounting
1. Soldering temperature conditions
If the internal temperature of the package exceeds 260°C, the characteristics of the crystal resonator may deteriorate
and the package may be damaged. Therefore, before using this module, be sure to confirm what temperatures it
will be exposed to during the mounting process. If the mounting temperature conditions are ever changed, the
suitability of those temperature conditions for this package must be confirmed again.
Soldering conditions: Up to 260°C for up to 10 seconds, twice, or up to 230°C for up to 3 minutes.
Example of SMD Product Soldering Conditions
Infrared reflow
Vapor phase reflow
Temp.( °C)
Temp.( °C)
10 sec. max
30 sec. max
235 ° C max
200
1 to 5 °C/sec
200
220 ° C max
1 to 5 °C/sec
1 to 5 ° C/sec
100
0
1 to 5 ° C/sec
100
1 to 5 ° C/sec
pre-heating
60 sec. min
0
200 sec. max
1 to 5 ° C/sec
pre-heating
60 sec. min
Time
200 sec. max
Time
2. Mounters
While this module can be used with general-purpose mounters, be sure to confirm the force of impact that the
module will be subjected to during mounting, since certain machines or conditions can result in damage to the
internal crystal resonator. If the mounting conditions are ever changed, the suitability of those conditions for this
package must be confirmed again.
3. Ultrasonic cleaning
Under certain conditions, ultrasonic cleaning can damage the crystal resonator. Because we cannot specify the
conditions under which you perform ultrasonic cleaning (including the type of cleaner, the power level, the duration,
the condition of the inside of the chamber, etc.), Seiko-Epson does not warrant this product against ultrasonic
cleaning.
4. Mounting orientation
If this module is mounted backwards, it may be damaged.
mounting it.
Always confirm the orientation of the module before
5. Leakage between pins
If power is supplied to this module while it is dirty or while condensation is present, leakage between pins may result.
Be sure that the module is clean and dry before supplying power to it.
Page-12
Aug.1998