GRAPHICS SED1353 October 1998 SED1353 GRAPHICS LCD CONTROLLER ■ DESCRIPTION The SED1353 is a dot matrix graphic LCD controller supporting resolutions up to 1024x1024. It is capable of displaying a maximum of 256 simultaneous colors out of a possible 4096 or 16 gray shades. Design flexibility allows the SED1353 to interface to either an MC68000 family microprocessor or an 8/16-bit MPU/bus with minimum external logic. The Static RAM (SRAM) interface used for the display buffer is optimized for speed and performance, supporting up to 128K bytes. Two power save modes, combined with operating voltages of 2.7 volts through 5.5 volts, allow for a wide range of applications while providing minimum power consumption. ■ FEATURES • pin compatible with the SED1352 • 16-bit 16 MHz MC68xxx MPU interface • 8/16-bit MPU interface controlled by a READY (or WAIT#) signal • option to use built-in index register or direct-mapping to access one of sixteen internal registers • 2-terminal crystal or external oscillator support • 8/16-bit SRAM interface configurations • split screen display support allowing two different images to be simultaneously displayed • virtual display support (displays images larger than the panel size through the use of panning) • display modes: black-and-white display 2/4 bits per pixel, 4/16-level gray-scale display 2/4/8 bits per pixel, 4/16/256-level color display • two software power-save modes • low power consumption • display memory interface: 128K bytes using one 64Kx16 SRAMs 128K bytes using two 64Kx8 SRAMs 64K bytes using two 32Kx8 SRAMs 40K bytes using one 8Kx8 and one 32Kx8 SRAM 32K bytes using one 32Kx8 SRAM 16K bytes using two 8Kx8 SRAMs 8K bytes using one 8Kx8 SRAM • LCD panel configurations: single-panel, single-drive passive display dual-panel, dual-drive passive display • maximum number of vertical lines: 1,024 lines (single-panel, single-drive display) 2,048 lines (dual-panel, dual-drive display) • QFP5-100-S2 package (F0A) • QFP15-100-STD package (F1A) ■ SYSTEM BLOCK DIAGRAM CLOCK DATA MPU 80xx Z80 68xxx CONTROL ADDRESS SED1353 LCD PANEL SRAM X18A-C-001-08 1 GRAPHICS SED1353 ■ INTERFACE OPTIONS Interface with 16-Bit MC68xxx MPU and 16K bytes SRAM (2 of 8K x 8) MC68xxx A20 to A23 FC0 to FC1 SED1353 Decoder MEMCS# A14 to A16 Decoder IOCS# A10 to A19 VD8-15 VD0-7 VWE# A1 to A19 AB1 to AB19 D0 to D15 DB0 to DB15 DTACK# READY UDS# AB0 LDS# BHE# AS# R/W# IOR# IOW# WE# 64 Kbit WE# 64 Kbit CS# CS# WE# WE# VCS0# VCS1# VA0-12 Note: Example implementation, actual may vary. Interface with 8-Bit Z80 MPU and 16K bytes SRAM (2 of 8K x 8) Z80 Decoder MREQ# MI# SED1353 MEMCS# A10 to A15 Decoder IORQ# A0 to A15 D0 to D7 WAIT# WR# RD# RESET# IOCS# VD0-7 VWE# AB0 to AB15 DB0 to DB7 READY 64 Kbit CS# 64 Kbit CS# MEMW# MEMR# VCS0# IOR# VCS1# IOW# VA0-12 RESET Note: Example implementation, actual may vary. 2 X18A-C-001-08 GRAPHICS SED1353 Interface with 16-Bit 8086 MPU and 64K bytes SRAM (2 of 32K x 8) 8086 (Maximum mode) CLK CLK READY RESET# RDY SED1353 8288 CLK READY RESET# S2# S1# S0# AMWC# S1# S0# DEN 8284A MEMR# MEMW# MRDC# S2# VD0-7 VWE# IOR# IORC# IOW# AIOWC# WE# DT/R ALE 256 Kbit A16 to A19 CS# AB16 to AB19 Decoder A16 BHE# AD0 to AD15 VCS0# VA0-14 M/IO# AB0 to AB15 BHE# BHE# A0 to A16 MEMCS# STB IOCS# WE# D0 to D15 DB0 to DB15 CS# 256 Kbit T OE Transceiver RESET READY VCS1# VD8-15 Note: Example implementation, actual may vary. Interface with 8-Bit ISA Bus and 40K bytes SRAM (1 of 8K x 8 and 1 of 32K x 8) 8-Bit ISA Bus REFRESH SED1353 SA13 to SA16 VD0-7 VWE# MEMCS# Decoder SMEMW# MEMW# SMEMR# MEMR# IOCHRDY READY SD0 to SD7 DB0 to DB7 SA10 to SA15 SA(1 or 4) to SA9 Decoder IOCS# AEN IOW# IOW# IOR# IOR# RESET 0WS# 64 Kbit CS# AB0 to AB19 SA0 to SA19 RESET# WE# VCS0# VA0-14 WE# 256 Kbit optional CS# Decoder VCS1# Note: Example implementation, actual may vary. X18A-C-001-08 3 GRAPHICS SED1353 Interface with 16-Bit ISA Bus and 128K bytes SRAM (1 of 128K x 8) 16-bit ISA Bus SED1353 REFRESH SA14 to SA16 MEMCS# Decoder SMEMW# MEMW# SMEMR# MEMR# IOCHRDY READY VWE# SD0 to SD15 DB0 to DB15 SA0 to SA19 AB0 to AB19 SA10 to SA15 SA(1 or 4) to SA9 Decoder IOCS# AEN IOW# IOW# IOR# SBHE# RESET# IOR# BHE# WE# 1 Mbit VCS0# LB# VCS1# UB# A0-15 VA0-15 RESET IOCS16# VD0-7 I/O 1-8 VD8-15 I/O 9-16 Decoder LA17 to LA23 Decoder MEMCS16# Note: Example implementation, actual may vary. ■ SUPPORTED RESOLUTIONS Example Display Size Display RAM Monochrome X 8K byte 16K byte Y 320 x 200 512 x 256 4 Grays/ Colors X Y 256 x 128 320 x 200 16 Grays/ Colors X Y 128 x 128 256 Colorsa X SRAM Type CPU Interface 1 of 8Kx8 8-bit 8-bit 8-bit 8-bit/16-bit 16-bit 16-bit SRAM Interface Y — 200 x 160 160 x 100a a 2 of 8Kx8 32K byte 512 x 512 512 x 256 256 x 256 192 x 100 1 of 32Kx8 8-bit 8-bit 40K byte 1024 x 320 512 x 320 320 x 256 320 x 128a 1 of 8Kx8 and 1 of 32Kx8 8-bit 8-bit 64K byte 1024 x 512 512 x 512 512 x 256 256 x 256a 2 of 32Kx8 8-bit 8-bit/16-bit 16-bit 16-bit 128K byte 1024 x 1024 1024 x 512 512 x 512 512 x 256a 1 of 64Kx16 16-bit 16-bit 2 of 64Kx8 16-bit 16-bit a. 256 colors must use 16-bit SRAM interface The above listed display sizes are examples based on bits/pixel and available memory. 4 X18A-C-001-08 GRAPHICS SED1353 ■ BLOCK DIAGRAM Control Registers IOR#, IOW#, IOCS#, MEMCS#, MEMR#, MEMW#, BHE#, AB[19:0] Bus Signal Translation READY DB[15:0] Port Decoder Sequence Controller Memory Decoder Lookup Table Data Bus Conversion Address Generator Timing Generator Power Save Oscillator LCD Panel Interface UD[3:0] LD[3:0] LP, YD, XSCL, WF(XSCL2) Display Data Formatter MPU/CRT Selector SRAM Interface VD[15:0] VA[15:0] VSC0#, VSC1# VOE# VWE# OSC2 OSC1 X18A-C-001-08 LCDENB 5 GRAPHICS SED1353 ■ FUNCTIONAL BLOCK DESCRIPTION Bus Signal Translation According to configuration setting VD2, Bus Signal Translation translates either MC68000 type MPU signals or Ready type MPU signals to internal bus interface signals. Data Bus Conversion According to configuration setting VD0, Data Bus Conversion maps the external data bus, either 8-bit or 16-bit, into the internal odd and even data bus. Control Registers The Control Register contains 16 internal control and configuration registers. These registers can be accessed by either direct-mapping or using the built-in internal index register. Address Generator The Address Generator generates display refresh addresses to be used to access display memory. Sequence Controller The Sequence Controller generates horizontal and vertical display timings according to the configuration registers settings. LCD Panel Interface The LCD Panel Interface performs frame rate modulation and output data pattern formatting for both passive monochrome and passive color LCD panels. Look-Up Table The Look-Up Table contains three 16x4-bit wide palettes. In gray shade modes, the “green” palette can be configured for the re-mapping of 16 possible shades of gray. In color modes, all three palettes can be configured for the re-mapping of 4096 possible colors. Port Decoder According to configuration settings VD1, VD12 VD4, IOCS# and address lines AB9-1, the Port Decoder validates a given I/O cycle. Memory Decoder According to configuration settings VD15 VD13, MEMCS# and address lines AB19-17, the Memory Decoder validates a given memory cycle. 6 MPU / CRT Selector The MPU / CRT Selector grants access to the display memory from either the MPU or the display refresh circuitry. Display Data Formatter The Display Data Formatter reads in the display data from the display memory and outputs the correct format for all supported gray shade and color selections. Clock Inputs / Timing Clock Inputs / Timing generates the internal master clock according to gray-level / color selected and display memory interface.The master clock (MCLK) can be: - MCLK = input clock - MCLK = 1/2 input clock - MCLK = 1/4 input clock. Pixel clock = input clock = fOSC. SRAM Interface The SRAM Interface generates the necessary signals to interface to the Display Memory (SRAM). X18A-C-001-08 GRAPHICS SED1353 ■ DC SPECIFICATIONS Absolute Maximum Ratings Symbol Parameter Rating Units VSS - 0.3 to + 6.0 V VDD Supply Voltage VIN Input Voltage VSS - 0.3 to VDD + 0.5 V VOUT Output Voltage VSS - 0.3 to VDD + 0.5 V TSTG Storage Temperature -65 to 150 °C TSOL Solder Temperature/Time 260 for 10 sec. max at lead °C Recommended Operating Conditions Parameter Symbol VDD Supply Voltage VIN Input Voltage IOPR Operating Current TOPR Operating Temperature PTYP Typical Active Power Consumption X18A-C-001-08 Condition Min Typ Max Units VSS = 0 V 2.7 3.0/3.3/5.0 5.5 V VSS -- VDD V fOSC = 6 MHz 256 colors 4.5/5.0/11 -40 fOSC = 6 MHz 256 colors 25 13.5/16.5/55 mA 85 °C mW 7 GRAPHICS SED1353 Input Specifications Symbol 8 Parameter Condition Min Typ Max Units 0.8 0.4 0.3 V VIL Low Level Input Voltage VDD = 4.5V VDD = 3.0V VDD = 2.7V VIH High Level Input Voltage VDD = 5.5V VDD = 3.6V VDD = 3.3V VT+ Positive-going Threshold VDD = 5.0 VDD = 3.3 VDD = 3.0 VT- Negative-going Threshold VDD = 5.0 VDD = 3.3 VDD = 3.0 0.6 0.5 0.4 V VH Hysteresis Voltage VDD = 5.0 VDD = 3.3 VDD = 3.0 0.1 0.1 0.1 V IIZ Input Leakage Current -- -1 CIN Input Pin Capacitance f =1 MHz, VDD= 0V RPD Pull Down Resistance RPD Pull Down Resistance RPD Pull Down Resistance VDD = 5.0V VI = VDD VDD = 3.3V VI = VDD VDD = 3.0V VI = VDD 2.0 1.3 1.2 V 2.4 1.4 1.3 V 1 µA 12 pF 50 100 200 kΩ 90 180 360 kΩ 100 200 400 kΩ X18A-C-001-08 GRAPHICS SED1353 Output Specifications Symbol Parameter Condition Low Level Output Voltage VDD = Min VOL (5.0V) Type 1 - TS1D2, CO1 Type 2 - TS2, CO2 Type 3 - TS3, CO3, CO3S IOL = 4 mA IOL = 8 mA IOL = 12 mA Low Level Output Voltage VDD = Min VOL (3.3V) Type 1 - TS1D2, CO1 Type 2 - TS2, CO2 Type 3 - TS3, CO3, CO3S IOL = 2 mA IOL = 4 mA IOL = 6 mA Low Level Output Voltage VDD = Min VOL (3.0V) Type 1 - TS1D2, CO1 Type 2 - TS2, CO2 Type 3 - TS3, CO3, CO3S High Level Output Voltage VOH (5.0V) Type 1 - TS1D2, CO1 Type 2 - TS2, CO2 Type 3 - TS3, CO3, CO3S IOL = 1.8 mA IOL = 3.5 mA IOL = 5 mA IOH = -4 mA IOH = -8mA IOH = -12 mA Units 0.4 V 0.3 V 0.3 V V VDD-0.3 V IOH = -1.8 mA IOH = -3.5 mA IOH = -5 mA VDD-0.3 V -1 VOH (3.3V) Type 1 - TS1D2, CO1 Type 2 - TS2, CO2 Type 3 - TS3, CO3, CO3S IOL = -2 mA IOL = -4 mA IOL = -6 mA VDD = Min 1 µA f =1 MHz, VDD= 0V 12 pF f =1 MHz, VDD= 0V 12 pF IOZ Output Leakage Current -- COUT Output Pin Capacitance CBID Bidirectional Pin Capacitance X18A-C-001-08 Max VDD-0.4 VDD = Min VOH (3.0V) Type 1 - TS1D2, CO1 Type 2 - TS2, CO2 Type 3 - TS3, CO3, CO3S Typ VDD = Min Low Level Output Voltage High Level Output Voltage Min 9 GRAPHICS SED1353 ■ SED1353F0A PIN OUT UD1 UD0 LD3 LD2 LD1 LD0 YD 51 VD7 52 VSS 53 VDD 54 VD8 55 VD9 56 VD10 57 VD11 58 VD12 59 VD13 60 VD14 61 VD15 62 VA11 63 VA12 64 VA13 65 VA14 66 VA15 67 VWE# 68 VCS0# 69 VCS1# 70 UD3 71 UD2 72 73 74 75 76 77 78 LP WF/XSCL2* XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# MEMR# READY BHE# OSC1 OSC2 DB0 DB1 DB2 DB3 DB4 DB5 DB6 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VD6 VD5 VD4 VD3 VD2 VD1 VD0 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0 RESET AB19 SED1353F0A 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 AB18 AB17 AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 30 29 28 27 26 25 24 23 22 21 20 19 18 AB5 17 AB4 16 AB3 15 AB2 14 AB1 13 AB0 12 DB15 11 DB14 10 DB13 9 DB12 8 DB11 7 DB10 6 DB9 5 DB8 4 VDD 3 VSS 2 DB7 1 * Pin 80 = WF in all display modes except format 1 for 8-bit single color panel. * Pin 80 = XSCL2 in format 1 for 8-bit single color panel. 10 X18A-C-001-08 GRAPHICS SED1353 ■ SED1353F1A PIN OUT UD1 UD0 LD3 51 VD8 52 VD9 53 VD10 54 VD11 55 VD12 56 VD13 57 VD14 58 VD15 59 VA11 60 VA12 61 VA13 62 VA14 63 VA15 64 VWE# 65 VCS0# 66 VCS1# 67 UD3 68 UD2 69 70 71 LD2 LD1 LD0 YD SED1353F1A VDD VSS VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0 RESET AB19 AB18 AB17 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 AB16 24 AB15 23 AB14 22 AB13 21 AB12 20 AB11 19 AB10 18 AB9 17 AB8 16 AB7 15 AB6 14 AB5 13 AB4 12 AB3 11 AB2 10 AB1 9 AB0 8 DB15 DB14 7 DB13 6 DB12 5 DB11 4 DB10 3 DB9 2 DB8 1 LP WF/XSCL2* XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# MEMR# READY BHE# OSC1 OSC2 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VSS VDD 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 * Pin 77 = WF in all display modes except format 1 for 8-bit single color panel. * Pin 77 = XSCL2 in format 1 for 8-bit single color panel. X18A-C-001-08 11 GRAPHICS SED1353 ■ SED1353D0A PIN OUT VSS 80 VDD VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 XSCL LCDENB VOE# IOCS# IOW# VA11 VA12 VA13 VA14 VA15 VWE# VCS0# VCS1# YD UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 LP 90 WF/XSCL2* Dummy Pad 70 VD7 100 VD6 VD5 VD4 VD3 VD2 60 VD1 VD0 IOR# MEMCS# MEMW# MEMR# VA10 VA9 110 50 SED1353D0A READY BHE# VA8 VA7 OSC1 OSC2 VA6 VA5 DB0 DB1 VA4 VA3 120 AB18 = = = = 30 AB17 Chip Size Chip Thickness Pad Size Pad Pitch 20 AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 10 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 VDD VSS Dummy Pad 1 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 DB7 VA2 VA1 VA0 RESET AB19 40 DB2 DB3 DB4 DB5 DB6 5.030 mm x 5.030 mm 0.400 mm 0.090 mm x 0.090 mm 0.126 mm (Min.) * Pad 97 = WF in all display modes except format 1 for 8-bit single color panel. * Pad 97 = XSCL2 in format 1 for 8-bit single color panel. 12 X18A-C-001-08 GRAPHICS SED1353 PAD Coordinates Pad No. Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VSS --VDD DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 --AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 --AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 --AB17 AB18 ----AB19 X18A-C-001-08 Pad Center Coordinate X Y -2.165 -2.390 -2.000 -2.390 -1.840 -2.390 -1.685 -2.390 -1.535 -2.390 -1.388 -2.390 -1.246 -2.390 -1.106 -2.390 -0.969 -2.390 -0.835 -2.390 -0.703 -2.390 -0.573 -2.390 -0.444 -2.390 -0.317 -2.390 -0.190 -2.390 -0.063 -2.390 0.063 -2.390 0.190 -2.390 0.317 -2.390 0.444 -2.390 0.573 -2.390 0.703 -2.390 0.835 -2.390 0.969 -2.390 1.106 -2.390 1.246 -2.390 1.388 -2.390 1.535 -2.390 1.685 -2.390 1.840 -2.390 2.000 -2.390 2.165 -2.390 2.390 -2.340 2.390 -2.000 2.390 -1.840 2.390 -1.685 Pad No. Pin Name 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 RESET VA0 VA1 VA2 --VA3 VA4 --VA5 VA6 --VA7 VA8 --VA9 VA10 --VD0 VD1 --VD2 VD3 VD4 VD5 VD6 ----VD7 VSS --VDD VD8 VD9 VD10 VD11 VD12 Pad Center Coordinate X Y 2.390 -1.535 2.390 -1.388 2.390 -1.246 2.390 -1.106 2.390 -0.969 2.390 -0.835 2.390 -0.703 2.390 -0.573 2.390 -0.444 2.390 -0.317 2.390 -0.190 2.390 -0.063 2.390 0.063 2.390 0.190 2.390 0.317 2.390 0.444 2.390 0.573 2.390 0.703 2.390 0.835 2.390 0.969 2.390 1.106 2.390 1.246 2.390 1.388 2.390 1.535 2.390 1.685 2.390 1.840 2.390 2.000 2.390 2.165 2.165 2.390 2.000 2.390 1.840 2.390 1.685 2.390 1.535 2.390 1.388 2.390 1.246 2.390 1.106 2.390 13 GRAPHICS SED1353 14 Pad No. Pin Name 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 VD13 VD14 VD15 --VA11 VA12 VA13 VA14 VA15 VWE# VCS0# VCS1# --UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 YD --LP WF/XSCL2 ----XSCL LCDENB Pad Center Coordinate X Y 0.969 2.390 0.835 2.390 0.703 2.390 0.573 2.390 0.444 2.390 0.317 2.390 0.190 2.390 0.063 2.390 -0.063 2.390 -0.190 2.390 -0.317 2.390 -0.444 2.390 -0.573 2.390 -0.703 2.390 -0.835 2.390 -0.969 2.390 -1.106 2.390 -1.246 2.390 -1.388 2.390 -1.535 2.390 -1.685 2.390 -1.840 2.390 -2.000 2.390 -2.340 2.390 -2.390 2.165 -2.390 2.000 -2.390 1.840 -2.390 1.685 -2.390 1.535 Pad No. Pin Name 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 VOE# IOCS# IOW# --IOR# MEMCS# --MEMW# MEMR# --READY BHE# --OSC1 OSC2 --DB0 DB1 --DB2 DB3 DB4 DB5 DB6 ----DB7 Dummy Pad Dummy Pad Pad Center Coordinate X Y -2.390 1.388 -2.390 1.246 -2.390 1.106 -2.390 0.969 -2.390 0.835 -2.390 0.703 -2.390 0.573 -2.390 0.444 -2.390 0.317 -2.390 0.190 -2.390 0.063 -2.390 -0.063 -2.390 -0.190 -2.390 -0.317 -2.390 -0.444 -2.390 -0.573 -2.390 -0.703 -2.390 -0.835 -2.390 -0.969 -2.390 -1.106 -2.390 -1.246 -2.390 -1.388 -2.390 -1.535 -2.390 -1.685 -2.390 -1.840 -2.390 -2.000 -2.390 -2.165 2.390 2.390 -2.390 -2.390 X18A-C-001-08 GRAPHICS SED1353 ■ PIN DESCRIPTION Key I O I/O P = = = = Input Output Bidirectional Power Bus Interface Pin Name Type F0A Pin # F1A Pin # D0A Pad # Description DB0-DB15 I/O 94 - 100, 91 - 98, 1, 4 -11 1 - 8 118-119, 121-125, These pins are connected to the system data bus. In 8-bit bus mode, DB8128, DB15 must be tied to VDD. 4-11 AB0 12 9 13 In MC68000 MPU interface, this pin is connected to the Upper Data Strobe (UDS#) pin of MC68000. In other bus interfaces, this pin is connected to the system address bus. 10 - 28 14-20, 22-30, 32-33, 36 These pins are connected to the system address bus. I AB1-AB19 I 13 - 31 BHE# I 91 88 113 In MC68000 MPU interface, this pin is connected to the Lower Data Strobe (LDS#) pin of MC68000. In other bus interfaces, this pin is the Byte High Enable input for use with 16-bit system. In 8-bit bus mode, tie BHE# input to VDD. IOCS# I 84 81 103 Active low input to select one of fifteen internal registers. 104 In MC68000 MPU interface, this pin is connected to the R/W# pin of MC68000. This input pin will define whether the data transfer is a read (active high) or write (active low) cycle. In other bus interfaces, this is the active low input to write data into an internal register. IOW# I 85 82 IOR# I 86 83 106 In MC68000 MPU interface, this pin is connected to the AS# pin of MC68000. This input pin will indicate a valid address is available on the address bus. In other bus interfaces, this is the active low input to read data from an internal register. MEMCS# I 87 84 107 Active low input to indicate the attempt to access the display memory. MEMW# I 88 85 109 Active low input to write data to the display memory. This pin should be tied to VDD in an MC68000 MPU interface. MEMR# I 89 86 110 Active low input to read data from the display memory. This pin should be tied to VDD in an MC68000 MPU interface. READY O 90 87 112 For MC68000 MPU interface, this pin is connected to the DTACK# pin of MC68000 and will be driven low when ever a data transfer is complete. In other bus interfaces, this output is driven low to force the system to insert wait states when needed. READY is placed in a high-impedance (Hi-Z) state after the transfer is completed. RESET I X18A-C-001-08 32 29 37 Active high input to force all signals to their inactive states. 15 GRAPHICS SED1353 Display Memory Interface Pin Name Type VD0-VD15 I/O F0A Pin # 44 - 51, 54 - 61 F1A Pin # D0A Pad # 41 - 48, 51 - 58 54-55, 57-61, 64, 68-75 30 - 40 59 - 63 Description These pins are connected to the display memory data bus. For 16-bit interface, VD0-VD7 are connected to the display memory data bus of even byte addresses and VD8-VD15 are connected to the display memory data bus of odd byte addresses. The output drivers of these pins are tri-stated when RESET is high. On the falling edge of RESET the values of VD0-VD15 are latched into the chip to configure various hardware options. 38-40, 42-43, 45-46, 48-49, 51-52, 77-81 VA0-VA15 O 33 - 43, 62 - 66 VCS1# O 69 66 84 Active low chip-select output to the second or odd byte address SRAM. VCS0# O 68 65 83 Active low chip-select output to the first or even byte address SRAM. VWE# O 67 64 82 Active low output used for writing data to the display memory. This pin is connected to the WE# input of the SRAMs. VOE# O 83 80 102 Active low output to enable reading of data from the display memory. This pin is connected to the OE# input of the SRAMs. These pins are connected to the display memory address bus. LCD Interface Pin Name FPDI-1TM Pin Namea Type F0A Pin # F1A Pin # D0A Pad # Description UD3-UD0 LD3-LD0 UD3-UD0 LD3-LD0 O 70 - 73 74 - 77 67 - 70 71 - 74 86 - 89 90 - 93 Panel display data bus. The data format depends on the specific panel connected. For 4-bit single panels, these bits are driven 0 (low state). XSCL FPSHIFT O 81 78 100 Display data shift clock. Data is shifted into the LCD X-drivers on the falling edge of this signal. LP FPLINE O 79 76 96 Display data latch clock. The falling edge of this signal is used to latch a row of display data in the LCD X-drivers and to turn on the row driver (Y driver). O 80 77 97 For format 1 of 8-bit single color panels this is the second shift clock. For all other modes,this is the LCD backplane BIAS signal. This output toggles once every n LP periods, as programmed in AUX[05] MOD WF/XSCL2 FPSHIFT2 YD FPFRAME O 78 75 94 Vertical scanning start pulse. A logic ‘1’ on this signal, sampled by the LCD module on the falling edge of LP, is used by the panel row driver (Y driver) to indicate the start of the vertical frame. LCDENB --- O 82 79 101 LCD enable signal output. It can be used externally to turn off the panel supply voltage and backlight. a. VESA Flat Panel Display Interface Standard (FPDI-1TM) 16 X18A-C-001-08 GRAPHICS SED1353 Clock Inputs Pin Name Type F0A Pin # F1A Pin # D0A Pad # Description OSC1 I 92 89 115 This pin, along with OSC2 is the 2-terminal crystal interface when using a 2-terminal crystal as the clock input. If an external oscillator is used as a clock source, then this pin is the clock input. OSC2 O 93 90 116 This pin, along with OSC1 is the 2-terminal crystal interface when using a 2-terminal crystal as the clock input. If an external oscillator is used as a clock source, then this pin should be left unconnected. Power Supply Pin Name Type F0A Pin # F1A Pin # D0A Pad # Description VDD P 3, 53 50, 100 3, 67 Voltage supply. VSS P 2, 52 49, 99 1, 65 Voltage Ground. ■ SUMMARY OF CONFIGURATION OPTIONS Pin Name value on this pin at falling edge of RESET is used to configure: (1/0) 1 0 VD0 16-bit host bus interface 8-bit host bus interface VD1 Use direct-mapping for I/O accesses Use indexed mapping for I/O accesses VD2 MC68000 MPU interface MPU / Bus interface with memory accesses controlled by a READY (WAIT#) signal VD3 Swap of high and low data bytes in 16-bit bus interface No byte swap of high and low data bytes in 16-bit bus interface Select I/O mapping address bits [9:1]. VD12-VD4 These nine bits are latched on power-up and are compared to the MPU address bits [9-1]. A valid I/O cycle combined with a valid address will enable the internal I/O decoder. Therefore, both types of I/O mapping are limited to even address boundaries to determine either the absolute or indexed I/O address of the first register. Note that a “valid I/O cycle” includes IOCS# being toggled low. Select memory mapping address bits [3:1] These three bits are latched on power-up and are compared to the MPU address bits [19-17]. A valid memory cycle combined with a valid address will enable the internal memory decoder. As only the three most significant VD15-VD13 bits of the address are compared, the maximum amount of memory supported is 128K bytes. Note that a “valid memory cycle” includes MEMCS# being toggled low. When using 128K byte memory it must be mapped at an even address such that all 128K bytes is available without a change in state on A17, as this would invalidate the internal compare logic. X18A-C-001-08 17 GRAPHICS SED1353 Example: If an ISA bus (no byte swap) with memory segment “A” and I/O location 300h are used, the corresponding settings of VD15-VD0 would be: Pin Name VD0 VD1 VD2 VD3 VD12-VD4 VD15-VD13 8-Bit ISA Bus 16-Bit ISA Bus Index Index Direct Mapping Direct Mapping Register Register 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 11 0000 000 11 0000 xxx 11 0000 000 11 0000 xxx 101 101 101 101 Where x = don’t care; 1 = connected to pull-up resistor; 0 = not connected to pull-up resistor 18 X18A-C-001-08 GRAPHICS SED1353 ■ MONOCHROME PASSIVE STN LCD PANEL INTERFACE 4-Bit Single Panel LP : 240 PULSES LP: 4 PULSES YD LP WF UD[3:0] LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 LP WF XSCL: 80 CLOCK PERIODS XSCL UD3 1-1 1-5 1-317 UD2 1-2 1-6 1-318 UD1 1-3 1-7 1-319 UD0 1-4 1-8 1-320 Example Timing for a 320x240 single panel X18A-C-001-08 19 GRAPHICS SED1353 ■ MONOCHROME PASSIVE STN LCD PANEL INTERFACE 8-Bit Single Panel LP : 480 PULSES LP: 4 PULSES YD LP WF UD[3:0], LD[3:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 LP WF XSCL:80 CLOCK PERIODS XSCL UD3 1-1 1-9 1-633 UD2 1-2 1-10 1-634 UD1 1-3 1-11 1-635 UD0 1-4 1-12 1-636 LD3 1-5 1-13 1-637 LD2 1-6 1-14 1-638 LD1 1-7 1-15 1-639 LD0 1-8 1-16 1-640 Example timing for a 640x480 panel 20 X18A-C-001-08 GRAPHICS SED1353 ■ MONOCHROME PASSIVE STN LCD PANEL INTERFACE 8-Bit Dual Panel LP : 240 PULSES LP: 2 PULSES YD LP WF UD[3:0], LD[3:0] LINE1/241 LINE2/242 LINE3/243 LINE4/244 LINE1/241 LINE 239/479 LINE240/480 LINE2/242 LP WF XSCL: 160 CLOCK PERIODS XSCL UD3 1-1 1-5 1-637 UD2 1-2 1-6 1-638 UD1 1-3 1-7 1-639 UD0 1-4 1-8 1-640 LD3 241-1 241-5 241-637 LD2 241-2 241-6 241-638 LD1 241-3 241-7 241-639 LD0 241-4 241-8 241-640 Example timing for a 640x480 panel X18A-C-001-08 21 GRAPHICS SED1353 ■ COLOR PASSIVE STN LCD PANEL INTERFACE 4-Bit Single Panel LP: 4 PULSES LP : 240 PULSES YD LP UD[3:0] LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 LP WF XSCL: 240 CLOCK PERIODS XSCL 1-R1 1-G2 1-B3 1-B319 UD2 1-G1 1-B2 1-R4 1-R320 UD1 1-B1 1-R3 1-G4 1-G320 UD0 1-R2 1-G3 1-B4 1-B320 UD3 Example timing for a 320x240 panel 22 X18A-C-001-08 GRAPHICS SED1353 ■ COLOR PASSIVE STN LCD PANEL INTERFACE 8-Bit Single Panel - Format 1 LP: 480 PULSES LP: 4 PULSES YD LP UD[3:0] LD[3:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 LP XSCL2: 120 CLOCK PERIODS XSCL2 XSCL: 120 CLOCK PERIODS XSCL UD3 1-R1 1-G1 1-G6 1-B6 1-B11 1-R12 1-B635 1-R636 UD2 1-B1 1-R2 1-R7 1-G7 1-G12 1-B12 1-G636 1-B636 UD1 1-G2 1-B2 1-B7 1-R8 1-R13 1-G13 1-R637 1-G637 UD0 1-R3 1-G3 1-G8 1-B8 1-B13 1-R14 1-B637 1-R638 LD3 1-B3 1-R4 1-R9 1-G9 1-G14 1-B14 1-G638 1-B638 LD2 1-G4 1-B4 1-B9 1-R10 1-R15 1-G15 1-R639 1-G639 LD1 1-R5 1-G5 1-G10 1-B10 1-B15 1-R16 1-B639 1-R640 LD0 1-B5 1-R6 1-R11 1-G11 1-G16 1-B16 1-G640 1-B640 Example timing for a 640x480 panel X18A-C-001-08 23 GRAPHICS SED1353 ■ COLOR PASSIVE STN LCD PANEL INTERFACE 8-Bit Single Panel - Format 2 LP: 4 PULSES LP : 240 PULSES YD LP UD[3:0] LD[3:0] LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 LP WF XSCL: 120 CLOCK PERIODS XSCL UD3 1-R1 1-B3 1-G6 1-G318 UD2 1-G1 1-R4 1-B6 1-B318 UD1 1-B1 1-G4 1-R7 1-R319 UD0 1-R2 1-B4 1-G7 1-G319 LD3 1-G2 1-R5 1-B7 1-B319 LD2 1-B2 1-G5 1-R8 1-R320 LD1 1-R3 1-B5 1-G8 1-G320 LD0 1-G3 1-R6 1-B8 1-B320 Example timing for a 320x240 panel 24 X18A-C-001-08 GRAPHICS SED1353 ■ COLOR PASSIVE STN LCD PANEL INTERFACE 8-Bit Dual Panel LP: 2 PULSES LP: 240 PULSES YD LP LINE1 UD[3:0] LINE2 LINE241 LINE242 LD[3:0] LINE3 LINE4 LINE239 LINE240 LINE243 LINE244 LINE479 LINE480 LINE1 LINE2 LINE241 LINE242 LP WF XSCL: 480 CLOCK PERIODS XSCL UD3 1-R1 1-G2 1-B3 1-R637 1-G638 1-B639 UD2 1-G1 1-B2 1-R4 1-G637 1-B638 1-R640 UD1 1-B1 1-R3 1-G4 1-B637 1-R639 1-G640 UD0 1-R2 1-G3 1-B4 1-R638 1-G639 1-B640 LD3 241-R1 241-G2 241-B3 241-R637 241-G638 241-B639 LD2 241-G1 241-B2 241-R4 241-G637 241-B638 241-R640 LD1 241-B1 241-R3 241-G4 241-B637 241-R639 241-G640 LD0 241-R2 241-G3 241-B4 241-R638 241-G639 241-B640 Example timing for a 640x480 panel X18A-C-001-08 25 GRAPHICS SED1353 ■ COLOR PASSIVE STN LCD PANEL INTERFACE 16-Bit Single Panel With External Circuit LP : 480 PULSES LP: 4 PULSES YD LP Pixel Data LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 WF XSCL: 120 CLOCKS 1-G636 1-R639 UD1 1-R5 1-R637 1-B639 UD0 1-R3 1-B5 1-B637 1-G640 LD3 1-G1 1-R4 1-R636 1-B638 LD2 1-R2 1-B4 1-B636 1-G639 LD1 1-B2 1-G5 1-G637 1-R640 LD0 1-G3 1-R6 1-R638 1-B640 UD7 1-R1 1-B635 UD6 1-B1 1-G636 UD5 1-G2 1-R637 UD4 1-R3 1-B637 UD3 1-B3 1-G638 UD2 1-G4 1-R639 UD1 1-R5 1-B 639 UD0 1-B5 1-G640 LD7 1-G1 1-R636 LD6 1-R2 1-B636 LD5 1-B2 1-G637 LD4 1-G3 1-R638 LD3 1-R4 1-B638 LD2 1-B4 1-G639 LD1 1-G5 1-R640 LD0 1-R6 1-B640 Example timing for a 640x480 panel 26 CK 1-G4 1-G2 XSCL 1-B1 Q UD2 D 1-B635 1-G638 FROM SED1353 1-B3 UD[7:4] LD[7:4] 1-R1 UD[3:0] LD[3:0] UD3 TO 16-BIT PANEL XSCL UD[3:0] LD[3:0] 16-BIT PANEL INPUTS SED1353 OUTPUTS LP X18A-C-001-08 GRAPHICS SED1353 ■ COLOR PASSIVE STN LCD PANEL INTERFACE 16-Bit Dual Panel With External Circuit LP: 2 PULSES LP : 240 PULSES YD LP Pixel Data LINE1/241 LINE2/242 LINE3/243 LINE4/244 LINE239/479 LINE240/480 LINE1/241 LINE2/242 WF XSCL: 240 CLOCKS XSCL 1-R4 1-B638 1-R640 UD1 1-R3 1-G4 1-R639 1-G640 UD0 1-R2 1-G3 1-B4 1-G639 1-B640 LD3 241-R1 241-G2 241-B3 241G638 241B639 LD2 241-G1 241-B2 241-R4 241B638 241R640 LD1 241-B1 241-R3 241-B4 241R639 241G640 LD0 241-R 2 241-G3 241-B4 241G639 241B640 1-R1 1-G638 UD6 1-G1 1-B638 UD5 1-B1 1-R639 UD4 1-R2 1-G639 UD3 1-G2 1-B 639 UD2 1-B2 1-R640 UD1 1-R3 1-G640 UD0 1-G3 1-B640 LD7 241-R1 241-G638 LD6 241-G1 241-B638 LD5 241-B1 241-R639 LD4 241-R2 241-G639 LD3 241-G2 241B639 LD2 241-B2 241R640 LD1 241-R3 241G640 LD0 241-G3 241B640 X18A-C-001-08 FROM SED1353 Example timing for a 640x480 panel D UD7 CK 1-B2 1-B1 XSCL 1-G1 UD[7:4] LD[7:4] 1-B3 Q UD2 1-G638 1-B639 1-G2 TO 16-BIT PANEL 1-R1 UD[3:0] LD[3:0] UD3 UD[3:0] LD[3:0] 16-BIT PANEL INPUTS SED1353 OUTPUTS LP 27 GRAPHICS SED1353 ■ PACKAGE DIMENSIONS: SED1353F0A QFP5-100PIN-S2 (SED1353F0A) 23.2± 0.04 20.0± 0.1 80 51 81 Index 31 100 0.65± 0.1 0.30± 0.1 30 2.7± 0.1 1 0.15± 0.05 17.2± 0.04 14.0± 0.1 50 0~12° 0.8± 0.1 All dimensions in mm 1.6 Actual Size 28 X18A-C-001-08 GRAPHICS SED1353 ■ PACKAGE DIMENSIONS: SED1353F1A QFP15-100PIN-STD (SED1353F1A) 16.0 ± 0.4 14.0 ± 0.1 75 51 16.0 ± 0.4 50 14.0 ± 0.1 76 Index 26 1 1.4 ± 0.1 0.125 ± 0.1 100 0.168± 0.1 25 0.5 0.5 ± 0.2 1 0~12° All dimensions in mm Actual Size X18A-C-001-08 29 GRAPHICS SED1353 ■ COMPREHENSIVE SUPPORT TOOLS Seiko Epson Corp. provides the designer and manufacturer a complete set of resources and tools for the development of LCD Graphics Systems. Documentation • Technical Manuals • Evaluation/Demonstration Board Manual Evaluation/Demonstration Board • Assembled and Fully Tested Graphics Evaluation/Demonstration Board • Schematic of Evaluation/Demonstration Board • Parts List • Installation Guide • CPU Independent Software Utilities • Evaluation Software • Windows CE Display Driver ■ APPLICATION ENGINEERING SUPPORT Seiko Epson Corp. offers the following services through their Sales and Marketing Network: • Sales Technical Support • Customer Training CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS: • SED1353 Technical Manual • SDU1353 Evaluation Boards • CPU Independent Software Utilities Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110 Taiwan, R.O.C. Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan, R.O.C. Tel: 02-2717-7360 Fax: 02-2712-9164 Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716 Copyright ©1997, 1998 Epson Research and Development, Inc. All rights reserved. VDC Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/ EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. 30 X18A-C-001-08