PF805-04 SRM20V100LLMX77 SRM20V100LLMX 1M-Bit Static RAM ge lta Vo ion w t Lo pera cts O odu Pr ● Low Supply Voltage ● Wide Temperature Range ● Low Supply Current ● Access Time 70ns (2.7V) ● 131,072 Words×8-Bit Asynchronous ■ DESCRIPTION The SRM20V100LLMX 7 is an 131,072 words×8-bit asynchronous, static, random access memory on a monolithic CMOS chip. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage with back-up batteries. And —25 to 85°C operating temperature range makes it ideal for portable equipment. The asynchronous and static nature of the memory requires no external clock or refreshing circuit. Both the input and output ports are TTL compatible and 3-state output allows easy expansion of memory capacity. ■ FEATURES ■ PIN CONFIGURATION CS2 OE WE Address Buffer Y Decoder N.C. A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/01 I/02 I/03 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 I/08 I/07 I/06 I/05 I/04 (TSOP/Slim-TSOP) A11 A9 A8 A13 WE CS2 A15 VDD N.C. A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SRM20V100LLTX/KX 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/08 I/07 I/06 I/05 I/04 VSS I/03 I/02 I/01 A0 A1 A2 A3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 I/01 I/02 I/03 VSS I/04 I/05 I/06 I/07 I/08 CS1 A10 OE (TSOP-R1/Slim-TSOP-R1) 1024 Memory Cell Array 1024×128×8 128×8 7 CS1, CS2 Chip Control CS1 10 OE, WE Chip Control A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 X Decoder ■ BLOCK DIAGRAM (SOP6) SRM20V100LLMT ● Wide temperature range ..... –25 to 85°C ● Fast Access time ................. SRM20V100LLMX7 70ns (Max.) ● Low supply current .............. standby: 0.6µA (Typ.): LL Version 0.3µA (Typ.): SL Version operation: 8mA/1MHz (Typ.) ● Completely static ................. No clock required ● Supply voltage..................... 2.7V to 3.6V ● TTL compatible inputs and outputs ● 3-state output with wired-OR capability ● Non-volatile storage with back-up batteries SOP6-32pin (plastic) ● Package ...... SRM20V100LLMX7 SRM20V100LLTX7 TSOP ( I )-32pin (plastic) SRM20V100LLRX7 TSOP ( I )-32pin-R1 (plastic) SRM20V100LLKX7 Slim-TSOP ( I )-32pin (plastic) SRM20V100LLYX7 Slim-TSOP ( I )-32pin-R1 (plastic) 128 Column Gate 8 I/O Buffer I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 A4 A5 A6 A7 A12 A14 A16 N.C. VDD A15 CS2 WE A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SRM20V100LLRX/YX ¡PIN DESCRIPTION A0 to A16 Address Input WE Write Enable OE Output Enable CS1, CS2 Chip Select I/O1 to I/O8 Data I/O VDD Power Supply (2.7V to 3.6V) VSS Power Supply (0V) N. C. No connection 1 ■ ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage Input voltage Input/Output voltage Power dissipation Operating temperature Storage temperature Soldering temperature and time ✻VI, (VSS = 0V) Symbol VDD VI VI/O PD Topr Tstg Tsol V V V W °C °C — VI/O (Min.) = –3.0V (Pulse width is 50ns) ■ DC RECOMMENDED OPERATING CONDITIONS Parameter Supply voltage Input voltage ✻If Unit Ratings –0.5 to 4.6 –0.5 to VDD+0.3 –0.5 to VDD+0.3 0.5 –25 to 85 –65 to 150 260°C, 10s (at lead) Symbol VDD VSS VIH VIL Min. 2.7 0 2.2 –0.3✻ Conditions — — — — (VSS = 0V, Ta = –25 to 85°C) Typ. Max. Unit V 3.0 3.6 V 0 0 V — VDD+0.3 0.4 V — pulse width is less than 50ns, it is –3.0V ■ ELECTRICAL CHARACTERISTICS ● DC Electrical Characteristics (VDD = 2.7 to 3.6V, VSS = 0V, Ta = –25 to 85°C) Symbol Conditions Min. Typ.✻ Max. Unit Input leakage ILI VI=0 to VDD –1 — 1 µA Output leakage ILO CS1 = VIH or CS2 = VIL or WE = VIL or OE = VIH, VIO = 0 to VDD –1 — 1 µA IDDS CS1 = VIH or CS2 = VIL Parameter Standby supply current IDDS1 CS1 = CS2≥VDD—0.2V or CS2≤0.2V — — 1.0 mA LL — 0.6 60 — 0.3 30 µA SL IDDA VI = VIL, VIH II/O = 0mA, tcyc = Min. — 20 35 mA IDDA1 VI = VIL, VIH II/O = 0mA, tcyc = 1µs — 8 15 mA Operating supply current IDDO VI = VIL, VIH II/O = 0mA — 8 15 mA High level output voltage VOH VDD≥3V, IOH = –2.0mA 2.4 — — IOH = –100µA VDD—0.2 — — Low level output voltage VOL VDD≥3V, IOL = –2.0mA — — 0.4 IOL = 100µA — — 0.2 Average operating current ✻Typical values are measured at Ta=25°C and V V DD=3.0V ● Terminal Capacitance (f = 1MHz, Ta = 25°C) Symbol Conditions Min. Typ. Max. Unit Address Capacitance CADD VADD=0V — — 8 pF Input Capacitance CI VI=0V — — 8 pF I/O Capacitance CI/O VI/O=0V — — 10 pF Parameter 2 V SRM20V100LLMX7 ● AC Electrical Characteristics ❍ Read Cycle Parameter Read cycle time Address access time Chip select1 access time Chip select2 access time Output enable access time Chip select1 output set time Chip select1 output floating Chip select2 output set time Chip select2 output floating Output enable output set time Output enable output floating Output hold time (VDD = 2.7V to 3.6V, VSS = 0V, Ta = –25 to 85°C) Symbol tRC tACC tACS1 tACS2 tOE tCLZ1 tCHZ1 tCLZ2 tCHZ2 tOLZ tOHZ tOH Conditions Symbol tWC tCW1 tCW2 tAW tAS tWP tWR tDW tDH tWHZ tOW Conditions Min. 70 — — — — 5 — 5 — 0 — 10 ✻1 ✻2 ✻1 ❍ Write Cycle Min. 70 60 60 60 0 55 0 30 0 — 5 ✻1 ✻2 ✻ Max. — — — — — — — — — 30 — Unit ns ns ns ns ns ns ns ns ns ns ns ✻ 1 Test Conditions 1. Input pulse level: 0.4V to 2.4V +3V 2. t r = t f = 5ns 3. Input and output timing reference levels : 1.5V Unit ns ns ns ns ns ns ns ns ns ns ns ns (VDD = 2.7V to 3.6V, VSS = 0V, Ta = –25 to 85°C) Parameter Write cycle time Chip select time1 Chip select time2 Address enable time Address setup time Write pulse width Address hold time Input data setup time Input data hold time WE Output floating WE Output setup time 4. Output load CL = 100pF Max. — 70 70 70 40 — 30 — 30 — 30 — 1.0kΩ 2 Test Conditions 1. Input pulse level : 0.4V to 2.4V +3V 2. tr = tf = 5ns 3. Input timing reference levels: 1.5V 4. Output timing reference levels: I/O CL 920Ω 1.0kΩ I/O ±200mV (the level displaced from stable output voltage level) CL 920Ω 5. Output load CL = 5pF CL=100pF (Includes Jig Capacitance) CL=5pF (Includes Jig Capacitance) 3 ● Timing chart ❍Read Cylcle✻1 ❍Write Cycle (1) (CS1 Control)✻2 tRC tWC Address tACC tACS1 tOH CS1 tCLZ1 tACS2 tCHZ1 Address CS1 tAW tCW1 tAS tWR CS2 CS2 tCLZ2 tWR tCHZ2 WE tOE OE tWHZ tCLZ1 tOHZ tOLZ Dout tDW Dout tDH Din ❍Write Cycle (2) (CS2 Control)✻2 ❍Write Cycle (3) (WE Control)✻3, ✻4 tWC tWC Address Address tAW tCW2 tAW CS1 CS1 tAS tWR tAS CS2 tWR CS2 tWP WE tWP WE tWHZ tWHZ Dout tDW tCLZ2 tDH Din tOW Dout tDW tDH Din Note : 1. During read cycle time, WE is to be "H" level. 2. During write cycle time that is controlled by CS1 or CS2, Output Buffer is in high impedance state, whether OE level is "H" or "L". 3. During write cycle time that is controlled by WE, Output Buffer is high impedance state if OE is "H" level. 4. When I/O terminals are output mode, be careful that do not give the opposite signals to the I/O terminals. ● DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY (VSS = 0V, Ta = –25 to 85°C) Min. Typ. Max. Unit 2.0 — 3.6 V LL — 0.5✻ 50 SL — 0.25✻ 25 tCDR 0 — — ns tR 5 — — ms Parameter Symbol Data retention Supply voltage VDDR Data retention current IDDR Chip select data hold time Operation recovery time ✻Ta Conditions VDD = 2.7V CS1 = CS2≥VDD—0.2V or CS2≤0.2V = 25°C Data retention timing (CS1 Control) Data retention timing 2.7V VDDR≥2.0V VDD 2.7V tCDR VIH (CS2 Control) Data hold mode Data hold mode VDD CS1 µA VIH VDDR≥2.0V tCDR tR CS1≥VDD—0.2V 2.7V CS2 VIL 2.7V tR CS2≥0.2V VIL ✻ when retaining data in standby mode, supply voltage can be lowered with in a certain range. But read or write cycle cannot be performed while the supply voltage is low. 4 SRM20V100LLMX7 ■ FUNCTIONS ● Truth Table CS1 CS2 OE WE DATA I/O Mode IDD H X X X Hi-Z Unselected IDDS, IDDS1 X L X X Hi-Z Unselected IDDS, IDDS1 L H X L Input data Write IDDO L H L H Output data Read IDDO L H H H Hi-Z Output disable IDDO X : "H" or "L" ● Reading data Data is able to be read when the address is set while holding CS1 = "L", CS2 = "H", OE = "L" and WE = "H". Since DATA I/O terminals are in high impedance state when OE = "H", the data bus line can be used for any other objective, then access time apparently is able to be cut down. ● Writing data There are the following four ways of writing data into the memory. (1) Hold CS2 = "H", WE = "L", set addresses and give "L" pulse to CS1. (2) Hold CS1 = "L", WE = "L" ,set addresses and give "H"pulse to CS2. (3) Hold CS1 = "L", CS2 = "H", set addresses and give "L" pulse to WE. (4) After setting addresses, give "L" pulse to CS1, WE and give "H" pulse to CS2. Anyway, data on the Data I/O terminals are latched up into the SRM20V100LLMX 7 at the end of the period that CS1, WE are "L" level, and CS2 is "H" level. As Data I/O terminals are in high impedance state when any of CS1, OE = "H", or CS2 = "L", the contention on the data bus can be avoided. ● Standby mode When CS1 is "H" or CS2 is "L" level, the SRM20V100LLMX 7 is in the standby mode which has retaining data operation. In this case Data I/O terminals are Hi-Z, and all inputs of addresses, WE and data can be any "H" or "L". When CS1 and CS2 level are in the range over V DD-0.2V, CS2 level is in the range under 0.2V, in the SRM20V100LLMX7 there is almost no current flow except through the high resistance parts of the memory. 5 ■ PACKAGE DIMENSIONS Plastic SOP6-32pin 20.85max (0.82max) ±0.1 20.45+0.004 (0.805 –0.003 ) ±0.3 14.135 +0.012 ±0.1 11.295 +0.003 (0.556 –0.011 ) 17 (0.445 –0.004 ) 32 2.7±0.1 +0.004 16 3.1max (0.122max) 1 (0.106 –0.003 ) 0° 8° 0.15±0.05 +0.001 (0.006 –0.002 ) 0.8±0.2 +0.008 (0.031 –0.007 ) 0.2 ( (0.008) 1.27 (0.05) 0.4±0.1 +0.003 0.016 –0.004 ) 1.42 (0.056) Unit : mm (inch) Plastic TSOP ( I ) -32pin-R1 Plastic TSOP ( I ) -32pin 20±0.2 +0.008 20±0.2 +0.008 (0.787 –0.007 ) (0.787 –0.007 ) ±0.2 18.4+0.008 (0.724 –0.007 ) ±0.2 18.4+0.008 (0.724–0.007) 16 32 17 8±0.2 8±0.2 (0.315±0.007) (0.315±0.007) INDEX INDEX 32 1 17 0° 10° ±0.1 0.5+0.003 1 (0.006 –0.003 ) ±0.1 0.5+0.003 0.2±0.1 +0.003 0.5 (0.02) (0.02 –0.004 ) +0.07 0.15 –0.075 +0.002 0.5 (0.02) (0.02 –0.004 ) (0.008 –0.004 ) 0.8±0.2 +0.008 (0.031 –0.007 ) 1 +0.07 0.15 –0.075 +0.002 (0.006 –0.003 ) 1.27max (0.05max) (0.039) 0° 10° 0.2±0.1 +0.003 (0.008 –0.004 ) 0.8±0.2 +0.008 (0.031–0.007) Unit : mm (inch) Plastic Slim-TSOP ( I ) -32pin 1.27max (0.05max) 16 (0.039) 1 Unit : mm (inch) Plastic Slim-TSOP ( I ) -32pin-R1 13.4±0.3 13.4±0.3 (0.528±0.011) (0.528±0.011) 11.8±0.1 11.8±0.1 (0.465±0.003) (0.465±0.003) 1 16 32 17 (0.315±0.007) 8±0.2 8±0.2 (0.315±0.007) INDEX INDEX 17 32 1 0° 10° ±0.1 0.5+0.003 (0.02 –0.004 ) 0.5 (0.02) 0.2±0.1 +0.003 ±0.1 0.5+0.003 (0.008 –0.004 ) (0.02 –0.004 ) 0.8±0.2 +0.008 (0.031 –0.007 ) 1 0.2±0.1 +0.003 (0.008 –0.004 ) 0.8±0.2 +0.008 (0.031 –0.007 ) Unit : mm (inch) 6 0.5 (0.02) 1.27max +0.07 0.15 –0.075 +0.002 (0.006 –0.003 ) (0.039) 1 1.27max (0.05max) (0.039) +0.07 0.15 –0.075 +0.002 (0.006 –0.003 ) 0° 10° (0.05max) 16 Unit : mm (inch) SRM20V100LLMX7 ■ CHARACTERISTICS CURVES Normalized IDDA—Ta Normalized IDDA—Frequency 1.7 VDD = 3.0V READ, WRITE 1.6 1.5 1 1.6 0.9 1.5 Ta = 25°C VDD = 3.0V 0.8 1.4 1.3 Normalized IDDA—VDD Ta = 25°C READ, WRITE 1.4 0.7 1.3 0.6 1.2 0.5 1.1 WRITE READ 1.2 1.1 WRITE 1 1 0.4 READ WRITE READ 0.3 0.9 0.9 0.8 0.2 0.8 0.7 0.1 0.7 0.6 0 –40 –20 0 20 40 Ta (°C) 60 80 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) 1/tRC, 1/tWC Normalized IDDS1—Ta 0.6 2.4 Normalized IDDS1—VDD 100 3 3.3 VDD (V) 3.6 3.9 Normalized IOH—VOH 100 VDD = 3.0V 2.7 Ta = 25°C 2.4 Ta = 25°C VDD = 3.0V 2.2 2 10 1.8 1.6 1.4 1 1 1.2 1 0.8 0.1 0.6 0.4 0.2 0.01 –40 –20 0 20 40 Ta (°C) 60 80 0.1 2.4 2.7 3 3.3 VDD (V) 3.6 3.9 0 0.5 1 1.5 2 2.5 VOH (V) 3 3.5 7 SRM20V100LLMX7 tACC Normalized tACS1—Ta tACS2 tACC Normalized tACS1—VDD tACS2 1.4 Normalized IOL—VOL 2.2 1.3 VDD = 3.0V 1.3 1.2 Ta = 25°C 1.25 2 1.2 1.8 1.6 1.15 1.4 1.1 1.1 Ta = 25°C VDD = 3.0V 1.2 1.05 1 1.0 1 0.8 0.95 0.9 0.8 0.4 0.85 0.2 0.7 –40 –20 0 20 40 Ta (°C) 60 0.6 0.9 80 0.8 2.4 tACC Normalized tACS1—CL tACS2 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0 2.7 3 3.3 VDD (V) 3.6 3.9 0 0.2 0.4 0.6 VOL (V) 0.8 1 Normalized IDDR—Ta 100 VDD=2.7V Ta = 25°C VDD = 3.0V 10 1 0.1 0.01 0 100 200 300 CL (pF) 400 –40 –20 0 20 40 60 Ta (°C) 80 NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. © Seiko Epson Corporation 1996 All right reserved. ELECTRONIC DEVICE MARKETING DEPARTMENT IC Marketing & Engineering Group 421–8 Hino, Hino–shi, Tokyo 191, JAPAN Phone: 0425–87–5816 FAX: 0425–87–5624 International Marketing Department I (Europe & U. S. A.) 421-8 Hino, Hino-shi, Tokyo 191, JAPAN Phone: 0425–87–5812 FAX: 0425–87–5564 International Marketing Department II (Asia) 8421-8 Hino, Hino-shi, Tokyo 191, JAPAN Phone: 0425–87–5814 FAX: 0425–87–5110 First issue Oct. 1995, printed Feb. 1997 in Japan T