February 1999 PBD 3517/1 Stepper Motor Drive Circuit Description Key Features PBD 3517/1 is a bipolar, monolithic, integrated circuit, intended to drive a stepper motor in a unipolar, bilevel way. One PBD 3517/1 and a minimum of external components form a complete control and drive unit for LS-TTL- or microprocessor-controlled stepper motor system for currents up to 500mA. The driver is suited for applications requiring least-posssible RFI. Motor performance can be increased by operating in a bilevel drive mode. This means that a high voltage pulse is applied to the motor winding at the beginning of a step, in order to give a rapid rise of current. • Complete driver and phase logic on chip • 2 x 350 mA continuous-output current • Half- and full-step mode generation • LS-TTL-compatible inputs • Bilevel drive mode for high step rates • Voltage-doubling drive possibilities • Half-step position-indication output • Minimal RFI • 16-pin plastic DIP package or 16 pin small outline wide body VCC VSS 35 17 /1 PBD 3517/1 LA Mono F-F P B RC D PQR LB STEP 17 /1 PA PB1 D PB 35 PB2 B HSM Phase Logic P DIR INH PA2 OA PA1 OB GND 16-pin plastic DIP 16-pin SO (wide body) Figure 1. Block diagram. 1 PBD 3517/1 Maximum Ratings Parameter Pin No. Symbol Min Max Unit Voltage Logic supply Second supply Logic input 16 15 6, 7, 10, 11 VCC VSS VI 0 0 -0.3 7 45 6 V V V Current Phase output Second-level output Logic input The zero output 1, 2, 4, 5 13, 14 6, 7, 10, 11 8, 9 IP IL II IΟ 0 -500 -10 500 0 6 mA mA mA mA Temperature Operating junction temperature Storage temperature TJ TS -40 -55 +150 +150 °C °C Power Dissipation (Package Data) Power dissipation at TA = 25°C, DIP package. Note 2. Power dissipation, SO package. Note 3. PD PD 1.6 1.3 W W Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Logic supply voltage Second-level supply voltage Phase output current Second-level output current Operating junction temperature Set-up time Step-pulse duration VCC VSS IP IL TJ ts tp 4.75 10 0 -350 -20 400 800 5 5.25 40 350 0 +125 V V mA mA °C ns ns ISS tr ICC VCC VSS 16 15 tf VI PBD 3517/1 VLCE Sat HSM or DIR PQR t RC 12 Mono F-F 13 LA IL 14 LB ILL STEP VSS STEP VCC II IIL IIH VI 7 DIR 6 HSM 10 INH OA OB 8 Phase Logic PA 1 PB2 2 PB1 11 5 PA2 9 4 PA1 3 GND PB VIL t IP IP IPL VL VPCE Sat VIH VOCE Sat VP ts t tp td Figure 2. Definition of symbols. 2 Figure 3. Timing diagram. PBD 3517/1 Electrical Characteristics Electrical characteristics at TA = +25°C, VCC = +5.0 V, VMM = +40 V, VSS = +40 V unless otherwise specified. Ref. Parameter Symbol Fig. Conditions ICC 2 2 INH = LOW INH = HIGH VPCE Sat IPL td td 4 2 3 3 IP = 350 mA VP = 0 V +70°C +125°C Second-level outputs Saturation voltage Leakage current On time VLCE Sat ILL tOn 4 2 11 IL = -350 mA VL = 0 V (note 4) Logic inputs Voltage level, HIGH Voltage level, LOW Input current, low Input current, high VIH VIL IIL IIH 2 2 2 2 VI = 0.4 V VI = 2.4 V Logic outputs Saturation voltage VØCE Sat 5 IØ = 1.6 mA Supply current Phase outputs Saturation voltage Leakage current Turn on, turn off Min -500 220 Typ Max Unit 45 12 60 mA mA 0.85 500 3 6 V µA µs µs 2.0 V µA µs 260 300 2.0 20 V V µA µA 0.4 V 0.8 -400 Notes 1. All voltages are with respect to ground. Current are positive into, negative out of specified terminal. 2 Derates at 12,8 mW/°C above +25°C. 3. Derates at 10.4 mW/°C above +25°C. 4. RT = 47 kΩ, CT = 10 nF. Allowable power dissipation [W] VLCE sat [V] Output Current [A] 2.5 0.5 2.0 0.4 1.5 1.5 0.3 1.0 1.0 0.2 0,5 0,5 0.1 2.5 TA= +25° C 2.0 0 0 0.1 0.2 0.3 0.4 0.5 IL [A] Figure 4. Typical phase output saturation voltage vs. output current. 0 0 50 100 150 0 TA= +25° C 0 Ambient temrature [°C] Figure 5. Typical second level saturation voltage vs output current. 0.2 0.4 0.6 0.8 1.0 Output Voltage [V] Figure 3 PBD 3517/1 Output Current [A] Diagrams Output Pulse Width [s] 10 1 TA= +25° C TA= +25° C 8 How to use the diagrams: 10 -1 1. k 10 -2 6 Rt 10 -3 = 0M 1 t= 0 10 R • The ambient temperature sets the maximum allowable power dissipation in the IC, which relates to the motor currents and the duty cycle of the bilevel function. For PBD 3517/1, without any measures taken to reduce the chip temperature via heatsinks, the power dissipation vs. temperature follows the curve in figure 4. k t= 10 R 4 10 -4 t= 1k R 2 10 -5 10 -6 0 0 0.2 0.4 0.6 0.8 1.0 0.01 0.1 Figure 7. Typical IØ vs. VØCE Sat. “Zero output” saturation. 1 10 100 1000 Ct Capacitance [nF] Output Voltage [V] Figure 8. Typical tOn vs. CT/RT. Output pulse width vs. capacitance/resistance. Output Pulse Width [s] • Figures 9 and 10 give the relationship between motor currents and their dissipations. The sum of these power dissipations must never exceed the previously-established value, or life expectancy will be drastically shortened. (II = 0) Output Current [A] 1 0.5 10 10 -1 TA= +25° C 0% 10 10 -2 TA= +25° C 0.4 Du % tyc yk 50 • When no bilevel or voltage doubling is utilized, the maximum motor current can be found directly in figure 9. 0.3 le % 10 -3 1% 0.2 10 -4 25 2. % 0.1 10 -5 0 0.001 0.01 0.1 1 10 100 0 0.2 0.4 0.6 0.8 1.0 Power Dissipation [W] fs Step frequency [kHz] Figure 9. Typical tOn vs. fs/dc. Output pulse width vs. step frequency/duty cycle. Figure 10. Typical PDP vs. IP. Power dissipation without second-level supply (includes 2 active outputs = FULL STEP). 3. -0.5 Motor Current [mA] TA= +25° C -0.4 10% 50% Normal 100% -0.3 Bilevel without time limit -0.2 -0.1 0 0.2 0.4 0.6 0.8 1.0 tON Time Power Dissipation [W] Figure 11. Typical PDI vs. II. Power dissipation in the bilevel pulse when raising to the II value. One active output. 4 4. Figures 4, 5 and 6 show typical saturation voltages vs. output current levels for different output transistors. 5. Shaded areas represent operating conditions outside the safe operating area. Bilevel 350 0 What is the maximum tOn pulse-width at a given frequency? • Figure 8 shows the relationship between duty cycle, pulse width, and step frequency. Check specifications for the valid operating area. (Ip = 0) Output Current [A] How to choose timing components. • Figure 7 shows the relationship between CT, RT, and tOn. Care must be taken to keep the tOn time short, otherwise the current in the winding will rise to a value many times the rated current, causing an overheated IC or motor. 0. 1% 10 -6 What is the maximum motor current in the application? Figure 12 . Motor Current 1p. PBD 3517/1 PB2 1 16 VCC PB1 2 15 VSS 14 LB GND 3 PA1 4 PA2 5 PBD 3517/1N 13 LA PB2 1 16 VCC PB1 2 15 VSS GND 3 PA1 4 PA2 5 12 RC 14 LB PBD 13 LA 3517/1SO 12 RC DIR 6 DIR 6 STEP 7 ØB 8 11 INH STEP 7 10 HSM 11 INH 10 HSM ØB 8 9 ØA 9 ØA Figure 13. Pin configuration. Pin Description DIP SO-pack. Symbol Description 1 1 PB2 Phase output 2, phase B. Open collector output capable of sinking max 500 mA. 2 2 PB1 Phase output 1, phase B. Open collector output capable of sinking max 500 mA. 3 3 GND Ground and negative supply for both VCC and VSS. 4 4 PA1 Phase output 1, phase A. 5 5 PA2 Phase output 2, phase A. 6 6 DIR Direction input. Determines in which rotational direction steps will be taken. 7 7 STEP Stepping pulse. One step is generated for each negative edge of the step signal. 8 8 ØB Zero current half step position indication output for phase B. 9 9 ØA Zero current half step position indication output for phase A. 10 10 HSM Half-step mode. Determines whether the motor will be operated in half or full-step mot. When pulled low, one step pulse will correspond to a half step of the motor. 11 11 INH A high level on the inhibit input turns all phase output off. 12 12 RC Bilevel pulse timing pin. Pulse time is approximately ton = 0.55 • RT • CT 13 13 LA Second level (bilevel) output, phase A. 14 14 LB Second level (bilevel) output, Phase B. 15 15 VSS Second level supply voltage, +10 to +40 V. 16 16 VCC Logic supply voltage, nominally +5 V. 5 PBD 3517/1 Functional Description determined by VSS voltage and motor data, the L/R time-constant. In a low-voltage system, where high motor performance is needed, it is also possible to double the motor voltage by adding a few external components, see figure 14. The time the circuit applies the higher voltage to the motor is controlled by a monostable flip-flop and determined by the timing components RT and CT. The circuit can also drive a motor in traditional unipolar way. An inhibit input (INH) is used to switch off the current completely. The circuit, PBD 3517/1, is a high perform-ance motor driver, intended to drive a stepper motor in a unipolar, bilevel way. Bilevel means that during the first time after a phase shift, the voltage across the motor is increased to a second voltage supply, VSS, in order to obtain a more-rapid rise of current, see figure 11. The current starts to rise toward a value which is many times greater than the rated winding current. This compensates for the loss in drive current and loss of torque due to the back emf of the motor. After a short time, tOn, set by the monostable, the bilevel output is switched off and the winding current flows from the VMM supply, which is chosen for rated winding current. How long this time must be to give any increase in performance is STEP — Stepping pulse One step is generated for each negative edge of the STEP signal. In half-step mode, two pulses will be required to move one full step. Notice the set up time, ts, of DIR and HSM signals. These signals must be latched during the negative edge of STEP, see timing diagram, figure 3. DIR — Direction DIR determines in which direction steps will be taken. Actual direction depends on motor and motor connections. DIR can be changed at any time, but not simultaneously with STEP, see timing diagram, figure 3. HSM determines whether the motor will be controlled in full-step or half-step mode. When pulled low, a step-pulse will correspond to a half step of the motor. HSM can be changed at any time, but not simultaneously with STEP, see timing diagram, figure 3. Logic inputs All inputs are LS-TTL compatible. If any of the logic inputs are left open, the circuit will accept it as a HIGH level. PBD 3517/1 contains all phase logic necessary to control the motor in a proper way. VSS D3 VMM + 5V + + C3 VCC PBD 3517/1 + C4 D2 D1 R11 R10 C5 VCC VSS 16 15 PQR RC 12 Mono F-F CMOS, TTL-LS Input / Output-Device R9 R8 RT C T STEP STEP DIR CW / CCW HALF / FULL STEP NORMAL /INHIBIT (Optional Sensor) 13 LA 14 LB MOTOR 7 Phase Logic 6 D3-D6 PA 1 PB2 2 PB1 11 5 PA2 9 4 PA1 3 GND HSM 10 INH OA OB 8 PB D3-D6 are UF 4001 or BYV 27 trr < 100 ns GND GND (VCC) GND (VMM,VSS) Figure 14. Typical application. VMM + 5V + VCC R1 + C3 PBD 3517/1 D1 C4 VCC VSS 16 15 R10 PQR Q1 12 R9 R8 Mono F-F 13 LA 14 LB + RC CMOS, TTL-LS Input / Output-Device C1 RT CT Q3 R2 STEP CW / CCW HALF / FULL STEP NORMAL /INHIBIT (Optional Sensor) STEP 7 DIR 6 HSM 10 Phase Logic PA PB 1 PB2 2 PB1 PA2 PA1 INH 11 5 OA 9 4 OB 8 Equal to Phase A 1/2 MOTOR R12 R13 R4 Q5 Q6 R5 3 GND GND GND (VCC) GND (VMM,VSS) 6 Figure 15. Voltage doubling with external transistors. PBD 3517/1 INH — Inhibit Purpose of external components For figures 14 and 15. Note that “Larger than …” is normally the vice versa of “Smaller than … .” Component Purpose Value Larger than value Smaller than value D1, D2 Passes low power to motor and prevents high power from shorting through low power supply I f = 1A Increases price Inductive current supressor I f = 1A Increases price Decreases current turn-off capability trr = 100nS Slows down turnoff time. Voltage at anode might exceed voltage breakdown Speeds up turnoff time. Slows down Q1’s turn-on and Q4’s turn-off time. Speeds up Q1’s turn-on and Q4’s turn-off time. Slows down Q1’s turn-off and Q4’s turn-on time. Speeds up Q1’s turn-off and Q4’s turn-on time. Decreases ext. transistor IC max. Lowers 3517 power dissipation. Increases ext. transistor IC max. Increases 3517 power dissipation. Increases noise sensitivity, worse logic-level definition Increases noise immunity, better logic-level definition. D3 … D6 1N4001, UF4001 e.g. R1 Base drive current limitter BYV27 UF4001 RGPP10G RGPP30D R = 20ohm ( Vmm P = R1 R2, R3 ) R1 + R2 Base discharge resistor R = 240ohm ( Vmm P = R1 R4 … R7 2 2 ) R1 + R2 External transistor base Vmm- Vbe- V ce R= driver Vbe I4 R12 2 P > (I 4) • R4 Check hfe. ( ) R8, R9 ØA, ØB pull-up resistors R = 5ohm @ pull-up voltage = 5V. P= R10, R11 2 (VCC) R Less stress on ØA, Stress on ØA, ØB ØB output output transistors transistors. Vmm-VMotor -VCESat Decreases motor Limit max. motor current. current. Resistors may R = I Motor max be omitted. (Check motor specifications first.) Vbe R12 … R15 External transistor base R= ª discharge. I12 Slows down external transistor turn-off time. Lowers 3517 power dissipation 15W P > Vbe• I12 RT, CT Sets LA and LB on time R = 47kohm, C = 10nf when triggered by P < 250mW STEP. C1, C2 Stores the doubling voltage. C3 … C5 C = 100µ F Increases price, better filtering, decreases risk of IC breakdown Q3, Q4 Q5 … Q8 Charging of voltage doubling capacitor Motor current drive transistor. IC as motor requires. I C= IC as motor requires. PNP power trans. Increases price. Decreases price, more compact solution. An internal Power-On Reset circuit connected to Vcc resets the phase logic and inhibits the outputs during power up, to prevent false stepping. Output Stages The output stage consists of four opencollector transistors. The second highvoltage supply contains Darlington transistors. Phase Outputs The phase outputs are connected directly to the motor as shown in figure 14. Bilevel Technique The bilevel pulse generator consists of two monostables with a common RC network. The internal phase logic generates a trigger pulse every time the phase changes state. The pulse triggers its own monostable which turns on the output transistors for a precise period of time: tOn = 0.55 • CT • RT. See pulse diagrams, figures 16 through 20. The ØA and ØB outputs are generated from the phase logic and inform an external device if the A phase or the B phase current is internally inhibited. These outputs are intended to support if it is legal to correctly go from a half-step mode to a full-step mode without loosing positional information. The PBD 3517/1 can act as a controller IC for 2 driver ICs, the PBL 3770A. Use PA1 and PB1 for phase control, and ØA and ØB for I0 and I1 control of current turn-off. Applications Information Risk for capacitor breakdown. Decreases max Im during voltage doubling. (Vmm - Vf -VCE ) • C1 ( Reset Bipolar Phase Logic Output Speeds up external transistor turn-off time. Increases 3517 power dissipation Increases effective Decreases on-time during effective on-time voltage doubling during voltage doubling. VC ≥ 45V Filtering of supplyC ≥ 10 µF voltage ripple and takeup of energy feedback from D3 … D6 Activation transistor of voltage doubling. Increases motor current. Increases on time. Decreases on time. VRated >V ,V or Vcc Increases price mm ss Q1, Q2 Decreases max current capability A HIGH level on the INH input,turns off all phase outputs to reduce current consumption. ) 1 - 0.55 • RT • CT fStep Increases max Decreases max current capability. current capability. Logic inputs If any of the logic inputs are left open, the circuit will treat it as a high-level input. Unused inputs should be connected to proper voltage levels in order to get the highest noise immunity. Phase outputs 7 PBD 3517/1 Phase outputs use a current-sinking method to drive the windings in a unipolar way. A common resistor in the center tap will limit the maximum motor current. Fast free-wheeling diodes must be used to protect output transistors from inductive spikes. Alternative solutions are shown in figures 21 through 25 on pages 6 - 10. Series diodes in VMM supply, prevent VSS voltage from shorting through the VMM power supply. However, these may be omitted if no bilevel is used. The VSS pin must not be connected to a lower voltage than VMM, but can be left unconnected. DIR INH HSM STEP H L H P OB LB PB1 PB2 PA1 PA2 LA OA L P P P P P P L Figure 16. Full-step mode, forward. 4-step sequence. Gray-code +90° phase shift. DIR INH HSM STEP H L H P OB LB PB1 PB2 PA1 PA2 LA OA L P P P P P P L Zero outputs ØA and ØB, “zero A” and “zero B,” are open-collector outputs, which go high when the corresponding phase output is inhibited by the half-step-mode circuitry. A pull-up resistor should be used and connected to a suitable supply voltage (5 kohms for 5V logic). See “Bipolar phase logic output.” Interference To avoid interference problems, a good idea is to route separate ground leads to each power supply, where the only common point is at the 3517/1’s GND pin. Decoupling of VSS and VMM will improve performance. A 5 kohm pull-up resistor at logic inputs will improve level definitions, especially when driven by open-collector outputs. Input and Output Signals for Different Drive Modes The pulse diagrams, figures 16 through 20, show the necessary input signals and the resulting output signals for each drive mode. On the left side are the input and output signals, the next column shows the state of each signal at the cursor position marked “C.” STEP is shown with a 50% duty cycle, but can, of course, be with any duty cycle, as long as pulse time (tp) is within specifications. PA and PB are displayed with low level, showing current sinking. LA and LB are displayed with high level, showing current sourcing. Figure 17. Full-step mode, reverse. 4-step sequence. Gray-code -90° phase shift. DIR INH HSM STEP H L L P OB LB PB1 PB2 PA1 PA2 LA OA P P P P P P P P C Figure 18. Half-step mode, forward. 8-step sequence. DIR INH HSM STEP L L L P OB LB PB1 PB2 PA1 PA2 LA OA P P P P P P P P C Figure 19. Half-step mode, reverse. 8-step sequence. DIR INH HSM STEP L H L P OB LB PB1 PB2 PA1 PA2 LA OA P P H H H H P P C Figure 20. Half-step mode, inhibit. 8 PBD 3517/1 RExt Figure 21. Diode turn-off circuit. VZ R i Figure 22. Resistance turn-off circuit. V1 CS Figure 23. Zener diode turn-off circuit. 7. To change actual motor rotation direction, exchange motor connections at PA1 and PA2 (or PB1 and PB2). 8. Half-stepping. in the half-step mode, the power input to the motor alternates between one or two phase windings. In half-step mode, motor resonances are reduced. In a twophase motor, the electrical phase shift between the windings is 90 degrees. The torque developed is the vector sum of the two windings energized. Therefore, when only one winding is energized, which is the case in half-step mode for every second step, the torque of the motor is reduced by approximately 30%. This causes a torque ripple. 9. Ramping. Every drive system has inertia which must be considered in the drive scheme. The rotor and load inertia plays a big role at higher speeds. Unlike the DC motor, the stepper motor is a synchronous motor and does not change speed due to load variations. Examination of typical stepper motors’ torque versus speed curves indicates a sharp torque drop-off for the start-stop without error curve. The reason for this is that the torque requirements increase by the cube of the speed change. As it can be seen, for good motor performance, controlled acceleration and deceleration should be considered. V2 0V Power supply Figure 24. Power return turn-off circuit. Figure 25. Power return turn-off circuit for bilevel . necessary to connect in series with center tap. This changes the L/R time constant. User Hints 1. Never disconnect ICs or PC-boards when power is supplied. 2. If second supply is not used, disconnect and leave open VSS, LA, LB, and RC. Preferably replace the VMM supply diodes (D1, D2) with a straight connection. Remember that excessive voltages might be generated by the motor, even though clamping diodes are used. Choice of motor. Choose a motor that is rated for the current you need to establish desired torque. A high supply voltage will gain better stepping performance. If the motor is not specified for the VMM voltage, a current limiting resistor will be 3. 4. 5. Never use LA or LB for continuous output at high currents. LA and LB ontime can be altered by changing the RC net. An alternative is to trigger the mono-flip-flop by taking a STEP and then externally pulling the RC pin (12) low (0V) for the desired ontime. 6. Avoid VMM and VSS power supplies with serial diodes (without filter capacitor) and/or common ground with VCC. The common place for ground should be as close as possible to the IC’s ground pin (pin 3). 9 PBD 3517/1 Common Fault Conditions • VMM supply not connected, or VMM supply not connected through diodes. • The inhibit input not pulled low or floating. Inhibit is active high. • A bipolar motor without a center tap is used. Exchange motor for unipolar version. Connect according to figure 14. • External transistors connected without proper base-current supply resistor. • Insufficient filtering capacitors used. • Current restrictions exceeded. • LA and LB used for continuous output at high currents. Use the RC network to set a proper duty cycle according to specifications, see figures 6 through 11. • A common ground wire is used for all three power supplies. If possible, use separate ground leads for each supply to minimize power interference. Drive Circuits Zener diode T O C (figure 23) If high performance is to be achieved from a stepper motor, the phase must be energized rapidly when turned on and also de-energize rapidly when turned off. In other words, the phase current must increase/decrease rapidly at phase shift. Relatively high VZ gives: Phase Turn-off Considerations When the winding current is turned off the induced high voltage spike will damage the drive circuits if not properly suppressed. Different turn-off circuits are used; e. g. : Diode turn-off circuit (figure 21) — Relatively fast current decay — Energy lost mainly in VZ — Potential cooling problems Power return T O C for unipolar drive (figure 24) Relatively high VZ gives: — Relatively fast current decay — Energy returned to power supply — Only small energy losses — Winding leakage flux must be considered — Potential cooling problems — Slow current decay Power return to T O C for bilevel drive (figure 25) — Energy lost mainly in winding resistance — Very fast current decay — Energy returned to power supply — Potential cooling problems. — Only small energy losses — Winding leakage flux must be considered Resistance T O C (figure 22) — Somewhat faster current decay — Energy lost mainly in R-Ext Ordering Information — Potential cooling problems Package DIP Tube SO Tube SO Tape & Reel Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Components. These products are sold only according to Ericsson Components' general conditions of sale, unless otherwise confirmed in writing. Specifications subject to change without notice. 1522-PBD 3517/1 Uen Rev. C © Ericsson Components AB 1999 Ericsson Components AB SE-164 81 Kista-Stockholm, Sweden Telephone: +46 8 757 50 00 10 Part No. PBD 3517/1NS PBD 3517/1SOS PBD 3517/1SOT