TPA3106D1 HLQFP www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 40-W MONO CLASS-D AUDIO POWER AMPLIFIER FEATURES APPLICATIONS • • • • • 1 • • • • • 40-W Into an 8-Ω Load From a 25-V Supply Operates From 10 V to 26 V Efficient Class-D Operation Eliminates the Need for Heat Sinks Four Selectable, Fixed Gain Settings Differential Inputs Thermal and Short-Circuit Protection With Auto Recovery Feature Clock Output for Synchronization With Multiple Class-D Devices Surface Mount 7×7, 32-pin HLQFP Package Televisions Powered Speakers DESCRIPTION The TPA3106D1 is a 40-W efficient, Class-D audio power amplifier for driving bridged-tied stereo speakers. The TPA3106D1 can drive stereo speakers as low as 4Ω. The high efficiency, ~92%, of the TPA3106D1 eliminates the need for an external heat sink when playing music. The gain of the amplifier is controlled by two gain select pins. The gain selections are 20, 26, 32, 36 dB. The outputs are fully protected against shorts to GND, VCC, and output-to-output shorts with an auto recovery feature and monitor output. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC Supply voltage VI Input voltage AVCC, PVCC –0.3 V to 30 V SHUTDOWN, MUTE –0.3 V to VCC + 0.3 V GAIN0, GAIN1, INN, INP, MSTR/SLV, SYNC Continuous total power dissipation –0.3 V to VREG + 0.5 V See Dissipation Rating Table TA Operating free-air temperature range –40°C to 85°C TJ Operating junction temperature range (2) –40°C to 150°C Tstg Storage temperature range –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds RLoad 3.2 Ω Minimum Load resistance Electrostatic discharge (1) 260°C Human body model (3) Charged-device model (all pins) (4) ±2 kV (all pins) ±500 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The TPA3106D1 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection shutdown. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical Briefs SLMA002 for more information about using the HTQFP thermal pad. In accordance with JEDEC Standard 22, Test Method A114-B. In accordance with JEDEC Standard 22, Test Method C101-A (2) (3) (4) TYPICAL DISSIPATION RATINGS PACKAGE (1) TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C 32-pin VFP (HLQFP) 3.57 W 29 mW/°C (2) 2.29 W 1.86 W (1) (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. This data was taken using a 2 oz trace and copper pad that is soldered directly to a 2-layer high-k PCB (EVM) and they are typical values. The thermal pad must be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SLMA002 for more information about using the HLQFP thermal pad. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX 10 26 VCC Supply voltage PVCC, AVCC VIH High-level input voltage SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV, SYNC VIL Low-level input voltage SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV, SYNC 0.8 SHUTDOWN, VI = VCC, VCC = 24 V 125 IIH High-level input current 2 MUTE, VI = VCC, VCC = 24 V 75 GAIN0, GAIN1, MSTR/SLV, SYNC, VI = VREG, VCC = 24 V 2 SHUTDOWN, VI = 0, VCC = 24 V 2 Low-level input current SYNC, MUTE, GAIN0, GAIN1, MSTR/SLV, VI = 0 V, VCC = 24 V 1 VOH High-level output voltage FAULT, IOH = 1 mA VOL Low-level output voltage FAULT, IOL = -1 mA fOSC Oscillator frequency ROSC resistor = 100 kΩ TA Operating free-air temperature Submit Documentation Feedback V V IIL 2 UNIT VREG – 0.6 V µA µA V AGND + 0.4 V 200 300 kHz –40 85 °C Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 DC CHARACTERISTICS TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Class-D output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB Bypass reference for input amplifier VBYP, no load 4-V internal supply voltage VREG, no load, VCC = 10 V to 26 V PSRR DC Power supply rejection ratio VCC = 12 V to 24 V, inputs ac coupled to AGND, Gain = 36 dB ICC Quiescent supply current SHUTDOWN = 2 V, MUTE = 0 V, no load ICC(SD) Quiescent supply current in shutdown mode SHUTDOWN = 0.8 V, no load ICC(MUTE) Quiescent supply current in mute mode MUTE = 2 V, no load rDS(on) Drain-source on-state resistance VCC = 12 V, IO = 500 mA, TJ = 25°C | VOS | GAIN1 = 0.8 V G Gain GAIN1 = 2 V TYP MAX UNIT 5 50 1.2 1.35 1.55 V 3.8 4.1 4.4 V –70 mV dB 14 17 215 250 µA 6 9 mA High Side 200 Low side 200 Total 400 500 mA mΩ GAIN0 = 0.8 V 19 20 21 GAIN0 = 2 V 25 26 27 GAIN0 = 0.8 V 31 32 33 GAIN0 = 2 V 35 36 37 dB dB tON Turn-on time C(VBYP) = 1 µF, SHUTDOWN = 2 V 25 ms tOFF Turn-off time C(VBYP) = 1 µF, SHUTDOWN = 0.8 V 0.1 ms DC CHARACTERISTICS TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Class-D output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB Bypass reference for input amplifier VBYP, no load 4-V internal supply voltage VREG, no load PSRR DC Power supply rejection ratio VCC = 12 V to 24 V, Inputs ac coupled to AGND, Gain = 36 dB ICC Quiescent supply current SHUTDOWN = 2 V, MUTE = 0 V, no load ICC(SD) Quiescent supply current in shutdown mode SHUTDOWN = 0.8 V, no load ICC(MITE) Quiescent supply current in mute mode MUTE = 2 V, no load | VOS | rDS(on) Drain-source on-state resistance VCC = 12 V, IO = 500 mA, TJ = 25°C G Gain GAIN1 = 2 V UNIT 5 50 1.2 1.35 1.55 V 3.8 4.1 4.4 V –70 mV dB 10 14 mA 130 180 µA 5 7 mA High Side 200 Low side 200 Total GAIN1 = 0.8 V TYP MAX mΩ 400 500 GAIN0 = 0.8 V 19 20 21 GAIN0 = 2 V 25 26 27 GAIN0 = 0.8 V 31 32 33 GAIN0 = 2 V 35 36 37 dB dB tON Turn-on time C(VBYP) = 1 µF, SHUTDOWN = 2 V 25 ms tOFF Turn-off time C(VBYP) = 1 µF, SHUTDOWN = 0.8 V 0.1 ms Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 3 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 AC CHARACTERISTICS TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted) PARAMETER KSVR PO Supply ripple rejection Continuous output power TEST CONDITIONS MI N 200 mVPP ripple from 20 Hz–1 kHz, Gain = 20 dB, Inputs ac-coupled to AGND TYP MAX –88 THD+N = 7%, f = 1 kHz, VCC = 24 V 32 THD+N = 10%, f = 1 kHz, VCC = 24 V 40 THD+N < 7%, f = 1 kHz, VCC = 24 V, RL = 4 Ω, Thermally limited by package 25 THD+N Total harmonic distortion + noise f = 1 kHz, PO = 20 W (half-power) Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB SNR Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, A-weighted UNIT dB W 0.2% Thermal trip point Thermal hysteresis 125 µV –80 dBV 102 dB 150 °C 30 °C AC CHARACTERISTICS TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted) PARAMETER KSVR PO Supply ripple rejection Continuous output power TEST CONDITIONS MIN –88 THD+N = 7%, f = 1 kHz 8.7 THD+N = 10%, f = 1 kHz 9.2 THD+N = 7%, f = 1 kHz, RL = 4 Ω 15.6 THD+N = 10%, f = 1 kHz, RL = 4 Ω 0.11% RL = 4 Ω, f = 1 kHz, PO = 8 W 0.15% Total harmonic distortion + noise Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB SNR Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, A-weighted Thermal trip point Thermal hysteresis Submit Documentation Feedback MAX UNIT dB W 16.4 RL = 8 Ω, f = 1 kHz, PO = 5 W THD+N 4 TYP 200 mVPP ripple from 20 Hz–1 kHz, Gain = 20 dB, Inputs ac-coupled to AGND 100 µV –80 dBV 98 dB 150 °C 30 °C Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 32-PIN HTQFP (VFP) (TOP VIEW) TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION SHUTDOWN 29 I Active low. Shutdown signal for IC (LOW = disabled, HIGH = operational). TTL logic levels with compliance to AVCC. INN 1 I Negative audio input INP 2 I Positive audio input GAIN0 5 I Gain select least significant bit. TTL logic levels with compliance to VREG. GAIN1 6 I Gain select most significant bit. TTL logic levels with compliance to VREG. MUTE 30 I Active high. Mute signal for quick disable/enable of outputs (HIGH = outputs high-Z, LOW = outputs enabled). TTL logic levels with compliance to AVCC. FAULT 31 O TTL compatible output. HIGH = short-circuit fault. LOW = no fault. Only reports short-circuit faults. Thermal faults are not reported on this terminal. 23 I/O Bootstrap I/O for left channel, positive high-side FET. BSP PVCC 14, 15, 26–28 Power supply for left channel H-bridge, not internally connected to AVCC. OUTP 21, 22 PGND 16, 17, 24, 25 OUTN 19, 20 O Class-D 1/2-H-bridge negative output BSN 18 I/O Bootstrap I/O for left channel, negative high-side FET. VCLAMP 13 AGND 3, 4, 12 ROSC 9 O Class-D 1/2-H-bridge positive output Power ground for H-bridge. Internally generated voltage supply forbootstrap capacitor. Analog ground for digital/analog cells in core. I/O I/O for current setting resistor of ramp generator. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 5 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. I/O DESCRIPTION Master/Slave select for determining direction of SYNC terminal. HIGH=Master mode, SYNC terminal is an output; LOW = slave mode, SYNC terminal accepts a clock input. TTL logic levels with compliance to VREG. MSTR/SLV 7 I SYNC 8 I/O Clock input/output for synchronizing multiple class-D devices. Direction determined by MSTR/SLV terminal. Input signal not to exceed VREG. VBYP 11 O Reference for preamplifier. Nominally equal to 1.25 V. Also controls start-up time via external capacitor sizing. VREG 10 O 4-V regulated output for use by internal cells, GAINx, MUTE, and MSTR/SLV pins only. Not specified for driving other external circuitry. AVCC 32 Thermal Pad — High-voltage analog power supply. Not internally connected to PVCCL. — Connect to AGND and PGND – should be star point for both grounds. Internal resistive connection to AGND and PGND. Thermal vias on the PCB should connect this pad to a large copper area on an internal or bottom layer for the best thermal performance. The Thermal Pad must be soldered to the PCB for mechanical reliability. FUNCTIONAL BLOCK DIAGRAM PVCC PVCC PVCC VBYP VCLAMP BSN VBYP AVCC AVCC Gain Control INN Gate Drive Gain Control INP OUTN VClamp Gen PWM Logic VBYP GAIN0 GAIN1 BSP Gain Control To Gain Adj. Blocks & Startup Logic 4 Gate Drive OUTP Gain Control FAULT PGND SC Detect VBYP AVCC ROSC SYNC PVCC Thermal VREG Ramp Generator Biases & References MSTR/SLV Startup Protection Logic VREGok AVCC VCCok VREG VREG 4V Reg SHUTDOWN TTL Input Buffer (VCC Compliant) MUTE TTL Input Buffer (VREG Compliant) AGND 6 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS TABLE OF GRAPHS Y-AXIS X-AXIS FIGURE Total Harmonic Distortion + N (%) Frequency (Hz) (BTL) Figure 1 Total Harmonic Distortion + N (%) Frequency (Hz) (BTL) Figure 2 Total Harmonic Distortion + N (%) Frequency (Hz) (BTL) Figure 3 Total Harmonic Distortion + N (%) Frequency (Hz) (BTL) Figure 4 Total Harmonic Distortion + N (%) Frequency (Hz) (BTL) Figure 5 Total Harmonic Distortion + N (%) Frequency (Hz) (BTL) Figure 6 Total Harmonic Distortion + N (%) Output Power (W) (BTL) Figure 7 Total Harmonic Distortion + N (%) Output Power (W) (BTL) Figure 8 Total Harmonic Distortion + N (%) Output Power (W) (BTL) Figure 9 Total Harmonic Distortion + N (%) Output Power (W) (BTL) Figure 10 Total Harmonic Distortion + N (%) Output Power (W) (BTL) Figure 11 Total Harmonic Distortion + N (%) Output Power (W) (BTL) Figure 12 Closed Loop Response Frequency (Hz) (BTL) Figure 13 Closed Loop Response Frequency (Hz) (BTL) Figure 14 PO – Output Power (W) Supply Voltage (V) (BTL) Figure 15 PO – Output Power (W) Supply Voltage (V) (BTL) Figure 16 Efficiency (%) Output Power (W) (BTL) Figure 16 Efficiency (%) Output Power (W) (BTL) Figure 18 Efficiency (%) Output Power (W) (BTL) Figure 19 ICC – Supply Current (A) PO – Total Output Power (W) (BTL) Figure 20 ICC – Supply Current (A) PO – Total Output Power (W) (BTL) Figure 21 kSVR – Supply Rejection Ratio (dB) Frequency (Hz) (BTL) Figure 22 kSVR – Supply Rejection Ratio (dB) Frequency (Hz) (BTL) Figure 23 kSVR – Supply Rejection Ratio (dB) Frequency (Hz) (BTL) Figure 24 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 10 VCC = 12 V, RL = 8W, Gain = 20 dB PO = 2.5 W 1 0.1 PO = 5 W PO = 0.5 W 0.01 0.003 20 100 1k f - Frequency - Hz 10k 20k VCC = 18 V, R L = 8W , Gain = 20 dB PO = 5 W 1 0.1 PO = 10 W PO = 1 W 0.01 0.003 20 Figure 1. 100 1k f - Frequency - Hz 10k 20k Figure 2. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 7 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 10 VCC = 24 V, R L = 8 W, Gain = 20 dB PO = 5 W 1 0.1 PO = 10 W PO = 1 W 0.01 0.003 20 100 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY VCC = 18 V, L = 22 mH, C = 1 mF, Gain = 20 dB PO = 5 W 0.2 0.05 PO = 10 W PO = 1 W 0.02 0.01 0.005 0.002 0.001 20 0.5 0.2 0.1 PO = 1 W 0.05 0.02 0.01 0.005 0.002 100 200 1k 2k f - Frequency - Hz 10k 20k 100 200 1k 2k f - Frequency - Hz 10k 20k 10 5 2 1 VCC = 12 V, RL = 4 W, L = 15 mH, C = 2 mF, Gain = 20 dB PO = 5 W 0.5 0.2 0.1 PO = 1 W 0.05 0.02 0.01 0.005 0.002 0.001 20 100 200 1k 2k 10k 20k f - Frequency - Hz Figure 5. 8 PO = 5 W TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 0.5 0.1 L = 15 mH, C = 2 mF, Gain = 20 dB TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 1 1 RL = 6 W, Figure 4. RL = 6 W, 2 2 VCC = 12 V, Figure 3. 10 5 5 0.001 20 10k 20k 1k f - Frequency - Hz 10 Figure 6. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 20 VCC = 12 V, THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 20 RL = 8 W, Gain = 20 dB 1 1 kHz 10 kHz 0.1 20 Hz 0.01 10m 100m 1 10 VCC = 18 V, RL = 8 W, Gain = 20 dB 1 10 kHz 20 Hz 0.1 1 kHz 0.01 10m 10 20 40 100m PO - Output Power - W Figure 8. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 VCC = 24 V, RL = 8 W, Gain = 20 dB 1 10 kHz 20 Hz 0.1 1 kHz 0.01 10m 100m 1 10 20 40 THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 10 20 40 Figure 7. 20 10 1 PO - Output Power - W VCC = 12 V, R L = 6 W, L = 22 mH, C = 1 mF, Gain = 20 dB 1 1 kHz 10 kHz 0.1 20 Hz 0.01 10m PO - Output Power - W Figure 9. 100m 1 10 PO - Output Power - W 50 Figure 10. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 9 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 10 THD+N - Total Harmonic Distortion + Noise - % RL = 6 W, L = 22 mH, C = 1 mF, Gain = 20 dB 1 1 kHz 10 kHz 0.1 20 Hz 0.01 10m 1 100m PO - Output Power - W 10 50 VCC = 12 V, RL = 4 W, L = 15 mH, C = 2 mF, Gain = 20 dB 1 1 kHz 10 kHz 0.1 20 Hz 0.01 10m 100m 1 Figure 12. CLOSED LOOP RESPONSE vs FREQUENCY CLOSED LOOP RESPONSE vs FREQUENCY +200 +200 20 VCC = 24 V, VI = 100 mVrms VCC = 12 V, VI = 100 mVrms +100 +100 1 Measurement Low-Pass Filter: R = 100 W, C = 10 nF +0 100m -100 10m 1m 20 100 1k 10k f - Frequency - Hz -200 100k Deg - ° Voltage - V Voltage - V 1 Measurement Low-Pass Filter: R = 100 W, C = 10 nF +0 100m -100 10m 1m 20 Figure 13. 10 50 PO - Output Power - W Figure 11. 20 10 Deg - ° THD+N - Total Harmonic Distortion + Noise - % VCC = 18 V, 100 10k 1k f - Frequency - Hz -200 100k Figure 14. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 OUTPUT POWER vs SUPPLY VOLTAGE OUTPUT POWER vs SUPPLY VOLTAGE 45 25 RL = 8 W Gain = 20 dB 40 20 PO − Output Power − W Power Out – W THD+N=10% 15 10 THD+N=1% 35 30 THD+N = 10% 25 THD+N = 1% 20 15 5 10 RL = 4 W Gain = 20 dB 0 10 11 12 13 Supply Voltage – V 5 14 10 12 14 16 18 20 22 24 26 VCC - Supply Voltage - V Figure 15. Figure 16. EFFICIENCY vs OUTPUT POWER (BTL) EFFICIENCY vs OUTPUT POWER (BTL) 90 100 80 90 VCC = 12 V 70 70 Efficiency –% Efficiency –% 60 50 40 30 60 50 40 30 20 20 10 10 0 0.1 VCC = 18 V 80 RL = 4 W VCC = 12 V 3 7 11 15 Power Out – W PLACE HOLDER Figure 17. 19 23 0 0.1 RL = 6 W 3 7 11 15 19 23 Power Out – W PLACE HOLDER Figure 18. 27 31 35 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 39 11 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 EFFICIENCY vs OUTPUT POWER (BTL) SUPPLY CURRENT vs TOTAL OUTPUT POWER 100 2.5 VCC = 18 V VCC = 12 V RL = 8 Ω Gain = 32 dB 90 VCC = 24 V 70 Efficiency –% 2 ICC − Supply Current − A 80 60 50 40 30 20 10 0 0.1 VCC = 18 V VCC = 12 V 1.5 VCC = 24 V 1 0.5 RL = 8 W 3 7 11 15 19 23 27 31 0 35 39 0 10 Power Out – W PLACE HOLDER SUPPLY CURRENT vs TOTAL OUTPUT POWER SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY +0 1.5 VIN = 12 V RL = 4 W Gain = 20 dB 1 0.5 1 3 5 7 9 11 13 Power Out – W PLACE HOLDER 15 17 19 PSRR - Power Supply Rejection Ratio - dB ICC Supply Current – A 40 Figure 20. 2 VCC = 12 V, Vripple = 200 mVp-p -20 RL = 8 W -40 -60 -80 -100 20 Figure 21. 12 30 Figure 19. 2.5 0 0.1 20 PO − Total Output Power − W 100 1k f - Frequency - Hz 10k 20k Figure 22. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY +0 VCC = 18 V, Vripple = 200 mVp-p -20 PSRR - Power Supply Rejection Ratio - dB PSRR - Power Supply Rejection Ratio - dB +0 RL = 8 W -40 -60 -80 -100 VCC = 24 V, Vripple = 200 mVp-p RL = 8 W -20 -40 -60 -80 -100 20 100 1k f - Frequency - Hz 10k 20k 20 Figure 23. 100 1k f - Frequency - Hz 10k 20k Figure 24. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 13 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 APPLICATION INFORMATION 1 mF 220 mF SDZ MUTE FAULT PGND PVCC PVCC SDZ MUTE AVCC FAULT Analog Audio In PVCC VCC 1 mF 10 mF VCC LINP PGND LINN BSP 1.0 mF 1.0 mF AGND AGND OUTN GAIN1 GAIN1 OUTN VCC 220 mF 1 mF 1 mF 1 mF 1nF 1μF 1μF 33 mH 20 Ω PGND PVCC PVCC VCLAMP 10nF VBYP PGND AGND BSN SYNC ROSC MSTR/SLV VREG C17 1nF OUTP TPA3106D1 GAIN0 SYNC 33 mH OUTP GAIN0 MSTR/SLV 20 Ω 0.22 μF Connected at PowerPad with single point connection PGND AGND Figure 25. TPA3106D1 Application Circuit With Single-Ended Inputs 14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 CLASS-D OPERATION This section focuses on the class-D operation of the TPA3106D1. Traditional Class-D Modulation Scheme The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output where each output is 180 degrees out-of-phase and changes from ground to the supply voltage, VCC. Therefore, the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields 0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in Figure 26. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high, causing high loss and thus causing a high supply current. OUTP OUTN +12 V Differential Voltage Across Load 0V -12 V Current Figure 26. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms into an Inductive Load With No Input TPA3106D1 Modulation Scheme The TPA3106D1 uses a modulation scheme that still has each output switching from 0 to the supply voltage. However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 15 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 OUTP OUTN Differential Voltage Across Load Output = 0 V +12 V 0V -12 V Current OUTP OUTN Differential Voltage Across Load Output > 0 V +12 V 0V -12 V Current Figure 27. The TPA3100D2 Output Voltage and Current Waveforms Into an Inductive Load Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 x VCC, and the time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive. The TPA3106D1 modulation scheme has little loss in the load without a filter because the pulses are short and the change in voltage is VCC instead of 2 x VCC. As the output power increases, the pulses widen, making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most applications the filter is not needed. An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance but higher impedance at the switching frequency than the speaker, which results in less power dissipation, therefore increasing efficiency. 16 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 When to Use an Output Filter for EMI Suppression Design the TPA3106D1 without the filter if the traces from amplifier to speaker are short (< 10 cm). Powered speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without a filter. Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high impedance at high frequencies, but low impedance at low frequencies. Use an LC output filter if there are low frequency (<1 MHz) EMI-sensitive circuits and/or there are long wires from the amplifier to the speaker. When both an LC filter and a ferrite bead filter are used, the LC filter should be placed as close as possible to the IC followed by the ferrite bead filter. 33 mH OUTP L1 C2 1 mF 33 mH OUTN L2 C3 1 mF Figure 28. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω 15 mH OUTP L1 C2 2.2 mF 15 mH OUTN L2 C3 2.2 mF Figure 29. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 4 Ω Ferrite Chip Bead OUTP 1 nF Ferrite Chip Bead OUTN 1 nF Figure 30. Typical Ferrite Chip Bead Filter (Chip Bead Example: Fair-Rite 2512067007Y3) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 17 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 Adaptive Dynamic Range Control TPA3106D1 V - Voltage = 1 V/div V - Voltage = 10 V/div TPA3106D1 Nearest Competitor Nearest Competitor t - Time = 20 ms/div t - Time = 100 ms/div Figure 31. 1-kHz Sine Output at 10% THD+N Figure 32. 8-kHz Sine Output at 10% THD+N The Texas Instruments patent-pending adaptive dynamic range control (ADRC) technology removes the notch inherent in class-D audio power amplifiers when they come out of clipping. This effect is more severe at higher frequencies as shown in Figure 32. Gain Setting via GAIN0 and GAIN1 Inputs The gain of the TPA3106D1 is set by two input terminals, GAIN0 and GAIN1. The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside the amplifier. This causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors. For design purposes, the input network (discussed in the next section) should be designed assuming an input impedance of 12.8 kΩ, which is the absolute minimum input impedance of the TPA3106D1. At the lower gain settings, the input impedance could increase as high as 38.4 kΩ Table 1. Gain Setting 18 AMPLIFIER GAIN (dB) INPUT IMPEDANCE (kΩ) TYP TYP 20 32 1 26 16 1 0 32 16 1 1 36 16 GAIN1 GAIN0 0 0 0 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 INPUT RESISTANCE Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 16 kΩ ±20%, to the largest value, 32 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the –3 dB or cutoff frequency may change when changing gain steps. Zf Ci IN Input Signal Zi The –3-dB frequency can be calculated using Equation 1. Use the ZI values given in Table 1. f = 1 2p Zi Ci (1) INPUT CAPACITOR, CI In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a high-pass filter with the corner frequency determined in Equation 2. -3 dB fc = 1 2p Zi Ci fc (2) The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider the example where ZI is 20 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 2 is reconfigured as Equation 3. Ci = 1 2p Zi fc (3) In this example, CI is 0.4 µF; so, one would likely choose a value of 0.47 µF as this value is commonly used. If the gain is known and is constant, use ZI from Table 1 to calculate CI. A further consideration for this capacitor is the leakage path from the input source through the input network (CI) and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 2 V, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset voltages and it is important to ensure that boards are cleaned properly. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 19 TPA3106D1 SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 www.ti.com Power Supply Decoupling, CS The TPA3106D1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF to 1 µF placed as close as possible to the device VCC lead works best. For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 100 µF per input lines (Pins 14, 15 and pins 26, 27, 28) or greater placed near the audio power amplifier is recommended. The 100 µF capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power to the output transistors, so a 100 µF or larger capacitor should be placed on each PVCC terminal. A 10 µF capacitor on the AVCC terminal is adequate. The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 25 V, must be connected from each output to its corresponding bootstrap input. Specifically, one 220-nF capacitor must be connected from xOUTP to BSxx, and one 220-nF capacitor must be connected from xOUTN to BSxx. (See the application circuit diagram in Figure 25.) The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on. VCLAMP Capacitors To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, two internal regulators clamp the gate voltage. Two 1-µF capacitors must be connected from VCLAMPL and VCLAMPR to ground and must be rated for at least 16 V. The voltages at the VCLAMPx terminals may vary with VCC and may not be used for powering any other circuitry. Internal Regulated 4-V Supply (VREG) The VREG terminal (pin 10) is the output of an internally generated 4-V supply, used for the oscillator, preamplifier, and gain control circuitry. It requires a 10-nF capacitor, placed close to the pin, to keep the regulator stable. This regulated voltage can be used to control GAIN0, GAIN1, MSTR/SLV, and MUTE terminals, but should not be used to drive external circuitry. VBYP Capacitor Selection The internal bias generator (VBYP) nominally provides a 1.25-V internal bias for the preamplifier stages. The external input capacitors and this internal reference allow the inputs to be biased within the optimal common-mode range of the input preamplifiers. The selection of the capacitor value on the VBYP terminal is critical for achieving the best device performance. During power up or recovery from the shutdown state, the VBYP capacitor determines the rate at which the amplifier starts up. When the voltage on the VBYP capacitor equals VBYP, the device starts a 16.4-ms timer. When this timer completes, the outputs start switching. The charge rate of the capacitor is calculated using the standard charging formula for a capacitor, I = C x dV/dT. The charge current is nominally equal to 250µA and dV is equal to VBYP. For example, a 1-µF capacitor on VBYP would take 5 ms to reach the value of VBYP and begin a 16.4-ms count before the outputs turn on. This equates to a turn-on time of <30 ms for a 1-µF capacitor on the VBYP terminal. A secondary function of the VBYP capacitor is to filter high-frequency noise on the internal 1.25-V bias generator. A value of at least 0.47µF is recommended for the VBYP capacitor. For the best power-up and shutdown pop performance, the VBYP capacitor should be greater than or equal to the input capacitors. 20 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 ROSC Resistor Selection The resistor connected to the ROSC terminal controls the class-D output switching frequency using Equation 4: 1 FOSC = 2 x ROSC x COSC (4) COSC is an internal capacitor that is nominally equal to 20 pF. Variation over process and temperature can result in a ±15% change in this capacitor value. For example, if ROSC is fixed at 100 kΩ, the frequency from device to device with this fixed resistance could vary from 217 kHz to 294 kHz with a 15% variation in the internal COSC capacitor. The tolerance of the ROSC resistor should also be considered to determine the range of expected switching frequencies from device to device. It is recommended that 1% tolerance resistors be used. Differential Input The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA3106D1 with a differential source, connect the positive lead of the audio source to the INP input and the negative lead from the audio source to the INN input. To use the TPA3106D1 with a single-ended source, ac ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply the audio source to either input. In a single-ended input application, the unused input should be ac grounded at the audio source instead of at the device input for best noise performance. SHUTDOWN OPERATION The TPA3106D1 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute minimum level during periods of nonuse for power conservation. The SHUTDOWN input terminal should be held high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state. Never leave SHUTDOWN unconnected, because amplifier operation would be unpredictable. For the best power-off pop performance, place the amplifier in the shutdown or mute mode prior to removing the power supply voltage. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 21 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 MUTE OPERATION The MUTE pin is an input for controlling the output state of the TPA3106D1. A logic high on this terminal disables the outputs. A logic low on this pin enables the outputs. This terminal may be used as a quick disable/enable of outputs when changing channels on a television or transitioning between different audio sources. The MUTE terminal should never be left floating. For power conservation, the SHUTDOWN terminal should be used to reduce the quiescent current to the absolute minimum level. The MUTE terminal can also be used with the FAULT output to automatically recover from a short-circuit event. When a short-circuit event occurs, the FAULT terminal transitions high indicating a short-circuit has been detected. When directly connected to MUTE, the MUTE terminal transitions high, and clears the internal fault flag. This causes the FAULT terminal to cycle low, and normal device operation resumes if the short-circuit is removed from the output. If a short remains at the output, the cycle continues until the short is removed. If external MUTE control is desired, and automatic recovery from a short-circuit event is also desired, an OR gate can be used to combine the functionality of the FAULT output and external MUTE control, see Figure 33. TPA3106D1 External GPIO Control MUTE FAULT Figure 33. External MUTE Control MSTR/SLV and SYNC operation The MSTR/SLV and SYNC terminals can be used to synchronize the frequency of the class-D output switching when using multiple amplifiers in a single application. When the MSTR/SLV terminal is high, the output switching frequency is determined by the selection of the resistor connected to the ROSC terminal (see ROSC Resistor Selection). The SYNC terminal becomes an output in this mode, and the frequency of this output is also determined by the selection of the ROSC resistor. This TTL compatible, push-pull output can be connected to other TPA310X devices such as TPA3100D2, configured in slave mode. The output switching is synchronized to avoid beat frequencies that could occur in the audio band when two class-D amplifiers in the same system are switching at slightly different frequencies. When the MSTR/SLV terminal is low, the output switching frequency is determined by the incoming square wave on the SYNC input. The SYNC terminal becomes an input in this mode and accepts a TTL compantible square wave from another TPA310X audio amplifier configured in teh master mode or from an external GPIO. If connecting to an external GPIO, recommended frequencies are 200 kHz to 300 kHz for proper device operation, and the maximum amplitude is 4 V. The sync drive on the TPA3106D1 has been improved relative to other TPA310X devices, so please use the TPA3106D1 as the MASTER when connected in synchronous operation with other device of the TPA310X family. USING LOW-ESR CAPACITORS Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor. 22 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATURE The TPA3106D1 has short-circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts, output-to-GND shorts, and output-to-VCC shorts. When a short circuit is detected on the outputs, the part immediately disables the output drive. This is a latched fault and must be reset by cycling the voltage on the SHUTDOWN pin or MUTE pin. This clears the short-circuit flag and allows for normal operation if the short was removed. If the short was not removed, the protection circuitry again activates. The FAULT terminal can be used for automatic recovery from a short-circuit event, or used to monitor the status with an external GPIO. For automatic recovery from a short-circuit event, connect the FAULT terminal directly to the MUTE terminal. When a short-circuit event occurs, the FAULT terminal transitions high indicating a short-circuit has been detected. When directly connected to MUTE, the MUTE terminal transitions high, and clears the internal fault flag. This causes the FAULT terminal to cycle low, and normal device operation resumes if the short-circuit is removed from the output. If a short remains at the output, the cycle continues until the short is removed. If external MUTE control is desired, and automatic recovery from a short-circuit event is also desired, an OR gate can be used to combine the functionality of the FAULT output and external MUTE control, see Figure 33. THERMAL PROTECTION Thermal protection on the TPA3106D1 prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 30°C. The device begins normal operation at this point with no external system interaction. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 23 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 PRINTED-CIRCUIT BOARD (PCB) LAYOUT GENERAL GUIDELINES Because the TPA3106D1 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit board (PCB) should be optimized according to the following guidelines for the best possible performance. • Decoupling capacitors—The high-frequency 1-µF decoupling capacitors should be placed as close to the PVCC and AVCC terminals as possible. The VBYP capacitor, VREG capacitor, and VCLAMP capacitor should be placed near the TPA3106D1 on the PVCCL, PVCCR, and AVCC. • Grounding—The AVCC decoupling capacitor, VREG capacitor, VBYP capacitor, and ROSC resistor should each be grounded to analog ground. Analog ground and power ground should be connected at the thermal pad, which should be used as a central ground connection or star ground for the TPA3106D1. • Output filter—The ferrite EMI filter (if used) should be placed as close to the output terminals as possible for the best EMI performance. The LC filter should be placed close to the outputs. For an example layout, see the TPA3106D1 Evaluation Module User Manual, (SLOU191). Both the EVM user manual and the thermal pad application note are available on the TI Web site at http://www.ti.com. BASIC MEASUREMENT SYSTEM This application note focuses on methods that use the basic equipment listed below: • Audio analyzer or spectrum analyzer • Digital multimeter (DMM) • Oscilloscope • Twisted-pair wires • Signal generator • Power resistor(s) • Linear regulated power supply • Filter components • EVM or other complete audio circuit Figure 34 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine wave is normally used as the input signal because it consists of the fundamental frequency only (no other harmonics are present). An analyzer is then connected to the APA output to measure the voltage output. The analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to reduce the noise and distortion injected into the APA through the power pins. A System Two audio measurement system (AP-II) (Reference 1) by Audio Precision includes the signal generator and analyzer in one package. The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling capacitors, (CIN), so no additional coupling is required. The generator output impedance should be low to avoid attenuating the test signal, and is important because the input resistance of PAs is not high. Conversely, the analyzer-input impedance should be high. The output resistance, ROUT, of the PA is normally in the hundreds of milliohms and can be ignored for all but the power-related calculations. Figure 34(a) shows a class-AB amplifier system. It takes an analog signal input and produces an analog signal output. This amplifier circuit can be directly connected to the AP-II or other analyzer input. This is not true of the class-D amplifier system shown in Figure 34(b), which requires low-pass filters in most cases in order to measure the audio output waveforms. This is because it takes an analog input signal and converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some analyzers. 24 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 Power Supply Signal Generator APA RL Analyzer 20 Hz - 20 kHz (a) Basic Class-AB Power Supply Low-Pass RC Filter Signal Generator Class-D APA RL (See note A) Low-Pass RC Filter Analyzer 20 Hz - 20 kHz (b) Filter-Free and Traditional Class-D A. For efficiency measurements with filter-free Class-D, RL should be an inductive load like a speaker. Figure 34. Audio Measurement Systems The device uses a modulation scheme that does not require an output filter for operation, but they do sometimes require an RC low-pass filter when making measurements. This is because some analyzer inputs cannot accurately process the rapidly changing square-wave output and therefore record an extremely high level of distortion. The RC low-pass measurement filter is used to remove the modulated waveforms so the analyzer can measure the output sine wave. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 25 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 DIFFERENTIAL INPUT AND BTL OUTPUT All of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs. Differential inputs have two input pins per channel and amplify the difference in voltage between the pins. Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180 degrees out of phase. The load is connected between these pins. BTL configuration has the added benefits of quadrupling the output power to the load and eliminating a dc blocking capacitor. A block diagram of the measurement circuit is shown in Figure 35. The differential input is a balanced input, meaning the positive (+) and negative (–) pins have the same impedance to ground. Similarly, the BTL output equates to a balanced output. Evaluation Module Audio Power Amplifier Generator Analyzer Low-Pass RC Filter CIN RGEN VGEN RIN ROUT RIN ROUT CIN RGEN Twisted-Pair Wire RL Low-Pass RC Filter RANA CANA RANA CANA Twisted-Pair Wire Figure 35. Differential Input, BTL Output Measurement Circuit The generator should have balanced outputs, and the signal should be balanced for best results. An unbalanced output can be used, but it may create a ground loop that affects the measurement accuracy. The analyzer must also have balanced inputs for the system to be fully balanced, thereby cancelling out any common-mode noise in the circuit and providing the most accurate measurement. The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs: • Use a balanced source to supply the input signal. • Use an analyzer with balanced inputs. • Use twisted-pair wire for all connections. • Use shielding when the system environment is noisy. • Ensure that the cables from the power supply to the APA, and from the APA to the load, can handle the large currents (see Table 2). Table 2 shows the recommended wire size for the power supply and load cables of the APA system. The real concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations are based on 12-inch long wire with a 20-kHz sine-wave signal at 25°C. Table 2. Recommended Minimum Wire Size for Power Cables 26 DC POWER LOSS (MW) AWG Size AC POWER LOSS (MW) POUT (W) RL(Ω) 10 4 18 22 16 40 18 42 2 4 18 22 3.2 8 3.7 8.5 1 8 22 28 2 8 2.1 8.1 < 0.75 8 22 28 1.5 6.1 1.6 6.2 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 CLASS-D RC LOW-PASS FILTER An RC filter is used to reduce the square-wave output when the analyzer inputs cannot process the pulse-width modulated class-D output waveform. This filter has little effect on the measurement accuracy because the cutoff frequency is set above the audio band. The high frequency of the square wave has negligible impact on measurement accuracy because it is well above the audible frequency range, and the speaker cone cannot respond at such a fast rate. The RC filter is not required when an LC low-pass filter is used, such as with the class-D APAs that employ the traditional modulation scheme (TPA032D0x, TPA005Dxx). The component values of the RC filter are selected using the equivalent output circuit as shown in Figure 36. RL is the load impedance that the APA is driving for the test. The analyzer input impedance specifications should be available and substituted for RANA and CANA. The filter components, RFILT and CFILT, can then be derived for the system. The filter should be grounded to the APA near the output ground pins or at the power supply ground pin to minimize ground loops. Load CFILT RL AP Analyzer Input RC Low-Pass Filters RFILT VL= VIN CANA RANA CANA RANA VOUT RFILT CFILT To APA GND Figure 36. Measurement Low-Pass Filter Derivation Circuit-Class-D APAs The transfer function for this circuit is shown in Equation 5 where ωO = REQCEQ, REQ = RFILT || RANA and CEQ = (CFILT + CANA). The filter frequency should be set above fMAX, the highest frequency of the measurement bandwidth, to avoid attenuating the audio signal. Equation 6 provides this cutoff frequency, fC. The value of RFILT must be chosen large enough to minimize current that is shunted from the load, yet small enough to minimize the attenuation of the analyzer-input voltage through the voltage divider formed by RFILT and RANA. A general rule is that RFILT should be small (~100 Ω) for most measurements. This reduces the measurement error to less than 1% for RANA ≥ 10 kΩ. ( ) VOUT VIN ( = RANA RANA + RFILT 1 + j ) ( ) w wO (5) fc = Ö2 x fmax (6) An exception occurs with the efficiency measurements, where RFILT must be increased by a factor of ten to reduce the current shunted through the filter. CFILT must be decreased by a factor of ten to maintain the same cutoff frequency. See Table 3 for the recommended filter component values. Once fC is determined and RFILT is selected, the filter capacitance is calculated. When the calculated value is not available, it is better to choose a smaller capacitance value to keep fC above the minimum desired value calculated in Equation 7. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 27 TPA3106D1 www.ti.com SLOS516A – OCTOBER 2007 – REVISED NOVEMBER 2007 CFILT = 1 2p x fc x RFILT (7) Table 3 shows recommended values of RFILT and CFILT based on common component values. The value of fC was originally calculated to be 28 kHz for an fMAX of 20 kHz. CFILT, however, was calculated to be 57,000 pF, but the nearest values of 56,000 pF and 51,000 pF were not available. A 47,000-pF capacitor was used instead, and fC is 34 kHz, which is above the desired value of 28 kHz. Table 3. Typical RC Measurement Filter Values 28 MEASUREMENT RFILT CFILT Efficiency 1000 Ω 5,600 pF All other measurements 100 Ω 56,000 pF Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPA3106D1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Nov-2007 TAPE AND REEL BOX INFORMATION Device TPA3106D1VFPR Package Pins VFP 32 Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) SITE 60 330 16 9.6 9.6 1.9 12 Pack Materials-Page 1 W Pin1 (mm) Quadrant 16 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Nov-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) TPA3106D1VFPR VFP 32 SITE 60 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security RFID www.ti-rfid.com Telephony www.ti.com/telephony Low Power Wireless www.ti.com/lpw Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2007, Texas Instruments Incorporated