54ACT16657, 74ACT16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS SCAS164A – JANUARY 1991 – REVISED APRIL 1996 D D D D D D D Members of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings 54ACT16657 . . . WD PACKAGE 74ACT16657 . . . DL PACKAGE (TOP VIEW) 1OE NC 1ERR GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2ERR NC 2OE description The ’ACT16657 contain two noninverting octal transceiver sections with separate parity generator/checker circuits and control signals. For either section, the transmit/receive (1T/R or 2T/R) input determines the direction of data flow. When 1T/R (or 2T/R) is high, data flows from the 1A (or 2A) port to the 1B (or 2B) port (transmit mode); when 1T/R (or 2T/R) is low, data flows from the 1B (or 2B) port to the 1A (or 2A) port (receive mode). When the output-enable (1OE or 2OE) input is high, both the 1A (or 2A) and 1B (or 2B) ports are in the high-impedance state. Odd or even parity is selected by a logic high or low level, respectively, on the 1ODD/EVEN (or 2ODD/EVEN) input. 1PARITY (or 2PARITY) carries the parity bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity generator/checker in the receive mode. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1T/R 1ODD/EVEN 1PARITY GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2PARITY 2ODD/EVEN 2T/R NC – No internal connection In the transmit mode, after the 1A (or 2A) bus is polled to determine the number of high bits, 1PARITY (or 2PARITY) is set to the logic level that maintains the parity sense selected by the level at the 1ODD/EVEN (or 2ODD/EVEN) input. For example, if 1ODD/EVEN is low (even parity selected) and there are five high bits on the 1A bus, then 1PARITY is set to the logic high level so that an even number of the nine total bits (eight 1A-bus bits plus parity bit) are high. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 54ACT16657, 74ACT16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS SCAS164A – JANUARY 1991 – REVISED APRIL 1996 description (continued) In the receive mode, after the 1B (or 2B) bus is polled to determine the number of high bits, the 1ERR (or 2ERR) output logic level indicates whether or not the data to be received exhibits the correct parity sense. For example, if 1ODD/EVEN is high (odd parity selected), 1PARITY is high, and there are three high bits on the 1B bus, then 1ERR is low, indicating a parity error. The 74ACT16657 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54ACT16657 is characterized for operation over the full military temperature range of –55°C to 125°C. The 74ACT16657 is characterized for operation from –40°C to 85°C. FUNCTION TABLE NUMBER OF A OR B INPUTS THAT ARE HIGH 0 2 0, 2, 4, 4 6 6, 8 1 3 1, 3, 5 5, 7 Don’t care 2 INPUTS OUTPUTS OE T/R ODD/EVEN INPUT/OUTPUT PARITY L H H H L H L L Z Transmit L L H H H Receive L L H L L Receive L L L H L Receive L L L L H Receive L H H L Z Transmit L H L H Z Transmit L L H H L Receive L L H L H Receive L L L H H Receive L L L L L Receive H X X Z Z Z POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ERR OUTPUT MODE Z Transmit 54ACT16657, 74ACT16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS SCAS164A – JANUARY 1991 – REVISED APRIL 1996 logic symbol† 1OE 1T/R 1ODD/EVEN 2OE 2T/R 2ODD/EVEN 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1 56 55 28 29 30 5 6 G3 3 EN1/3G5 [REC] 3 EN2 [XMIT] N4 G8 8 EN6/8G10 [REC] 8 EN7 [XMIT] N9 1 1 Z11 1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2 51 8 49 9 48 10 47 12 45 13 44 14 43 11 2A1 52 15 16 2k 54 • • • 4, 2 18 4, 1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1PARITY 5 3 6 1 Z21 1 42 7 41 17 40 19 38 20 37 21 36 23 34 24 33 21 1B1 2k 31 • • • 9, 7 10 28 9, 6 26 1ERR 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2PARITY 2ERR † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 54ACT16657, 74ACT16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS SCAS164A – JANUARY 1991 – REVISED APRIL 1996 logic diagram, each transceiver (positive logic) T/R OE A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 PARITY ODD/EVEN ERR 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 54ACT16657, 74ACT16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS SCAS164A – JANUARY 1991 – REVISED APRIL 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 mA Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils. recommended operating conditions (see Note 3) 54ACT16657 NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 High-level output current IOL ∆t/∆v Low-level output current High-level input voltage 74ACT16657 MIN 2 2 0.8 Input transition rise or fall rate TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating. UNIT V V 0.8 V VCC VCC V –24 –24 mA 24 24 mA VCC VCC 0 0 V 0 10 0 10 ns/V –55 125 –40 85 °C PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 54ACT16657, 74ACT16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS SCAS164A – JANUARY 1991 – REVISED APRIL 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 4.5 V IOH = –50 50 µA VOH 24 mA IOH = –24 IOH = –75 mA† II IOZ‡ Control inputs ICC IOL = 75 mA† VI = VCC or GND VO = VCC or GND VI = VCC or GND, MIN IO = 0 MAX 74ACT16657 MIN 4.4 4.4 5.5 V 5.4 5.4 5.4 4.5 V 3.94 3.8 3.8 5.5 V 4.94 4.8 4.8 3.85 3.85 0.1 0.1 MAX UNIT V 0.1 5.5 V 0.1 0.1 0.1 4.5 V 0.36 0.44 0.44 5.5 V 0.36 0.44 0.44 1.65 1.65 ±1 ±1 µA 5.5 V One input at 3.4 V, Other inputs at VCC or GND ∆ICC§ 54ACT16657 4.4 4.5 V IOL = 24 mA A or B ports TA = 25°C TYP MAX 5.5 V IOL = 50 µA VOL MIN V 5.5 V ±0.1 5.5 V ±0.5 ±5 ±5 µA 5.5 V 8 80 80 µA 5.5 V 0.9 1 1 mA Ci Control inputs VI = VCC or GND 5V 4.5 pF Co ERR Cio A or B ports VO = VCC or GND VO = VCC or GND 5V 11 pF 5V 12 pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ For I/O ports, the parameter IOZ includes the input leakage current. § This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPLH tPHL A PARITY tPLH tPHL ODD/EVEN PARITY ERR PARITY, tPLH tPHL B ERR tPLH tPHL PARITY ERR tPZH tPZL OE A B, A, B PARITY, PARITY or ERR tPHZ tPLZ OE A B, A, B PARITY, PARITY or ERR MIN TA = 25°C TYP MAX POST OFFICE BOX 655303 74ACT16657 MIN MAX MIN MAX 4.1 7.3 9.6 4.1 10.7 4.1 10.7 3.2 6.8 9.8 3.2 10.6 3.2 10.6 4 8.6 12.9 4 14.3 4 14.3 4.3 9 13.1 4.3 14.3 4.3 14.3 3.7 8.3 12.3 3.7 13.7 3.7 13.7 4.1 8.8 12.8 4.1 14.1 4.1 14.1 3.9 8.6 13 3.9 14.6 3.9 14.6 4.3 9 13.3 4.3 14.7 4.3 14.7 3.8 8.4 12.2 3.8 13.8 3.8 13.8 4.1 8 12.8 4.1 14.2 4.1 14.2 2.6 6.1 10.1 2.6 11.3 2.6 11.3 3.2 7.2 11.7 3.2 13 3.2 13 5.9 8.6 10.5 5.9 11.2 5.9 11.2 5.3 8 9.8 5.3 10.5 5.3 10.5 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 54ACT16657 • DALLAS, TEXAS 75265 UNIT ns ns ns ns ns ns ns 54ACT16657, 74ACT16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS SCAS164A – JANUARY 1991 – REVISED APRIL 1996 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d TEST CONDITIONS Outputs enabled Power dissipation capacitance per transceiver Outputs disabled pF CL = 50 pF, TYP f = 1 MHz 76 35 UNIT pF PARAMETER MEASUREMENT INFORMATION 2 × VCC 500 Ω From Output Under Test S1 Open GND 500 Ω CL = 50 pF (see Note A) LOAD CIRCUIT Input Output Control (low-level enabling) 3V 1.5 V 1.5 V 0V tPHL tPLH VOH Output 50% VCC 50% VCC VOL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND 1.5 V 1.5 V 3V 0V tPZL Output Waveform 2 S1 at GND (see Note B) [ VCC tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) 50% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS 20% VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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