MP7542 5 V CMOS 4-Bit Input, 12-Bit Digital-to-Analog Converter FEATURES • • • • • 12-Bit DAC with a 4-Bit Parallel Address for 4 & 8-Bit Microprocessor or Microcontroller Interface • Nonlinearity +1/2 LSB Tmin to Tmax • Latch-Up Free • Low Sensitivity to Output Amplifier VOS • Low Output Capacitance +5 V Supply Operation Low Power Consumption: 40mW Max. Low Cost Serial Version: MP7543 cycle of a static RAM. A CLEAR input allows the 12-bit DAC register to be reset to all zeros. GENERAL DESCRIPTION The MP7542 is a precision, 12-bit CMOS 4-quadrant multiplying Digital-to-Analog Converter designed for direct interface to 4 and 8-bit microprocessors. The MP7542 is manufactured using advanced thin-film on monolithic double metal CMOS fabrication process. A unique decoding technique is utilized yielding excellent accuracy and stability. The MP7542 consists of three 4-bit registers, a 12-bit DAC register, address decoding logic, and a 12-bit CMOS multiplying DAC. Data is loaded into the data registers in three 4-bit nibbles and subsequently transferred to the 12-bit DAC register. All data loading or data transfer operations are identical to the WRITE The MP7542 reduces the additional linearity errors due to output amplifier offset to only 330µV per millivolt of offset versus 670 µV for the standard R-2R ladder CMOS DACs. SIMPLIFIED BLOCK DIAGRAM VREF RFB 12-Bit Multiplying DAC IOUT1 IOUT2 AGND CLR 12-Bit DAC Register VDD WR CS A0 Address Decode Logic H-Byte Data Register M-Byte Data Register L-Byte Data Register DGND A1 DB0 (LSB) DB1 DB2 DB3 (MSB) Rev. 2.00 1 MP7542 ORDERING INFORMATION Package Type Temperature Range Part No. INL (LSB) DNL (LSB) Gain Error (LSB) Plastic Dip –40 to +85°C MP7542JN +1 +2 +14.5 Plastic Dip –40 to +85°C MP7542KN +1/2 +1 +14.5 MP7542JS +1 +2 +14.5 +1/2 +1 +14.5 SOIC –40 to +85°C SOIC –40 to +85°C MP7542KS Ceramic Dip –40 to +85°C MP7542AD +1 +2 +14.5 Ceramic Dip –40 to +85°C MP7542BD +1/2 +1 +14.5 Ceramic Dip –55 to +125°C MP7542SD* –55 to +125°C +1 +2 +14.5 Ceramic Dip MP7542TD* +1/2 +1 +14.5 *Contact factory for non-compliant military processing PIN CONFIGURATIONS IOUT1 IOUT2 AGND DB3 DB2 DB1 DB0 CS See Packaging Section for Package Dimensions 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 IOUT1 IOUT2 AGND DB3 DB2 DB1 DB0 CS RFB VREF VDD CLR DGND A1 A0 WR 16 Pin CDIP, PDIP (0.300”) D16, N16 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 RFB VREF VDD CLR DGND A1 A0 WR 16 Pin SOIC (Jedec, 0.300”) S16 PIN OUT DEFINITIONS PIN NO. 1 2 NAME IOUT1 IOUT2 PIN NO. DESCRIPTION DAC current output. Normally terminated at op amp. NAME DESCRIPTION 8 CS Chip Select Input 9 WR Write Input DAC current output. Normally terminated at ground. 10 A0 Address Bus Input A1 Address Bus Input 3 AGND Analog Ground 11 4 DB3 Data Input Bit 3 (MSB) 12 DGND Digital Ground CLR Clear Input 5 DB2 Data Input Bit 2 13 6 DB1 Data Input Bit 1 14 VDD +5 V Supply Input 7 DB0 Data Input Bit 0 (LSB) 15 VREF Reference Input 16 RFB DAC Feedback Resistor Rev. 2.00 2 MP7542 ELECTRICAL CHARACTERISTICS (VDD = + 5 V, VREF = +10 V unless otherwise noted) Parameter Symbol Min N 12 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments STATIC PERFORMANCE1 Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) J, A, S K, B, T Differential Non-Linearity J, A, S K, B, T Gain Error J, A, S, K, B, T 12 Bits INL LSB Best Fit Straight Line Spec. (Max INL – Min INL) / 2 LSB Monotonicity 11 Bits Guaranteed 12 Bits Guaranteed LSB Using Internal RFB +2 ppm/°C ∆Gain/∆Temperature |∆Gain/∆VDD| ∆VDD = + 5% +1 +1/2 +1 +1/2 +2 +1 +2 +1 +12.3 +14.5 DNL GE Gain Temperature Coefficient2 TCGE Power Supply Rejection Ratio PSRR +50 +100 ppm/% IOUT +10 +200 nA Output Leakage Current DYNAMIC PERFORMANCE Current Settling Time2 AC Feedthrough at IOUT12 RL=100Ω, CL=13pF 2.0 2.5 µs mV p-p 20 kΩ ILKG CIN 0.8 +1 8 0.8 +1 8 V V µA pF COUT1 COUT1 COUT2 COUT2 260 100 50 210 260 100 50 210 pF pF pF pF DAC Inputs all 1’s DAC Inputs all 0’s DAC Inputs all 1’s DAC Inputs all 0’s +5.5 2.5 V mA All digital inputs = 0 V or all = 5 V tS FT 2.0 2.5 Full Scale Change to 1/2 LSB VREF = 10kHz, 20 Vp-p, sinewave REFERENCE INPUT Input Resistance RIN 5 VIH VIL 3.0 10 20 5 DIGITAL INPUTS3 Logical “1” Voltage Logical “0” Voltage Input Leakage Current Input Capacitance2 3.0 ANALOG OUTPUTS Output Capacitance2 POWER SUPPLY Supply Voltage5 Supply Current VDD IDD +4.5 +5.5 2.5 Rev. 2.00 3 +4.5 MP7542 ELECTRICAL CHARACTERISTICS (CONT’D) Parameter Symbol Min tWR tAWH tCWH tCLR 120 50 50 200 60 80 50 50 60 120 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments SWITCHING CHARACTERISTICS2, 4 WR Pulse Width Address to WR Hold Time CS to WR Hold Time CLR Pulse Width Byte Loading, CS to WR Setup Byte Loading, Address to WR Setup Byte Loading, WR to Data Setup Byte Loading, WR to Data Hold DAC Loading, CS to WR Setup DAC Loading, Address to WR Setup tCWS1 tAWS1 tDS tDH tCWS2 tAWS2 220 65 100 300 130 180 65 65 150 240 ns ns ns ns ns ns ns ns ns ns NOTES: 1 2 3 4 5 Full Scale Range (FSR) is 10V for unipolar mode. Guaranteed but not production tested. Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. See timing diagram. Specified values guarantee functionality. Refer to other parameters for accuracy. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3 Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V Digital Input Voltage to GND (2) . GND –0.5 to VDD +0.5 V IOUT1, IOUT2 to GND . . . . . . . . . . . GND –0.5 to VDD +0.5 V VREF to GND (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V VRFB to GND (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality Guaranteed +0.5 V) Lead Temperature (Soldering, 10 seconds) . . . . . . +300°C Package Power Dissipation Rating to 75°C CDIP, PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . 700mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 10mW/°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. 3 GND refers to AGND and DGND. Rev. 2.00 4 MP7542 ADDRESS BUS VALID A0 - A1 VINH VINL tAWS1 CS tAWH tCWS1 VINH VINL tAWS2 tCWH tWR WR tCWS2 tDS tDH VINH VINL DB3 - DB0 DATA BUS VALID Figure 1. Timing Diagram MP7542 Control Inputs MP7542 Operation A1 A0 CS WR CLR X X X X 0 Resets DAC 12-bit register to code 0000 0000 0000 X X 1 1 1 No operation; device not selected 0 0 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 0 1 1 1 0 0 1 Load LOW byte data register on edges as shown 1 0 0 1 Load MIDDLE byte data register on edges as shown 1 0 0 1 Load applicable data register with data at D0 - D3 Load HIGH byte data register on edges as shown 1 Load 12-bit DAC register with data in LOW byte, MIDDLE byte, & HIGH byte data registers NOTES 1. 1 indicates logic HIGH 2. 0 indicates logic LOW 3. X indicates don’t care 4. indicates LOW to HIGH transition 5. MSB XXXX XXXX XXXX LSB high middle low byte byte byte 6. Although positive-going edge of either CS or WR will load data register, timing is optimized by using WR to latch data and using CS as a device enable. Table 1. Truth Table Rev. 2.00 5 MP7542 APPLICATION NOTES Refer to Section 8 for Applications Information ing the MP7542 in a unipolar mode a CLEAR sets the DAC output to zero scale output. In the bipolar mode a CLEAR causes the DAC output to go to –VREF. Interface Logic Information The MP7542 is designed to interface as a memory-mapped output device. In summary: A typical system configuration is shown below. CS is the decoded device address, and is derived by decoding the 14 higher order address bits. A0 and A1 are the MP7542 operation address bits, and are decoded internally in the MP7542 to point to the desired loading operation (i.e. load high byte, middle byte, low byte or DAC register). See Table 1. 1. The MP7542 DAC register can be asynchronously cleared with the CLR input. 2. Each MP7542 requires only 4 bits of memory. 3. Any of the four basic loading operations (i.e. load low byte data register, middle byte data register, high byte data register or 12-bit DAC register) are accomplished by executing a memory WRITE operation to the applicable address location for the required DAC operation. All data loading operations are identical to the write cycle of a RAM. Additionally, the CLR input allows the MP7542 DAC register to be cleared asynchronously to 0000 0000 0000. When operat- ADDR ALE 8085 or comparable (8) A2 - 15 ADDRESS BUS (16) A0-15 A0 A1 ADDRESS (16) Address Decode 8212 DECODED A2 - 15 USED AS CHIP SELECT WR ADDR/DATA (8) AD0-7 DATA (8) DATA AD0 AD1 AD2 AD3 A0 DB3 +5 V DB2 A1 WR CS MP7542 DB1 DB0 CLR FROM SYSTEM RESET Figure 2. 8085/MP7542 Interface (Memory Mapped Output) Rev. 2.00 6 MP7542 16 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) N16 S 16 9 1 8 Q1 E1 E D A1 Seating Plane A L B B1 e α MILLIMETERS INCHES SYMBOL MIN MAX MIN –– 0.200 –– 5.08 A1 0.015 –– 0.38 –– B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 0.745 0.785 18.92 19.94 E 0.295 0.325 7.49 8.26 E1 0.220 0.310 5.59 7.87 A e 0.100 BSC MAX 2.54 BSC L 0.115 0.150 2.92 3.81 α 0° 15° 0° 15° Q1 0.055 0.070 1.40 1.78 S 0.020 0.080 0.51 2.03 Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. Rev. 2.00 7 C MP7542 16 LEAD CERAMIC DUAL-IN-LINE (300 MIL CDIP) D16 S1 See Note 1 S 16 9 1 8 E1 E D Q Base Plane Seating Plane A L e c b INCHES SYMBOL L1 b1 NOTES MILLIMETERS MIN MAX MIN A –– 0.200 –– 5.08 –– b 0.014 0.023 0.356 0.584 –– b1 0.038 0.065 0.965 1.65 2 c 0.008 0.015 0.203 0.381 –– D –– 0.840 –– 21.34 4 E 0.220 0.310 5.59 7.87 4 E1 0.290 0.320 7.37 8.13 7 e 0.100 BSC MAX 2.54 BSC NOTES 5 L 0.125 0.200 3.18 5.08 –– L1 0.150 –– 3.81 –– –– Q 0.015 0.060 0.381 1.52 3 S –– 0.080 –– 2.03 6 0.005 –– 0.13 –– 6 0° 15° 0° 15° –– S1 α α Rev. 2.00 8 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center. MP7542 16 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S16 D 16 9 E H 8 h x 45° C A Seating Plane B e α A1 L INCHES SYMBOL MIN MILLIMETERS MAX MIN MAX A 0.097 0.104 2.46 2.64 A1 0.0050 0.0115 0.127 0.292 B 0.014 0.019 0.356 0.482 C 0.0091 0.0125 0.231 0.318 D 0.402 0.412 10.21 10.46 E 0.292 0.299 7.42 7.59 e 0.050 BSC 1.27 BSC H 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 L 0.016 0.035 0.406 0.889 α 0° 8° 0° 8° Rev. 2.00 9 MP7542 Notes Rev. 2.00 10 MP7542 Notes Rev. 2.00 11 MP7542 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.00 12