EXAR XR88C681N/40

XR88C681
FEATURES
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GENERAL DESCRIPTION
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ORDERING INFORMATION
Part No.
Pin Package
Operating
Temperature Range
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XR88C681
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Figure 1. Block Diagram of the XR88C681
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XR88C681
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PIN CONFIGURATION
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XR88C681
PIN DESCRIPTION
44 PLCC/
LCC
40 DIP,
CDP
28 DIP,
CDIP
Symbol
Type
7
1
Description
No Connection.
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XR88C681
44 PLCC/
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40 DIP,
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28 DIP,
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Symbol
Type
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XR88C681
44 PLCC/
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Output 4 (General Purpose Output). (% (
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Description
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XR88C681
44 PLCC/
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Symbol
Type
Description
1=
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XR88C681
DC ELECTRICAL CHARACTERISTICS1, 2, 3
Test Conditions: J >" ; J 6; 6K %% (% %'(+($
Symbol
Parameter
Min.
Typ.
Max.
Unit
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6
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Conditions
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Notes
1. Parameters are valid over the specified temperature and operating supply ranges. Typical values are 25C, V
CC = 5V and typical
processing parameters.
2. All voltages are referenced to ground (GND). For testing, input signal levels are 0.4V and 2.4V with a transition time of 20ns
maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V as appropriate. See Figure 50.
3. For prime grade N, P, J, L, M, ML, V
CC = 5V + 10%.
4. Measured operating with a 3.6864MHz crystal and with all outputs open.
=
XR88C681
AC ELECTRICAL CHARACTERISTICS 1, 2, 3
Test Conditions: J >" ; J 6; 6K %% (% %'(+($
Symbol
Parameter
Min.
Typ.
Max.
Unit
Reset Timing (See Figure 51)
2
22 ,% B($
•
XR88C681 Read and Write Cycle Timing (Figure 52)4
1 ( " B
9
%
8
1 8$ ( + " B
9
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8(-
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Z-Mode Interrupt Cycle Timing (Figure 53)
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Interrupt Output Timing (Figure 55)
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Clock Timing (Figure 56)
9:
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8I
Conditions
XR88C681
AC ELECTRICAL CHARACTERISTICS 1, 2, 3 (CONT’D)
Test Conditions: J >" ; J 6; 6K %% (% %'(+($
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
Clock Timing (Figure 56) (Cont’d.)
5
+5
.( 2!
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E
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5
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2!
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16
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6
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Transmitter Timing (Figure 57)
5
5
58
5 & 5
2!
9
5 & 5
#
9
5 ( 5
2!
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5 8$ ( + 5
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%
%
Notes
1. Parameters are valid over the specified temperature and operating supply ranges. Typical values are 25C, V
CC = 5V and typical
processing parameters.
2. All voltages are referenced to ground (GND). For testing, input signal levels are 0.4V and 2.4V with a transition time of 20ns
maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V as appropriate. See Figure 50.
3. AC test conditions for outputs: CL = 50pF, RL = 2.7k• to V .
CC
4. If CS is used as the strobing input, this parameter defines the minimum high time between CSs.
5. Consecutive write operations to the same register require at least three edges of the X1 clock between writes.
6. This specification imposes a 6 MHz maximum 68000 clock frequency if a read or write cycle follows immediately after the previous
read or write cycle. A higher 68000 clock can be used if this is not the case.
7. This specification imposes a lower bound on CS and IACK low, guaranteeing that they will be low for at least one CLK period.
8. The minimum high time must be at least 1.5 times the X1/CLK period and the minimum low time must be at least equal to the X1/CLK
period if either channel’s Receiver is operating in external 1X clock mode.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS1
& ;- >;
- /6 6 ;-% (
%' 0
$ 6; A>;
1. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the “Electrical Characteristics” section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
XR88C681
2. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive stat-
ic charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltage larger than the rated
maximum.
XR88C681
SYSTEM DESCRIPTION
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PRINCIPLES OF OPERATION
Figure 1 %
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Figure 2
XR88C681
.B
B
2 ''3
22
22
Figure 2. External Logic Circuitry required to interface a 6800 Family
Processor to the XR88C681 Device
B.1 DUART Register Addressing
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Table 1 Please note that some of the
registers are “Read Only” and others are “Write Only”. 2' '
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XR88C681
Address (Hex)
Read Mode Registers
Write Mode Registers
Register Name
Symbol
Register Name
Symbol
$ -(%"
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" % -(%"
'3 ' -(%"
%3$ #
% -(%
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*" *
$ -(%"
*
*" *
% -(%"
*
*
'3 ' -(%"
*
*
22;2
$ -(%"
*
*
*
! 8$(
- -(%"
*
8*
! 8$(
- -(%"
*
8*
#
;'
-(%
#;
#
;'
-(%
#;
#
,
#,
,
+(-(
-(%
, ,>
,
2
.(
$
, *(%
$
,*
.(
$
, *(%
$
,*
Table 1. DUART Port and Register Addressing
Note: The shaded blocks are not Read/Write registers but are rather “Address-Triggered” Commands.
Table 1 (
$('% ' '
(% E($ ( $ -(%% %%'($ ( ' + % $ -(%
(% (% C$ -(%D (
(
'(.%&% 22 ' (
(% C(
(
- D
'
-(% Please note that the suffix “n” is used at the end of many of the DUART registers symbols in
order to refer, generically, to either channels A or B 8" '
% + (
( %(+ + $$%%
+ -(% + -(%" ($(& +(
- & $ B( ''%% -(%
(
( '
(
C(
D -(% ( $ % ''% ( C22 ,#72D '
$ % (
3$ C22 ,#72D '
$ '
(%%$ & ((
- ( $ ( '
H% $ -(% +" $ -(%%" ((
-(
<
XR88C681
'
" % -(' $$%% +% $ +
'(
% + '
$ & $
-(%% $(%'%%$ (
$( (
Section G.3
B.2 Command Decoding
2' '
(% E($ ( $ -(% #
-
" + % $ -(%% .$(% %(" .$(% '(" - ( +'(((
- %(% + (%'
%
'
$% ( + + ' $ -(% (% %
$ (
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Miscellaneous Commands
Enable/Disable
Receiver
Enable/Disable
Transmitter
(
- !
J 7 -
J 2
!
J (% !
J 7 ($ $ %
J 7 -
J 2
!
J (% !
J 7 ;($ %
Table 2. (CRA, CRB) Bit Format for Command Registers of Channels A & B
+
'(
+ ( + $ -(%% (% +(& %(-+$ (% ( (% %$ ( $(% %( $. '(
( + $ -(% (% %$ (
3 %(% + (%'
% '
$% Table 3 $+(
% '
$% %%'($ ( ( + $ -(%% Please note that the upper nibble commands
116 through B16 effects only the performance of Command Register’s Channel 8" '
$% / $ /
++'% %&% '( (
Bit 7
Bit 6
Bit 5
Bit 4
Description
Null Command.
Reset MRn Pointer. %% H% (
(
Reset Receiver. % (
$(($ '
'( % (+ 8$ % % ($
'( (% $(%$ $ # (% +%$
Reset Transmitter. %% (
$(($ '
%( % (+ 8$ % $ ($
5
(% +'$ (- Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers,
Unless Otherwise Specified (Cont’d Next Page)
6
XR88C681
Bit 7
Bit 6
Bit 5
Bit 4
Description
Reset Error Status. % '($ *3
*" ,(& 2 ,2" (
- 2 2 $
2 2 %% (%" N>41O
'(+('&" (+ 2 $" + (' '
(% % C*'3D 2 $" (% '
$ (
% + '( 2 #
$('% (
%
-(% #
*'3 2 $" ' ( ,2"
2" 2" * ''%" ( '
(
+--$ (
% -(%" ( (% '
$ (%
(%%$
#+ 2 $" + (' '
(% % C' 2 $D" '
% + % -(% + ,2" 2" $ * +'$ '' & '' %(% #
C'
2 $D" % + % (
$('% (% %$
& '' (% + 8
2 (
$(' (% &% %
$ % C*'3
2 $D (
$('" $ E(% (% '
$ %
Reset Break Change Interrupt. % '
H% 3 '
- (
%% (
Start Break. '% 5
%( % $ % 3 #+ %( (% &" % + 3 & $&$ ( (% #+ %( (% '
(" 3 -(
% %(%%(
+
% ''% (
8 (% '$" (I"
52, % + 3 ( -(
Stop Break. 5
(
( - (- ((
( (% 5
( (
(- + ( ( + ! ''" (+ &" (% %($
Set Rx BRG Select Extend Bit. % '
H%
C'( *0 ' 2!
$ *(D Clear Rx BRG Select Extend Bit. % '
H% C'( *0 ' 2!
$ *(D Set Tx BRG Select Extend Bit. % '
H%
C
%( *0 ' 2!
$ *(D Clear Tx BRG Select Extend Bit. % '
H% C
%( *0 ' 2!
$ *(D Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers,
Unless Otherwise Specified (Cont’d)
/
XR88C681
Bit 7
Bit 6
Bit 5
Bit 4
Description
Set Standby Mode (Channel A). B
(% '
$ (% (
3$ ( $ -(%
" (% $ + ' + %(%"
'(%" '
.( $ $$((
'('(% ' (
%
$& $ Please note that this command effects the
operation of the entire chip 7 (
(% %$ & $ % & (
3(
- C2
#;2 2D '
$
Reset IUS Latch (Channel B). B
(% '
$
(% (
3$ ( * $ -(%"
$ (% (
- (
?$" ( '%%
#
$(' # ' %
(%" (
" ( '% #2 --
C(-D
Set Active Mode (Channel A). B
(% '
$ (% (
3$ ( $ -(%
" (% $ + $& $
$ %% (
Set Z-Mode (Channel B). B
(% '
$ (%
(
3$ ( * $ -(%" (% '
$((
$ (
?$ $($ $(%'%%(
+ H% (
(
(
?$" ,% % Section C.6.2 7 (
+ = (
#, '3-$ $('%
Reserved.
Reserved.
Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers,
Unless Otherwise Specified (Cont’d)
& (
- ( " (
%
% (% '$
(% .( ( (
(( '
(
- $($
$(%'%%(
(
(
+ .(" %
% Section D.2
#
$$((
'
$% (' ( -
'
$ -(%%" % ++%
C$$%%(--$D '
$% % '
$% (%$ (
Table 1" C , 7 20#2
2#70DL $ + ($
(+($ & (
C%$$D (
Table 1 '(+('&" % '
$% 4
! + $$%%(--$ '
$% (%
C2 , , *#D $ (%
'
$ (% (
3$ & +(
- ( + $ $$%% 2/ B
% (
3% (%
'
$" .% (% %(
- '(
(% CD ((
, , -(% (%" ((
,
%'(+($ %" '
-$ % + (
% '
% + (
$(($ (%
((
, 8
'" (+ ,NO (% % CD" % +
'%
$(
- (
" ," (% % -(' CD %E
&" '
(
3 + C2
, , *#D '
$ % C92
, , ,#7D '
$ $($
$(%'%%(
(
(
+ ,%" %
% Section F
72.#2 7
, 72.#2 7
2 , , *# 7
92 , , *# 7
2' + % '
$% (
3$ & ( $(
- ((
- $ ( '%
$(
- $$%%% %
%'(+($ (
Table 1
2!4
72.#2 7 (% (
3$ &
'$ + $(
- $$%% 2/ Please
note that this “Read Operation” will not result in placing
the contents of a DUART register on the data bus. >
XR88C681
'( # * 2
$ + '($ *3 (
% *
2
$ + .( '$
- + (
(
%" #," #," #," #,1
#
*'3 '
%(%% + #
%
-(%% #" #
%3 -(%% #" %3$ #
% -(%% # $ #
;' -(% #; Table 4 (%% %
-(%%" ( $$%% '(
((
C. INTERRUPT CONTROL BLOCK
#
*'3 % % & (
C#
(
D (
(
'$% (
E% %(-
#7" (' & -$ %%$ ''
' + & + +(
- %4
%( 8$ -(% * $&
'( 8$ -(% * $&
Register
Description
Address Location
(in DUART Address Space)
#
#
#
#;
#
% -(%
#
%3 -(%
%3$ #
% -(%
#
;' -(%
6/ $ &
6/ B( &
/ $ &
/
Table 4. Listing and Brief Description of Interrupt System Registers
''(
- #
-
" '
% + # ( (
$('
'%%" %' %
+ #
E% + +" & (
%(' (
+ %$ -(
& $(
( (% -(% # %3$ #
%
-(% (+ + # (% %
$ (
Table 54
$ % + ' + % -(%% $+(
$ C.1 Interrupt Status Registers (ISR)
'
% + # (
$('% %% + (
(
'
$((
% #+ & (% ((
% -(%% --$ C(-D" '%
$(
- '
$((
% (%
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Input Port
Change
Delta Break
B
RXRDY/
FFULLB
TXRDYB
Counter
Ready
Delta Break
A
RXRDY/
FFULLA
TXRDYA
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
Table 5. ISR Bit Format
$+(
((
+ (
- (
$ ' + % (% (%
%
$ (
$(($ #
, (
'
-$ %
+(
% + ($ (
%" +(
- + $($ $%'((
+ #," % Section F
ISR[7]: Input Port Change of State
Please note that in order to enable this Interrupt
Condition, the user must do two things:
#+ (% ( (% -(' CD" '
- + % %
$'$ #
, (
% #, #,1 % $
%(' (% (
& $(
- #, (+ #N>O J #N>O (% '$ , % $ #
,
+(-(
-(% #, *& $(
- #," % ( $(
4
B( ( $ ( + !((& -(%" N14O #
(% %" % (% %'(+&(
- (' #
,(
% %$ (-- C#
, -D #
E%
=
XR88C681
'% $$ (
8* ( %( (%
$(%$ ( %($
B( -(' CD #N>O
ISR[6] Delta Break Indicator - Channel B
ISR[3] Counter Ready
B
(% ( (% %" ( (
$('% *
'( % $'$ -(
(
- $ + '($
3 * (% ( (% '$ % ,
(
3% '
* C22 *2: 8702
#72,D '
$ % Table 3
(
+(
(
H% %
% *2:
'
$((
" % % Section G.2
#
#2 $" . .( ( %
#N1O ' ' '&' + %
%E ( ,1 (
#N1O ( '$ &
(
3(
- C, 72D '
$ * (
(
$"
(
#2 $" C, 72D
'
$ ( % .
#
72 $" (% ( (% % '
'% (
'
/ $ (% '$ '
(% %$ & C, 72D
'
$ B
.( (% (
72
$" C, 72D '
$ ( % .(
ISR[5] RXRDY/FFULL B - Channel B Receiver Ready
or FIFO Full
+
'(
+ (% ( (% %'$ & -(
*N/O #+ -$ % '( $&
(
$(' 5G*" ( (
$('% % '' + $ (% (
8* $ (% $& $ & , (% ( (% % '' (% %+$ +
'( %(+ -(% 8* $ (% '$ , $% 8* #+ %( ''% (
8* + $ (
" ( ( % -(
+ 8* (% C$D
ISR[2]: Delta Break A - Channel A Change in Break
%%(
+ (% ( (
$('% '
'(
% $'$ -(
(
- + $ + '($
3 * (% ( (% '$ , (
3% '
C22 *2: 8702 #72,D
'
$
(
+(
(
H%
%
% *2: '
$((
" % % Section G.2
#+ (% ( (% -$ % # + (
$(' 99*"
( (% % '' (% %+$ + 8* $ %+ '%% 8* ' + (%
( (% '$ , $% 8*L $ &
C(
-D # " 3(
- + ! '' #+
'' (% ((
- (
'% 8* (% +"
(% ( ( % -(
+ $ (
" '' (% $$ (
8*
ISR[1] RXRDYA/FFULL A - Channel A Receiver
Ready or FIFO Full
+
'(
+ (% ( (% %'$ & -(
N/O #+ -$ % '( $&
(
$(' 5G" (% ( (
$('% (% %
'' + $ (
8" $ (% $& $ &
, (% ( (% % '' (% %+$
+ 8 $ (% '$ ,
$% C%D 8 #+ %( ''%
(
8" +(
- $ (
" ( ( %
-(
+ 8 (% C$D
Note:
If this bit is configured to reflect the FFULLB indicator, this
bit will not be set (nor will produce an interrupt request) if
one or two characters are still remaining in RHRB, following
data reception. Hence, it is possible that the last two characters in a string of data (being received) could be lost due
to this phenomenon.
#+ (% ( (% -$ % # 8 + (
$('
99" ( (% % '' (% %+$ +
8 $ & %+$ ''
'%% 8 ' + (% ( (% '$ , $% 8 #+ '' (% ((
- (
'% 8 (% +" (% ( ( % -(
" +(
$ (
" '' (% $$ (
8
ISR[4] TXRDYB - Channel B Transmitter Ready
(% ( (% $(' + 5G *" *NO
(% (" %" (
$('% 8* (% & $ (%
$& '' '' + , ( (%
'$ , (% '' 8*L
$ (% % -(
" '' (% %+$ 5G* (% % %( (% (
((&
$ $ (% '$ %( (% $(%$
Note:
If this bit is configured to reflect the FFULLA indicator, this
bit will not be set (nor will produce an interrupt request) if
XR88C681
'% $$ (
8 ( %( (%
$(%$ ( %($
one or two characters are still remaining in RHRA, following
data reception. Hence, it is possible that the last two characters in a string of data (being received) could be lost due
to this phenomenon. Therefore, the user is advised to read
RHRA until empty.
C.2 Interrupt Mask Register (IMR)
#
%3 -(% (% CB( &D -(%
(' % % %' '
$((
% (
'% (%% #
E% '%% #
$%" % % (
+
%3(
- '3(
- '(
'
$((
% + '%(
- (%% #
E% +" (+ + # (% %%
(& % % #
8" + '
%%" *( + # (%
%
$ ISR[0]: Channel A Transmitter Ready
(% ( (% $(' + 5G " NO
(% (" %" (
$('% 8 (% & $ (%
$& '' '' + , ( (%
'$ , (% '' 8L
$ (% % -(
" '' (% %+$ 5G (% % %( (% (
((&
$ $ (% '$ %( (% $(%$
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Input Port
Change
Delta Break
B
RXRDY/
FFULLB
TXRDYB
Counter
Ready
Delta Break
A
RXRDY/
FFULLA
TXRDYA
J ++
J J ++
J J ++
J J ++
J J ++
J J ++
J J ++
J J ++
J Table 6. IMR Bit Format
#+ % (%% '(
(
" .%
%$ ( CD ( ((
#" '%
$(
#
$((
9(3(%" $(% %3
'(
'
$((
'%(
- (
" %
%$ ( CD ( '(
'%
$(
- '
$((
(
% % $ (
/ CD% (% -(%%
&" + ' $$((
$ $
%+ $ E($ % (% '((& '
((
$ ( % + #
C.4 Interrupt Vector Register, IVR
(% -(% (% & %$ + #
;' -
(
(% '
$$ (
%'( ?$
B( (
(% $" '
% + #; (% &('&
$ %(
- $$%% + % #
(' (
(%" (
#$" #
;' -
(
(% &('& +$ ++'( B
(% (
- (
#$" #; '
%$ % -
% $.( -(%% +
#;" ( (% (
- (
?$ (%
%
$ (
Section C.6
Please note that IMR is a Write Only Registers, and can
therefore not be read by the processor.
C.3 Masked Interrupt Status Register (MISR)
'
+ # -(% (% %('& %% +
7(
- # $ # -
# J N# %O N# %O
(((
+ #
(' (
% & $(
- # (% (% ((
# '
-- C(-D $ ( '%
$(
- '
$((
%
& $ & # +"
%" +(
- $(
- #
% -(%"
( 3 (%(
% +L $ !' C(&(D
7 + # $ # '
% (
' # (% CB( &D -(% $ '
$ & '%%"
'
% + # ( %$ (
%&%
C.5 Limitations of the DUART Interrupt Structure
#
' ++$ & % % - -
(
% (
%
% '(
8 $ 8 # '
$((
%L .( $& '
$((
" $ '
-% (
*3 $((
'( 8" %($ +
C *3 $((
D *" H% #
' $% + (
E%% $ XR88C681
'( % %' % ,(& 2 ,2" '(
2 2" (
- 2 2 % $% ++ % ((& '
+(- +
% & ''
' + & + %
'
$((
% +" %% % (% (
(
% % + C 9(
3 9&D ''3(
- %'
%' % " % (% $(%$ C($D '($ $ & +E
& $(
- % -(%L
$ ''3(
- + & I ( % (%
(% %'(& '% (+ % % % 2 $ C'D N6O J ==• ,
==6• ,
/=8• ?=• , #
$% $ 8" %$ (
- (
?$
(
+'(
- +(
- (''%%%.
(''
%
===• ,
==/• ,
==/ =<=/• ,%
,
(• ,
?=• , #
$% ! + %'(
% ( ($ $($ $(%'%%(
% +
.(''%% (
+'(
- $ (
'%%(
- ' + (
$
(''%%%
(% $(%'%%(
" $($
$%'((
+ #$ #
'%%(
- $ ?$
#
'%%(
- ( -
C.6 Servicing DUART Interrupts
#
%('(
- ( 5==/= +% (
$ '-(%4 #$ $ ?$ #$ %
(%('& +$ % C#
D $ 9(3(%"
?$ % +$ % C?(-D $
B
(% (
- (
?$" ( ' = ( C(
'D $ %" ," $(
- C#
'3
$-D #: '&'
, ( $ (% (
' + *%"
$ $(
+ #
;' $ '(
+ ( (
%(' (
" (
%&% & $$((
&" ?$ -(% %
$ ' (((I (
E%%
- % ( $('% (% (% $(%'%%$ (
- $( (
Section C.6.2
C.6.1 I-Mode Interrupt Servicing
( (
#$ +(
- + #" $ % #
-
" , (
+'(
- (
- (
#$" ( +
'(
% +%"
$(
- (
%('(
-
#+ E(% (
%(' + ," (
( %%% #7 (
, ' , %
$'$ (
E%" ( ( $(
'(
+ ( (
%(' (
" $
( ' - '
'(
, (
''(% + (% ( ($(
- C#
'3
$-D %(-
& + (
'(
( ' , % ((
$ '%% + H% (
E%" ( -
(% #7 (
, ( !( CD
(
%(' (
$ ( % '%%(
-
B
(% (
- (
#$" ( ($ & (
' (
+(
," $(
- #: '&' #
;' (
+(
"
& % - '
(
#
(' (
" (% ''(%$ !
( (
#$ +(
- $ % % % (
3 C ?$D
'
$" (
$ '
$ (
?$
#
-
'% ,%
'
& % ' ( (
%('
(
" (
+'$ ( #$ (' #
,'%%(
2!
;'$#
,'%%(
-
- #$ % +$ % C#
D
$" $ ?$ % C?(-D $L (% $% % %$ & (
?$ (
+'(
- ?(- (''%%" (
#$ (
+'(
- #
(''%% $((%(
#$ $ ?$ (% '%%&
- C'D (
% #+ & (
+'(
- +(
- (''%%%. (''
%" % (
#$
=6• ,
Direct Interrupt Processing
#+ , &% C(' #
,'%%(
-D '
, % $'$ (
E%" $ %
'$ (% '
(
%'(
" , ( '
- '
%'(+(' '(
(
%&% &
XR88C681
,% & $(' (
%" (% C'(
D (%
+(!$ & , '('(& (%+
'% '(
+ (
%(' (
(%
$(
$ & $ C!
D % ,%" %' % == $ ==6• ," (%
C(
'D (
+(
(% & '$ + 99 (
%'(
%'( C2 %(
D
'(
+ (% C2 %(
D (% +(!$ &
, '('( $%(-
#+ % &% (% ' +
(
'%%(
-" .% (% %
%( + (
%(
( (
%(' (
" '
$((
' (
%'(
(
%('
(
%($% (% '(
(
&
2!4
#+ #7 (
E% (
(
" + =6• " (%
%%$" , ( ' - '
'(
1/ (
%&% & (% '(
(% +(!$ & '('(
$%(-
+ =6• , $ '
'
-$ & %
(External) Vectored Interrupt Processing
2' + % #
,'%%(
- '
(E% ( %
$ (
- $( (
+(
- %'(
%
,% & (% + + (
'%%(
&('& #
'3
$- (
(%
C#:D C#7D ( %$ - C(
'D (
+(
*%" ( !
$ C2!
D (% %$ $%'( (% + + '$(
'%%(
-L
% (
$ (" %$ (
- (
#$" (
+'$ • ,.• %
$ (
Table 7 Table 7 % %
% & + (
'%%(
- (% &$ & ' + % • ,%.• %
• P/• C
Type of Interrupt Processing
Comments
=6• ('
=6 • % !
#
E% (
%4 #7
$ #7
==• ,
2!
;'$
== • , ( % + = $(++
'$%
+ C99D (
%'(
% #
(' (
%
== , $ ( (
'
3
$- " #7" (' '
%$ C-D
C99D (
%'(
% *%
==6• ,
(' $ 2!
;'$
/=8• ('
?=• ,
#
$ 2!
;'$
?= , %% !' % ' % %
$
+ == ,
?=• ,
(' #
?= ( ' 1=8 (
%&% & (+ #7
(
E% (
(% %%$
==6 • , % C('D !
#
E%
(
%4 >6" /6" $ 66 $$((
&" (% • ,
% !' % C'D (
% % $% == • ,
/=8 • % %(
- C%3D !
#
E% (
L #)
Table 7. Summary of • P/• C and their types of Interrupt Processing (I - Mode)
(
+(
%
$ (
Table 7 (% $(%'%%$ (
$( (
+(
- %'(
%
XR88C681
C.6.1.1 8051 Microcontroller
=6 +(& + (''
% (% +'$ & #
$ '% ( (& + ((% + %
((% (
'$4
'( %( = ( #. , ,1
/ ( (%
<3 &% + = &% + Figure 3 %
% '3 $(- + =6 (''
" $ Figure 4 %
% (
+ (% $('
#7
#7
( =1.=6
( ( ( ,
#
-(%%
25
= &%
=1.=6
( =1.=6
: =1.=1
<: =6
=: =6
= &%
( ( ,
%'(
2
( ,
#. ,%
*% 92
,27
,
,
,
,1
Figure 3. Block Diagram of the 8051 Microcontroller
1
5
5
XR88C681
,
<
;
,
1
, ,
1
1=
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Figure 15. A Diagram of Numerous DUARTs Configured in an Interrupt
Daisy Chain (for Z-Mode Operation)
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IEI - Interrupt Enable Input
Note:
Once the IEO pin has toggled “low”, and the CPU has acknowledged the interrupt request and has completed the interrupt service routine, the IEO pin will remain “low” until the user
invokes the “RESET IUS” command (see Table 3). Therefore,
if the DUART is going to operate in the Z-Mode, the user must
include the “RESET IUS” Command at the very end of the
DUART interrupt service routine.
(% '((- (
(% & ( (+ (%
'
+(-$ (
?$ #+ (% (
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E%%" +
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Note:
Those interrupts which have been masked out by the IMR are
still disabled. However, if this input is at a logic “low”, then all
interrupts (whether masked or unmasked) are disabled.
Hence, IEI can act to globally disable all DUART interrupt
requests.
System Level Application of the IEI and IEO pins
Figure 15 $('% %(% + % '
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Figure 16. Timing Diagram Illustrating the Sequence of Events Occurring Between the
DUART and the CPU During an Interrupt Request/Acknowledge and Servicing
==/• ,
Additional Things to Note About Z-Mode Operation
==/ =6=/• ,
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Family of microprocessors to an I-Mode DUART,
however, additional components and design complexity
would be required in order to accomplish this '
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Table 12. Z-80 CPU Restart Instructions
Used with Vectored Interrupts
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that if the IEI input to the DUART (or Zilog peripheral
device) is “low” then the DUART (or Zilog peripheral
device) will be disabled from generating any interrupt
requests to the CPU
2!4
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Most Significant Byte
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Least Significant Byte
Bit 9
% + # -(% ((
,
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
> % (-
(+('
*(% ((
#
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Note: The LSB of the IVR is always set to “0” once read by the CPU. Interrupt Service Routines must begin at even ddresses.
Table 13. The Relationship between the Contents of the Interrupt Vector Register (of the DUART)
and the location of the Interrupt Service Routine (Z-80 CPU)
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Figure 19. Schematic of an Approach to Interface the DUART to the Z-80
CPU (for Z-Mode Operation)
<<
XR88C681
C.6.2.2 8086 Microprocessor
==/ (''%% (% / ( (''%% +'$ & #
(
Figure 20 %
% (
$(- + (% # Please note that in (- , pins 24 - 31 have some additional labels, located off to the right of the
package. These additional labels will be explained later in this text.
07
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Figure 20. Pin Out of the 8086 Microprocessor Device
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Table 14 B
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Pin Number
MN/MX = 1 (Min Mode)
MN/MX = 0 (Max Mode)
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89
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92
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Table 14. MN/MX Mode and Function of Pins 24-31 of 8086 CPU Device.
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8288 Active Output
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Table 15. 8086 Processor State/8288 Bus Controller Active Output as a function of S0, S1 and S2
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Figure 21. Schematic of the 8086 CPU Mode (Min Mode)
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Figure 22. Schematic of the 8086 CPU Mode (Max Mode)
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Please note that the DUART has been configured to
operate in the Z-Mode. Therefore, the user must account
for the IEI input to the DUART device
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27
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Figure 23. Schematic of the XR88C681 DUART Device Interfacing to a
“Min” Mode 8086 CPU Device
D. TIMING CONTROL BLOCK
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Figure 24. Block Diagram of DUART Timing Control Block
2' + ((
- *'3 (% $(%'%%$
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Table 18
Figure 25 %
% '
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D.1 Oscillator Circuit:
'&% %'( (% &('& '
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% %'( ('(
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% % $ + %
'&% %'(" $ ++% %(
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-
6
XR88C681
4 A & Q 6 4 A & Q 6 4 4 5
XR88C681
5
1/=/<8I
, %
&%
Figure 25. A Recommended Schematic for the XTAL Oscillator Circuitry
Note: The user also has an option to drive the Oscillator Circuit with a TTL input signal, in lieu of using a crystal oscillator. If this
approach is used, the TTL must be driven into the X1/CLK pin, and the X2 pin must be left floating.
#+ % $%(% % % + %(
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% ' $ '%%& '('(& ''(% (% M'(
XR88C681
5
5
G
5 (
% +
%
1/=<8I
><8<
Figure 26. A Recommended Schematic to Drive Multiple DUARTs From the Same Crystal Oscillator.
Note: The user is urged not to use the 74LS14 Schmitt Trigger Inverter in lieu of the 74HC14 device. The input of the 74LS14 tends to
load down the oscillating signal from the DUART, to the point that the Schmitt Trigger inverter can no longer change state or
respond to the oscillator signal.
6
XR88C681
D.2 Bit Rate Generator
''3 +E
'(% + *0 / (%
% %
*0 *( 0
''% ((
- + %'( ('( $ -
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+
1 '
& %$ $ '
('(
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will only generate these standard bit rates if the Oscillator
Circuit is running at 3.6864 MHz $$((
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Section D.5 '3
$(- + *0 '('(& (% %
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Figure 27
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14 5
5
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5.9:
5
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14 5
5*
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14 5
5*
Figure 27. Block Diagram of the Bit Rate Generator portion of the Timing Control Block
6
XR88C681
((
- %'% + .( '
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%( .( $" ((
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D.3 Counter/Timer
((
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Figure 28 %
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(($ & /
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5
5*
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Figure 28. A Block Diagram of the Circuitry Associated with the
Counter/Timer
Bit 6
Bit 5
Bit 4
C/T Mode
Timing Source
2!
#
#,
5 5 '3 + %(
5* 5 '3 + * %(
5.9: #
(($$ & /
(
2!
#
#,
(
2!
#
#," (($$ & /
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5.9: #
(
5.9: #
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Table 16. ACR[6:4] Bit Field Definition - C/T
61
XR88C681
(
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D.3.1 Timer Mode:
Please note that of the two C/T Modes, the Timer Mode is
the only mode which is relevant to the function of Bit Rate
Selection. 8" + '
%%" $ (% % $(%'%%$ #
( $" . '% % -
$(($ $ -
% %E % ($ (%
(' (
''3 ($% + '
% + .( -(%%" $ 9 . '
%$ % - ( -
(
$ $' /5 ''3 + & ( ($$ & *0 %E" (-(
(
- + . (%
, (
" ,1
D.3.2 COUNTER MODE
#
$" . '
% $
+
%% (
(
.9" -(
(
- '(
+ C 72D '
$
72.2G %% ( #N1O (% % '(
- '
+ / . ( '
(
'
% / $ $+ ( ! '
(
/ ( ( (% %$ & , ( C,
72D '
$ #+ ,1 (% -$ + ." ( (
(- ( (
'
(% '$" (' ( -%
# % (- % $ #N1O (% '$
. (% %$ ( C, 72D
'
$ C 72D '
$ ( '
(% (
- %% '
( % (
.9 , & '
- '
% +
9 & ( '
3% ++'
& + %%E
72
'
$ #+ % -$ (% % %$ $ %$ + !
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+E
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. E
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E
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% + -(% (
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% + 9 -(% (
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(
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&
'('(&" %(
- ( (% ./ +E
'& + . %(-
+" (
" $($ + . '
!%%$ % +%4
D.4 External Inputs
% + % + #
, (
% #, #,6 %$ % $(' !
(
% ((
*'3 % ((
- %'% + %(% $
'(% + '
% Please note that the user can
specify whether a clock signal, applied to one of these
external inputs, is a 1X or a 16X clock signal; via the Clock
Select Registers % Section D.5. $($
$(%'%%(
#
, (
% $ ( +
'(
"
% % Section E
*( J
E
'& + '$ ((
- '
1RNOR = + N9O '
% + $ 9 -(%% & '
-$ & (" ( & -(
3 ++' ! + '&' + %E . -(
%
(
%(
- % (
.9 '( +
$$%%(-- C 72D '
$ Table 1
D.5 Clock Select Registers, CSRA and CSRB
. % '
(
%& %%E
C
72D '
$ '%% . (
'
((
- '&' $ -(
((
- '&' %(
'
% %$ (
$ 9 72 2G %% (" (
#
%
-(% #N1O" (% % ' ' '&' + %E
(% % % + . % ($('
#
Figure 24" '3 ' -(%% 14
5H% '3 ' -(%% % % '
%' (' ''3 %(-
% ( $( %(% $ '(% + '
% %
% %' 1 $(++
%
$$ ( %
+ *0" .( " % !
(
% ((
- %' + %(%
6<
XR88C681
$ '(% Table 17 $ Table 18 %
(
%( '
% + % $ ''3 %'
$((
- %(% $ '(%
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
'( '3 '
%( '3 '
Table 18
Table 18
Bit 0
Table 17. Bit Format of the Clock Select Registers, CSRA and CSRB
Field
Bit Rate
CSR[7:4]
ACR[7] = 0
CSR[3:0]
ACR[7] = 1
X=0
X=1
X=0
X=1
6
>6
>6
6
1<6
1<6
1<6
1<6
6
6
1
1/
1
1/
/
<<:
/
<<:
==:
==:
6
6>/:
6>/:
<
6:
<
6:
<=
<=
<=
<=
>
=
=
>
/
/
/
/
1=<:
:
:
1=<:
(
(
(
(
2!
/5
2!
/5
2!
/5
2!
/5
2!
5
2!
5
2!
5
2!
5
Note: the b suffix denotes a binary expression. x = don’t care value.
Table 18. Bit Format of the Clock Select Registers, CSR[3:0] and CSR[7:4]
Please note that = calls for the user to specify the
following parameters4
X - The Select Extend bit
N>O % %(-
(+('
( * + !(
(& -(%
2' %( $ '(" ((
% !
$ ( '
% '$ & ((
- ( $ '
H% $ -(%
- (% (
+(
'
+
$ (
Table 3
Table 19 %(I% % '
$%" $ ( ++'
2!
$ (%
5 2!
$ (
N>O (% * + !((& -(%" $
'
%(& -$ & ((
- !!!!!!! !!!!!!! " (
$ % '"
%'(&
66
XR88C681
Register
Contents
Resulting Action
$ -(% " =/
! *0 ' 2!
$ *( 5 J $ -(% " /
! *0 ' 2!
$ *( 5 J $ -(% *" *
/
! *0 ' 2!
$ *( 5 J $ -(% *" *
*/
! *0 ' 2!
$ *( 5 J Table 19. Command Register Controls Over the Extend Bit
Note: If the user programs either nibble of the Clock Select Register (CSRn[7:4] or CSRn[3:0]) with values ranging from 016 to C16,
then the user is using the BRG as a source for timing. However, these standard bit rates (presented in Table 18) apply only if
the X1/CLK pin is driven with a 3.6864 MHz signal. If a signal with a different frequency (fo) is applied to the X1/CLK pin, then
the DUART channel is running at the following baud rate:
Actual Baud Rate =
N / *$ ;O R +
1/=/< 8I
provided that fo is between 2.0 MHz and 4.0 MHz.
Additionally, as in the case for standard baud rates, the actual frequency of the clock signal will be 16 times these values.
1X vs 16X Clock Signals
% C5 '3D $ C/5 '3D ($
- (% ! +" ( (% (
$(%'%%
( (
- $ %(-
(+('
'
C/5 ''3D
%% '($ %( $ & +' + /
B% C5 ''3D & %% %(-
% ' ( ($ (% %$ ''& '
'$ - '''& ( % '($ (
% + /5 ''3 (
( + 5 ''3 +(
- -% ( '(+& %
%
% %( $ %(%%(
%&%
% $('$ (
Figure 29 (% %&% '
%(%% + %( 5" $ ' '( 5
'( (
+ '
% (% ''3$ & ' ((
- %' + ((
- *'3 #+ (%
'( (% '( $ (% '((
- $ + %( %(" %( (% % ''3$ & (%
' ((
- %' 8
'" (% -
''3 +E
'& + '( (% !'& % % + %( (% (% ''(%('
+
%&
'
%
%(
$
'
('(
- '( $ %( -$ '( $
%( $ !'& % $ " %++('(
$(++
'% (
+E
'(% + ''3 %'%
' '( $ %( '
'
( ( % (
'((
- '%%" % %
$ (
+(
- $(%'%%(
%(
5
'(
5
5 '3
5 '3
Figure 29. Example of a Serial Data
Transmission System
9 % + %% '( (% ''3$ & %' (% %(-& +% + %("
$ '( (% & %(
- %( $ '
( ($ Figure 30 %
% %% + (%
6/
XR88C681
Figure 30. Receiver (1X) Sampling, if the RX Clock is Slightly Faster Than the TX Clock
Figure 30 %% % (
%( '(H% %(
- (
$ ' %( $ ( (% '
-(
-
#
(% '%" '( (% %(
- ' %( $ (" ( $ ( (
( ($" ( ' %''%%( $
( (% (% 3
% '( $(+ #+ (% ''(
+ '( $(+" ( & % (
%(%%(
$ '(
+ (% %( $" % $('$ (
Figure 31
'($ ' Figure 31. Illustration of an Error due to Receiver Drift
Figure 31 %% '( %(
- (- ( %(
- + $ ( ( It is interesting to note that, in
Figure 31, the Receiver sampled 01010010 # %$ $ '( $(+ '
% (% '
'( (% % %( ''3
6>
XR88C681
#
-
(" + (% C
''$D %&%
(% +
'(
+ ((
- $(++
'% 5 $
5 ' ''3 %(-
% 8" (
$ '' +
'( (+ $ (
((I *2 $(
- %( $
%(%%(
" & % (
3 '" &
'( %(
- + ( B
(%
+ (% &$" '(" $'(
+ (" ( -(
%(
- (% ( &
% (
- +' &('&" + % %
$&
%" (% % +' (% / 5==/=
$(' % ''$% /5 '( %(
- +
( +" (
% $('%" '( $'% ''
' + (" ( '( ( -(
%(
- (% ( & +' + / 8" + > /5 ''3 ($% %
%$" '( ( %% (% (
((
( ($ (
+ ( ($" $ (
'% %(
- + ( $ + %%E
$ (% (
" - $ + ''" '( ( % %( $ %
5 $ &" ' '( %
'$" ( (% ($(
+ (" '( (" + (
" -(
%(
- %( $ ( ($ (
% Figure 32 +
'( % '($ , (" ( ( ( ''
' + ( ' ( %
$'$" (% %(
- '$ (% $
%
%
($(
+ *(
*( ,($
> /5 ''3
($%
Figure 32. The Typical Sampling Pattern of Each Receiver Within the XR88C681 Device.
6=
XR88C681
< B( !!!!!!! (% % %'% C*( D
S Table 18 + (% $ %
%(
- '
(E ((-% & + %(
$ ( % & (
- $M% '(
%(
- (
" ($(
+ ( ($%" '' '' %(% (% ' (% %''%%+
+ %
%4
B %++(! $
% (
& !%%(
" $ !
$
% C$
H 'D + (
& !%%(
# ++% ($(' ''(
'( %(
(
6 B( ==/ (% % %% '( $
%( ( + 63% Table 17 $ Table 18
# ((% '( $(+ %(
- (
$M%
% &('& % (%
= ( '' A (& $ , (%
Example B: Programming the Bit Rate via the
Counter/Timer
+" (+ % %'% '( $ $ + / $L $'(
+ (" '( ( -(
%(
- $ / ! / J
61"/8I
8" ' '( %
%$ > 61/38I ''3 %" ( (
3 (% '(
% ($(
+ ( (% (
" 61/38I ''3 %(-
(% $(($$ & / -
% ''3 /8I + (
(
$ $ $ (% + ''
% % (%% %( $ '( $ /63% ( * Please note that this particular
bit rate is not offered by the BRG #
(% '% % '
$ +(
-
( < 8I 9 %(-
(
5.9: (
" (
5 (
(% + +(
-
B( / $ / 9 (% %%
%% (
. -
(
- %E +
+E
'& J < 8I.NO J 8I
5==/= $('% -(% % (
$' !
(
''3 %(-
% ( 5 /5 ''3 %(-
B
% (% -(
'(' % ( 5 /5 ''3 %(-
'3 '
-(%%" % (% $(%$ &% % /5
''3" (
$ ((- ++'% + '( $(+ % (% + $(%$ % 5 ''3 +%
+ " %% (
'(
- %( $ % (%
%&
'
% ( '( 5 ''3
1 B( N/4<O (% ( % . (
( $" $ %' ((
- %' + .
5.9: (
< B( / * (% ( %'(+& ((
%' + '( $ %( + *
( $($ + . Please note that when the
DUART is programmed in this configuration, the C/T
output represents a 16X over sample of the
Transmitted and Received data +" '(
'('(& ( $(($ 8I %E & /" M%
(3 + ''3 %(-
% (-(
(
- + *0
D.6 Application Examples using the Timing Control
Block
%4 *( J 8I./ J /63%
#
$ '(+& % + %%% ((
((
*'3" !% (
'$$
Example C: Using the External Input Ports
Example A: Using the BRG
% " (
$$((
(
- * /63% % 2! *" .% % %( $
'( $ % ( % % (%% '( $ %( $
+ 63% ( % % $
+(
-4
% $% + + %% %
$ (
2! *" - ( +(
-4
% 1/=/< 8I '&% %'( '%% 5.9: $ 5 (
%L $((
- 1/=/< 8I 9
%(-
(
5.9: (
( 5 (
+(
-
B( !!!!!! ,
+(-(
-(%
,
B( / $ -(% (% % ( %
%( *0 ' 2!
$ ( 5 J (% % % 8I %E + . ,1
1 B( =/ $ -(% (% % ( %
'( *0 ' 2!
$ ( 5 J 74 ! J $
H '
%++(! $
% (
& !%%(
6
XR88C681
2!
& '
' ,1 (
#,1 $ #,< (
%
& &(
- 8I %E (
% (
(
%
1 B(
/
incoming serial data stream is synchronous with the 1
MHz (1X) clock signal; in order to minimize bit errors
D.7 Explanation of Clock Timing Signals
(% % ( %'(+& ((
- %' + %( $ '( + ( $($
+ (
(
% #,1 $ #,<" %'(& $$((
&"
(% % $ % % (
%(-
5 %(-
% 8
'" (% $((%(
&/ + (% %(-
+" ( +
(% %
% + (% %'(
(% !(
%'(+('(
((
- *'3 % #
%" (% %M' % %' + '
%($
'
+%(
& % %%
5==/= %
% +(
%'(+('(
% (
C 292#9 82##D
Please note that if the user were to apply this example,
he/she would be responsible for ensuring that the
Symbol
Parameter
Min.
9:
5.9: 2!
8(- 9 (
+9:
5.9: &% 2!
E
'&
.( 2!
'3 8(- 9
( #, #
+
.( 2!
'3 E
'& #,
#
5
5 $ 5 2!
8(- 9 ( ( #," #,1" #,< $ #,6
+5
5 $ 5 2!
E
'& ( #,"
#,1" #,<" $ #,6
+5 /5
+5 5
/5
5
Typ.
Max.
%
1/=/<
<
8I
%
<
Units
8I
%
8I
8I
Table 20. Clock Timing (Figure 13)
7" (% !
(
+ ' + % %
tCTC - Counter/Timer External Clock High or Low
Time - IP2 Input
(% '% (( + (
%(-
" (
- ($ #, (
" + % & .(" '
%($ (- $ %%
Please note that this limit has no relationship with the
parameter tRTX, which is another spec associated with
the IP2 input.
fCTC - Counter/Timer External Clock Frequency IP2 Input
(% '% (( + (
+E
'& (
- ($ #, (
" + % & .( %' %('& %% %(-
( +E
'& < 8I '
($ #,
(
" $ %( & $$ & .(
(% %' (% $ 5" (' %
tCLK - X1/CLK (External) High or Low Time
&% $&
(' -(' - ' +
(% '('(& +" ((% 9: $ +9: $$ (
$ % $(' ( +
'(
& (% M% '% (( + ( %(-
($ - 5.9:
(
% %($ (- $ %%
fCLK - X1/CLK Crystal High or Low Time
(% %'(+(% - + +E
'(%
(%%( 5.9: (
" ( ( '&%
%'( ($ 9 (
%(-
+" %
'
& & $ < 8I (% (
/
XR88C681
% $%(% ((
- *'3 -(% %
''%% +(
- %'%4
1 $(++
%
$$ ( % ( *0
.(" (' '
'
+(-$ -
( % (' ( + *0
#
% ((
- *'3 ( % #
, (
% (' % % + !
''3 %(-
% -
'% ( %'(+(% ((% %(-
% ($ #, (
(
%" + % 2!
'3 ' + %(
$ '(%
tRTX - RXC and TXC (External) High or Low Time
- via IP2, IP3, IP4 and IP5
(% %' '% (( + ( %(-
" (
- ($ 0
,% #
,(
%"
#, #,6" + % % %( $ '( '3
%'" '
%($ (- % (% %' %
(
%( " - ( (% % (% #
(
#,
E. INPUT PORT
#
, '
%$ % -
% (
'
-$ % % + %
(
% + %'( +
'(
% '
% + (
% (% '$ '
$ & , &
$(
- #, -(% + %% + #, #,6 (-
(
%(-
#,
(
%% (
-(' CD (
#,N
O
( %((
" ((
#, -(% 9(3(%" CD (
%(-
#,
(
%% (
-(' CD (
#,N
O (
%((
" ((
#, -(%
fRTX - RXC and TXC (External) Frequency - via
IP2, IP3, IP4, and IP5
(% %' '% ((% 5 $ /5 !
%(-
% %$ ''3 %(% $
'(% #+ % (%% % 5 ''3" .%
'
& & %(-
( +E
'(% 8I
(% (
( %% (
( + % % 2!
#+ % (%% % /5 ''3" .% '
&
& %(-
( +E
'(% 8I (
' (%
%(-
(% /5 %(-
" (% ( % (
( +
63%
E.1 Alternate Functions for the Input Port
Table 17 $%'(% %% + (
(
%"
%' % ''3 (
% $ $ + '
%(-
% $
(
'$% (+ %& % - +
'(
$ + #, -(%% ( % -(' %
(
" -$%% + (% -$ +
'(
#
%&" ((
- '3 -(% % ((& -
(& & $ /
XR88C681
Input Port
Alternate Function(s)
Approach to Program Alternate Functions
#,
CTSA4 $ (
+ #,
CTSB4 $ (
+ *
#,
CT_EX4 .( 2!
'3 #
74 (% (
(% '( 9" + +
'(
#, '
-$ +
'(
% (
& %(
- N<O J $($
$(%'%%(
(% +
'(
" % % Section
G.3.
#, '
-$ +
'(
% *
74 (% (
(% '( 9 + +
'(
(
& %(
- *N<O J $($
$(%'%%(
(% +
'(
" % % Section G.3.
#, '
-$ +
'(
% !
''3 (
+ .( & %(
N/4<O J N" " O $($ $(%'%
%(
(
++' + (% '(
% % Section
D.2
#, '
% -$ +
'(
% !
''3 (
+ '( + *
& %(
- *N>4<O J N" " " O + /5
'3" *N>4<O J N" " " O + 5 '3
RXCB4 2!
'3 (
+ '(
*
#,1
TXCA: 2!
'3 (
+ %(
#,1 '
-$ +
'(
% !
''3 (
+ %( + & %
(
- N14O J N" " " O + /5 '3" N14O J N" " " O + 5 '3
#,<
RXCA4 2!
'3 (
+ '(
#,< '
-$ +
'(
% !
''3 (
+ '( + & %(
N>4<O J N" " " O + /5 '3" N>4<O J N" " " O + 5 '3
#,6
TXCB4 2!
'3 (
+ %(
*
#,6 '
-$ +
'(
% !
''3 (
+ %( + * & %
(
- *N14O J N" " " O + /5 '3" *N14O J N" " " O + 5 '3
Table 21. Listing of Alternate Function for the Input Port
E.2 Input Port Configuration Registers (IPCR)
- + % $'% ($$ + (
(
% #, - #,1 % (
% %$ & 1=<38I + *0 <3% ! / (- (- %((
% (
%(
- % ''3 ($%
!(& 6• % ( -
'%
$(
- ( (
(
'
- -(% #, ( %"
- ( & % & '
- + % % % % 6• % ( + + #, +% %% (% (
#, #,N>4<O '$ -(% (% $ & , & '
- + % '
% -$ -
(
( C#
, - + D (
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Delta IP3
Delta IP2
Delta IP1
Delta IP0
IP3
IP2
IP1
IP0
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
J 9
J 8(-
J 9
J 8(-
J 9
J 8(-
J 9
J 8(-
Table 22. Input Port Configuration Register - IPCR
/
XR88C681
#
$ C#
, - + D (
" % $ +(
-
B( ( $ ( + ( +% + (% %
$ (
Table 23 Please
note that the applicable bits, within the ACR register, are shaded.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BRG Set
Select
Counter/Timer Mode and Source
Delta IP3
Interrupt
Delta IP2
Interrupt
Delta IP1
Interrupt
Delta IP0
Interrupt
J J Table 7
J
J 7
J
J 7
J
J 7
J
J 7
Table 23. ACR- Auxiliary Control Register
(
- #N>O
Note: This “two-tiered” interrupt enabling/disabling approach, for the “Input Change of State” interrupt allows tremendous flexibility
for the user. Setting or clearing the bits in ACR[3:0] allows the user to specify exactly which Input Port pins to be enabled (or
disabled) for generating the “Input Port Change of State” interrupt. Setting or clearing IMR[7] allows the user to “globally”
enable or disable this interrupt.
-(% ," $ (
% %%
'
% + , '
% + '
% + , (
%
( + #, ( (
$(' (' + +
(
(
% !(
'$ C
- + D ( + #, '
(
% %
% + %
(
(
% +" $(
- #," (
%
% C
- + D (
" , (
$(
4
2!4
#+ ( ,N6O (% % -(' CD" (% ( % (
,6 (
(
- -(' CD 9(3(%" (+ ( ,N6O (%
% -(' CD" (% %% (
,6 (
(
- -('
CD (
- 3% -(
- ( $$ (% '$ % % ''(% (% + B
((
- (% " % (
3 + $$%% (--$
'
$%4 2 , , *# $ 92
, , *# It is important to note that when
invoking the “SET OUTPUT PORT BITS” command, the
user is setting the bits (to logic “1”) in the OPR 8"
(% '(
%% (
%(
- '%
$(
- , (
% -(' CDL $ '
&
(
%( % + , (
% $
(% (
, 9(3(%" 92 ,
, *# '
$ (% (
3$" %'(+($ (%"
((
, C'$D -(' CD 8" '%
$(
- , (
% % -(' CD
%
(
(
% --$
+(
% + '
-(
- (
(
E.3 28 Pin Packaged DUARTs
= (
'3-$ % ' ( & (
(
" #, +" & ( +
'(
% ( $(' ( (% (
(
F25 . 2!
'3 #
$ 5* 2!
'3 (
+ '( *
F. OUTPUT PORT
'
%(%% + = ( , , '
%$ % -
% '
%$ + ((
- $ %% %(-
% &
(& -(
- + $ -(%% "
* $ " * $ % '
+(-(
-(%" , B
%$ %% %(-
% , (
% $(
" (' % ( % (
( (
%'
% + ' ( ((
," +(
- ,
% ," (% CD +" % + '
, (
" +(
- , (% -(' CD
,-(
- , (% ( $(++
+ '
(
(% &(' $
% , '('(& '
%(%% + ,
(% + , '
% $ '$ (
$(($& ( (% % & $$%%(--$ C2 , ,
*#D '
$ % Table 1 ( ''
&(
-
/1
XR88C681
2/" % + '%
$(
- (" ((
, (%
'
-$
$" *%" %'(+&(
- (%" ((
,"
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F.1 Writing Data to the OPR/Output Port Pins
2!4
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Section F.1.1
#+ ( +(
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F.1.1 Set Ouput Port Bits Command
,N>4O J N" " " " " " " O
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3 C2 ,
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$ (% % % ((
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Figure 33
+ , ,(
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#
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*%" > (
,N>4O
$$%% 2
Figure 33. Illustration of the “SET OUTPUT PORT BIT” Command and its Effect
on the Output Port Register and the State of the Output Port Pins.
/<
XR88C681
% + '%
$(
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% + , (
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F.1.2 Clear Output Port Bits Command
#+ ( N>""O J N" " " " " " " O $$%% /" %(
- '
% + , -(% ( 4
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3(
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Figure 34
+ , ,(
% ,>,
#
(( , N>4O
*%" > (
, N>4O
$$%% Figure 34. Illustration of the “CLEAR OUTPUT PORT BIT” Command and its Effect
on the Output Port Register and the State of the Output Port Pins.
#
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J " %% (
'
- + ,N
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/6
XR88C681
F.2 Output Port Configuration Register (OPCR)
, (
% '
%$ % 0
,% (
%" & '
'
+(-$ %$ (
+
'(
% Table 24 (%% '(
% + ' + , (
%
Output Port
Alternate Function(s)
,
RTSA4 E%
$ + 74 (% (% '(
,
RTSB4 E%
$ + * 74 (% (% '(
,
TXCA_16X Output4 /5 %( '3 TXCA_1X Output4 5 %( '3 RXCA_1X Outpu4 5 '( '3 ,1
TXCB_1X Output4 * 5 %( '3 RXCB_1X Output4 * 5 '( '3 C/T_RDY4 .( $& + . S 74 (% (% (
%$ % .( $& ,<
RXRDY/FFULL_A Output4 '( $&. # #
$(' 74
(% (% (
+ 5G. 99F +
'(
,6
RXRDY/FFULL_B Output4 * '( $&. # #
$(' 74
(% (% (
+ 5G. 99F* +
'(
,/
TXRDY_A Output4 %( $& #
$(' (% (% (
+ 5GF +
'(
,>
TXRDY_B Output4 * %( $& #
$(' (% (% (
+ 5GF* +
'(
9 + +
'(
9 + +
'(
Table 24. Listing of the Alternate Functions for the Output Port
& + '(
% + (% , (
% %'$ & ((
- ( $ ,
( + + (% -(% +%
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OP7
OP6
OP5
OP4
OP3
OP2
J ,N>O
J 5G*
J ,N/O
J 5G
J ,N6O
J 5G.
99*
J ,N<O
J 5G.
99
J ,N1O
J . S J 5* 5
J 5* 5
J ,NO
J 5 /5
J 5 5
J 5 5
Note: OPCR only addresses the alternate functions for Output Port pins, OP7 - OP2. OP0 and OP1 assume their RTS roles if either
MR1n[7] = 1 or MR2n[5] = 1. Setting those Mode Register bits enables the RTS function. Otherwise, these two ports will only
be General Purpose Output Ports.
Table 25. Output Port Configuration Register - OPCR
//
XR88C681
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+ $ % $(%'%%% %'%
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F.3 28 Pin DIP Packaged DUARTs
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Figure 35. A Simplified Drawing Depicting the Transmit Shift Register and the Transmit Holding Register.
/>
XR88C681
B
%( (% ($ (
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+ (' '
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#
(% '%" %( (% %
$ 6/" ( =7
' = (% ''" 7(&" *(
%( #$
*(
5
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Figure 36. The Output Waveform of the Transmitter While Sending
5D16 (8-N-1 Protocol).
'
-$ -
#
E% , & %(
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% " $ *" %'(& #
(% '%" $ -
#
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G.2 Receiver (RSR and RHR
+
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#
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Figure 37. A Simplified Drawing of the Receiver Shift Register
and Receiver Holding Register
%(% % (
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'3 (% +$
Please note that if a 16X clock is selected for the receiver,
this over-sampling procedure occurs with each and every
start bit.
'( ( '
(
% $ '( '
( + '' +% (" (
( (
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+ ''H% * '( ( ''3 (& (+ -$ ( %
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XR88C681
' -(
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#
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Receiver Errors
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#
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99 '
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Section G.3
C'($ *3D '
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% -(% N>O J C*3D '' (% $$ (
8
8" + $ (% '($ $$ (
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(
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G.3 Mode Registers, MR1n and MR2n
1 '%
$(
- C *3D (
(%
E%$ (+ -$ $ +--$ (
#
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$ -(%%" % %'(+& + ' % .% (% '
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Table 26
' 5
(
% C3D '
$((
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8" $
'%
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'
$((
(
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rx RTS
Control
Rx Interrupt
Select
Error Mode
Parity Mode
Select
Select
Parity
Select Number of Bits per
Character
J 7
J G%
J!G
J 99
J'
J *'3
J B( ,(&
J ' ,(&
J 7 ,(&
J ( $
J 2
J $$
J 6
J /
J >
J =
Note: MR1n for each channel is accessed when the channel’s MR pointer points to MR1. The pointer is set to MR1n by a hardware
RESET or by a “RESET MR POINTER” command invoked via the channel’s command register. After any read or write to
MR1, the MR pointer will automatically point to MR2.
Table 26. Mode Registers - MR1A, MR1B
>
XR88C681
Bit 7
Bit 6
Bit 5
Bit 4
Channel Mode
Tx RTS
Control
CTS Enable
Tx
J 7
J 2'
J 9' 9
J 9
J 7
J G%
J 7
J G%
Bit 3
Bit 2
Bit 1
Bit 0
Bit Length
J 6/1
J /6
J /==
1 J >6
< J =1
6 J =>6
/ J 1=
> J = J 6/1
J /6
J /==
* J >6
J =1
J =>6
2 J 1=
J Table 27. Mode Registers - MR2A, MR2B
+ %% + ''% '(
- + # %(
' % C22 2 D '
$
+ % (%%$
MR1n[7] - Receiver Request to Send Control
$(
(&" E% $ (% %%$ -$
& (
3(
- C2 , , *# 7D
C92 , , *# 7D (
( 8" (+ N>O J (% %" '( ( '
-(
+ '(+('&" %(
- (% ( ( '( - (+ (% 8 (% + (% C+
'
D '
(E (% %+ (
(
- '(
2%
MR1n[4:3] - Parity Mode Select
#+ C( (&D C+' (&D (
(% -$" (& ( (% $$$ %($ ''% $ '( +% (& ''3 '($ ''%
Section H.2 + $%'((
+ ( $
(
Figure 42 %
% $(- (' (%% '(
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$ +
'(
MR1n[2] - Parity Type Select
(% ( %'% 2;27 (& (+ CB#8 ,#G
2D (% -$ $ % + +'$ (&
( (+ C 2 ,#GD $ (% -$ #
( $ ( %'% % + . +- (
(% ( % ++' (+ C7 ,#GD (% %'$ (
N<41O
MR1n[6] - Receiver Interrupt Select
(% ( %'% ( 5G %% ( 99
%% ( + '
%$ % '(( +
-
(
- #
E% ," #NO +
$ #N6O + *
MR1n[1:0] - Bits per Character Select
'% + (% %($ $ '($
(
$ +($ + '' (% $% (
'$
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MR1n[5] - Error Mode Select
(% ( '
% (
+ # %% (%
,2" 2" '($ *3 + #+ (% ( (% %
CD" (% (' '
( (
C'D 2 $ #+ (% (% (% % CD" (%
(' '
( (
C*'3D 2 $
Mode Register 2 (Channels A and B)
+ ' (% ''%%$ H%
,(
(
% " (' ''% + &
''%% H% -(% %E
C$%D C(%D $% '
- '
%
+ (
#
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& + # #
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>
XR88C681
(
- N>4/O J '% '
(
(' 2' $" (' ('& %(%
'($ $ Figure 39 %
% $(- $
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+
(
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$((
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MR2n[7:6] - Channel Mode Select
2' '
(
+ + $%
(
- N>4/O J '
+(-% '
(
7 $ #
(% $" '(
$ %( (
$
$
& Figure 38
%
% $(- $('(
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5
5
#
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'( (+ -(%
%( (+ -(%
5
-(
- (
%( 8$(
-(%
'( 8$(
-(%
=
=
*%
, $ + ,
*%
$ & ,
Figure 38. A Block Diagram Depicting Normal Mode Operation.
>
XR88C681
5
5
#
'(
( 5
%( (+ -(%
'( (+ -(%
5
-(
- (
%( 8$(
-(%
'( 8$(
-(%
=
, % ''%% %(
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Figure 39. A Block Diagram Depict Automatic Echo Mode
#
(% $4
'($ $ (% %($ '
H% 5
/ '($ 3 (% '$ % '($ ( !
($ % ( (% $'$
'( % $ %( $
$
> , '( '
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3 (% $(%$
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+ $(-
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$ +
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Local Loopback Mode
(% $ (% %'$ & %(
- N>4/O J Figure 40 (% $(- $('(
- 9' 9'3 $
(
6 ' +(
- (% ''3$ % (% %($ % '($
>1
XR88C681
;
5
'( (+ -(%
5
%( (+ -(%
5
%( 8$(
-(%
'( 8$(
-(%
=
=
*%
$ & ,
*%
, + ,
Figure 40. A Block Diagram depicting Local Loopback Mode Operation
#
(% $4
%( (% (
& '
'$ '( (
%( ''3 (% %$ + '(
1 '
H% 5
(% $ 3(
- (-
< '
H% 5
(
(% (-
$
6 %( (% $" '($ $ $
/ , %( $ '( '
('(
%
'
(
&
Remote Loopback Mode.
(% $ (% %'$ & %(
- N>4/O J Figure 41 %
% $(- $('(
- 9'3 $ (
><
XR88C681
#
'(
( 5
5
5
'( (+ -(%
%( (+ -(%
5
-(
( %( 8$(
-(%
'( 8$(
-(%
Note: The CPU has no access to the Serial Data during Remote Loopback Mode.
Figure 41. A Block Diagram Depicting Remote Loopback Mode
#
(% $4
'($ $ (% %($ '
H% 5
( + ''% (
$ 8 %($ $ &
'($ $ (% %
, $ %% '
$((
% ''3$
Figure 44 %
% $(- (% %(
$ E%
$ '
+(-(
$ +
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1 ,(& $ +(
- % (% %($ %
'($
< '( % $
MR2n[4] - Clear to Send Control
6 '($ 3 (% '$ % '($ ( ! ($ % ( (% $'$
#+ (% ( (% " '
% (
#, + " #, + * % ++' %( #+
( (% CD" %( ( ''3 % + (%
(
' ( (% ( $& %
$ '' #+
(% CD" '' (% %($ #+
(% (- -$" 5
(
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3(
% $ %(%%(
+ ! '' (%
$&$ ( -% -% (
(
( '' (% (
- %((I$ $ ++'
%(%%(
+ '' (% (%
+ (%$ (
Figure 42 $ Figure 44
MR2n[5] - Transmitter Request-to-Send Control
$(
(&" E% $ (% %%$
-$ & (
3(
- C2 , , *#
7D C92 , , *#
7D (
( " & %&%
%+ 8" %(
- N6O J % %( - ('&" (
>6
XR88C681
MR2n[3:0] - Stop Bit Length
G.4 Status Register, SRn
(% ( +($ -% $(
+ % (%
$$ ' %($ '' (
$(
+ ./ ( ( $ ./ ( (%" (
(
'
% + ./ (% '
-$ + ''
-% + /" > $ = (% 6 ( ''" % (
$(
'
-$ + ./ ( (%
% -(% ($% % ( %% 8 $ 8 '( $ %( # %"
%'(&L $ %% ($ , ( % + E(& + '(
+ $ & '(
# % (
$('% %+ (
$
%&%% $ % , ''3 $ % (+ %( (% & $. (% $& + $ + , # % (
$('% % (
$(' 8 % ''" (' (% ((
- $
& ," (% + $ (
' + '((
- & ''% ( %( $
'( # %% (
$('% '$ (
( + % -(%
#+ !
! ''3 (% -$ + %(
''3 5
" N1O J %'% % ( $(
+
( ( $ N1O J %'% $(
+ (
(% + %(%%(
'( & ''3% + 3 '
$((
'
+ +(% % ( (%" ( ( + % $ (& ( (% %$ -$%% + -$
%($ % ( - #+ '( $% %
C3D C 2D 2 (% +--$ (
%
-(%
( + % -(% % % +
& $ '(
% (+ + %
-(% $ $(%'%%(
+ ' ( +%4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Received
Break
Framing Error
Parity Error
Overrun
Error
TXEMT
TXRDY
FFULL
RXRDY
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
Table 28. Status Register - SRA, SRB
(
(% - -(' C(-D " (
!
''
SRn[7] Received Break
(% ( (
$('% I '' + -$ '' - % '($ ( % ( & %(
- # %((
(% ''($ 3 (% '($ $$((
%+% (
# (
(($ ( 5 (
% 3(
- % +
% + ( ( (% (% $+(
$ % %''%%(
$-% + (
!
! ''3
#+ C2D $ % % C*'3D $" (%
(" ' % ( (
%%$ ( C22
2 D '
$ % (
3$ %
% Table 3 Please note that if the Error Mode is “Block”
this bit, in the Status Register will remain set, for all
subsequent characters, independent of the condition of
these received characters, until the “RESET ERROR
STATUS” command has been invoked.
B
(% ( (% %" '
H% C8702 #7 *2:
D ( (
# (% % ( (
# (% % %
$ + 3 '
$((
" % $+(
$ " (%
$'$
SRn[6] Framing Error
(
- '(
+ '' (%" $ &
%%'($ (& (" '( ( ''3 + C3D
'
$((
(( +(
- % $ (& (
(% C3D '
$((
(% , ( #+ '(
$% $' C3D (% (" ( (% --$
C(-D +--(
- ''
' + 2 2
'(H% 3 $' -(' '
$' 3% -(
(
($$ + '' 8" 3 %
%(% ( $ + ! '' ( (
$ + (
$'$
#+ 2 $" + '
" % % C'D $" (% ( & (% ' + 8 (% ( ( '$ (+ 5
#+ 2 $ % % C'D $" (%
( & (% ' + 8 #+
>/
XR88C681
(% ( (% % + -(
''" ( ( '$ (+ , ( (% & $'$ (
! ''
SRn[3] Transmitter Empty (TXEMT)
(% ( (% % %( $
% # (% %
+ %(%%(
+ % % ( + '' $ (+
(% '' (
8 ((
%(%%(
(% ( (% '$ %( (%
$(%$" , (% '' 8
#+ C2D $ % % C*'3D $" (%
(" ' % ( (
%%$ ( C22
2 D '
$ % (
3$ %
% Table 3 Please note that if the Error Mode is “Block”
this bit, in the Status Register will remain set, for all
subsequent characters, independent of the condition of
these received characters, until the “RESET ERROR
STATUS” command has been invoked.
SRn[2] Transmitter Ready (TXRDY)
(% (" %" (
$('% 8 (% & $
$& '' '' + , ( (%
'$ , (% '' 8"
$ (% % '' (% %+$ 5G (% % %( (% (
((& $ $
(% % %( (% $(%$ '%
$$ (
8 ( %( (% $(%$ (
%($
SRn[5] Parity Error
(% ( (% % CB#8 ,#GD C 2
,#GD $% -$ $ (+ '%
$(
- '' (
$ # % '($
( (
'' (&
#+ 2 $ % % C'D $" (%
( & (% ' + 8 #+
(% ( (% % + -(
''" ( ( '$ (+ '($ (& (% '' (
! ''
SRn[1] FIFO Full (FFULL)
(% ( (% % '' (% %+$ + 8 $ %+ '%% ( ' +"
(" # %((
% ''($ # (% % , $% 8 #+ '' (% ((
- (
'% # (% +"
99 ( %
, $% 8
#+ C2D $ % % C*'3D $" (%
(" ' % ( (
%%$ ( C22
2 D '
$ % (
3$ %
% Table 3 Please note that if the Error Mode is “Block”
this bit, in the Status Register will remain set, for all
subsequent characters, independent of the condition of
these received characters, until the “RESET ERROR
STATUS” command has been invoked.
SRn[0] Receiver Ready (RXRDY)
(% ( (
$('% % '' % '($ $ (% ((
- (
# $ & ,
# (% % '' (% %+$ + 8 $ (% '$ ( , $% %
'' '
& %$ (
# SRn[4] Overrun Error
#+ %" (% ( (
$('% ''% (
'($ $ %" ( (% % '( + '' # (% + $ '' (%
$& (
((
- + & # %((
B
(% ''%" '' (
(% (
Please note that some of the conditions that are flagged
by the Status Register can also be programmed to
generate an Interrupt Request to the CPU. 8"
% '
$((
% +--$ & %
-(% '
-$ -
#
% '
$((
% (%$ 4
Please note that unlike the Status Register bits for FE
(Framing Error), PE (Parity Error) and RB (Received
Break), the OE (Overrun Error) indicator is always flagged
on a “Block” Error Mode basis 2 '
$((
(% +--$ '''' %(%" $ &
'$ C22 2 D '
$ (%
(
3$
N/O (
- 2
N6O ,(& 2
N<O 2
+" (+ %&% ''3(
- (% &$"
% (% '
$$ ($ ' '' &
''3(
- % -(%
>>
XR88C681
H. SPECIAL MODES OF OPERATION
H.1.1 Receiver-Controlled RTS/CTS Handshaking
H.1 RTS/CTS Handshaking
#
(% $" '( % ((& ('&
- %((
- $('
'(+('&" (% $ % '( - %(-
(+ (% 8 (% +L $" (% &" & ++'(
(
(
- '( 2% Figure 42
%
% $(- + ! (%(
- (
+ '(
$ '
+(-(
'
-$ % .
8
$%3(
-" % % + $ + '
( $('% (% %'(
( $%'( ' + (
% % % (
(
(
- .
8
$%3(
- '(+('&" % (
% 4
'(
$ . 8
$%3(
%(
$ . 8
$%3(
-
'((
- ('
99
%((
- ('
,
*
#,
5
5*
5
5*
#,
*
,
,<
,
99
5
Figure 42. Block Diagram and Timing Sequence of Two DUARTs Connected
in the Receiver-RTS Controlled Configuration
>=
XR88C681
#+ , $% C%D 8 + '((
('" 8 ( - +" $ 99
(
$(' ( -- +% #
(% '%" 99
(
$(' (% '
'$ % (
+ , #
%
% 99 --(
- +%" , $
(
(% C
-($-D +
99 % #
E% , $ %(' (% C#
D &
C((
-D N>""O J N" " " " " " " O $$%% 2/ (% '(
!'% C2 ,
, 7D $ '%% ,NO -- C(-D
$ , (
, -- CD
%E
&" (% %%$
Figure 42 %% $('%" C'((
('D $ C
%((
- ('D % $('% $ %' '% + ( (
(% ! %+
+ $ (% ! (% -(
- (-
" +
( (
-" +' C'((
- ('D % %( $ C
%((
- ('D % '( " (% !" (% %(
- + C'((
- ('D $ * + C
%((
('D
! %% ( %%(
C'((
- ('D % -$ %' N>O J ''$(
- Section G.3" (% %% (
-(
- C'((
- ('D + '( $$((
&" C
%((
- ('D % -$ %' *N<O J ''$(
- Section G.3" %( + * + C
%((
- ('D % -$ $ * (
'
#
(% !" C'((
- ('D '
% %(-
(% %(-
(% +$ $('& (
* (
+ %((
- ('
B( + C'((
- ('D (
%%$ (
+ C
%((
- ('D (%
%%$" % $ $ %(%%(
+ C
%((
- ('D C'((
- ('D (% ($
Figure 42 %% 5 (
'((
- $ +
% %%$ 8" (
(% !" (%
& '($ '' '%% 8 + C'((
- ('D + 99 (
$('
%% (% %%$ $ + C'((
('D (% ('& -$ ( '(
'
%(-
+" %(%%(
+ * + %((
- (' (%" ' -(
"
(
(($
#+ 8 + C'((
- ('D (% + % $('$ &
99 (
- -(' C(-D" (
('& -$ & ( + '(
$ +% %E
&" *
%( + C
%((
- ('D ( (%
* (
-$ $ ( ($ %(
& $ 5 + C'((
- ('D
Figure 43 %
% + $(- (%(
- -( '$ %$ (
(
(
- '(
$ . 8
$%3(
- $
>
XR88C681
'((
- ('
N>O J %((
- ('
*N>O J %% B( ) $$%% 2
(% (
3% C2 ,
, *# 7D $ %%
, (
" , -('
CD
7
#%
99
%%$T
7
G%
(% ('&
7-$ & '(
$ '(
#%
99
7-$T
G%
Figure 43. A Flow Diagram Depicting an Algorithm That Could be Used to Apply
the Receiver-Controlled RTS/CTS Handshaking Mode
H.1.2 Transmitter-Controlled RTS/CTS Handshaking
#
(% $" %( % ((& - '((
- (' '(+('&" (%
$ % %( -& %(-
" ( ($ + &(
- 8 $ =
XR88C681
%((
- ('
'((
- ('
,
#,
(
#,
,1
5
5*
5GF
,>
,
5GF
5
Figure 44. Block Diagram and Timing Sequence of Two DUARTs Connected
in the Transmitter-RTS Controlled Configuration.
=
XR88C681
Figure 44 %% $('%" $
C
%((
- ('D $ " C'((
- ('D
(% ! %% ( %%(
C
%( ('D % -$ %' N6O J " (' %% (
-(
- C
%((
- ('D + %( (%
! + %%% C
%((
- ('D
% -$ %' N<O J ''$(
Section G.3" %( + + C
%((
- ('D % -$ $ (
'
C
%((
- ('D $ ( %( $ C'((
- ('D
' %( % ($ (% 8
$ + $" ( ( - " ( C
%( D + B
C
%((
- ('D (% --$ C(-D" #,
(
(% % --$ C(-D" & -
(
C#
- + D (
E% , B( #,NO J " (3& #
('
(
$ CB(D N>"" O J N" " " " " " "
O $$%% / #
(% %" #
(' (
$ (
3 C92 ,
, *# 7D" $ (
'%% -- ,1
C(-D (% $ (
- (
+ C
%((
- ('D $ (
(( %(%%(
+ $ + + C
%((
- ('D
#
'% + C'((
- ('D" #, (
%
-$ -
C#
, - +
D (
E% , +( + #
(' (
% (% (
%' (+ #,
(
'
- $ #,NO J " , $
C(D N>"" O J N" " " " " " " O $$%% 2/ #
(% %" #
(' (
$ (
3 C2 , , *#
7D" $ (
'%% -- ,N1O -('
C(-D $ , (
" ,1" -('
CD (% $" (
" %% (
+ Figure 45 %
% (- (' $('% -( '$ %$ (
%(
. 8
$%3(
- $
Please note that the shaded block pertain to occurrences
within the “Receiving Device” B% CB(D '3
(
(
((
C
%((
- ('D
=
XR88C681
0
C#
, - + D
#
#, (
'((
- ('
2 B( $$%% 2
0092 ,1 F ,#7
C9BD
B( = $$%% 2
P #7, # 22
%(%%(
(% ($
7
#%
#, J T
G%
#%
52
%%$
T
7
G%
P (% ('& 7-$ &
'( $ '(
, --% C8(-D
0092 ,1 F ,#7
C8#08D
B( = $$%% #7, # 7202
%(%%(
(% $(%$
G%
#%
5G
7-$T
7
Figure 45. A Flow Diagram depicting an Algorithm that could be used to Realize the
Transmitter-Controlled RTS/CTS Handshaking Mode
H.2 Multi-drop (8051 9 bit) Mode
H.2.1 Concept of Multi-Drop Mode
2' %( '
+ '
'
+(-$ (
3 $ %+ + ($ ('%% ('(
% (% %'(
( +(% %
'
' + ( $ +$%" +
'(
$ '$ + (
- (
( $ (% $(%'%%$ (
Section H.2.1
(% $ (% '( ( %( C7(
( $D +
=6 +(& (''% #
(% $ + (
C% %(
D" '
'$ !( + 6/ %
%(
(% %%(" % $('$ (
Figure 46
=1
XR88C681
% ('
5
5
5
5
5
('%
Figure 46. An Illustration Depicting the Concept of Multi-Drop Mode
9*
* .
= *( '
$$%%. *(
Figure 47. Bit Format of Character Data Being Transmitted in the Multi-Drop Mode
C% (
D '
('% C
(
%D & %((
- '' &('& & (
C$$%%.D ( +- $$ $ + '' (% &('& %% (
(
(% + (
%($ + & '' &" % %
$ (
Figure 47
B
C% (
D % %( '3 +
$ + % %%" ( +(% %
$% $$%%
& ($
(+(% C- D $$%% &
$(++% + $ & (
(
( (% CD (
$$%% *& $ CD (
*&
=<
XR88C681
$$%% *&" " (
% C%D % ' '
!(
'($ & % (+ ( (
$(($ % $(' (% (
- $$%%$ '(
+ $$%%$ % ( $ $ ( +
'(
+ $ &% +% %% $$%%$ ( % ( '(% $(%$"
$ ( '
(
(-
$ &% +%
& ( (
$ -(
! $$%% &
(% %($ & C% ('D
-$ + $ (%" $$%%.
. +- (L $ -$ , ( - .
J (
$('% '' (% $" ( . J ($
(+(% ( % $$%%
Transmitter Operation During Multi-Drop Mode
%., '
% % + %($
'' & -(
- NO + '
(
$(
- $ (% (
8 (
- NO J
CD %% (
. J CD $ %(
- NO J CD %% (
. J CD Figure 48 %
% '$ + $(-
+ %((
- ''% $$%% " ( (
( $
H.2.2 DUART Multi-Drop Operation
-(
'
" ((
(% -$ (
( $ & %(
- N<41O J C" D #
(%
$" %($ '' '
%(%% + ("
#
3 C22 ,#72D '
$
B( ! (
$ -(%
. *( CD
B( !!!!!!! -(%
. *( CD
B( !!!!!!! -(%
%( '
('
B( ' 8
%( $$%%
' ('
B( ' 8
'%
B( '(
('T
#
3 C22 ,#72D '
$
B( ! (
$ -(%
G%
7
Figure 48. A Flow Diargam Depicting a Procedure That Can Be Used to
Transmit Characters in the Multi-Drop Mode
=6
XR88C681
'($ ''% ''%%( , & $(
8 % + . +- ( (% ( N6O" % -(% ( & %$ (
$('
C,(& 2D +" (
'
M
'(
( '(
' ''" , %$ '
(
(
N6O (
$ (+& ( (% CD ''%
Receiver Operation During Multi-Drop Mode
B
'
% -$ (
( $" $ '( % $(%$ &(' '
+(-(
" '( ( $ ''
(
8 $ % 5G (
$(' $.
(
(+ . ( (% CD $$%% +- 8" '' ( $(%'$$ (+ (% . ( (% CD +-
+" (
%
% 5G (
$('" ,
%$ $ '($ '' $ $(
(+
$$%% ( %
% '% + , #+
$$%%% $ '" (
$('(
- ( (% -
" , %$ '(" (
(
+ %%E
'3% + $
' C- ,D $'% $$%% ''"
N6O JCD" ( %$ ' (% $$%% ( (% #+ $$%%% $ '" (% , (% (
$$ '((
+ ! '3 + $" $ %$ $(% '( Figure 49 %
% +
$(- $('(
- '
$$ '$ +
$(
- '($ ''% ( (
(
$
' '( % $ '( (
( '%%$ % (
7 (
%
7& '($
$$%% '
, $$%%
T
'( (% (%$
(% $$
(
( $
N<41O J N" O
7
M' '
'( (
% (%$
G%
7
2
'(
B( ! ( $ -(%
8%
5G #
$('
%%$
T
$ (
'
+ 8
'3 N6O
G%
$ (
$$%%
' + 8
#% 7 ' '
N6O J T
7
G%
Figure 49. A Flow Diagram Depicting a Procedure That Can Be Used to Receive
Characters in the Multi-Drop Mode.
=/
XR88C681
(
?$
(% (% $ '3 + #:" #2#" $ #2 (
%
H.3 Standby Mode
& '$ (
%
$& $ '
% (% (
(% E($ %" ( (
C#;2 ,2#7D
$ C2 7*G 2D '
$ (%%$ (
'
$ -(% $(%% ''3% $(' !' + '&% %'(" ('
%(-
(+('
& $'% (
- '
#
(% $
& +
'(
% (' ( ''& $(
(
" ((
- $ C2
#;2 2D '
$ " % (
3$ (
$ -(%" %% $(' (
((
6• % %(
- %(%
$ '(% $ ((
- (
# #
%3
-(% + -(
- (
$& $ (%
'
$$ & %(% (
% +
(
- -
$ '( %$ -$ +
C2 #;2 2D '
$ %(
' -(%
'
% -
$ (
% $(
- %
$& $ '( (
'
% %$ (
$ %
+ $ %3(
- +
'(
%
(% (% $ '3 + & (
%
J. PROGRAMMING
(
+ (% -$ & ((
- '
$% (
( -(%%" ( (
+$'3 (% ($$ & %% -(%% (' '
$
& , -(% $$%%(
- (% %
(
$ % '% '
% + " #"
#" ," $ , -(%% $ (
(((I% #; / (
- (
" ' %$ !'(%$ (+ '
% + '
-(%% '
-$" %(
'
'(
'
-% & % (
( (
2!4
-(
- + (% '' ( $ (%
(
- '($ & % (
'(
+ %
'' #
-
" '
-% -(%% (' '
'( %( (
%$ $ &
( %( '( $(%$" $ '(
'
-% %$ $ & . (%
%$
I. COMMENTS ABOUT THE XR88C681 IN 28 PIN
DIP PACKAGE
' + (% $ % $(%'%%$ +% (' ( % (' '3-$ (
< (
#, << (
,9 8" '% + $'$ + (
% % (
= (
'3- $ +(
- +%
$" '
$" ''3 %'" $ %% -(%% $('$ + ' '
($ (
$
$
(
Table 29 - Table 41 %(I% (
%%(-
% + ' -(%
REGISTER SUMMARY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Rx RTS
Control
Rx Int Select
Error Mode
Parity Mode
Select
Parity
Select
Number of Bits/Char.
J 7
J G%
J5G
J 99
J J *'3
J 2
J $$
J 6
J /
J >
J =
J B( ,(&
J ' ,(&
J 7 ,(&
J ( $
Table 29. Mode Registers 1: MR1A, MR1B
=>
Bit 1
Bit 0
XR88C681
Bit 7
Bit 6
Bit 5
Bit 4
Channel Mode
Tx RTS
Control
CTS Enable
Tx
J 7
J 2'
J 9' 9
J 9
J 7
J G%
J 7
J G%
Bit 3
Bit 2
Bit 1
Bit 0
Stop Bit Length
J 6/1
J /6
J /==
1 J >6
< J =1
6 J =>6
/ J 1=
> J = J 6/1
J /6
J /==
* J >6
J =1
J =>6
2 J 1=
J Table 30. Mode Register 2: MR2A, MR2B
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Receiver Clock Select
Transmitter Clock Select
Table 9
Table 9
Bit 0
Table 31. Clock Select Registers: CSRA, CSRB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Miscellaneous Commands
Enable/Disable Tx
Enable/Disable Rx
! (
Section B.2
J 7 -
J 2
!
J (% !
J 7 $
7 %
J 7 -
J 2
!
J (% !
J 7 $
7 %
Table 32. Command Registers: CRA, CRB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Received
Break
Framing
Error
Parity Error
Overrun
Error
TXEMT
TXRDY
FFULL
RXRDY
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
Bit 1
Bit 0
Table 33. Status Registers: SRA, SRB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
OP7
OP6
OP5
OP4
OP3
OP2
J,N>O
J5G*
J,N/O
J5G
J,N6O
J5G.
99*
J,N<O
J5G.
99
J ,N1O
J . S J 5* 5
J 5* 5
J ,NO
J 5 /5
J 5 5
J 5 5
Table 34. Output Port Configuration Register: OPCR
==
XR88C681
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BRG Set
Select
Counter/Timer #1 Mode and Source
Delta IP3
Interrupt
Delta IP2
Interrupt
Delta IP1
Interrupt
Delta IP0
Interrupt
J J Table 7
J
J 7
J
J 7
J
J 7
J
J 7
Table 35. Auxiliary Control Register: ACR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Delta IP3
Delta IP2
Delta IP1
Delta IP0
IP3
IP2
IP1
IP0
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
J 9
J 8(-
J 9
J 8(-
J 9
J 8(-
J 9
J 8(-
Table 36. Input Port Configuration Register , IPCR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Input Port
Change
Delta Break
B
RXRDY/
FFULLB
TXRDYB
Counter #1
Ready
Delta Break
A
RXRDY/
FFULLA
TXRDYA
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
J 7
J G%
Table 37. Interrupt Status Register, ISR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Input Port
Change
Delta Break
B
RXRDY/
FFULLB
TXRDYB
Counter #1
Ready
Delta Break
A
RXRDY/
FFULLA
TXRDYA
J ++
J J ++
J J ++
J J ++
J ++
J J J ++
J J ++
J ++
J J Table 38. Interrupt Mask Register, IMR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
.6
.<
.1
.
.
.
.
.=
Table 39. Counter/Timer Upper Byte Register, CTUR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
.>
./
.6
.<
.1
.
.
.
Table 40. Counter/Timer Lower Byte Register, CTLR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
#;>
#;/
#;6
#;<
#;1
#;
#;
#;
Table 41. Interrupt Vector Register: IVR
=
XR88C681
K. TIMING DIAGRAMS
;
<;
=;
;
% 9%
=;
Figure 50. Input and Output Levels for Timing Measurements
Note: AC testing inputs are driven at 0.4V for a logic “0” and 2.4V for a logic “1” except for -40 to 85(C and -55 to 125(C, logic “1” shall
be 2.6V. Timing measurements are made at 0.8V for a logic “0” and 2.0V for a logic “1”.
22
2
Figure 51. Reset Timing
XR88C681
1
8
8
B
B
>
$
9
7
;9#
;9#
9
B
B
>
B(
8
;9#
Figure 52. XR88C681 Read and Write Cycle Timing
XR88C681
#7
#8
#:
#
B
2#
>
9
7
;9#
;2
9
#2#
#2
#
#
2
22 #
7
Figure 53. XR88C681 Z Mode Interrupt Cycle Timing
XR88C681
,
,8
#, #,/
B , ,>
72B 9 ,
Figure 54. Port Timing
B
#
#
Figure 55. Interrupt Timing
1
XR88C681
4
4
4
4
A & Q 6 A & Q 6 4 6 A & Q 6 4 6 A & Q 6 5
5
XR88C681
XR88C681
5
1/=/<8I
1/=/<8I
, %
&%
5
, %
&%
9:
5.9:
. 9:
5
5
5
9:
5
Figure 56. Clock Timing
<
XR88C681
*( (
/ '3%
5
#
5
5
5
5 Figure 57. Transmitter Timing
5
5 #
5
58
5
Figure 58. Receiver Timing
6
XR88C681
44 LEAD PLASTIC LEADED CHIP CARRIER
(PLCC)
Rev. 1.00
C
D
D
(
- ,
45 x H1
45 x H2
A2
<<
B1
D
D1
B D
2
D3
e
R
D3
A1
A
INCHES
SYMBOL
MILLIMETERS
MAX
MIN
MAX
/6
=
<
<6>
16
UUU
6
UUU
*
1
11
61
*
/
1
//
=
=
1
1
/=6
/6
><
>/6
/6
/6/
/6
///
6
/1
<
/
1
MIN
6 &
6 *
> &
> *
8
<
6/
>
<
8
<
<=
>
6
<6
/<
<
Note: The control dimension is the inch column
/
XR88C681
40 LEAD CERAMIC DUAL-IN-LINE
(600 MIL CDIP)
Rev. 1.00
<
E
E1
D
A1
Base
Plane
Seating
Plane
A
L
c
e
B
B1
INCHES
SYMBOL
MILLIMETERS
MIN
MAX
MIN
6
6<
MAX
6>
6
>6
1=
*
<
/
1/
//
*
<6
/6
<
/6
'
=
=
</
666
61
2
66
/
1>
6<
2
/ *
6< *
*
6< *
9
6
1=
6=
6
6
Note: The control dimension is the inch column
>
XR88C681
40 LEAD PLASTIC DUAL-IN-LINE
(600 MIL PDIP)
Rev. 1.00
<
E1
E
D
A2
Seating
Plane
A
L
A1
C
B
B1
e
INCHES
SYMBOL
eA
eB
MILLIMETERS
MIN
MAX
MIN
MAX
/
6
</
/16
6
>
1=
>=
6
6
1=
<6
*
<
<
1/
6/
*
1
>
>/
>=
=
<
1=
=
6
6
61
2
/
/6
6<
6==
2
<=6
6=
1
<>1
*
6< *
/ *
6< *
*
/
>
6<
>>=
9
6
6=
6
6
Note: The control dimension is the inch column
=
XR88C681
7#2
25 (
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