SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES020F – JULY 1995 – REVISED MAY 2002 D D D D DGG OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus Family Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE description This 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE 27 A buffered output-enable (OE) input can be used 23 26 to place the eight outputs in either a normal logic 24 25 state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. 22 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. ORDERING INFORMATION TOP-SIDE MARKING Tube SN74ALVCH16373DL Tape and reel SN74ALVCH16373DLR TSSOP – DGG Tape and reel SN74ALVCH16373DGGR ALVCH16373 VFBGA – GQL Tape and reel SN74ALVCH16373KR VH373 SSOP – DL –40°C 40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA ALVCH16373 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES020F – JULY 1995 – REVISED MAY 2002 GQL PACKAGE (TOP VIEW) 1 2 3 4 5 terminal assignments 6 1 2 3 4 5 6 A A 1OE NC NC NC NC 1LE B B 1Q2 1Q1 GND GND 1D1 1D2 C C 1Q4 1Q3 D 1Q5 VCC GND 1D4 1Q6 VCC GND 1D3 D 1D5 1D6 E 1Q8 1Q7 1D7 1D8 F 2Q1 2Q2 2D2 2D1 G 2Q3 2Q4 GND GND 2D4 2D3 H 2Q5 2Q6 2Q8 VCC GND 2D5 2Q7 VCC GND 2D6 J 2D8 2D7 K 2OE NC NC NC NC 2LE E F G H J K NC – No internal connection FUNCTION TABLE (each 8-bit section) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) 1OE 1LE 1D1 1 2OE 48 47 2LE C1 2 1D 1Q1 24 25 C1 2D1 36 To Seven Other Channels To Seven Other Channels Pin numbers shown are for the DGG and DL packages. 2 POST OFFICE BOX 655303 1D • DALLAS, TEXAS 75265 13 2Q1 SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES020F – JULY 1995 – REVISED MAY 2002 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL VI VO IOH Low-level input voltage MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 0 0 IOL Low level output current Low-level ∆t/∆v Input transition rise or fall rate VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V V 0.8 Output voltage VCC = 2.7 V VCC = 3 V V 1.7 Input voltage High level output current High-level V 0.65 × VCC VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V VCC = 2.3 V UNIT VCC VCC V V –4 –12 –12 mA –24 4 12 12 mA 24 10 ns/V TA Operating free-air temperature –40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES020F – JULY 1995 – REVISED MAY 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA IOZ ICC ∆ICC Ci Data inputs 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 UNIT V 0.2 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.6 V ±5 VI = 0.58 V VI = 1.07 V 1.65 V 25 1.65 V –25 VI = 0.7 V VI = 1.7 V 2.3 V 45 2.3 V –45 VI = 0.8 V VI = 2 V 3V 75 3V –75 V µA µA VI = 0 to 3.6 V‡ 3.6 V ±500 VO = VCC or GND VI = VCC or GND, 3.6 V ±10 µA 3.6 V 40 µA 750 µA One input at VCC – 0.6 V, Control inputs 2.3 V 0.45 IOL = 24 mA VI = VCC or GND II(hold) ( ) MAX VCC–0.2 1.2 1.65 V IOL = 12 mA II TYP† 1.65 V to 3.6 V IOL = 4 mA IOL = 6 mA VOL MIN IO = 0 Other inputs at VCC or GND 3 V to 3.6 V VI = VCC or GND 3 33V 3.3 pF 6 Co Outputs VO = VCC or GND 3.3 V 7 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.8 V tw tsu MIN § Pulse duration, LE high or low MAX VCC = 2.5 V ± 0.2 V MIN 3.3 MAX MIN UNIT MAX 3.3 ns 1 1 1.1 ns 1.5 1.7 1.4 ns th Hold time, data after LE↓ § This information was not available at the time of publication. § 4 • DALLAS, TEXAS 75265 POST OFFICE BOX 655303 MIN VCC = 3.3 V ± 0.3 V 3.3 § Setup time, data before LE↓ MAX VCC = 2.7 V SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES020F – JULY 1995 – REVISED MAY 2002 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) PARAMETER D tpd d MIN MAX 1 † Q OE VCC = 2.5 V ± 0.2 V TYP † Q LE ten VCC = 1.8 V TO (OUTPUT) tdis Q OE † This information was not available at the time of publication. VCC = 2.7 V MIN VCC = 3.3 V ± 0.3 V UNIT MAX MIN MAX 4.5 4.3 1.1 3.6 1 4.9 4.6 1 3.9 † 1 6 5.7 1 4.7 ns † 1.2 5.1 4.5 1.4 4.1 ns ns operating characteristics, TA = 25°C PARAMETER Cpd d Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled CL = 50 pF, pF VCC = 1.8 V TYP † f = 10 MHz † VCC = 2.5 V TYP VCC = 3.3 V TYP 19 22 4 5 UNIT pF † This information was not available at the time of publication. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES020F – JULY 1995 – REVISED MAY 2002 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test VLOAD Open S1 GND CL (see Note A) RL TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUT VCC 1.8 V 2.5 V ± 0.2 V 2.7 V 3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V tw VI Timing Input VM VM VM 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VM VM 0V tPLH Output Control (low-level enabling) VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLZ VLOAD/2 VM tPZH tPHL VOH VM VI VM tPZL VI Input VOLTAGE WAVEFORMS PULSE DURATION th VI Data Input VM 0V 0V tsu Output VI VM Input VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VOH VM VOH – V∆ 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2002, Texas Instruments Incorporated