TI SN54HC374J

SN54HC374, SN74HC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS141C – DECEMBER 1982 – REVISED JULY 1998
D
D
D
D
SN54HC374 . . . J OR W PACKAGE
SN74HC374 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
Eight D-Type Flip-Flops in a Single Package
High-Current 3-State True Outputs Can
Drive up to 15 LSTTL Loads
Full Parallel Access for Loading
Package Options Include Plastic Shrink
Small-Outline (DB), Small-Outline (DW),
Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) DIPs
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
description
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
1D
1Q
OE
VCC
8Q
SN54HC374 . . . FK PACKAGE
(TOP VIEW)
The eight flip-flops of the ’HC374 devices are
edge-triggered D-type flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs
are set to the logic levels that were set up at the
data (D) inputs.
2D
2Q
3Q
3D
4D
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
CLK
5Q
5D
An output-enable (OE) input places the eight
outputs in either a normal logic state (high or low
logic levels) or the high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive
bus lines without interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54HC374 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74HC374 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54HC374, SN74HC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS141C – DECEMBER 1982 – REVISED JULY 1998
logic symbol†
1
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
11
3
EN
C1
2
1D
4
5
7
6
8
9
13
12
14
15
17
16
18
19
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE
CLK
1
11
C1
1D
3
1D
2
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
2
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SN54HC374, SN74HC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS141C – DECEMBER 1982 – REVISED JULY 1998
recommended operating conditions (see Note 3)
SN54HC374
VCC
VIH
Supply voltage
VCC = 2 V
VCC = 4.5 V
High-level input voltage
VCC = 6 V
VCC = 2 V
VIL
VI
VO
tt
Low-level input voltage
NOM
MAX
2
5
6
Input voltage
Output voltage
VCC = 2 V
VCC = 4.5 V
MIN
NOM
MAX
2
5
6
1.5
1.5
3.15
3.15
4.2
VCC = 4.5 V
VCC = 6 V
Input transition (rise and fall) time
SN74HC374
MIN
UNIT
V
V
4.2
0
0.5
0
0.5
0
1.35
0
1.35
0
1.8
0
1.8
0
0
0
VCC
VCC
0
VCC
VCC
0
1000
0
1000
0
500
0
500
V
V
V
ns
VCC = 6 V
0
400
0
400
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VOL
VI = VCC or 0,
MIN
MAX
SN74HC374
MIN
MAX
UNIT
1.998
1.9
1.9
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
IOH = –6 mA
IOH = –7.8 mA
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
5.34
2V
0.002
0.1
0.1
0.1
IOL = 20 µA
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
6V
±0.01
±0.5
±10
±5
µA
8
160
80
µA
10
10
10
pF
IOL = 6 mA
IOL = 7.8 mA
ICC
Ci
SN54HC374
1.9
VI = VIH or VIL
VI = VCC or 0
VO = VCC or 0
TA = 25°C
TYP
MAX
2V
VI = VIH or VIL
II
IOZ
MIN
4.5 V
IOH = –20 µA
VOH
VCC
IO = 0
6V
2 V to 6 V
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3
• DALLAS, TEXAS 75265
V
V
3
SN54HC374, SN74HC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS141C – DECEMBER 1982 – REVISED JULY 1998
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
fclock
Clock frequency
tw
Pulse duration, CLK high or low
Setup time, data before CLK↑
↑
tsu
Hold time, data after CLK↑
↑
th
TA = 25°C
MIN
MAX
SN54HC374
MIN
MAX
SN74HC374
MIN
MAX
2V
6
4
5
4.5 V
30
20
24
6V
35
24
28
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
10
13
12
4.5 V
5
5
5
6V
5
5
5
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
ten
tdis
tt
4
CLK
OE
OE
Any Q
Any Q
Any Q
Any Q
VCC
TA = 25°C
MIN
TYP
MAX
SN54HC374
MIN
MAX
SN74HC374
MIN
2V
6
12
4
5
4.5 V
30
60
20
24
6V
35
70
24
MAX
MHz
28
2V
63
180
270
225
4.5 V
17
36
54
45
6V
15
31
46
38
2V
60
150
225
190
4.5 V
16
30
45
38
6V
14
26
38
32
2V
36
150
225
190
4.5 V
17
30
45
38
6V
16
26
38
32
2V
28
60
90
75
4.5 V
8
12
18
15
6V
6
10
15
13
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UNIT
ns
ns
ns
ns
SN54HC374, SN74HC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS141C – DECEMBER 1982 – REVISED JULY 1998
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
ten
tt
CLK
OE
Any Q
Any Q
Any Q
VCC
MIN
TA = 25°C
TYP
MAX
SN54HC374
MIN
MAX
SN74HC374
MIN
2V
6
12
5
4.5 V
30
60
24
6V
35
70
28
MAX
UNIT
MHz
2V
80
230
345
290
4.5 V
22
46
69
58
6V
19
39
58
49
2V
70
200
300
250
4.5 V
25
40
60
50
6V
22
34
51
43
2V
45
210
315
265
4.5 V
17
42
63
53
6V
13
36
53
45
ns
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance per flip-flop
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TEST CONDITIONS
TYP
UNIT
No load
100
pF
5
SN54HC374, SN74HC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS141C – DECEMBER 1982 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
VCC
From Output
Under Test
CL
(see Note A)
PARAMETER
S1
Test
Point
tPZH
ten
RL
1 kΩ
tPZL
tPHZ
tdis
S2
RL
Data
Input
VCC
50%
10%
50%
50%
0V
In-Phase
Output
50%
10%
tPHL
90%
90%
tr
tPHL
Out-ofPhase
Output
90%
tf
Closed
Open
Open
Open
VCC
th
90%
90%
VCC
50%
10% 0 V
tf
50%
10%
Output
Control
(Low-Level
Enabling)
VCC
50%
50%
0V
tPZL
VOH
50%
10% V
OL
tf
Output
Waveform 1
(See Note B)
tPLZ
≈ VCC
50%
≈ VCC
10%
VOL
tPZH
tPLH
50%
10%
Closed
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VCC
tPLH
Open
tr
VOLTAGE WAVEFORMS
PULSE DURATIONS
50%
Open
0V
0V
Input
Closed
tsu
0V
50%
Closed
50%
50%
tw
Low-Level
Pulse
Open
50 pF
or
150 pF
––
Reference
Input
VCC
S2
50 pF
1 kΩ
LOAD CIRCUIT
50%
S1
tPLZ
tpd or tt
High-Level
Pulse
CL
50 pF
or
150 pF
90%
VOH
VOL
Output
Waveform 2
(See Note B)
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
90%
VOH
≈0V
tPHZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured when the input duty cycle is 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
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Copyright  1998, Texas Instruments Incorporated