SN74AHCT1G00 SINGLE 2-INPUT POSITIVE-NAND GATE SCLS316M – MARCH 1996 – REVISED JANUARY 2003 D D D D D D D DBV OR DCK PACKAGE (TOP VIEW) Operating Range of 4.5 V to 5.5 V Max tpd of 7.1 ns at 5 V Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 5 V Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) A B GND 1 5 VCC 4 Y 2 3 description/ordering information The SN74AHCT1G00 performs the Boolean function Y = A • B or Y = A + B in positive logic. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA SOT (SOT (SOT-23) 23) – DBV –40°C 40°C to 85°C (SC 70) – DCK SOT (SC-70) Reel of 3000 SN74AHCT1G00DBVR Reel of 250 SN74AHCT1G00DBVT Reel of 3000 SN74AHCT1G00DCKR Reel of 250 SN74AHCT1G00DCKT TOP-SIDE MARKING‡ B00 B00_ BA BA_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ The actual top-side marking has one additional character that designates the assembly/test site. FUNCTION TABLE INPUTS OUTPUT Y A B H H L L X H X L H logic diagram (positive logic) 1 A 4 2 Y B Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74AHCT1G00 SINGLE 2-INPUT POSITIVE-NAND GATE SCLS316M – MARCH 1996 – REVISED JANUARY 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage VO IOH Output voltage IOL ∆t/∆v Low-level output current MIN MAX 4.5 5.5 High-level input voltage 2 UNIT V V 0.8 V 0 5.5 V 0 VCC –8 High-level output current Input transition rise or fall rate V mA 8 mA 20 ns/V TA Operating free-air temperature –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH IOH = –50 mA IOH = –8 mA 45V 4.5 VOL IOL = 50 mA IOL = 8 mA 45V 4.5 II ICC VI = 5.5 V or GND VI = VCC or GND, ∆ICC‡ Ci One input at 3.4 V, 4.4 TA = 25°C TYP MAX MIN 4.5 4.4 3.94 POST OFFICE BOX 655303 UNIT V 3.8 0.1 0.1 0.36 0.44 V mA ±0.1 ±1 1 10 mA 5.5 V 1.35 1.5 mA 10 pF VI = VCC or GND 5V 2 10 ‡ This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC. 2 MAX 5.5 V 0 V to 5.5 V IO = 0 Other inputs at VCC or GND MIN • DALLAS, TEXAS 75265 SN74AHCT1G00 SINGLE 2-INPUT POSITIVE-NAND GATE SCLS316M – MARCH 1996 – REVISED JANUARY 2003 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A or B Y CL = 15 pF tPLH tPHL A or B Y CL = 50 pF MIN TA = 25°C TYP MAX MIN MAX 5 6.2 1 7.1 5 6.2 1 7.1 5.5 7.9 1 9 5.5 7.9 1 9 UNIT ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP UNIT 10.5 pF 3 SN74AHCT1G00 SINGLE 2-INPUT POSITIVE-NAND GATE SCLS316M – MARCH 1996 – REVISED JANUARY 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point RL = 1 kΩ From Output Under Test VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL 1.5 V tPLZ ≈VCC 50% VCC Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPZL tPZH tPLH 50% VCC 3V Output Control VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDS025C – FEBRUARY 1997 – REVISED FEBRUARY 2002 DCK (R-PDSO-G5) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 5 0,10 M 4 1,40 1,10 1 0,13 NOM 2,40 1,80 3 Gage Plane 2,15 1,85 0,15 0°–8° 0,46 0,26 Seating Plane 1,10 0,80 0,10 0,00 0,10 4093553-2/D 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. 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