SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
D Available in the Texas Instruments
D
D
D
D
D
D
D
DCT OR DCU PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
1.65-V to 5.5-V VCC Operation
High On-Off Output Voltage Ratio
High Degree of Linearity
High Speed, Typically 0.5 ns (VCC = 3 V,
CL = 50 pF)
Low On-State Resistance, Typically ≈6.5 Ω
(VCC = 4.5 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
COM
INH
GND
GND
1
8
2
7
3
6
4
5
VCC
Y1
Y2
A
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
GND
GND
INH
COM
4 5
3 6
2 7
1 8
A
Y2
Y1
VCC
description/ordering information
This dual analog multiplexer/demultiplexer is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G53 can handle both analog and digital signals. The device permits signals with amplitudes of
up to 5.5 V (peak) to be transmitted in either direction.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
NanoStar − WCSP (DSBGA)
0.17-mm Small Bump − YEA
SN74LVC2G53YEAR
NanoFree − WCSP (DSBGA)
0.17-mm Small Bump − YZA (Pb-free)
−40°C to 85°C
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
SN74LVC2G53YZAR
Reel of 3000
VSSOP − DCU
_ _ _C4_
SN74LVC2G53YEPR
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
SSOP − DCT
TOP-SIDE
MARKING‡
SN74LVC2G53YZPR
Reel of 3000
SN74LVC2G53DCTR
Reel of 3000
SN74LVC2G53DCUR
Reel of 250
SN74LVC2G53DCUT
C53_ _ _
C53_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright 2003, Texas Instruments Incorporated
!"#$%&'(!$" !) *+%%,"( ') $# -+./!*'(!$" 0'(,1
%$0+*() *$"#$%& ($ )-,*!#!*'(!$") -,% (2, (,%&) $# ,3') ")(%+&,"()
)('"0'%0 4'%%'"(51 %$0+*(!$" -%$*,))!"6 0$,) "$( ",*,))'%!/5 !"*/+0,
(,)(!"6 $# '// -'%'&,(,%)1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
FUNCTION TABLE
CONTROL
INPUTS
INH
A
ON
CHANNEL
L
L
Y1
L
H
Y2
H
X
None
logic diagram (positive logic)
A
5
SW
SW
INH
7
6
1
2
Y1
Y2
COM
NOTE A: For simplicity, the test conditions shown in Figures 1 through 4 and 6 through 10 are for the demultiplexer configuration. Signals can
be passed from COM to Y1 (Y2) or from Y1 (Y2) to COM.
simplified schematic, each switch (SW)
COM
2
Y
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Control input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/O port diode current, IIOK (VI/O < 0 or VI/O > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
On-state switch current, IT (VI/O = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 4): DCT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C/W
DCU package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 140°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 102°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 5.5 V maximum.
4. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 5)
MIN
VCC
VI/O
VIH
UNIT
Supply voltage
1.65
5.5
V
I/O port voltage
0
VCC
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
High-level input voltage, control input
VIL
Low-level input voltage, control input
VI
Control input voltage
∆t/∆v
MAX
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC × 0.65
VCC × 0.7
VCC × 0.35
VCC × 0.3
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
0
Input transition rise/fall time
V
VCC × 0.7
VCC × 0.7
VCC × 0.3
VCC × 0.3
V
5.5
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
20
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
10
20
ns/V
10
TA
Operating free-air temperature
−40
85
°C
NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
ron
TEST CONDITIONS
VI = VCC or GND,
VINH = VIL
(see Figures 1 and 2)
On-state switch resistance
ron(p)
VI = VCC to GND,
VINH = VIL
(see Figures 1 and 2)
Peak on-state resistance
VCC
MIN
TYP†
MAX
IS = 4 mA
IS = 8 mA
1.65 V
13
30
2.3 V
10
20
IS = 24 mA
IS = 32 mA
3V
8.5
17
4.5 V
6.5
13
IS = 4 mA
IS = 8 mA
1.65 V
86.5
120
2.3 V
23
30
IS = 24 mA
IS = 32 mA
3V
13
20
4.5 V
8
15
IS = 4 mA
IS = 8 mA
1.65 V
7
2.3 V
5
IS = 24 mA
IS = 32 mA
3V
3
4.5 V
2
UNIT
Ω
Ω
Difference of on-state resistance
between switches
VI = VCC to GND,
VC = VIH
(see Figures 1 and 2)
IS(off)
Off-state switch leakage current
VI = VCC and VO = GND or
VI = GND and VO = VCC,
VINH = VIH (see Figure 3)
5.5 V
IS(on)
On-state switch leakage current
VI = VCC or GND, VINH = VIL,
VO = Open (see Figure 4)
5.5 V
±1
±0.1†
II
Control input current
VC = VCC or GND
5.5 V
±1
±0.1†
µA
ICC
∆ICC
Supply current
VC = VCC or GND
VC = VCC − 0.6 V
5.5 V
1
µA
500
µA
Cic
Control input capacitance
∆ron
Supply-current change
±1
±0.1†
5.5 V
5V
3.5
Y
Cio(off)
Switch input/output capacitance
Cio(on)
Switch input/output capacitance
Ω
µA
A
µA
A
µA
pF
6.5
5V
COM
pF
10
5V
19.5
pF
† TA = 25°C
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 5)
PARAMETER
tpd‡
ten§
tdis¶
ten§
FROM
(INPUT)
TO
(OUTPUT)
COM or Y
Y or COM
INH
COM or Y
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
2
MAX
VCC = 3.3 V
± 0.3 V
MIN
1.2
MAX
VCC = 5 V
± 0.5 V
MIN
0.8
UNIT
MAX
0.6
3.3
9
2.5
6.1
2.2
5.4
1.8
4.5
3.2
10.9
2.3
8.3
2.3
8.1
1.6
8
ns
ns
2.9
10.3
2.1
7.2
1.9
5.8
1.3
5.4
A
COM or Y
ns
tdis¶
2.1
9.4
1.4
7.9
1.1
7.2
1
5
‡ tPLH and tPHL are the same as tpd. The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and
the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
§ tPZL and tPZH are the same as ten.
¶ tPLZ and tPHZ are the same as tdis.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
analog switch characteristics, TA = 25°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
VCC
CL = 50 pF, RL = 600 Ω,
fin = sine wave
(see Figure 6)
Frequency response†
(switch on)
COM or Y
Y or COM
CL = 5 pF, RL = 50 Ω,
fin = sine wave
(see Figure 6)
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 7)
Crosstalk‡
(between switches)
COM or Y
Y or COM
CL = 5 pF, RL = 50 Ω,
fin = 1 MHz (sine wave)
(see Figure 7)
Crosstalk
(control input to signal output)
INH
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (square wave)
(see Figure 8)
COM or Y
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 9)
Feed-through attenuation‡
(switch off)
COM or Y
Y or COM
CL = 5 pF, RL = 50 Ω,
fin = 1 MHz (sine wave)
(see Figure 9)
k ,
CL = 50 pF, RL = 10 kΩ,
fin = 1 kHz (sine wave)
(see Figure 10)
Sine-wave distortion
COM or Y
Y or COM
CL = 50 pF, RL = 10 kΩ,
k ,
fin = 10 kHz (sine wave)
(see Figure 10)
TYP
1.65 V
35
2.3 V
120
3V
190
4.5 V
215
1.65 V
>300
2.3 V
>300
3V
>300
4.5 V
>300
1.65 V
−58
2.3 V
−58
3V
−58
4.5 V
−58
1.65 V
−42
2.3 V
−42
3V
−42
4.5 V
−42
1.65 V
35
2.3 V
50
3V
70
4.5 V
100
1.65 V
−60
2.3 V
−60
3V
−60
4.5 V
−60
1.65 V
−50
2.3 V
−50
3V
−50
4.5 V
−50
1.65 V
0.1
2.3 V
0.025
3V
0.015
4.5 V
0.01
1.65 V
0.15
2.3 V
0.025
3V
0.015
4.5 V
0.01
UNIT
MHz
dB
mV
dB
%
† Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads −3 dB.
‡ Adjust fin voltage to obtain 0 dBm at input.
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
f = 10 MHz
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
9
• DALLAS, TEXAS 75265
10
VCC = 3.3 V
TYP
10
VCC = 5 V
TYP
12
UNIT
pF
5
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
S
VCC
A
VIL or VIH
VA
INH
VIL
Y2
2
GND
IS
r on +
V
VI − VO
Figure 1. On-State Resistance Test Circuit
100
VCC = 1.65 V
r on − Ω
VCC = 2.3 V
VCC = 3.0 V
10
VCC = 4.5 V
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VI − V
Figure 2. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC
6
VIH
VO
(On)
0.5
VIL
2
S
COM
1
0.0
1
1
Y1
VINH
VI = VCC or GND
VA
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VI * VO
W
IS
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
VA
VIH
A
VI
VCC
A
VIL or VIH
INH
Y1
S
VA
1
VIL
2
VIH
1
S
VINH
VO
COM
Y2
(Off)
2
GND
Condition 1: VI = GND, VO = VCC
Condition 2: VI = VCC, VO = GND
Figure 3. Off-State Switch Leakage-Current Test Circuit
VCC
VA
VIL
VI
VCC
A
VIL or VIH
A
INH
Y1
S
VA
1
VIL
2
VIH
1
S
VINH
COM
Y2
2
VO
VO = Open
VI = VCC or GND
(On)
GND
Figure 4. On-State Switch Leakage-Current Test Circuit
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
RL
From Output
Under Test
CL
(see Note A)
VLOAD
Open
S1
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
VCC
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
VCC/2
VCC/2
2 × VCC
2 × VCC
2 × VCC
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
tPHL
VOH
VM
Output
VM
VOL
tPHL
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VM
VM
VM
0V
tPZL
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
VIL or VIH
VIL
0.1 µF
VCC
A
VA
INH
Y1
S
VA
1
VIL
2
VIH
1
S
VINH
VO
COM
Y2
2
RL
fin
(On)
50 Ω
CL
GND
VCC/2
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
Figure 6. Frequency Response (Switch On)
VIL or VIH
A
VCC
VA
TEST CONDITION
VIL
20log10(VO2/VI)
VCC
VIH
20log10(VO1/VI)
VA
Y1
VIL
0.1 µF
INH
VO1
RL
600 Ω
VINH
CL
50 pF
COM
VCC/2
Rin
600 Ω
fin
50 Ω
Y2
VO2
GND
RL
600 Ω
CL
50 pF
VCC/2
Figure 7. Crosstalk (Between Switches)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
A
VIL or VIH
VA
INH
Y1
S
VA
1
VIL
2
VIH
1
S
VINH
VO
Y2
50 Ω
COM
(On)
2
RL
600 Ω
CL
50 pF
GND
VCC/2
Rin
600 Ω
VCC/2
Figure 8. Crosstalk (Control Input, Switch Output)
VCC
VCC
A
VIL or VIH
S
VA
1
VIL
2
VIH
VA
INH
VIL
Y1
1
S
VINH
0.1 µF
VO
COM
Y2
2
RL
fin
50 Ω
RL
(Off)
GND
VCC/2
VCC/2
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
Figure 9. Feed Through (Switch Off)
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CL
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
A
VIL or VIH
VA
VIL
10 µF
INH
Y1
VA
1
VIL
2
VIH
1
10 µF
S
VINH
VO
COM
fin
S
Y2
(On)
600 Ω
2
RL
10 kΩ
CL
50 pF
GND
VCC/2
VCC = 1.65 V, VI = 1.4 VP-P
VCC = 2.30 V, VI = 2.0 VP-P
VCC = 3.00 V, VI = 2.5 VP-P
VCC = 4.50 V, VI = 4.0 VP-P
Figure 10. Sine-Wave Distortion
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
8
0,13 M
5
0,15 NOM
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
1
0,25
4
0° – 8°
3,15
2,75
0,60
0,20
1,30 MAX
Seating Plane
0,10
0,10
0,00
NOTES: A.
B.
C.
D.
4188781/C 09/02
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion
Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Amplifiers
Applications
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated