FUJITSU SEMICONDUCTOR DATA SHEET DS04-27226-1E ASSP For Power Management Applications 2-channel DC/DC Converter IC with Synchronous Rectifier MB3882 ■ DESCRIPTION The MB3882 is a 2-channel DC/DC converter IC using pulse width modulation (PWM) and synchronous rectification, designed for down conversion applications. This device is a power supply with high output drive capacity. Synchronous rectification also provides for high efficiency. In addition, a 5 V regulator is built in to reduce the number of system components. The result is an ideal built-in power supply for driving products with high speed CPU’s such as home TV game devices and notebook PC’s. ■ FEATURES • • • • • • • Synchronous rectification for high efficiency Supply voltage range : 5.5 V to 18 V High-precision reference voltage : 2.5 V ± 1% Error Amp. threshold voltage : 1.25 V ± 1% (0 °C to 85 °C) Oscillator frequency range : 10 kHz to 500 kHz Built-in soft start circuit with error Amp. input control Totem pole type output for N-ch MOSFET ■ PACKAGE 24-pin Plastic SSOP (FPT-24P-M03) MB3882 ■ PIN ASSIGNMENTS (TOP VIEW) CT : 1 24 : VREF RT : 2 23 : VCC 22 : CSCP SGND : 3 21 : CS2 CS1 : 4 20 : −INE2 −INE1 : 5 19 : FB2 FB1 : 6 18 : +INC2 +INC1 : 7 17 : OUT1-2 OUT1-1 : 8 VS1 : 9 16 : VS2 CB1 : 10 15 : CB2 14 : OUT2-2 OUT2-1 : 11 13 : VB PGND : 12 (FPT-24P-M03) 2 MB3882 ■ PIN DESCRIPTIONS Pin No. Symbol I/O Description 1 CT Triangular wave oscillator frequency setting capacitor connection terminal 2 RT Triangular wave oscillator frequency setting resistor connection terminal 3 SGND Ground terminal 4 CS1 CH1 soft start capacitor connection terminal. (Also used as channel control) 5 −INE1 I CH1 error Amp. inverted input terminal 6 FB1 O CH1 error Amp. output terminal 7 +INC1 I CH1 overvoltage comparator non-inverted input terminal 8 OUT1-1 O CH1 totem pole output terminal. (External main side FET gate drive) 9 VS1 CH1 external main side FET source connection terminal 10 CB1 CH1 boot capacitor connection terminal. Connect capacitor between the CB1 terminal and VS1 terminal. 11 OUT2-1 O CH1 totem pole output terminal. (External synchronous rectifier side FET gate drive) 12 PGND Ground terminal 13 VB O Output circuit bias output terminal 14 OUT2-2 O CH2 totem pole output terminal. (External synchronous rectifier side FET gate drive) 15 CB2 CH2 boot capacitor connection terminal. Connect capacitor between the CB2 terminal and VS2 terminal. 16 VS2 CH2 external main side FET source connection terminal. 17 OUT1-2 O CH2 totem pole output terminal. (External main side FET gate drive) 18 +INC2 I CH2 overvoltage comparator non-inverted input terminal 19 FB2 O CH2 error Amp. output terminal 20 −INE2 I CH2 error Amp. inverted input terminal 21 CS2 CH2 soft start capacitor connection terminal. (Also used as channel control) 22 CSCP Timer latch short protection capacitor connection terminal 23 VCC Reference voltage, control circuit power supply terminal 24 VREF O Reference voltage output terminal 3 MB3882 ■ BLOCK DIAGRAM VCC 23 13 VB 5 V Reg. FB1 6 < CH1 > 10 µA 10 CB1 Error Amp.1 PWM Comp.1-1 − + + −INE1 5 CS1 4 + OVP Comp.1 8 OUT1-1 PWM Comp.2-1 + +INC1 7 Drive1-1 − 1.25 V 9 VS1 + − 1.47 V VCC Latch1 R − 11 OUT2-1 Drive2-1 S Q FB2 19 < CH2 > 10 µA 15 CB2 Error Amp.2 PWM Comp.1-2 − + + −INE2 20 CS2 21 + 17 OUT1-2 Drive1-2 − 1.25 V + +INC2 18 PWM Comp.2-2 OVP Comp.2 − VCC 1.47 V 16 VS2 + − Latch1 R 14 OUT2-2 Drive2-2 12 PGND S Q SCP Comp. 1 µA − − + 1.9 V 1.3 V 2.1 V bias bias VCC Ref (2.5 V) Power 24 VREF 3 SGND CSCP 22 S R Latch UVLO OSC 1 CT 4 2 RT MB3882 ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Conditions Supply voltage VCC Boot voltage VCB CB terminal Rating Unit Min. Max. 20 V 25 V 120 mA Output current IO Peak output current IOP Duty ≤ 5% (t = 1 / fOSC × Duty) 800 mA Power dissipation PD Ta ≤ +25 °C 740* mW −55 +125 °C Storage temperature Tstg * : The packages are mounted on the dual-sided epoxy board (10cm × 10cm). WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 5 MB3882 ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Conditions Supply voltage VCC Boot voltage Value Unit Min. Typ. Max. 5.5 12 18 V VCB CB terminal 23 V Reference voltage output current IOR VREF terminal −1 0 mA Bias output current IOB VB terminal −1 0 mA VIN −INE terminal 0 VCC − 1.8 V VINC +INC terminal 0 VCC V −100 100 mA −700 700 mA Input voltage Output current IO Peak output current IOP Oscillator frequency fOSC 10 200 500 kHz Timing resistor RT 6.8 10 12 kΩ Timing capacitor CT 150 470 15000 pF Boot capacitor CB 0.1 1.0 µF Duty ≤ 5% (t = 1 / fosc × Duty) Reference voltage output capacitor CREF VREF terminal 0.1 1.0 µF Bias output capacitor CVB VB terminal 1.0 4.7 10 µF Soft start capacitor CS 0.1 1 µF CSCP 0.01 0.1 µF Ta −30 +25 +85 °C Short detection capacitor Operating ambient temperature WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 6 MB3882 ■ ELECTRICAL CHARACTERISTICS (VCC = 12 V, VB = 0 mA, VREF = 0 mA, Ta = +25 °C) Parameter 4. Soft Start Block [CS] 5. Short Detection Comparator Block [SCP] 6. Triangular Wave Oscillator Block [OSC] 7. Error Amp Block [Error Amp.] Value Unit Min. Typ. Max. 2.475 2.500 2.525 V 24 Ta = +25 °C ∆VREF/ VREF 24 Ta = 0 °C to +85 °C 0.5* % Line 24 VCC = 5.5 V to 18 V 1 10 mV Load 24 VREF = 0 mA to −1 mA 3 10 mV Short output current Ios 24 VREF = 2 V −28 −14 −7 mA Output voltage VB 13 4.95 5.05 5.15 V Threshold voltage VTH 23 2.6 2.9 3.2 V Hysteresis width VH 23 0.2* V VRST 23 1.7 2.1 2.5 V Charge current ICS 4, 21 −14 −10 −6 µA Threshold voltage VTH 22 0.63 0.68 0.73 V Input source current ICSCP 22 −1.4 −1.0 −0.6 µA Short detection time tSCP 22 CSCP = 0.01 µF 4.5 6.8 12.2 ms Oscillator frequency fOSC 1 RT = 10 kΩ, CT = 470 pF 170 190 210 kHz ∆fOSC/ fOSC 1 Ta = 0 °C to +85 °C 1* % VTH1 5, 20 FB = 1.6 V, Ta = +25 °C 1.241 1.2500 1.259 V VTH2 5, 20 FB = 1.6 V, Ta = 0 °C to +85 °C 1.2375 1.2500 1.2625 V Input bias current IB 5, 20 −INE = 0 V −200 −20 nA Voltage gain AV 6, 19 DC 60 100 dB 1. Reference Input stability Voltage Block Load stability [Ref] 3. Undervoltage Lockout Circuit Block [UVLO] Conditions VREF Output voltage 2. Bias Voltage Block [VB] Symbol Pin No. Reset voltage Frequency temperature variation rate Threshold voltage VCC = * : Typical setting value (Continued) 7 MB3882 (VCC = 12 V, VB = 0 mA, VREF = 0 mA, Ta = +25 °C) Parameter Frequency band width 7. Error Amp Block [Error Amp.] AV = 0 dB Value Unit Min. Typ. Max. 800* kHz 6, 19 VFBH 6, 19 2.2 2.5 V VFBL 6, 19 0.8 1.0 V ISOURCE 6, 19 FB = 1.6 V −100 −45 µA ISINK 6, 19 FB = 1.6 V 1.5 9.0 mA VTL 6, 19 Duty cycle = 0% 1.2 1.3 V VTH 6, 19 Duty cycle = Dtr 1.81 2.0 V Dtr 8, 17 RT = 10 kΩ, CT = 470 pF 85 90 95 % ISOURCE1 8, 17 Duty ≤ 5% (t = 1 / fOSC × Duty) −700* mA ISINK1 8, 17 Duty ≤ 5% (t = 1 / fOSC × Duty) 900* mA VOH1 8, 17 OUT1 = −100 mA, CB = 17 V, VS = 12 V CB − 2.5 CB − 0.9 V VOL1 8, 17 OUT1 = 100 mA, CB = 17 V, VS = 12 V VS + 0.9 VS + 1.4 V Output current ISOURCE2 (synchronous rectifier side) ISINK2 11, 14 Duty ≤ 5% (t = 1 / fOSC × Duty) −750* mA 11, 14 Duty ≤ 5% (t = 1 / fOSC × Duty) 900* mA Output voltage (synchronous rectifier side) VOH2 11, 14 OUT2 = −100 mA 2.5 4.1 V VOL2 11, 14 OUT2 = 100 mA 1.0 1.4 V Diode voltage VD 10, 15 VB = 10 mA 0.9 1.1 V Output voltage Output source current 8. PWM Threshold Comparator voltage Block [PWM Comp.] Maximum duty cycle Output current (main side) Output voltage (main side) 10. Output Block [Drive] Conditions BW Output sink current 9. Dead time Adjustment Block [DTC] Symbol Pin No. * : Typical setting value (Continued) 8 MB3882 (Continued) (VCC = 12 V, VB = 0 mA, VREF = 0 mA, Ta = +25 °C) Parameter Symbol Pin No. tD1 10. Output Block [Drive] 8, 11, 17, 14 Dead time tD2 11. Overvoltage Detection Comparator Block [OVP] 12. General Conditions Value Unit Min. Typ. Max. RT = 10 kΩ, CT = 470 pF OUT1 = OUT2 = OPEN, VS = 0 V OUT2 : − OUT1 : 100 200 ns RT = 10 kΩ, CT = 470 pF OUT1 = OUT2 = OPEN, VS = 0 V OUT1 : − OUT2 : 100 250 ns Threshold voltage VTH 7, 18 +INC = 1.44 1.47 1.50 V Input bias current IB 7, 18 +INC = 0 V −200 −30 nA Power supply current ICC 23 11 16.5 mA 9 MB3882 ■ TYPICAL CHARACTERISTICS Reference Voltage vs. Supply Voltage Supply Current vs. Supply Voltage 15.0 5 Reference voltage VREF (V) Ta = +25 °C Supply current ICC (mA) 12.5 10.0 7.5 5.0 2.5 0.0 Ta = +25 °C VREF = 0 mA 4 3 2 1 0 0 5 10 15 Supply voltage VCC (V) 0 20 5 10 15 Supply voltage VCC (V) 20 Reference Voltage vs. Ambient Temperature Reference voltage ∆VREF (%) 2.0 VCC = 12 V VREF = 0 mA 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 −40 −20 0 20 40 60 80 100 Triangular Wave Upper/Lower Limit Voltage vs. Triangular Wave Oscillator Frequency 2.5 Ta = +25 °C VCC = 12 V CTL = 5 V 2.0 Upper limit 1.5 1.0 0.5 1k Lower limit 10 k 100 k 1M Triangular wave oscillator frequency fosc (Hz) Triangular wave upper/lower limit voltage VCT (V) Triangular wave upper/lower limit voltage VCT (V) Ambient temperature Ta (°C) Triangular Wave Upper/Lower Limit Voltage vs. Ambient Temperature 2.5 VCC = 12 V RT = 10 kΩ CT = 470 pF 2.0 Upper limit 1.5 Lower limit 1.0 0.5 −40 −20 0 20 40 60 80 100 Ambient temperature Ta (°C) (Continued) 10 MB3882 Triangular Wave Oscillator Frequency vs. Timing Resistor Triangular wave frequency fOSC (Hz) 10 M Ta = +25 °C VCC = 12 V CTL = 5 V RT = 10 kΩ 1M 100 k 10 k 1k 10 100 1000 10000 10 M Ta = +25 °C VCC = 12 V CTL = 5 V 1M CTL = 150 pF 100 k CTL = 470 pF 10 k CTL = 15000 pF 1k 100 1k 100000 10 k Timing resistor RT (Ω) Triangular Wave Oscillator Frequency vs. Supply Voltage Triangular Wave Oscillator Frequency vs. Ambient Temperature Triangular wave frequency fOSC (Hz) Timing capacitor CT (pF) 250 Ta = +25 °C RT = 10 kΩ CT = 470 pF 240 230 220 210 200 190 180 170 160 150 0 5 10 15 Supply voltage VCC (V) 250 VCC = 12 V RT = 10 kΩ CT = 470 pF 240 230 220 210 200 190 180 170 160 150 −40 20 100 k −20 0 20 40 60 Ambient temperature Ta (°C) 80 100 Error Amp Gain, Phase vs. Frequency φ 20 0 AV −20 180 90 0 −90 VCC = 12 V Phase φ (deg.) Ta = +25 °C 40 Gain AV (dB) Triangular wave frequency fOSC (Hz) Triangular wave frequency fOSC (Hz) Triangular Wave Oscillator Frequency vs. Timing Capacitor 240 kΩ 4.7 kΩ − + IN 10 µF 4.7 kΩ 2.4 kΩ (20) 5 4 (21) 1.5 V −40 1k −180 10 k 100 k 1M Frequency f (Hz) − + + 6 (19) OUT 1.25 V Error Amp.1 (Error Amp.2) 10 M (Continued) 11 MB3882 (Continued) Power dissipation PD (mW) Power Dissipation vs. Ambient Temperature 800 740 700 600 500 400 300 200 100 0 −40 −20 0 20 40 60 Ambient temperature Ta (°C) 12 80 100 MB3882 ■ FUNCTION DESCRIPTION 1. DC/DC Converter Function (1) Reference Voltage Block The reference voltage circuit takes the voltage feed from the power supply terminal (pin 23) and generates a temperature compensated reference voltage (2.5 V typ.) , for use as the reference voltage for the power supply control unit. Also, an external load current can be obtained from the power supply at the VREF terminal (pin 24) , up to a maximum of 1 mA. (2) Triangular Wave Oscillator Block A triangular waveform with amplitude 1.3 V to 1.9 V can be generated by connecting a timing capacitor and resistor to the CT terminal (pin 1) and RT terminal (pin 2) , respectively. The triangular oscillator waveform can be input to the IC’s internal PWM comparator, as well as supplied externally from the CT terminal. (3) Error Amp Block (Error Amp.) The error Amp. is an amplifier that detects the output voltage from the DC/DC converter and outputs a PWM control signal. The error Amp. has a broad in-phase input voltage range of 0 to Vcc−1.8 V that can be easily set by the external power supply. In addition, an arbitrary loop gain can be set up by connecting a feedback resistor and capacitor between the error Amp. output terminal and inverter input terminal, providing stable phase compensation to the system. Also, power-on rush current can be prevented by connecting a soft start capacitor between the error Amp. noninverted input terminals CS1 terminal (pin 4) and CS2 terminal (pin 21) . The soft start function operates with a stable soft start time that is not dependent on the output load of the DC/DC converter. (4) PWM Comparator Block (PWM Comp.) This is a voltage - pulse width modulator that controls the output duty according to the input voltage. Main side : Turns the output transistor on in the intervals in which the error Amp. output voltage is higher than the triangular wave voltage. Synchronous rectifier side : Turns the output transistor on in the intervals in which the triangular wave voltage the is lower than error Amp. voltage. (5) Output Block The output block has totem pole configuration on both the main side and synchronous rectifier side, and can drive an external N-ch MOSFET. Also, the high output drive capability (700 mA max : duty ≤ 5%) provides high gate-source capacitor, enabling the use of low on-resistor FET devices. 13 MB3882 2. Channel Control Functions Channel ON/OFF control is provided by using the CS1 terminal (pin 4) and CS2 terminal (pin 21) setting functions. Channel On/Off Setting Functions CS terminal voltage level Channel output state CS1 CS2 CH1 CH2 GND GND OFF OFF GND Hi-Z OFF ON Hi-Z GND ON OFF Hi-Z Hi-Z ON ON 3. Protective Functions (1) Timer Latch Short Circuit Protection (SCP) The short circuit protection comparators read the output voltage levels. If the output voltage on either channel falls below the short detection voltage, the timer circuit is activated to start charging the external capacitor Cscp connected to the CSCP terminal (pin 22) . When capacitor voltage reaches approximately 0.68 V the output FET turns off, setting the idle interval to 100%. Once the protection circuit is activated, it can be reset by turning the power supply off and on again. (See “Setting the Timer Latch Short Circuit Protector Time Constant.”) (2) Undervoltage Lockout Circuit Block (UVLO) Transient status during normal power-on or momentary drops in supply voltage can cause abnormal operation in an control IC, leading to damage or degradation of system components. The undervoltage lockout circuit prevents such abnormal operations by reading the internal reference voltage level and switching the output transistor off, setting the idle interval to 100% and holding the CSCP terminal (pin 22) to “L” level. System operation is restored when the supply voltage rises back about the undervoltage lockout circuit threshold voltage. (3) Overvoltage Protection Block (OVP) The overvoltage protection circuit uses an overvoltage comparator (OVP Comp.) on each channel to read the output voltage levels from the DC/DC converter. If the output voltage exceeds the threshold voltage a latch is set, turning off the main side FET on the corresponding channel. 14 MB3882 ■ SETTING THE TIMER LATCH SHORT CIRCUIT PROTECTOR TIME CONSTANT Each channel has a short circuit protection comparator (SCP Comp.) which constantly compares the error Amp. output level to the reference voltage. When the DC/DC comparator load conditions are stable on all channels, the short circuit protection comparator output is at “H” level, transistor Q1 is on, and the CSCP terminal (pin 22) is held at input standby voltage (VSTB : = 50 mV) . If load conditions change rapidly, such as during a load short, causing output voltage to drop, the short circuit protection comparator output goes to “L” level. This causes the transistor Q1 to shut off, charging the short circuit protection capacitor Cscp (connected to the CSCP terminal) at 1 µA. Short detection time tscp (s) =: 0.68 × Cscp (µF) When the capacitor Cscp is charted to the threshold voltage (VTH : = 0.68 V) a latch is set, turning the external FET off (setting the idle interval to 100%) . At this time the latch input is closed and the CSCP terminal is held at the input latch voltage (VI : = 50 mV) . (When a short circuit is detected on either of the two channels, both channels are shut off.) 15 MB3882 10 µA 10 µA FB1 6 −INE1 CS1 − + + 5 Error Amp.1 Drive 8 OUT1-1 Drive 11 OUT2-1 Drive 17 OUT1-2 Drive 14 OUT2-2 4 1.25 V CS1 Q2 FB2 19 −INE2 CS2 − + + 20 Error Amp.2 21 1.25 V CS2 Q3 SCP Comp. − − + 1 µA bias CSCP 22 S CSCP Q1 Q4 2.1 V R Latch UVLO < Timer Latch Short Circuit Protection Circuit > 16 MB3882 ■ PROCESSING WITHOUT USING THE CSCP TERMINAL When the timer latch short circuit protection circuit is not used, the CSCP terminal (pin 22) should be shorted to GND using the shortest possible connection. 3 GND CSCP 22 < Operation Without Using the CSCP Terminal > 17 MB3882 ■ SOFT START TIME SETTING The soft start function prevents rush current events when the IC power is turned on, by connecting soft start capacitors (Cs1, Cs2) to the CS1 terminal (pin 4) for channel 1, and the CS2 terminal (pin 21) for channel 2. When the IC is activated (Vcc ≥ UVLO threshold voltage) , Q2 and Q3 are off and the CS1 and CS2 terminals begin charging the externally connected soft start capacitors (Cs1, Cs2) at 10 µA. Because the error Amp. output (FB1, FB2) is determined by the ratio of the lower of the two non-inverted input terminals (1.25 V, CS terminal voltage) to the inverted input terminal voltage (−INE) , the soft start interval (when CS terminal voltage < 1.25 V) FB is determined by the ratio of the −INE terminal voltage and CS terminal voltage. Thus the DC/DC converter output voltage rises in proportion to the rise in the CS terminal voltage as the soft start capacitor connected to the CS terminal charges. The soft start time is determined by the following formula. Soft start time (time to output 100%) ts (s) =: 0.125 × Cs (µF) CS terminal voltage 2.3 V Error Amp. block comparison voltage to −INE voltage 1.25 V 0V t Soft start time ts 18 MB3882 VREF 10 µA (FB2) FB1 19 6 (−INE2) 20 −INE1 5 − + + 21 (CS2) 4 CS1 CS1 (CS2) 10 µA Error Amp. 1.25 V Q2 (Q3) UVLO < Soft Start Block > 19 MB3882 ■ PROCESSING WITHOUT USING THE CS TERIMNALS When the soft start function is not used, the CS1 terminal (pin 4) and CS2 terminal (pin 22) should be left open. "Open" "Open" 4 CS1 CS2 21 < Operation Without Soft Start Setting > ■ OSCILLATOR FREQUENCY SETTING The oscillator frequency can be set by connecting a timing capacitor (CT) to the CT terminal (pin 1) and a timing resistor (RT) to the RT terminal (pin 2) . Oscillator frequency 893000 fosc (kHz) =: CT (pF) •RT (kΩ) ■ OUTPUT VOLTAGE SETTING VO FB1 6 VO = R1 −INE1 5 R2 CS1 − + + Error Amp. 4 1.25 V < CH1, 2 > 20 1.25 V R2 (R1 + R2) MB3882 ■ OVERVOLTAGE PROTECTION CIRCUIT VOTAGE SETTING Overvoltage conditions in the DC/DC converter output voltage can be detected by connecting external resistance from the DC/DC converter output voltage to the +INC1 terminal (pin 7) and +INC2 terminal (pin 18) on the respective overvoltage protection comparator circuits (OVP comp. 1, 2) . When the output voltage of the DC/DC converter rises above the detection voltage, the overvoltage protection comparator (OVP Comp. 1, 2) output goes to “H” level, setting a latch and shutting off the corresponding channel. Each of the overvoltage protection circuit latches operates independently. Detection voltage VOVP (V) =: 1.47 × (R3 + R4) /R4 Once the protection circuit has been activated, it can be reset by lowering the VCC voltage below the reset voltage (1.7 V min.) . VO VCC R3 R4 (+INC2) 18 7 +INC1 + OVP Comp. R Q S − 1.47 V 21 MB3882 ■ PRECAUTIONS RELATED TO INTERNAL IC POWER CONSUMPTION The internal power dissipation in the IC is greatly affected by the oscillator frequency and the FET total gate charge. When using the MB 3882 in an application, caution must be taken in relation to internal IC power consumption. As shown below, IB (average current) can be determined from the total gate charge Qg1, Qg2, charged from the gate capacitance (Ciss1, Ciss2, Crss1, Crss2) of the external FET Q1, Q2, by the following formula. Per individual channel : IB (A) = I1 + I2 =: Ibias1 × T1 Qg1 T2 Qg2 + + Ibias2 × + T T T T (Ibias1 = Ibias2 =: 2 mA) Because IC current consumption other than IB is 11 mA, power consumption can be determined from the following formula. Power consumption : Pc Pc (W) = 0.011 × VCC + 2 × VCC × IB − VB × IB 22 MB3882 Vin VCC 23 IB 5V 13 10 VB CVB A CB1 L1 Q1 I1 Drive 1-1 8 9 I2 VO1 Crss2 Crss1 OUT1-1 Q2 Ciss1 VS1 Ciss2 Drive 2-1 11 12 OUT2-1 PGND T VOUT1-1 VOUT2-1 I1 Bias current Ibias1 2 mA T1 I2 Bias current Ibias2 2 mA T2 t Using the above formulas to determine power consumption, settings should be made with reference to the “Power Consumption vs. Input Voltage” on the following page, as well as the “Power dissipation vs. Ambient Temperature.” 23 MB3882 Power Consumption vs. Input Voltage (Qg Parameters) Power consumption PC (W) 1.00 0.90 0.80 Qg1 = Qg2 = 70 nC 0.70 Qg1 = Qg2 = 50 nC Qg1 = Qg2 = 30 nC 0.60 Qg1 = Qg2 = 20 nC 0.50 Qg1 = Qg2 = 10 nC 0.40 0.30 Ta = +25 °C fOSC = 200 kHz SW1 = OFF SW2 = OFF 0.20 0.10 0.00 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Input voltage Vin (V) Power Consumption vs. Input Voltage (fosc Parameters) Power consumption PC (W) 1.00 Ta = +25 °C 0.90 Qg1 = Qg2 = 20 nC 0.80 SW1 = OFF 0.70 SW2 = OFF fOSC = 500 kHz 0.60 fOSC = 300 kHz fOSC = 200 kHz 0.50 0.40 fOSC = 100 kHz 0.30 fOSC = 10 kHz 0.20 0.10 0.00 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Input voltage Vin (V) 24 22 µF 0.1 µF SW2 B Channel On/Off signal SW1 0.1 µF 0.01 µF 7 CSCP 22 18 +INC2 0.1 µF −INE2 CS2 21 C4 20 19 2.7 kΩ R5 FB2 R23 10 kΩ C12 6.2 kΩ 10 kΩ R12 3.3 kΩ R22 R6 C3 0.022 µF R11 2 kΩ 5 6 −INE1 CS1 4 C2 2.7 kΩ R1 FB1 +INC1 6.2 kΩ R21 10 kΩ 10 kΩ R10 3.3 kΩ R20 R2 C1 0.022 µF R9 2 kΩ +C15 C14 A Channel On/Off signal Vin − + R SQ Latch2 OVP Comp.2 − + + SCP Comp. 1 µA VCC Latch1 Error Amp.2 1.47 V − + OVP Comp.1 − + + Error Amp.1 − − + S R Latch bias 2.1 V R 1.47 V VCC SQ 1.25 V 10 µA 1.25 V 10 µA UVLO − + PWM Comp.2-2 − + PWM Comp.1-2 − + PWM Comp.2-1 − + PWM Comp.1-1 23 VCC 2 CT RT C13 R13 470 pF 10 kΩ 1 OSC 3 Power VCC VB 12 14 16 17 15 PGND OUT2-2 VS2 OUT1-2 CB2 OUT2-2 11 9 VS1 OUT1-1 10 8 D3 CB1 13 VREF SGND C16 0.1 µF 24 (2.5 V) Ref bias 1.3 V 1.9 V Drive 2-2 Drive 1-2 <CH2> Drive 2-1 Drive 1-1 <CH1> 5 V Reg C17 0.1 µF D4 C5 4.7 µF Q3 C9 0.1 µF 0.1 µF 22 µF 0.1 µF +C19 C18 22 µF D1 Q4 D2 Q2 0.1 µF +C10 C7 Q1 C6 L1 2.2 µF C21 2.7 µH B L2 2.2 µF C20 2.7 µH A 68 µF × 3 +C11 Vo2 (2 V) 68 µF × 3 +C8 Vo1 (2 V) MB3882 ■ APPLICATION CIRCUIT 25 MB3882 ■ COMPONENT LIST COMPONENT ITEM SPECIFICATION VENDOR PARTS No. Q1 to Q4 FET VDS = 30 V IR IRF7811 D1, D2 D3, D4 Diode Diode VF=0.35V(Max.),at IF=1A VF=0.30V(Max.),at IF=10mA ROHM ROHM RB051L-40 RB495D L1, L2 Coil 2.7 µH TDK RLF12545T -2R7N8R7 C1 C2 C3 C4 C5 C6, C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 to C18 C19 C20, C21 Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Electrolytic Condenser Ceramics Condenser OS Condenser Electrolytic Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser OS Condenser Ceramics Condenser OS Condenser Ceramics Condenser 0.022 µF 0.1 µF 0.022 µF 0.1 µF 4.7 µF 0.1 µF 68 µF 0.1 µF 22 µF 68 µF 0.01 µF 470 pF 0.1 µF 22 µF 0.1 µF 22 µF 2.2 µF R1 R2 R5 R6 R9 R10 R11 R12 R13 R20 R21 R22 R23 Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor 2.7 kΩ 10 kΩ 2.7 kΩ 10 kΩ 2 kΩ 3.3 kΩ 2 kΩ 3.3 kΩ 10 kΩ 6.2 kΩ 10 kΩ 6.2 kΩ 10 kΩ Notes : IR : International Rectifier Corp. ROHM : Rohm, Ltd. TDK : TDK, Ltd. 26 12 A, 4.5 mΩ 6.3 V 25 V 6.3 V 25 V 25 V 1/4 W 1/4 W 1/4 W 1/4 W 1/4 W 1/4 W 1/4 W 1/4 W 1/4 W 1/4 W 1/4 W 1/4 W 1/4 W MB3882 ■ REFERENCE DATA Conversion Efficiency vs. Load Current Characteristics (Channel 1) 100 Ta = +25 °C 2 V output SW1 = OFF SW2 = ON Conversion efficiency η (%) 95 90 Vin = 6 V 85 Vin = 8.5 V Vin = 10 V 80 75 70 0 1 2 3 4 5 6 7 8 9 10 Load current IL (A) 27 MB3882 ■ PRECAUTIONARY INFORMATION • Printed circuit board ground lines should be designed with consideration for common impedance. • • • • • Take sufficient countermeasures should be taken to protect against static electricity. Always place semiconductors in containers that have anti-static provisions, or are conductive. After mounting, PC boards should be placed in conductive bags or containers for storage and handling. Working surfaces, tools, and measurement equipment should be grounded. Persons handling semiconductors should be grounded directly with resistance of 250 kΩ to 1 MΩ. • Do not apply negative voltages. • Application of negative voltage of −0.3 V or greater can create parasitic transistor effects on an LSI device, leading to abnormal operation. ■ ORDERING INFORMATION Part Number MB3882PFV 28 Package Plastic SSOP 24-pin (FPT-24P-M03) Remarks MB3882 ■ PACKAGE DIMENSION 24-pin, Plastic SSOP (FPT-24P-M03) * Dimensions include resin remainder. +0.20 * 7.75±0.10(.305±.004) 1.25 Ð0.10 +.008 .049 Ð.004 (Mounted height) 0.10(.004) * 5.60±0.10 INDEX 0.65±0.12(.0256±.0047) (.220±.004) +0.10 C 6.60(.260) NOM "A" +0.05 0.22 Ð0.05 0.15 Ð0.02 +.004 Ð.002 .006 Ð.001 .009 7.15(.281)REF 7.60±0.20 (.299±.008) Details of "A" part +.002 0.10±0.10(.004±.004) (STAND OFF) 0 10¡ 0.50±0.20 (.020±.008) 2000 FUJITSU LIMITED F24018S-2C-3 Dimensions in mm (inches) . 29 MB3882 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8588, Japan Tel: +81-44-754-3763 Fax: +81-44-754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 F0010 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. 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