TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 5.5-V TO 52-V INPUT, CURRENT-MODE BOOST CONTROLLER Check for Samples: TPS40210-HT FEATURES 1 • • • • • • • • • • • For Boost, Flyback, SEPIC, LED Driver Applications Wide Input Operating Voltage: 5.5 V to 52 V Adjustable Oscillator Frequency Fixed-Frequency Current-Mode Control Internal Slope Compensation Integrated Low-Side Driver Programmable Closed-Loop Soft Start Overcurrent Protection External Synchronization Capable Reference Voltage: 700 mV Low-Current Disable Function APPLICATIONS • • Down-Hole Drilling High Temperature Environments SUPPORTS EXTREME TEMPERATURE APPLICATIONS • • • • • • • • (1) Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Extreme (–55°C/210°C) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability Texas Instruments high temperature products utilize highly optimized silicon (die) solutions with design and process enhancements to maximize performance over extended temperatures. CONTENTS Device Ratings 2 Electrical Characteristics 3 Typical Characteristics 5 Terminal Information 10 Application Information 12 Additional References 25 Design Examples 26 DESCRIPTION The TPS40210 is a wide input voltage (5.5 V to 52 V) non-synchronous boost controller. It is suitable for topologies that require a grounded source N-channel FET, including boost, flyback, SEPIC, and various LED driver applications. Device features include programmable soft start, overcurrent protection with automatic retry, and programmable oscillator frequency. Current-mode control provides improved transient response and simplified loop compensation. VIN TPS40210 1 RC 2 SS BP 9 3 DIS/EN GDRV 8 4 COMP ISNS 7 5 FB GND 6 VOUT VDD 10 RSENSE UDG-07110 Custom temperature ranges available 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPS40210-HT SLVSAD8 – JUNE 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. BARE DIE INFORMATION DIE THICKNESS BACKSIDE FINISH BACKSIDE POTENTIAL BOND PAD METALLIZATION COMPOSITION BOND PAD THICKNESS 15 mils. Silicon with backgrind GND Al-Cu (0.5%) 0.6 µm 1238.4 µm NC (4) NC (5) 1 NC (3) NC (2) NC (1) 10 3 1245.6 µm 2 9 8 7 4 52.8 µm 6 5 0.0 52.2 µm 0.0 Table 1. Bond Pad Coordinates in Microns 2 DISCRIPTION PAD NUMBER X min Y min X max Y max RC 1 67.95 1089.45 168.75 1190.25 SS 2 28.8 714.15 129.6 814.95 DIS/EN 3 28.8 595.35 129.6 696.15 COMP 4 28.8 306.45 129.6 407.25 FB 5 28.8 115.29 129.6 216.09 GND 6 1108.62 117.45 1209.42 218.25 ISNS 7 1108.62 332.91 1209.42 433.71 GDRV 8 1108.62 451.71 1209.42 552.51 BP 9 1108.62 570.51 1209.42 671.31 VDD 10 1057.68 1114.02 1158.48 1214.82 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 Table 1. Bond Pad Coordinates in Microns (continued) DISCRIPTION PAD NUMBER X min Y min X max Y max NC (1) 962.55 1147.32 1030.05 1214.82 NC (2) 868.59 1147.32 936.09 1214.82 NC (3) 764.73 1147.32 832.23 1214.82 NC (4) 643.68 1147.32 711.18 1214.82 NC (5) 403.74 1147.23 471.24 1214.73 ORDERING INFORMATION (1) TA –55°C to 210°C (1) (2) PACKAGE (2) ORDERABLE PART NUMBER KGD (bare die) TPS40210SKGD1 NA HKK TPS40210SHKK TPS40210SHKK TOP-SIDE MARKING For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. DEVICE RATINGS ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) Input voltage range Output voltage range VDD –0.3 V to 52 V RC, SS, FB, DIS/EN –0.3 V to 10 V ISNS –0.3 V to 8 V COMP, BP, GDRV –0.3 V to 9 V TJ Operating junction temperature range –55°C to 210°C Tstg Storage temperature range –55°C to 210°C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN MAX VVDD Input voltage 5.5 52 UNIT V TJ Operating junction temperature –55 210 °C THERMAL CHARACTERISTICS FOR HKK PACKAGE over operating free-air temperature range (unless otherwise noted) PARAMETER qJC Junction-to-case thermal resistance TEST CONDITIONS to bottom of case to top of case - as if formed dead bug MIN TYP MAX 4.6 12.9 UNIT °C/W ELECTROSTATIC DISCHARGE (ESD) PROTECTION TYP Human-Body Model (HBM) 1500 Charged-Device Model (CDM) 1500 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT UNIT V 3 TPS40210-HT SLVSAD8 – JUNE 2010 www.ti.com ELECTRICAL CHARACTERISTICS TJ = –55°C to 210°C, VVDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS TA = –55°C to 125°C TA = 210°C UNIT MIN TYP MAX MIN TYP MAX 686 700 720 686 702 725 mV 52 5.5 52 V Voltage Reference Feedback voltage range VFB COMP = FB, 5.5 ≤ VVDD ≤ 52 V Input Supply VVDD Input voltage range IVDD Operating current 4.5 5.5 ≤ VVDD ≤ 52 V, no switching, VDIS < 0.8 1.5 2.5 1.5 3 mA 2.5 ≤ VDIS ≤ 7 V 10 20 23 90 mA 430 530 460 700 mA 4 4.25 4.50 4.60 V 140 195 240 195 mV VVDD < VUVLO(on), VDIS < 0.8 Undervoltage Lockout (UVLO) VUVLO(on) Turn on threshold voltage VUVLO(hyst) UVLO hysteresis Oscillator Oscillator frequency range (1) fOSC 35 Oscillator frequency RRC = 200 kΩ, CRC = 470 pF 260 Frequency line regulation 5.5 ≤ VDD ≤ 52 V –20 Slope compensation ramp VSLP 520 1000 35 340 260 7 –20 620 720 480 275 400 500 90 200 120 200 100 300 1000 300 640 kHz 400 7 % 750 mV PWM VVDD = 12 V (1) tON(min) Minimum pulse width tOFF(min) Minimum off time 170 VVLY Valley voltage 1.2 VSS(ofst) Offset voltage from SS pin to error amplifier input 700 RSS(chg) Soft-start charge resistance 320 450 600 305 375 600 kΩ RSS(dchg) Soft-start discharge resistance 840 1200 1600 700 968 1600 kΩ 1.5 3 VVDD = 30 V ns ns V Soft-Start 700 mV Error Amplifier GBWP Unity gain bandwidth product (1) 1.5 3 AOL Open loop gain (1) 60 80 IIB(FB) Input bias current (current out of FB pin) ICOMP(src) Output source current VFB = 0.6 V, VCOMP = 1 V 100 265 ICOMP(snk) Output sink current 1.2 2.3 120 150 111 VFB = 1.2 V, VCOMP = 1 V MHz dB 300 65 nA 100 280 mA 0.9 1.3 mA 120 150 Overcurrent Protection VISNS(oc) Overcurrent detection threshold (at ISNS 5.5 ≤ VDD < 52 V, –55°C ≤ TJ ≤ 210°C pin) DOC Overcurrent duty cycle (1) (1) 4 180 2 180 mV 2 % Specified by design Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 ELECTRICAL CHARACTERISTICS (continued) TJ = –55°C to 210°C, VVDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TA = –55°C to 125°C TEST CONDITIONS VSS(rst) Overcurrent reset threshold voltage (at SS pin) TBLNK Leading edge blanking TA = 210°C MIN TYP MAX MIN TYP MAX 100 150 350 100 150 350 75 UNIT mV ns Current-Sense Amplifier ACS Current sense amplifier gain IB(ISNS) Input bias current 4.2 5.6 7.2 1 3 4 4.8 7.2 V/V 1 3 mA Driver IGDRV(src) Gate driver source current VGDRV = 4 V, TJ = 25°C 280 335 180 280 mA IGDRV(snk) Gate driver sink current VGDRV = 4 V, TJ = 25°C 300 330 230 290 mA 7 8 9 4.8 8.45 Linear Regulator VBP Bypass voltage output 0 mA < IBP < 15 mA 10 V Disable/Enable VDIS(en) Turn-on voltage 0.7 1 1.3 0.7 1 1.3 V VDIS(hys) Hysteresis voltage 25 145 220 25 155 220 mV RDIS DIS pin pulldown resistance 0.7 1.1 1.5 0.5 0.9 1.5 MΩ 1000 Estimated Life (Years) 100 10 Electromigration Fail Mode 1 0 110 130 150 170 190 210 230 Continuous TJ (°C) Notes: 1. See datasheet for absolute maximum and minimum recommended operating conditions. 2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life). Figure 1. TPS40210SKGD1/TPS40210SHKK Operating Life Derating Chart Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT 5 TPS40210-HT SLVSAD8 – JUNE 2010 www.ti.com TYPICAL CHARACTERISTICS FREQUENCY vs TIMING RESISTANCE SWITCHING FREQUENCY vs DUTY CYCLE 1200 68 pF fSW - Frequency - kHz 800 100pF 220 pF 400 1000 fSW - Frequency - kHz 470 220 100 68 33 1000 600 1200 CT(pF) 33pF 200 800 600 400 200 470 pF 0 100 200 300 400 500 600 700 800 RT - Timing Resistance - kW 0 900 1000 0 0.6 0.8 D - Duty Cycle Figure 3. QUIESCENT CURRENT vs JUNCTION TEMPERATURE SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 1.0 1.2 50 52 V 12 V 1.4 IVDD - Shutdown Current - µA IVDD - Quiescent Current - mA 0.4 Figure 2. 1.8 1.6 0.2 1.2 1 0.8 4.5 V 0.6 0.4 40 30 20 10 0.2 0 -55 0 -55 -25 5 35 65 95 -25 5 35 65 95 125 155 185 215 125 155 185 215 TJ - Junction Temperature - °C TJ - Junction Temperature - °C Figure 4. 6 Figure 5. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 TYPICAL CHARACTERISTICS (continued) REFERENCE VOLTAGE CHANGE vs JUNCTION TEMPERATURE REFERENCE VOLTAGE CHANGE vs INPUT VOLTAGE 0.3 0.2 0.4 52 V 4.5 V VFB – Reference Voltage Change – % VFB - Reference Voltage Change - % 0.5 0.1 0 12 V -0.1 -0.2 -0.3 -0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -55 -25 5 35 65 95 -0.5 125 155 185 215 10 0 20 30 40 VVDD – Input Voltage – V TJ - Junction Temperature - °C Figure 6. Figure 7. UNDERVOLTAGE LOCKOUT THRESHOLD vs JUNCTION TEMPERATURE OVERCURRENT THRESHOLD vs JUNCTION TEMPERATURE 50 60 165 4.25 UVLO 164 Off On 4.20 UVLO On 4.15 4.10 4.05 UVLO Off 4.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – ° C VISNS(OC) - Overcurrent Threshold - mV VUVLO – Undervoltage Lockout Threshold – V 4.30 163 4.5 V 162 161 160 12 V 52 V 159 158 157 156 155 -55 -25 Figure 8. 5 35 65 95 125 155 185 215 TJ - Junction Temperature - °C Figure 9. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT 7 TPS40210-HT SLVSAD8 – JUNE 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) OVERCURRENT THRESHOLD vs INPUT VOLTAGE SWITCHING FREQUENCY CHANGE vs JUNCTION TEMPERATURE 5 155 fosc - Switching Frequency Change - % VISNS(OC) – Overcurrent Threshold – mV 4 154 153 152 151 150 149 148 147 3 2 4.5 V 1 12 V 0 -1 52 V -2 -3 -4 146 -5 -55 145 0 5 10 15 20 25 30 35 VVDD – Input Voltage – V 40 -25 5 35 65 95 125 155 185 215 45 TJ - Junction Temperature - °C Figure 10. Figure 11. OSCILLATOR AMPLITUDE vs JUNCTION TEMPERATURE SOFT-START CHARGE/DISCHARGE RESISTANCE vs JUNCTION TEMPERATURE RSS - Soft Start Charge/Discharge Resistance - kW 1600 Slope Compensation Ratio (VVDD/VSLP) 29 27 25 4.5 V 6.5 V 23 21 19 36 V 12 V 17 15 -55 -25 5 35 65 95 125 155 185 215 RSS(DSCH) Discharge 1400 1200 1000 800 600 400 RSS(CHG) Charge 200 0 -65 -40 -15 TJ - Junction Temperature - °C Figure 12. 8 10 35 60 85 110 135 160 185 210 TJ - Junction Temperature - °C Figure 13. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 TYPICAL CHARACTERISTICS (continued) FB BIAS CURRENT vs JUNCTION TEMPERATURE COMPENSATION SOURCE CURRENT vs JUNCTION TEMPERATURE 180 ICOMP(SRC) - Compensation Source Current - µA 300 IIB(FB) - Feedback Bias Current - nA 160 140 120 100 80 60 40 20 0 -55 -25 5 35 65 95 125 155 185 215 2 50 200 150 10 0 50 0 - 55 -25 TJ - Junction Temperature - °C 35 65 95 12 5 155 18 5 2 15 185 215 TJ - Junction Temperature - °C Figure 14. Figure 15. COMPENSATION SINK CURRENT vs JUNCTION TEMPERATURE VALLEY VOLTAGE CHANGE vs JUNCTION TEMPERATURE 3 5 2 VVLY - Valley Voltage Change - % ICOMP(SNK) - Compensation Sink Current - mA 5 4 3 2 1 1 0 -1 -2 -3 -4 -5 0 -55 -25 5 35 65 95 125 155 185 215 -6 -55 -25 TJ - Junction Temperature - °C Figure 16. 5 35 65 95 125 155 TJ - Junction Temperature - °C Figure 17. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT 9 TPS40210-HT SLVSAD8 – JUNE 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) REGULATOR VOLTAGE vs JUNCTION TEMPERATURE DIS/EN TURN-ON THRESHOLD vs JUNCTION TEMPERATURE 1.2 – – - DIS/EN Turn-On Threshold - V VDIS(EN) 9 VBP - Regulator Voltage - V 8.8 8.6 8.4 ILOAD = 0 m A 8.2 8 7.8 7.6 ILOAD = 5 m A 7.4 -65 -40 -15 10 35 60 85 110 135 160 185 210 1.18 1.16 1.14 1.12 1.1 1.08 1.06 1.04 1.02 1 -55 -25 TJ - Junction Temperature - °C 5 35 65 95 125 155 185 215 TJ - Junction Temperature - °C Figure 18. Figure 19. CURRENT SENSE AMPLIFIER GAIN vs JUNCTION TEMPERATURE ACS - Current Sense Amplifier Gain - V/V 7 6 5 4 3 2 1 0 -55 -25 5 35 65 95 125 155 185 215 TJ - Junction Temperature - °C Figure 20. 10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION BP 9 O Regulator output. Connect a 1.0-mF bypass capacitor from this pin to GND. COMP 4 O Error amplifier output. Connect control loop compensation network between COMP pin and FB pin. DIS/EN 3 I Disable/enable. Pulling this pin high places the part into a shutdown mode. Shutdown mode is characterized by a very low quiescent current. While in shutdown mode, the functionality of all blocks is disabled, and the BP regulator is shut down. This pin has an internal 1-MΩ pulldown resistor to GND. Leaving this pin unconnected enables the device. FB 5 I Error amplifier inverting input. Connect a voltage divider from the output to this pin to set the output voltage. Compensation network is connected between this pin and COMP. GDRV 8 O Connect the gate of the power N-channel MOSFET to this pin. GND 6 – Device ground ISNS 7 I Current sense. Connect an external current sensing resistor between this pin and GND. The voltage on this pin is used to provide current feedback in the control loop and detect an overcurrent condition. An overcurrent condition is declared when ISNS pin voltage exceeds the overcurrent threshold voltage, 150 mV typical. RC 1 I Switching frequency setting. Connect capacitor from RC pin to GND. Connect a resistor from RC pin to VDD of the IC power supply and a capacitor from RC to GND. SS 2 I Soft-start time programming. Connect capacitor from SS pin to GND to program converter soft-start time. This pin also functions as a timeout timer when the power supply is in an overcurrent condition. VDD 10 I System input voltage. Connect a local bypass capacitor from this pin to GND. Depending on the amount of required slope compensation, this pin can be connected to the converter output. See Application Information section for additional details. DGQ PHKK owerPAD PACKAGE PACKAGE (Top V iew) (TOP VIEW) RC 1 10 VDD SS 2 9 BP DIS/EN 3 8 GDRV COMP 4 7 ISNS FB 5 6 GND Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT 11 TPS40210-HT SLVSAD8 – JUNE 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM DIS/EN 3 COMP 4 FB 5 10 VDD + + SS 2 OC Fault Soft Start and Overcurrent E/A SS Ref 700 mV LDO Oscillator and Slope Compensation 1 BP 8 GDRV 6 GND 7 ISNS Driver Enable E/A RC 9 PWM Logic + Gain = 6 OC Fault 150 mV UVLO + LEB UDG-07107 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 APPLICATION INFORMATION Minimum On-Time and Off-Time Considerations The TPS40210 has a minimum off time of approximately 200 ns and a minimum on time of 300 ns. These two constraints place limitations on the operating frequency that can be used for a given input-to-output conversion ratio. See Figure 3 for the maximum frequency that can be used for a given duty cycle. The duty cycle at which the converter operates is dependent on the mode in which the converter is running. If the converter is running in discontinuous conduction mode, the duty cycle varies with changes to the load much more than it does when running in continuous conduction mode. In continuous conduction mode, the duty cycle is related primarily to the input and output voltages. VOUT + VD 1 = VIN 1- D æ æ VIN D = ç1 - ç ç V è è OUT + VD (1) öö ÷ ÷÷ øø (2) In discontinuous mode, the duty cycle is a function of the load, input and output voltages, inductance, and switching frequency. D= 2 ´ (VOUT + VD )´ IOUT ´ L ´ fSW (VIN )2 (3) All converters using a diode as the freewheeling or catch component have a load current level at which they transition from discontinuous conduction to continuous conduction. This is the point at which the inductor current falls to zero. At higher load currents, the inductor current does not fall to zero but remains flowing in a positive direction and assumes a trapezoidal wave shape as opposed to a triangular wave shape. This load boundary between discontinuous conduction and continuous conduction can be found for a set of converter parameters as shown in Equation 4. 2 VOUT + VD - VIN )´ (VIN ) ( IOUT(crit) = 2 2 ´ (VOUT + VD ) ´ fSW ´ L (4) For loads higher than the result of Equation 4, the duty cycle is given by Equation 2, and for loads less than the results of Equation 4, the duty cycle is given Equation 3. For Equation 1 through Equation 4, the variable definitions are as follows: • VOUT is the output voltage of the converter in V • VD is the forward conduction voltage drop across the rectifier or catch diode in V • VIN is the input voltage to the converter in V • IOUT is the output current of the converter in A • L is the inductor value in H • f SW is the switching frequency in Hz Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT 13 TPS40210-HT SLVSAD8 – JUNE 2010 www.ti.com Setting the Oscillator Frequency The oscillator frequency is determined by a resistor and capacitor connected to the RC pin of the TPS40210. The capacitor is charged to a level of approximately VVDD/20 by current flowing through the resistor and is then discharged by a transistor internal to the TPS40210. The required resistor for a given oscillator frequency is found from either Figure 2 or Equation 5. RT = 1 5.8 ´ 10 -8 ´ fSW ´ C T + 8 ´ 10 - 10 2 ´ fSW + 1.4 ´ 10 -7 ´ fSW - 1.5 ´ 10 - 4 + 1.7 ´ 10 - 6 ´ C T - 4 ´ 10 - 9 ´ C T 2 where • • • RT is the timing resistance in kΩ f SW is the switching frequency in kHz CT is the timing capacitance in pF (5) For most applications, a capacitor in the range of 68 pF to 120 pF gives the best results. Resistor values should be limited to between 100 kΩ and 1 MΩ as well. If the resistor value falls below 100 kΩ, decrease the capacitor size and recalculate the resistor value for the desired frequency. As the capacitor size decreases below 47 pF, the accuracy of Equation 5 degrades, and empirical means may be needed to fine tune the timing component values to achieve the desired switching frequency. Synchronizing the Oscillator The TPS40210 can be synchronized to an external clock source. Figure 21 shows the functional diagram of the oscillator. When synchronizing the oscillator to an external clock, the RC pin must be pulled below 150 mV for 20 ns or more. The external clock frequency must be higher than the free running frequency of the converter as well. When synchronizing the controller, if the RC pin is held low for an excessive amount of time, erratic operation may occur. The maximum amount of time that the RC pin should be held low is 50% of a nominal output pulse, or 10% of the period of the synchronization frequency. Under circumstances where the duty cycle is less than 50%, a Schottky diode connected from the RC pin to an external clock may be used to synchronize the oscillator. The cathode of the diode is connected to the RC pin. The trip point of the oscillator is set by an internal voltage divider to be 1/20 of the input voltage. The clock signal must have an amplitude higher than this trip point. When the clock goes low, it allows the reset current to restart the RC ramp, synchronizing the oscillator to the external clock. This provides a simple single-component method for clock synchronization. VDD 8 10 VIN + RRC External Frequency Synchronization (optional) RC Q R Q CLK + 1 + CRC S 150 mV GND 65 TPS40210/11 UDG-08063 Figure 21. Oscillator Functional Diagram 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 VDD Amplitude > 8 10 VIN VIN + 20 RRC Duty Cycle < 50% RC Q R Q CLK + 1 Frequency > Controller Frequency + CRC S 150 mV GND 65 TPS40210/11 UDG-08064 Figure 22. Diode Connected Synchronization Current Sense and Overcurrent The TPS40210 are current-mode controllers and use a resistor in series with the source terminal power FET to sense current for both the current-mode control and overcurrent protection. The device enters a current-limit state if the voltage on the ISNS pin exceeds the current-limit threshold voltage VISNS(oc) from the electrical specifications table. When this happens, the controller discharges the SS capacitor through a relatively high impedance and then attempts to restart. The amount of output current that causes this to happen is dependent on several variables in the converter. TPS40210/11 VIN 10 VDD TPS40210/11 L RT VOUT VDD 10 1 RC CT 6 GDRV 8 ISNS 7 GND UDG-07119 RIFLT CIFLT GND RISNS 6 UDG-07120 Figure 23. Oscillator Components Figure 24. Current Sense Components Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT 15 TPS40210-HT SLVSAD8 – JUNE 2010 www.ti.com The load current overcurrent threshold is set by proper choice of RISNS. If the converter is operating in discontinuous mode the current sense resistor is found in Equation 6. RISNS = fSW ´ L ´ VISNS(oc) 2 ´ L ´ fSW ´ IOUT(oc) ´ (VOUT + VD - VIN ) (6) If the converter is operating in continuous conduction mode RISNS can be found in Equation 7. RISNS = VISNS VISNS = æ IOUT ö æ IRIPPLE ö æ IOUT ö æ D ´ VIN ö + ç 1- D ÷ + ç 2 ÷ø çç (1 - D ) ÷÷ ç 2 ´ fSW ´ L ÷ è ø è ø è ø è where • • • • • • • • RISNS is the value of the current sense resistor in Ω. VISNS(oc) is the overcurrent threshold voltage at the ISNS pin (from electrical specifications) D is the duty cycle (from Equation 2) f SW is the switching frequency in Hz VIN is the input voltage to the power stage in V (see text) L is the value of the inductor in H IOUT(oc) is the desired overcurrent trip point in A VD is the drop across the diode in Figure 24 (7) The TPS40210 have a fixed undervoltage lockout (UVLO) that allows the controller to start at a typical input voltage of 4.25 V. If the input voltage is slowly rising, the converter might have less than its designed nominal input voltage available when it has reached regulation. As a result, this may decreases the apparent current-limit load current value and must be taken into consideration when selecting RISNS. The value of VIN used to calculate RISNS must be the value at which the converter finishes startup. The total converter output current at startup is the sum of the external load current and the current required to charge the output capacitor(s). See the Soft Start section of this data sheet for information on calculating the required output capacitor charging current. The topology of the standard boost converter has no method to limit current from the input to the output in the event of a short circuit fault on the output of the converter. If protection from this type of event is desired, it is necessary to use some secondary protection scheme such as a fuse or rely on the current limit of the upstream power source. Current Sense and Sub-Harmonic Instability A characteristic of peak current-mode control results in a condition where the current control loop can exhibit instability. This results in alternating long and short pulses from the pulse-width modulator. The voltage loop maintains regulation and does not oscillate, but the output ripple voltage increases. The condition occurs only when the converter is operating in continuous conduction mode, and the duty cycle is 50% or greater. The cause of this condition is described in Texas Instruments literature number SLUA101, available at www.ti.com. The remedy for this condition is to apply a compensating ramp from the oscillator to the signal going to the pulse-width modulator. In the TPS40210, the oscillator ramp is applied in a fixed amount to the pulse-width modulator. The slope of the ramp is given in Equation 8. æV ö s e = fSW ´ ç VDD ÷ è 20 ø (8) To ensure that the converter does not enter into sub-harmonic instability, the slope of the compensating ramp signal must be at least half of the down slope of the current ramp signal. Because the compensating ramp is fixed in the TPS40210, this places a constraint on the selection of the current sense resistor. The down slope of the current sense wave form at the pulse-width modulator is described in Equation 9. m2 = 16 A CS ´ RISNS ´ (VOUT + VD - VIN ) L Submit Documentation Feedback (9) Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 Since the slope compensation ramp must be at least half, and preferably equal to the down slope of the current sense waveform seen at the pulse-width modulator, a maximum value is placed on the current sense resistor when operating in continuous mode at 50% duty cycle or greater. For design purposes, some margin should be applied to the actual value of the current sense resistor. As a starting point, the actual resistor chosen should be 80% or less that the value calculated in Equation 10. This equation calculates the resistor value that makes the slope compensation ramp equal to one half of the current ramp downslope. Values no more than 80% of this result are acceptable. RISNS(max) = VVDD ´ L ´ fSW 60 ´ (VOUT + VD - VIN ) where • • • • • • • Se is the slope of the voltage compensating ramp applied to the pulse-width modulator in V/s f SW is the switching frequency in Hz VVDD is the voltage at the VDD pin in V m2 is the down slope of the current sense waveform seen at the pulse-width modulator in V/s RISNS is the value of the current sense resistor in Ω VOUT is the converter output voltage VIN is the converter power stage input voltage VD is the drop across the diode in Figure 24 (10) It is possible to increase the voltage compensation ramp slope by connecting the VDD pin to the output voltage of the converter instead of the input voltage as shown in Figure 24. This can help in situations where the converter design calls for a large ripple current value in relation to the desired output current limit setting. NOTE Connecting the VDD pin to the output voltage of the converter affects the startup voltage of the converter since the controller undervoltage lockout (UVLO) circuit monitors the VDD pin and senses the input voltage less the diode drop before startup. The effect is to increase the startup voltage by the value of the diode voltage drop. If an acceptable RISNS value is not available, the next higher value can be used and the signal from the resistor divided down to an acceptable level by placing another resistor in parallel with CISNS. Current Sense Filtering In most cases, a small filter placed on the ISNS pin improves performance of the converter. These are the components RIFLT and CIFLT in Figure 24. The time constant of this filter should be approximately 10% of the nominal pulse width of the converter. The pulse width can be found using Equation 11. tON = D fSW (11) The suggested time constant is then RIFLT ´ CIFLT = 0.1´ tON (12) The range of RIFLT should be from about 1 kΩ to 5 kΩ for best results. Higher values can be used, but this raises the impedance of the ISNS pin connection more than necessary and can lead to noise-pickup issues in some layouts. CISNS should be located as close as possible to the ISNS pin as well to provide noise immunity. Soft Start The soft-start feature of the TPS40210 is a closed-loop soft start, meaning that the output voltage follows a linear ramp that is proportional to the ramp generated at the SS pin. This ramp is generated by an internal resistor connected from the BP pin to the SS pin and an external capacitor connected from the SS pin to GND. The SS pin voltage (VSS) is level shifted down by approximately VSS(ofst) (approximately 1 V) and sent to one of the “+” inputs (the “+” input with the lowest voltage dominates) of the error amplifier. When this level-shifted voltage (VSSE) starts to rise at time t1 (see Figure 25), the output voltage that the controller expects rises as well. Since VSSE starts at near 0 V, the controller attempts to regulate the output voltage from a starting point of zero volts. It Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT 17 TPS40210-HT SLVSAD8 – JUNE 2010 www.ti.com cannot do this, due to the converter architecture. The output voltage starts from the input voltage less the drop across the diode (VIN – VD) and rises from there. The point at which the output voltage starts to rise (t2) is when the VSSE ramp passes the point where it is commanding more output voltage than (VIN – VD). This voltage level is labeled VSSE(1). The time required for the output voltage to ramp from a theoretical zero to the final regulated value (from t1 to t3) is determined by the time it takes for the capacitor connected to the SS pin (CSS) to rise through a 700-mV range, beginning at VSS(ofst) above GND. TPS40210/11 VSS RSS(chg) 700 mV REF Error Amplifier SS VSS(ofst)+700 mV VSSE VSS(ofst) RSS(dchg) VSSE(1) t0 + + 2 t1 VIN - VD VOUT t2 t3 DIS UVLO OC Fault FB 5 COMP 4 UDG-07121 Figure 25. SS Pin Voltage and Output Voltage 18 Figure 26. SS Pin Functional Circuit Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 The required capacitance for a given soft start time t3 – t1 in Figure 25 is calculated in Equation 13. CSS = tSS æ VBP - VSS(ofst) RSS ´ ln ç çV - V SS(ofst) + VFB è BP ( ö ÷ ÷ ø ) where • • • • • • tSS is the soft-start time RSS(chg) is the SS charging resistance in Ω, typically 500 kΩ CSS is the value of the capacitor on the SS pin, in F VBP is the value of the voltage on the BP pin in V VSS(ofst) is the approximate level shift from the SS pin to the error amplifier (~1 V) VFB is the error amplifier reference voltage, 700 mV typical (13) Note that tSS is the time it takes for the output voltage to rise from 0 V to the final output voltage. Also note the tolerance on RSS(chg) given in the electrical specifications table. This contributes to some variability in the output voltage rise time, and margin must be applied to account for it in design. Also take note of VBP. Its value varies depending on input conditions. For example, a converter operating from a slowly rising input initializes VBP at a fairly low value and increases during the entire startup sequence. If the controller has a voltage above 8 V at the input and the DIS pin is used to stop and then restart the converter, VBP is approximately 8 V for the entire startup sequence. The higher the voltage on BP, the shorter the startup time is and conversely, the lower the voltage on BP, the longer the startup time is. The soft-start time (tSS) must be chosen long enough so that the converter can start up without going into an overcurrent state. Since the overcurrent state is triggered by sensing the peak voltage on the ISNS pin, that voltage must be kept below the overcurrent threshold voltage VISNS(oc). The voltage on the ISNS pin is a function of the load current of the converter, the rate of rise of the output voltage and the output capacitance, and the current sensing resistor. The total output current that must be supported by the converter is the sum of the charging current required by the output capacitor and any external load that must be supplied during startup. This current must be less than the IOUT(oc) value used in Equation 6 or Equation 7 (depending on the operating mode of the converter) to determine the current sense resistor value. In these equations, the actual input voltage at the time that the controller reaches the final output voltage is the important input voltage to use in the calculations. If the input voltage is slowly rising and is at less than the nominal input voltage when the startup time ends, the output current limit is less than IOUT(oc) at the nominal input voltage. The output capacitor charging current must be reduced (decrease COUT or increase the tSS) or IOUT(oc) must be increased and a new value for RISNS calculated. IC(chg) = COUT ´ VOUT tSS (14) COUT ´ VOUT (IOUT(oc) - IEXT) tSS > where • • • • • • IC(chg) is the output capacitor charging current in A COUT is the total output capacitance in F VOUT is the output voltage in V tSS is the soft start time from Equation 13 IOUT(oc) is the desired over current trip point in A IEXT is any external load current in A (15) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT 19 TPS40210-HT SLVSAD8 – JUNE 2010 www.ti.com The capacitor on the SS pin (CSS) also plays a role in overcurrent functionality. It is used as the timer between restart attempts. The SS pin is connected to GND through a resistor, RSS(dchg), when the controller senses an overcurrent condition. Switching stops and nothing else happens until the SS pin discharges to the soft-start reset threshold, VSS(rst). At this point, the SS pin capacitor is allowed to charge again through the charging resistor RSS(chg), and the controller restarts from that point. The shortest time between restart attempts occurs when the SS pin discharges from VSS(ofst) (approximately 1 V) to VSS(rst) (150 mV) and then back to VSS(ofst) and switching resumes. In actuality, this is a conservative estimate since switching does not resume until the VSSE ramp rises to a point where it is commanding more output voltage than exists at the output of the controller. This occurs at some SS pin voltage greater than VSS(ofst) and depends on the voltage that remains on the output overvoltage the converter while switching has been halted. The fastest restart time can be calculated by using Equation 16, Equation 17, and Equation 18. æ VSS(ofst) tDCHG = RSS(dchg) ´ CSS ´ ln ç ç VSS(rst) è ( ( ö ÷ ÷ ø (16) ) ö÷ )÷ø æ V -V BP SS(rst) tCHG = RSS(chg) ´ CSS ´ ln ç ç V -V SS(ofst) è BP (17) tRSTRT(min ) = tCHG + tDCHG (18) VBP VSS tRSTR(min) VSS(ofst) VSS(rst) T - Time Figure 27. Soft Start During Overcurrent 20 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 BP Regulator The TPS40210 has an on-board linear regulator that supplies power for the internal circuitry of the controller, including the gate driver. This regulator has a nominal output voltage of 8 V and must be bypassed with a 1-mF capacitor. If the voltage at the VDD pin is less than 8 V, the voltage on the BP pin is also less, and the gate drive voltage to the external FET is reduced from the nominal 8 V. This should be considered when choosing a FET for the converter. Connecting external loads to this regulator can be done, but care must be taken to ensure that the thermal rating of the device is observed, because there is no thermal shutdown feature in this controller. Exceeding the thermal ratings causes out-of-specification behavior and can lead to reduced reliability. The controller dissipates more power when there is an external load on the BP pin and is tested for dropout voltage for up to 5-mA load. When the controller is in the disabled state, the BP pin regulator also shuts off so loads connected there power down as well. When the controller is disabled with the DIS/EN pin, this regulator is turned off. The total power dissipation in the controller can be calculated as follows. The total power is the sum of PQ, PG and PE. PQ = VVDD ´ IVDD(en) (19) PG = VVDD ´ Qg ´ fSW (20) PE = VVDD ´ IEXT where • • • • • • • • PQ is the quiescent power of the device in W VVDD is the VDD pin voltage in V IVDD(en) is the quiescent current of the controller when enabled but not switching in A PG is the power dissipated by driving the gate of the FET in W Qg is the total gate charge of the FET at the voltage on the BP pin in C f SW is the switching frequency in Hz PE is the dissipation caused be external loading of the BP pin in W IEXT is the external load current in A (21) Shutdown (DIS/EN Pin) The DIS/EN pin is an active-high shutdown command for the controller. Pulling this pin above 1.2 V causes the controller to completely shut down and enter a low current consumption state. In this state, the regulator connected to the BP pin is turned off. There is an internal 1.1-MΩ pull-down resistor connected to this pin that keeps the pin at GND level when left floating. If this function is not used in an application, it is best to connect this pin to GND Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT 21 TPS40210-HT SLVSAD8 – JUNE 2010 www.ti.com Control Loop Considerations There are two methods to design a suitable control loop for the TPS40210. The first (and preferred, if equipment is available) is to use a frequency-response analyzer to measure the open-loop modulator and power stage gain and to then design compensation to fit that. The usage of these tools for this purpose is well documented with the literature that accompanies the tool and is not discussed here. The second option is to make an initial guess at compensation, and then evaluate the transient response of the system to see if the compensation is acceptable to the application or not. For most systems, an adequate response can be obtained by simply placing a series resistor and capacitor (RFB and CFB) from the COMP pin to the FB pin as shown in Figure 28. VIN TPS40210 1 RC 2 SS 3 DIS/EN L VOUT VDD 10 BP 9 GDRV 8 CHF CFB RFB COUT RIFLT 4 COMP 5 FB ISNS 7 GND 6 CIFLT ROUT RSENSE R1 R2 UDG-07177 Figure 28. Basic Compensation Network The natural phase characteristics of most capacitors used for boost outputs combined with the current mode control provide adequate phase margin when using this type of compensation. To determine an initial starting point for the compensation, the desired crossover frequency must be considered when estimating the control to output gain. The model used is a current source into the output capacitor and load. When using these equations, the loop bandwidth should be no more than 20% of the switching frequency, f SW. A more reasonable loop bandwidth would be 10% of the switching frequency. Be sure to evaluate the transient response of the converter over the expected load range to ensure acceptable operation. K CO = gM ´ ZOUT (fCO ) = 19.1A 0.13 ´ L ´ gM = 22 fSW ROUT 2 V ´ 0.146 W = 2.80 (22) 0.13 ´ 10 mH ´ = 600kHz 240 W 2 (RISNS ) ´ (120 ´ RISNS + L ´ fSW ) (12mW ) ´ (120 ´ 12mW + 10 mH ´ 600kHz ) Submit Documentation Feedback = 19.1 A V (23) Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 (1+ (2p ´ f ´ R L ZOUT = ROUT ´ ( 2 ESR 2 ´ COUT ) 2 ) ) 2 1 + (ROUT ) + 2 ´ ROUT ´ RESR + (RESR ) ´ (2p ´ fL ´ COUT ) where • • • • • • • • • • KCO is the control to output gain of the converter, in V/V gM is the transconductance of the power stage and modulator, in S ROUT is the output load equivalent resistance, in Ω ZOUT is the output impedance, including the output capacitor, in Ω RISNS is the value of the current sense resistor, in Ω L is the value of the inductor, in H COUT is the value of the output capacitance, in mF RESR is the equivalent series resistance of COUT, in Ω f SW is the switching frequency, in Hz f L is the desired crossover frequency for the control loop, in Hz (24) These equations assume that the operation is discontinuous and that the load is purely resistive. The gain in continuous conduction can be found by evaluating Equation 23 at the resistance that gives the critical conduction current for the converter. Loads that are more like current sources give slightly higher gains than predicted here. To find the gain of the compensation network required for a control loop of bandwidth f L, take the reciprocal of Equation 22. K COMP = 1 K CO = 1 = 0.356 2.80 (25) The GBWP of the error amplifier is only specified to be at least 1.5 MHz. If KCOMP multiplied by the fL is greater than 750 kHz, reduce the desired loop crossover frequency until this condition is satisfied. This ensures that the high-frequency pole from the error amplifier response with the compensation network in place does not cause excessive phase lag at the f L and decrease phase margin in the loop. The R-C network connected from COMP to FB places a zero in the compensation response. That zero should be approximately 1/10th of the desired crossover frequency, f L. With that being the case, RFB and CFB can be found from Equation 26 and Equation 27 RFB = CFB = R1 = R1´ K COMP K CO (26) 10 2p ´ fL ´ RFB where • • R1 is in fL is the loop crossover frequency desired, in Hz. RFB is the feedback resistor in CFB is the feedback capacitance in mF. (27) Thought not strictly necessary, it is recommended that a capacitor be added between COMP and FB to provide high-frequency noise attenuation in the control loop circuit. This capacitor introduces another pole in the compensation response. The allowable location of that pole frequency determines the capacitor value. As a starting point, the pole frequency should be 10 × fL. The value of CHF can be found from Equation 28. CHF = 1 20p ´ fL ´ RFB (28) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT 23 TPS40210-HT SLVSAD8 – JUNE 2010 www.ti.com The error amplifier GBWP will usually be higher, but is ensured by design to be at least 1.5 MHz. If the gain required in Equation 25 multiplied by 10 times the desired control loop crossover frequency, the high-frequency pole introduced by CHF is overridden by the error amplifier capability and the effective pole is lower in frequency. If this is the case, CHF can be made larger to provide a consistent high-frequency roll off in the control loop design. Equation 29 calculates the required CHF in this case. CHF = 1 6 2p ´ 1.5 ´ (10 ) ´ RFB where • • CHF is the high-frequency roll-off capacitor value in mF RFB is the mid-band gain-setting resistor value in Ω (29) Gate Drive Circuit Some applications benefit from the addition of a resistor connected between the GDRV pin and the gate of the switching MOSFET. In applications that have particularly stringent load regulation (under 0.75%) requirements and operate from input voltages above 5 V, or are sensitive to pulse jitter in the discontinuous conduction region, this resistor is recommended. The recommended starting point for the value of this resistor can be calculated from Equation 30. RG = 105 QG where • • QG is the MOSFET total gate charge at 8-V VGS in nC. RG is the suggested starting point gate resistance in Ω. (30) VIN L TPS40210/11 VDD 10 VOUT RG GDRV 8 ISNS 7 GND 6 UDG-07196 Figure 29. Gate Drive Resistor TPS40211 The only difference between the TPS40210 and the TPS40211 is the reference voltage that the error amplifier uses to regulate the output voltage. The TPS40211 uses a 260-mV reference and is intended for applications where the output is actually a current instead of a regulated voltage. A typical example of an application of this type is an LED driver. An example schematic is shown in Figure 30. 24 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 VIN IOUT TPS40210/11 1 RC 2 SS 3 DIS/EN 4 COMP L VDD 10 BP 9 GDRV 8 ISNS 7 RIFB 5 GND FB 6 UDG-07197 Figure 30. Typical LED Drive Schematic The current in the LED string is set by the choice of the resistor RISNS as shown in Equation 31. RIFB = VFB IOUT where • • • RIFB is the value of the current sense resistor for the LED string in Ω. VFB is the reference voltage for the TPS40211 in V (0.260 V typ). IOUT is the desired DC current in the LED string in A. (31) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT 25 TPS40210-HT SLVSAD8 – JUNE 2010 www.ti.com ADDITIONAL REFERENCES References These references may be found on the web at www.power.ti.com under Technical Documents. Many design tools and links to additional references, may also be found at www.power.ti.com 1. Design and Application Guide for High Speed MOSFET Gate Drive Circuits, SEM 1400, 2001 Seminar Series 2. Designing Stable Control Loops, SEM 1400, 2001 Seminar Series 3. Additional PowerPADTM information may be found in Applications Briefs SLMA002 and SLMA004 4. QFN/SON PCB Attachment, Texas Instruments Literature Number SLUA271, June 2002 26 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 DESIGN EXAMPLE 1 12-V to 24-V Non-Synchronous Boost Regulator The following example illustrates the design process and component selection for a 12-V to 24-V non-synchronous boost regulator using the TPS40210 controller. + + Figure 31. TPS40210 Design Example – 8-V to 24-V at 2-A Table 2. TPS40210 Design Example Specifications PARAMETER CONDITIONS MIN NOM MAX UNIT INPUT CHARACTERISTICS VIN Input voltage IIN Input current 8 12 No load input current VIN(UVLO) 14 4.4 0.05 Input undervoltage lockout 4.5 V A V OUTPUT CHARACTERISTICS VOUT Output voltage 23.5 24.0 Line regulation 24.5 V 1% Load regulation 1% VOUT(ripple) Output voltage ripple 500 IOUT Output current IOCP Output overcurrent inception point 8 V ≤ VIN ≤ 14 V 0.2 1 2 3.5 mVPP A Transient response ΔI Load step Load slew rate Overshoot threshold voltage Settling time 1 A 1 A/ms 500 mV 5 ms Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT 27 TPS40210-HT SLVSAD8 – JUNE 2010 www.ti.com Table 2. TPS40210 Design Example Specifications (continued) PARAMETER CONDITIONS MIN NOM MAX UNIT 600 kHz SYSTEM CHARACTERISTICS fSW Switching frequency hPK Peak efficiency VIN = 12 V, 0.2 A ≤ IOUT ≤ 2 A 95% h Full load efficiency VIN = 12 V, IOUT = 2 A 94% TOP Operating temperature range 10 V ≤ VIN ≤ 14 V, 0.2 A ≤ IOUT ≤ 2 A 25 °C MECHANICAL DIMENSIONS W Width 1.5 L Length 1.5 h Height 0.5 in Step-By-Step Design Procedure Duty Cycle Estimation The duty cycle of the main switching MOSFET is estimated using Equation 32 and Equation 33. DMIN » DMAX » VOUT - VIN(max) + VFD VOUT + VFD = 24 V - 14 V + 0.5 V = 42.8% 24 V + 0.5 V (32) VOUT - VIN(m in) + VFD 24 V - 8 V + 0.5 V = = 67.3% VOUT + VFD 24 V + 0.5 V (33) Using and estimated forward drop of 0.5 V for a Schottky rectifier diode, the approximate duty cycle is 42.8% (minimum) to 67.3% (maximum). Inductor Selection The peak-to-peak ripple is limited to 30% of the maximum output current. ILrip(m ax) = 0.3 ´ IOUT(m ax) 1 - DMIN = 0.3 ´ 2 = 1.05 A 1 - 0.428 (34) The minimum inductor size can be estimated using Equation 35. VIN(max) 1 14 V 1 LMIN » ´ DMIN ´ = ´ 0.428 ´ = 9.5 mH ILrip(max) fSW 1.05 A 600kHz (35) The next higher standard inductor value of 10 mH is selected. The ripple current is estimated by Equation 36. IRIPPLE » VIN 1 12 V 1 ´D´ = ´ 0.50 ´ = 1.02 A L 10 m H 600 kHz fSW (36) V 1 8V 1 IRIPPLE(Vinmin) » IN ´ D ´ = ´ 0.673 ´ = 0.89 A fSW 10 mH L 600kHz (37) The worst-case peak-to-peak ripple current occurs at 50% duty cycle and is estimated as 1.02 A. Worst-case RMS current through the inductor is approximated by Equation 38. ILrms = (I ( ) ) + ( 2 L avg 1 I 12 RIPPLE ) 2 æ IOUT(max) » ç ç 1- D MAX è 2 ö ÷÷ + ø (112IRIPPLE(VINmin) ) 2 2 2 æ ö = ç ÷ + è 1 - 0.673 ø ((112)´ 0.817A ) 2 = 6.13 Arms (38) The worst case RMS inductor current is 6.13 Arms. The peak inductor current is estimated by Equation 39. 28 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 ILpeak » IOUT(max) 1 - DMAX + (12 )IRIPPLE(Vinmin) = 2 + (12 )0.718 = 6.57 A 1 - 0.673 (39) A 10-mH inductor with a minimum RMS current rating of 6.13 A and minimum saturation current rating of 6.57 A must be selected. A TDK RLF12560T-100M-7R5 7.5-A 10-mH inductor is selected. This inductor power dissipation is estimated by Equation 40. 2 PL » (ILrms ) ´ DCR (40) The TDK RLF12560T-100M-7R5 12.4-mΩ DCR dissipates 466 mW of power. Rectifier Diode Selection A low-forward voltage drop Schottky diode is used as a rectifier diode to reduce its power dissipation and improve efficiency. Using 80% derating, on VOUT for ringing on the switch node, the rectifier diode minimum reverse break-down voltage is given by Equation 41. V V(BR)R(min) ³ OUT = 1.25 ´ VOUT = 1.25 ´ 24 V = 30 V 0.8 (41) The diode must have reverse breakdown voltage greater than 30 V. The rectifier diode peak and average currents are estimated by Equation 42 and Equation 43. ID (avg ) » IOUT (m ax ) = 2 A (42) ID(peak ) = IL(peak ) = 6.57 A (43) For this design, 2-A average and 6.57-A peak is The power dissipation in the diode is estimated by Equation 44. PD(max) » VF ´ IOUT(max) = 0.5 V ´ 2 A = 1W (44) For this design, the maximum power dissipation is estimated as 1 W. Reviewing 30-V and 40-V Schottky diodes, the MBRS340T3 40-V 3-A diode in an SMC package is selected. This diode has a forward voltage drop of 0.48 V at 6 A, so the conduction power dissipation is approximately 960 mW, less than half its rated power dissipation. Output Capacitor Selection Output capacitors must be selected to meet the required output ripple and transient specifications. COUT = 8 ESR = IOUT ´ D æ 2 A ´ 0.673 ö 1 1 ´ = 8ç = 35 mF ÷´ VOUT(ripple) fSW è 500mV ø 600kHz (45) VOUT(ripple ) 7 7 500mV ´ = ´ = 95mW 8 IL(peak ) - IOUT 8 6.57 A - 2 A (46) A Panasonic EEEFC1V330P 35-V 33-mF, 120-mΩ bulk capacitor and 6.8-mF ceramic capacitor is selected to provide the required capacitance and ESR at the switching frequency. The combined capacitances of 39.8 mF and 60 mΩ are used in compensation calculations. Input Capacitor Selection Since a boost converter has continuous input current, the input capacitor senses only the inductor ripple current. The input capacitor value can be calculated by Equation 47 and Equation 48 . Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT 29 TPS40210-HT SLVSAD8 – JUNE 2010 CIN > www.ti.com IL(ripple ) 4 ´ VIN(ripple ) ´ fSW ESR < VIN(ripple ) 2 ´ IL(ripple ) = = 1.02 A = 7.0 mF 4 ´ 60mV ´ 600kHz (47) 60mV = 30mW 2 ´ 1.02 A (48) For this design, to meet a maximum input ripple of 60 mV, a minimum 7.0-mF input capacitor with ESR less than 30 mΩ is needed. A 10-mF X7R ceramic capacitor is selected. Current Sense and Current Limit The maximum allowable current sense resistor value is limited by both the current limit and sub-harmonic stability. These two limitations are given by Equation 49 and Equation 50. RISNS < RISNS < VOCP(min) ( 1.1´ IL(peak ) + IDrive = ) 110mV = 14.2mW 1.1´ 6.57 A + 0.50 A (49) VDDMAX ´ L ´ fSW 14 V ´ 10 mH ´ 600kHz = = 133mW 60 ´ (VOUT + Vfd - VIN ) 60 ´ (24 V + 0.48 V - 14 V) (50) The current limit requires a resistor less than 14.2 mΩ, and stability requires a sense resistor less than 133 mΩ. A 10-mΩ resistor is selected. Approximately 2-mΩ of routing resistance is added in compensation calculations. Current Sense Filter To remove switching noise from the current sense, an R-C filter is placed between the current sense resistor and the ISNS pin. A resistor with a value between 1 kΩ and 5 kΩ is selected, and a capacitor value is calculated by Equation 51. CIFLT = 0.1´ DMIN 0.1´ 0.428 = = 71pF fSW ´ RIFLT 600kHz ´ 1kW (51) For a 1-kΩ filter resistor, 71 pF is calculated and a 100-pF capacitor is selected. Switching MOSFET Selection The TPS40210 drives a ground referenced N-channel FET. The RDS(on) and gate charge are estimated based on the desired efficiency target. æ1 ö æ1 ö æ 1 ö - 1÷ = 2.526 W PDISS(total) » POUT ´ ç - 1÷ = VOUT ´ IOUT ´ ç - 1÷ = 24 V ´ 2 A ´ ç 0.95 h h è ø è ø è ø (52) For a target of 95% efficiency with a 24-V input voltage at 2 A, maximum power dissipation is limited to 2.526 W. The main power dissipating devices are the MOSFET, inductor, diode, current sense resistor and the integrated circuit, the TPS40210. PFET < PDISS(total) - PL - PD - PRisns - VIN(max) ´ IVDD (53) This leaves 740 mW of power dissipation for the MOSFET. This can likely cause an SO-8 MOSFET to get too hot, so power dissipation is limited to 500 mW. Allowing half for conduction and half for switching losses, we can determine a target RDS(on) and QGS for the MOSFET by Equation 54 and Equation 55. QGS < 3 ´ PFET ´ IDRIVE 3 ´ 0.50 W ´ 0.50 A = = 13.0nC 2 ´ VOUT ´ IOUT ´ fSW 2 ´ 24 V ´ 2 A ´ 600kHz (54) A target MOSFET gate-to-source charge of less than 13.0 nC is calculated to limit the switching losses to less than 250 mW. 30 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 RDS(on ) < PFET = 2 2 ´ (IRMS ) ´ D 0.50 W 2 ´ 6.132 ´ 0.674 = 9.8mW (55) A target MOSFET RDS(on) of 9.8 mΩ is calculated to limit the conduction losses to less than 250 mW. Reviewing 30-V and 40-V MOSFETs, an Si4386DY 9-mΩ MOSFET is selected. A gate resistor was added per Equation 30. The maximum gate charge at Vgs = 8 V for the Si4386DY is 33.2 nC, this implies RG = 3.3 Ω. Feedback Divider Resistors The primary feedback divider resistor (RFB) from VOUT to FB should be selected between 10-kΩ and 100-kΩ to maintain a balance between power dissipation and noise sensitivity. For a 24-V output a high feedback resistance is desirable to limit power dissipation so RFB = 51.1 kΩ is selected. RBIAS = VFB ´ RFB 0.700 V ´ 51.1kW = = 1.53kW VOUT - VFB 24 V - 0.700 V (56) RBIAS = 1.50 kΩ is selected. Error Amplifier Compensation While current mode control typically requires only Type II compensation, it is desirable to layout for Type III compensation to increase flexibility during design and development. Current mode control boost converters have higher gain with higher output impedance, so it is necessary to calculate the control loop gain at the maximum output impedance, estimated by Equation 57. ROUT(max ) = VOUT IOUT(min ) = 24 V = 240 W 0.1A (57) The transconductance of the TPS40210 current mode control can be estimated by Equation 58. 0.13 ´ L ´ gM = fSW ROUT 0.13 ´ 10 mH ´ = 2 (RISNS ) ´ (120 ´ RISNS + L ´ fSW ) 600kHz 240 W = 19.1 A 2 (12mW ) ´ (120 ´ 12mW + 10 mH ´ 600kHz ) V (58) The maximum output impedance ZOUT, can be estimated by Equation 59. (1+ (2p ´ f ´ R ESR ZOUT (f ) = ROUT ´ ( 2 ) ) )´ (2p ´ f ´ C 2 ´ COUT ) 1 + (ROUT ) + 2 ´ ROUT ´ RESR + (RESR 2 OUT )2 (59) (1+ (2p ´ 20kHz ´ 60mW ´ 39.8 mF) ) 1 + ((240 W ) + 2 ´ 240 W ´ 60mW + (60mW ) )´ (2p ´ 20kHz ´ 39.8 mF ) 2 ZOUT (fCO ) = 240 W ´ 2 2 2 = 0.146 W (60) The modulator gain at the desired cross-over can be estimated by Equation 61. K CO = gM ´ ZOUT (fCO ) = 19.1A V ´ 0.146 W = 2.80 (61) The feedback compensation network needs to be designed to provide an inverse gain at the cross-over frequency for unit loop gain. This sets the compensation mid-band gain at a value calculated in Equation 62. K COMP = 1 K CO = 1 = 0.356 2.80 (62) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT 31 TPS40210-HT SLVSAD8 – JUNE 2010 www.ti.com To set the mid-band gain of the error amplifier to KCOMP use Equation 63. R4 = R7 ´ K COMP = R7 51.1kW = = 18.2kW K CO 2.80 (63) R4 = 18.7 kΩ selected. Place the zero at 10th the desired cross-over frequency. C2 = 10 10 = = 2837pF 2p ´ fL ´ R4 2p ´ 30kHz ´ 18.7kW (64) C2 = 2200 pF selected. Place a high-frequency pole at about five times the desired cross-over frequency and less than one-half the unity gain bandwidth of the error amplifier: C4 » C4 > 1 1 = = 56.74pF 10p ´ fL ´ R4 10p ´ 30kHz ´ 18.7kW (65) 1 1 = = 11.35pF p ´ GBW ´ R4 p ´ 1.5MHz ´ 18.7kW (66) C4 = 47 pF selected. R-C Oscillator The R-C oscillator calculation as shown in Equation 5 substitutes 100 for CT and 600 for fSW. For a 600-kHz switching frequency, a 100-pF capacitor is selected and a 262-kΩ resistor is calculated (261 kΩ selected). Soft-Start Capacitor Because VDD > 8 V, the soft-start capacitor is selected by using Equation 67 to calculate the value. CSS = 20 ´ TSS ´ 10-6 (67) For TSS = 12 ms, CSS = 240 nF, a 220-nF capacitor selected. Regulator Bypass A regulator bypass capacitor of 1.0-mF is selected per the recommendation. 32 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 TEST DATA GAIN AND PHASE vs FREQUENCY FET Vds and Vgs VOLTAGES vs TIME 80 180 60 VIN = 8 V VOUT = 24 V IOUT = 2 A 135 40 90 20 45 0 0 Gain -20 -45 -40 -90 -60 -135 -80 100 GDRV (5 V/ div) Phase – ° Gain – dB Phase FET Vds (20 V/ div) -180 1M 1000 10 k 100 k fSW – Frequency – Hz T – Time – 400 ns Figure 32. Figure 33. EFFICIENCY vs LOAD CURRENT POWER LOSS vs LOAD CURRENT 6 100 VIN (V) 14 12 8 96 5 94 h – Efficiency – % VIN (V) 14 12 8 VIN = 14V PLOSS – Power Loss – W 98 92 VIN = 12 V 90 88 VIN = 8 V 86 VIN = 8 V 4 VIN = 12 V 3 2 VIN = 14 V 84 1 82 80 0 0 0.5 1.0 1.5 2.0 ILOAD – Load Current – A 2.5 0 Figure 34. 0.5 1.0 1.5 2.0 ILOAD – Load Current – A 2.5 Figure 35. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT 33 TPS40210-HT SLVSAD8 – JUNE 2010 www.ti.com OUTPUT VOLTAGE vs LOAD CURRENT 24.820 VIN (V) 14 12 8 VOUT – Output Voltage – V 24.772 24.724 VIN = 8 V 24.676 24.628 24.580 VIN = 14 V 24.532 VIN = 12 V 24.484 24.436 24.388 24.340 0 0.5 1.0 1.5 2.0 ILOAD – Load Current – A 2.5 Figure 36. List of Materials Table 3. List of Materials, Design Example 1 REFERENCE DESIGNATOR DESCRIPTION SIZE PART NUMBER MANUFACTURER 0.406 x 0.457 EEEFC1V101P Panasonic C1 100 mF, aluminum capacitor, SM, ± 20%, 35 V C2 2200 pF, ceramic capacitor, 25 V, X7R, 20% 0603 Std Std C3 100 pF, ceramic capacitor, 16 V, C0G, 10% 0603 Std Std C4 47 pF, ceramic capacitor, 16 V, X7R, 20% 0603 Std Std C5 0.22 mF, ceramic capacitor, 16 V, X7R, 20% 0603 Std Std C7 1.0 mF, ceramic capacitor, 16 V, X5R, 20% 0603 Std Std C8 10 mF, ceramic capacitor, 25 V, X7R, 20% 0805 C3225X7R1E106M TDK C9 0.1 mF, ceramic capacitor, 50 V, X7R, 20% 0603 Std Std C10 100 pF, ceramic capacitor, 16 V, X7R, 20% 0603 Std Std D1 Schottky diode, 3 A, 40 V SMC MBRS340T3 On Semi L1 10 mH, inductor, SMT, 7.5 A, 12.4 mΩ 0.325 x 0.318 inch RLF12560T-100M-7R5 TDK Q1 MOSFET, N-channel, 40 V, 14 A, 9 mΩ SO-8 Si4840DY Vishay R3 10 kΩ, chip resistor, 1/16 W, 5% 0603 Std Std R4 18.7 kΩ, chip resistor, 1/16 W, 1% 0603 Std Std R5 1.5 kΩ, chip resistor, 1/16 W, 1% 0603 Std Std R6 261 kΩ, chip resistor, 1/16 W, 1% 0603 Std Std R7 51.1 kΩ, chip resistor, 1/16 W, 1% 0603 Std Std R9 3.3 Ω, chip resistor, 1/16 W, 5% 0603 Std Std R10 1.0 kΩ, chip resistor, 1/16 W, 5% 0603 Std Std R11 10 mΩ, chip resistor, 1/2 W, 2% 1812 Std Std U1 IC, 4.5 V-52 V I/P, current mode boost controller DGQ10 TPS40210QDGQRQ1 TI 34 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT TPS40210-HT www.ti.com SLVSAD8 – JUNE 2010 DESIGN EXAMPLE 2 12-V Input, 700-mA LED Driver, Up to 35-V LED String Application Schematic L1 VIN C21 C1 GDRV C2 D1 B2100 R2 ISNS C3 R1 R11 C4 VIN R3 D2 C8 1 U1 TPS40210 TPS40211 VIN RC DD 10 C10 C9 Loop Response Injection R23 C6 R13 R4 DIS/EN C11 BP 9 DIS/EN GDRV 8 4 COMP ISNS 7 5 FB GND 6 2 SS 3 C6 LEDC GDRV LEDC ISNS C13 R24 R6 D3 R15 C14 PWM Dimming UDG-08015 Figure 37. 12-V Input, 700-mA LED Driver, Up to 35-V LED String Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT 35 TPS40210-HT SLVSAD8 – JUNE 2010 www.ti.com List of Materials Table 4. List of Materials, Design Example 2 REFERENCE DESIGNATOR TYPE DESCRIPTION SIZE C1, C2 10 mF, 25 V 1206 C3, C4 2.2 mF, 100 V 1210 C5 1 nF, NPO 0603 C6 100 pF, NPO 0603 C8 100 pF 0603 C9 0.1 mF 0603 C10 Capacitor 0.1 mF, 25 V 0805 C11 1 mF, 25 V 1206 C13 220 pF 0603 C14 10 nF, X7R 0603 C21 330 mF, 25 V electrolytic D1 D2 B2100, Schottky, 100 V, 2 A Diode D3 L1 Q1 Q3 BZT52C43 MMBD7000 Inductor MOSFET Wurth 7447709100, 10 mH, 6 A Si7850DP, 60 V, 31 mΩ 2N7002, 60 V, 0.1 A SMB SOD-123 SOT-23 12 × 12 × 10 mm SO-8 SOT-23 R1 15 mΩ 2512 R2 3.01 Ω 0805 R3 402 kΩ 0603 R4 14.3 kΩ 0603 0.36 Ω 2512 1 kΩ 0603 R13 30.1 kΩ 0603 R15 49.9 kΩ 0603 R24 10 kΩ 0603 R23 10 Ω R6 R11 U1 36 Resistor Integrated circuit TPS40211 Submit Documentation Feedback 0603 DGQ-10 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS40210-HT IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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