FUJITSU MB90641A

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13608-1E
16-bit Proprietary Microcontroller
CMOS
F2MC-16L MB90640A Series
MB90641A/P641A
■ DESCRIPTION
MB90640A series includes 16-bit microcontrollers optimally suitable for process control in a wide variety of
industrial and OA equipment. The series uses the F2MC*-16L CPU which is based on the F2MC-16 but with
enhanced high-level language and task switching instructions and additional addressing modes.
The internal peripheral resources consist of a 2-channel serial port incorporating a UART function (and
supporting I/O expansion serial mode), 8/16-bit 2-channel PPG, 5-channel 16-bit reload timer, 8-channel chip
select function, and 8-channel DTP/external interrupts.
Also, multiplexed or non-multiplexed operation can be selected for the address/data bus.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
F2MC-16L CPU
• Minimum instruction execution time: 58.8 ns/4.25 MHz oscillation (Uses PLL clock multiplication),
maximum multiplier = 4
• Instruction set optimized for controller applications
Upward object code compatibility with F2MC-16 (H)
Wide range of data types (bit/byte/word/long word)
Improved instruction cycles provide increased speed
Additional addressing modes: 23 modes
(Continued)
■ PACKAGE
100-pin Plastic LQFP
100-pin Plastic QFP
(FPT-100P-M05)
(FPT-100P-M06)
MB90640A Series
(Continued)
High code efficiency
Access methods (bank access/linear pointer)
Enhanced multiplication and division instructions (signed instructions added)
High precision operations are enhanced by use of a 32-bit accumulator
Extended intelligent I/O service (access area extended to 64 Kbytes)
Maximum memory space: 16 Mbytes
• Enhanced high level language (C)/multitasking support instructions
Use of a system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
Stack check function
• Improved execution speed: Four byte instruction queue
• Powerful interrupt function
• Automatic data transfer function (does not use instructions)
Internal peripherals
• RAM: 2 Kbytes
• General purpose ports Data bus, multiplexed mode: 56 ports max.
Non-multiplexed mode:
48 ports max.
Single-chip mode:
75 ports max.
• UART0, 1 (SCI): 2 channels
For either asynchronous or clocked serial transfer (I/O expansion serial)
• 8/16-bit PPG (programmable pulse generator): 2 channels
• 16-bit reload timer: 5 channels
• Chip select function: 8 channels
• DTP/external interrupts: 8 channels
• Timebase timer/watchdog timer
• PLL clock multiplier function
• CPU intermittent operation function
• Various standby modes
• Packages: LQFP-100 and QFP-100
• CMOS technology
2
MB90640A Series
■ PRODUCT LINEUP
Part number
MB90641A
MB90P641A
Classification
Mask ROM
One-time PROM
ROM size
64 Kbytes
64 Kbytes
RAM size
2 Kbytes
2 Kbytes
Item
CPU functions
Ports
Packages
UART0, 1 (SCI)
8/16-bit PPG
16-bit reload timer
Chip select function
DTP/external interrupts
PLL function
External bus terminal
control circuit
The number of instructions: 340
Instruction bit length:
8/16 bits
Instruction length:
1 to 7 bytes
Data bit length:
1/4/8/16/32 bits
Minimum execution time: 58.8 ns at 4.25 MHz (PLL multiplier = 4)
Interrupt processing time: 941 ns at 17 MHz (minimum)
8/16-bit data bus, multiplexed mode: 56 ports (max)
8-bit non-multiplexed mode:
48 ports (max)
Single-chip mode:
75 ports (max)
FPT-100P-M05
FPT-100P-M06
Two internal UARTs
Full-duplex, double-buffered
Selectable clock synchronous or asynchronous operation
Built-in dedicated baud rate generator
2 × 8-bit PPG outputs
(1 channel PPG output in 16-bit mode)
16-bit reload timer operation (selectable toggle output, one-shot output)
(Selectable count clock: 0.125 µs, 0.5 µs, or 2.0 µs for a 16 MHz machine cycle)
Selectable event count function, 5 internal channels
8 outputs
8 inputs
External interrupt mode
(Interrupts can be generated from four different types of request signal)
Selectable multiplier: 1/2/3/4
(Set a multiplier that does not exceed the assured operation frequency range.)
Multiplex and non-multiplex between the adress pin and the data pin is selectable.
3
P71/INT1
P72/INT2
P73/INT3/TIM4
P74/INT4/PPG0
P75/INT5/PPG1
P76/INT6
VCC
VCC
VSS
VSS
P60
P61
P62
P63
VSS
P64
P65
P66
P67
P80/INT7/TIM0
P81/INT0/TIM1
MD0
MD1
MD2
HST
P22/A02
P23/A03
P24/A04
P25/A05
P26/A06
P27/A07
P30/A08
P31/A09
VSS
P32/A10
P33/A11
P34/A12
P35/A13
P36/A14
P37/A15
P40/A16
P41/A17
P42/A18
P43/A19
P44/A20
VCC
P45/A21
P46/A22
P47/A23
C
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P21/A01
P20/A00
P17/D15/AD15
P16/D14/AD14
P15/D13/AD13
P14/D12/AD12
P13/D11/AD11
P12/D10/AD10
P11/D09/AD09
P10/D08/AD08
P07/D07/AD07
P06/D06/AD06
P05/D05/AD05
P04/D04/AD04
P03/D03/AD03
P02/D02/AD02
P01/D01/AD01
P00/D00/AD00
VCC
X1
X0
VSS
P57/ALE
P56/RD
P55/WRL
MB90640A Series
■ PIN ASSIGNMENT
(Top view)
(FPT-100P-M05)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RST
P54/WRH
P53/HRQ
P52/HAK
P51/RDY
P50/CLK
PA7/CS7
PA6/CS6
PA5/CS5
PA4/CS4
PA3/CS3
PA2/CS2
PA1/CS1
PA0/CS0
P95
P94
P93
P92/SCK1
P91/SOT1
P90/SIN1
P86/SCK0
P85/SOT0
P84/SIN0
P83/TIM3
P82/TIM2
MB90640A Series
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
P17/D15/AD15
P16/D14/AD14
P15/D13/AD13
P14/D12/AD12
P13/D11/AD11
P12/D10/AD10
P11/D09/AD09
P10/D08/AD08
P07/D07/AD07
P06/D06/AD06
P05/D05/AD05
P04/D04/AD04
P03/D03/AD03
P02/D02/AD02
P01/D01/AD01
P00/D00/AD00
VCC
X1
X0
VSS
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P57/ALE
P56/RD
P55/WRL
RST
P54/WRH
P53/HRQ
P52/HAK
P51/RDY
P50/CLK
PA7/CS7
PA6/CS6
PA5/CS5
PA4/CS4
PA3/CS3
PA2/CS2
PA1/CS1
PA0/CS0
P95
P94
P93
P92/SCK1
P91/SOT1
P90/SIN1
P86/SCK0
P85/SOT0
P84/SIN0
P83/TIM3
P82/TIM2
HST
MD2
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P74/INT4/PPG0
P75/INT5/PPG1
P76/INT6
VCC
VCC
VSS
VSS
P60
P61
P62
P63
VSS
P64
P65
P66
P67
P80/INT7/TIM0
P81/INT0/TIM1
MD0
MD1
P20/A00
P21/A01
P22/A02
P23/A03
P24/A04
P25/A05
P26/A06
P27/A07
P30/A08
P31/A09
VSS
P32/A10
P33/A11
P34/A12
P35/A13
P36/A14
P37/A15
P40/A16
P41/A17
P42/A18
P43/A19
P44/A20
VCC
P45/A21
P46/A22
P47/A23
C
P71/INT1
P72/INT2
P73/INT3/TIM4
(FPT-100P-M06)
5
MB90640A Series
■ PIN DESCRIPTION
Pin no.
LQFP*1
QFP*2
80,
81
82,
83
47 to 49
Pin name
Circuit
type
X0,
X1
A
49 to 51 MD0 to MD2
E
(CMOS)
Crystal oscillator pins
Input pins for specifying an opration mode.
Use these pins by directly connecting VCC or VSS.
75
77
RST
G
(CMOS/H)
External reset request input pin
50
52
HST
F
(CMOS/H)
Hardware standby input pin
83 to 90
85 to 92 P00 to P07
99,
100,
1 to 6
1,
2,
3 to 8
J
(TTL)
In non-multiplex mode, the I/O pins for the lower 8 bits of
the external data bus.
AD00 to AD07
In multiplexed mode, the I/O pins for the lower 8 bits of the
external address/data bus.
J
(TTL)
In non-multiplexed mode with a 16-bit external data bus,
the I/O pins for the upper 8 bits of the external data bus.
AD08 to AD15
In multiplexed mode, the I/O pins for the upper 8 bits of the
external address/data bus.
P20,
P21,
P22 to P27
B
(CMOS)
9,
P30,
10,
P31,
12 to 17 P32 to P37
18 to 22, P40 to P44,
24 to 26 P45 to P47
A16 to A20,
A21 to A23
*1: FPT-100P-M05
*2: FPT-100P-M06
General purpose I/O ports
This applies in multiplexed mode.
In non-multiplexed mode, the output pins for the lower 8
bits of the external address bus.
B
(CMOS)
A08,
A09,
A10 to A15
16 to 20,
22 to 24
General purpose I/O ports
This applies in non-multiplexed mode with an 8-bit external
data bus and in single-chip mode.
P08 to D15
A00,
A01,
A02 to A07
7,
8,
10 to 15
General purpose I/O ports
This applies in single-chip mode with an external data bus
in 8-bit mode.
D00 to D07
91 to 98 93 to 100 P10 to P17
6
Function
General purpose I/O ports
This applies in multiplexed mode.
In non-multiplexed mode, the output pins for the upper 8
bits of the external address bus.
B
(CMOS)
General purpose I/O ports
This applies when the upper address control register
specifies port operation.
Output pins for A16 to A23 of the external address bus
This applies when the upper address control register
specifies address operation.
(Continued)
MB90640A Series
Pin no.
LQFP*1
QFP*2
70
72
Pin name
P50
Circuit
type
I
(CMOS)
CLK
71
73
P51
74
P52
K
(TTL)
75
P53
I
(CMOS)
76
P54
K
(TTL)
78
P55
I
(CMOS)
79
P56
I
(CMOS)
80
P57
I
(CMOS)
*1: FPT-100P-M05
*2: FPT-100P-M06
General-purpose I/O port
This port is available in the single-chip mode.
Read strobe output pin for the data bus
I
(CMOS)
ALE
36 to 39, 38 to 41, P60 to P67
41 to 44 43 to 46
General purpose I/O port
This applies when output is disabled for the WRL pin.
Write strobe output pin for the lower 8 bits of the data bus
This applies when output is enabled for the WRL pin.
RD
78
General purpose I/O port
This applies in 8-bit external bus mode or when output is
disabled for the WRH pin.
Write strobe output pin for the upper 8 bits of the data bus
This applies in 16-bit external bus mode and when output is
enabled for the WRH pin.
WRL
77
General purpose I/O port
This applies when the hold function is disabled.
Hold request input pin
This applies when the hold function is enabled.
WRH
76
General purpose I/O port
This applies when the hold function is disabled.
Hold acknowledge output pin
This applies when the hold function is enabled.
HRQ
74
General purpose I/O port
This applies when the external ready function is disabled.
Ready input pin
This applies when the external ready function is enabled.
HAK
73
General purpose I/O port
This applies when CLK output is disabled.
CLK output pin
This applies when CLK output is enabled.
RDY
72
Function
General-purpose I/O port
This port is available in the single-chip mode.
Address latch enable output pin
C
Open-drain output ports
(Continued)
7
MB90640A Series
Pin no.
LQFP*1
QFP*2
26,
27
28,
29
Pin name
P71,
P72
Circuit
type
H
(CMOS/H)
INT1,
INT2
28
29,
30
31
30
31,
32
33
P73
8
General purpose I/O ports
This applies in all cases.
External interrupt request input pins
As the inputs operate continuously when external interrupts
are enabled, output to the pins from other functions must
be stopped unless done intentionally.
H
(CMOS/H)
General purpose I/O ports
This applies when output is disabled for reload timers.
INT3
External interrupt request input pins
As the inputs operate continuously when external interrupts
are enabled, output to the pins from other functions must
be stopped unless done intentionally.
TIM4
I/O pins for reload timers
Input is used only as necessary while serving as input for
the reload timer.
It is therefore necessary to stop output beforehand using
other functions unless intentionally used otherwise.
Their function as output terminals for the reload timer is
activated when the output specification is enabled.
P74,
P75
H
(CMOS/H)
General purpose I/O ports
This applies when the waveform outputs for PPG timers 0,
1 are disabled.
INT4,
INT5
External interrupt request input pin
As the input operates continuously when the external
interrupt is enabled, output to the pin from other functions
must be stopped unless done intentionally.
PPG0,
PPG1
Output pins for PPG timers
This applies when the waveform outputs for PPG timers 0,
1 are enabled.
P76
INT6
*1: FPT-100P-M05
*2: FPT-100P-M06
Function
H
(CMOS/H)
General purpose I/O port
This applies in all cases.
External interrupt request input pin
As the input operates continuously when the external
interrupt is enabled, output to the pin from other functions
must be stopped unless done intentionally.
(Continued)
MB90640A Series
Pin no.
LQFP*1
QFP*2
45,
46
47,
48
51,
52
53,
54
Pin name
P80,
P81
Circuit
type
H
(CMOS/H)
55
External interrupt request input pin
As the input operates continuously when the external
interrupt is enabled, output to the pin from other functions
must be stopped unless done intentionally.
TIM0,
TIM1
I/O pins for reload timers
Input is used only as necessary while serving as input for
the reload timer.
It is therefore necessary to stop output beforehand using
other functions unless intentionally used otherwise.
Their function as output terminals for the reload timer is
activated when the output specification is enabled.
P82,
P83
D
(CMOS/H)
P84
56
P85
D
(CMOS/H)
57
P86
D
(CMOS/H)
58
P90
SIN1
*1: FPT-100P-M05
*2: FPT-100P-M06
General purpose I/O port
This applies when serial data output is disabled for UART0.
Serial data output pin for UART0
This applies when serial data output is enabled for UART0.
D
(CMOS/H)
SCK0
56
General purpose I/O port
This applies in all cases.
Serial data input pin for UART0
As the input operates continuously when UART0 is set to
input operation, output to the pin from other functions must
be stopped unless done intentionally.
SOT0
55
General purpose I/O ports
This applies when output is disabled for reload timers.
I/O pins for reload timers
Input is used only as necessary while serving as input for
the reload timer. It is therefore necessary to stop output
beforehand using other functions unless intentionally used
otherwise.
Their function as output terminals for the reload timer is
activated when the output specification is enabled.
SIN0
54
General purpose I/O ports
This applies when output is disabled for reload timers.
INT7,
INT0
TIM2,
TIM3
53
Function
General purpose I/O port
This applies when the UART0 clock output is disabled.
Clock I/O pin for UART0
This applies when the UART0 clock output is enabled.
As the input operates continuously when UART0 is set to
input operation, output to the pin from other functions must
be stopped unless done intentionally.
D
(CMOS/H)
General purpose I/O port
This applies in all cases.
Serial data input pin for UART1
As the input operates continuously when UART1 is set to
input operation, output to the pin from other functions must
be stopped unless done intentionally.
(Continued)
9
MB90640A Series
(Continued)
Pin no.
LQFP*1
QFP*2
57
59
Pin name
P91
Circuit
type
Function
D
(CMOS/H)
General purpose I/O port
This applies when serial data output is disabled for UART1.
SOT1
58
60
P92
Serial data output pin for UART1
This applies when serial data output is enabled for UART1.
D
(CMOS/H)
SCK1
59 to 61
25
62 to 69
61 to 63 P93 to P95
27
Clock I/O pin for UART1
This applies when the UART1 clock output is enabled.
As the input operates continuously when UART1 is set to
input operation, output to the pin from other functions must
be stopped unless done intentionally.
D
(CMOS/H)
C
—
64 to 71 PA0 to PA7
I
(CMOS/H)
CS0 to CS7
General purpose I/O port
Capacitor pin for stabilizing power supply
Connect about 0.1 µF ceramic capacitor outside ROM.
MB90P641 doesn’t need to be connected the capacitor.
It isn’t problem even the capacitor is connected to
MB90P641A.
General purpose I/O ports
This applies for pins with chip select output disabled by the
chip select control register.
Output pins for the chip select function
This applies for pins with chip select output enabled by the
chip select control register.
21,
32,
33,
82
23,
34,
35,
84
VCC
Power
supply
Power supply for the digital circuits
9,
34,
35,
40,
79
11,
36,
37,
42,
81
VSS
Power
supply
Ground level for the digital circuits
*1: FPT-100P-M05
*2: FPT-100P-M06
10
General purpose I/O port
This applies when the UART1 clock output is disabled.
MB90640A Series
■ I/O CIRCUIT TYPE
Type
A
Circuit
Remarks
X1
Clock input
X0
• Max. 3 to 34 MHz
• Oscillation feedback resistance:approximately
1 MΩ
Standby control
B
Digital output
R
• CMOS level I/O
With standby control
• Pull-up resistor option
Digital output
Digital input
Standby control
C
R
Digital output
• N-channel open-drain output
• CMOS level hysteresis input
• Pull-up resistor option
Digital input
Standby control
D
Digital output
R
• CMOS level output
• CMOS level hysteresis input
With standby control
• Pull-up resistor option
Digital output
Digital input
Standby control
Note: For pins with pull-up resistors, the resistance is disconnected when the pin outputs the “L” level or when in
the standby state.
(Continued)
11
MB90640A Series
Type
Circuit
Remarks
E
• CMOS level input
No standby control
• Pull-up resistor option
R
Digital input
F
• CMOS level hysteresis input
No standby control
• Pull-up resistor option
R
Digital input
G
• CMOS level hysteresis input
No standby control
• With pull-up resistor
R
R
Digital input
H
Digital output
R
• CMOS level output
• CMOS level hysteresis input
No standby control
• Pull-up resistor option
Digital output
Digital input
I
Standby control
R
Digital output
R
Digital output
•
•
•
•
CMOS level output
CMOS level hysteresis input
Pull-up resistor approximately 50 kΩ
Pin goes to high impedance during stop mode.
Digital input
Standby control
Note: For pins with pull-up resistors, the resistance is disconnected when the pin outputs the “L” level or when in
the standby state.
(Continued)
12
MB90640A Series
(Continued)
Type
Circuit
Remarks
J
Digital output
R
• CMOS level output
• TTL level input
With standby control
• Pull-up resistor option
Digital output
Digital input
Standby control
K
Standby control
R
Digital output
R
Digital output
•
•
•
•
CMOS level output
TTL level input
Pull-up resistor approximately 50 kΩ
Pin goes to high impedance during stop mode.
Digital input
Standby control
Note: For pins with pull-up resistors, the resistance is disconnected when the pin outputs the “L” level or when in
the standby state.
13
MB90640A Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or less than VSS is applied to input and output pins
other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidlly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the anaolg power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is truned on and off.
2. Treatment of Unused Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resister.
3. Cautions when Using an External Clock
Drive the X0 pin only when using an external clock.
• Using an external clock
X0
OPEN
X1
MB90640A
4. Power Supply Pins
When there are several VCC and VSS pins, those pins that should have the same electric potential are connected
within the device when the device is designed in order to prevent misoperation, such as latchup. However, all
of those pins must be connected to the power supply and ground externally in order to reduce unnecessary
emissions, prevent misoperation of strobe signals due to an increase in the ground level, and to observe the
total output current standards.
In addition, give a due consideration to the connection in that current supply be connected to VCC and VSS with
the lowest possible impedance.
Finally, it is recommended to connect a ceramic capacitor of about 0.1 µF between VCC and VSS near this device
as a bypass capacitor.
5. Crystal Oscillation Circuit
Noise in the vicinity of the X0 and X1 pins will cause this device to operate incorrectly. Design the printed circuit
board so that the bypass capacitor connecting X0, X1 and the crystal oscillator (or ceramic oscillator) to ground
is located as close to the device as possible, and possibly take care not to cross over the other wiring with this
wiring.
In addition, because printed circuit board artwork in which the area around the X0 and X1 pins is surrounded
by ground provides stable operation, such an arrangement is strongly recommended.
14
MB90640A Series
■ PROGRAMMING TO THE ONE-TIME PROM ON THE MB90P641A
MB90P641A has a function PROM mode function equivalent to MBM27C1000/1000A, so it can be written by
general ROM writer using special adapter. But take attention it doesn’t corsespond to the elctronic signature
(the device identification code) mode.
1. Programming Procedure
Memory map in the PROM mode is as below. Write option data to the option setting erea refering to the 6 PROM
option bit map.
PROM mode
Normal operating made
1FFFFH
FFFFFFH
Program area
(PROM)
Program area
(PROM)
Address*1
Address*2
010000H
ROM image
Mirror
0002CH
00000H
004000H
Option
setting area
000000H
Product
Address*1
Address*2
Number of bytes
MB90P641A
10000H
FF0000H
64 Kbytes
Note: The 00 bank ROM image is 48 Kbyes. (This is a ROM image for FF4000H to FFFFFFH.
Only when the ROM mirror function selecting resister is enable.)
Porocedure of the programing to the one-time PROM microcomputer is as below.
(1) Set the EPROM programmer for the MBM27C1000/1000A.
(2) Load the program data into the EPROM programmer at address*1 to 1FFFFH. When specify the PROM
option, load the option data to 00000H to 00002CH to refering to “6. PROM Option Bitmap”.
(3) Insert the device in the socket adapter, and mount the socket adapter on the EPROM programmer. Pay
attention to the orientation of the device and of the socket adapter when doing so.
(4) Program to 00000H to 1FFFFH.
Notes: • Because the mask ROM products do not have a PROM mode, they cannot read date from the EPROM
programmer.
• Contact the sales department when purchasing an EPROM programmer.
15
MB90640A Series
2. Program Mode
In the MB90P641A, all of the bits are set to “1” when the IC is shipped from Fujitsu and after erasure. To input
data, program the IC by selectively setting the desired bits to “0”. Bits cannot be set to “1” electrically.
3. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
one-time PROM with microcontroller program.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
4. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked one-time PROM microcomputer, due to its
nature. For this reason, a programming yield of 100% cannot be assured at all times.
5. EPROM Programmer Socket Adapter and Recommended Programmer Manuffacturer
Part no.
MB90P641APF
MB90P641APFV
Package
QFP-100
LQFP-100
ROM-100QF-32DP
-FFMC-16L
ROM-100SQF-32DP
-FFMC-16L
1890A
Recommended
Recommended
1891
Recommended
Recommended
1930
Recommended
Recommended
Compatible socket adapter
Sun Hayato Co., Ltd.
Recommended
programmer
manufacturer
and programmer
name
Minato
Electronics
Inc.
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403
FAX: (81)-3-5396-9106
Minato Electronics Inc.: TEL: USA (1)-916-348-6066
JAPAN (81)-45-591-5611
16
MB90640A Series
6. PROM Option Bitmap
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Vacancy
RST
Pull-up
1: No
0: Yes
Vacancy
MD 1
Pull-up
1: No
0: Yes
MD 1
Pull-down
1: No
0: Yes
MD 0
Pull-up
1: No
0: Yes
MD 0
Pull-down
1: No
0: Yes
Vacancy
00004H
P07
Pull-up
1: No
0: Yes
P06
Pull-up
1: No
0: Yes
P05
Pull-up
1: No
0: Yes
P04
Pull-up
1: No
0: Yes
P03
Pull-up
1: No
0: Yes
P02
Pull-up
1: No
0: Yes
P01
Pull-up
1: No
0: Yes
P00
Pull-up
1: No
0: Yes
00008H
P17
Pull-up
1: No
0: Yes
P16
Pull-up
1: No
0: Yes
P15
Pull-up
1: No
0: Yes
P14
Pull-up
1: No
0: Yes
P13
Pull-up
1: No
0: Yes
P12
Pull-up
1: No
0: Yes
P11
Pull-up
1: No
0: Yes
P10
Pull-up
1: No
0: Yes
0000CH
P27
Pull-up
1: No
0: Yes
P26
Pull-up
1: No
0: Yes
P25
Pull-up
1: No
0: Yes
P24
Pull-up
1: No
0: Yes
P23
Pull-up
1: No
0: Yes
P22
Pull-up
1: No
0: Yes
P21
Pull-up
1: No
0: Yes
P20
Pull-up
1: No
0: Yes
00010H
P37
Pull-up
1: No
0: Yes
P36
Pull-up
1: No
0: Yes
P35
Pull-up
1: No
0: Yes
P34
Pull-up
1: No
0: Yes
P33
Pull-up
1: No
0: Yes
P32
Pull-up
1: No
0: Yes
P31
Pull-up
1: No
0: Yes
P30
Pull-up
1: No
0: Yes
00014H
P47
Pull-up
1: No
0: Yes
P46
Pull-up
1: No
0: Yes
P45
Pull-up
1: No
0: Yes
P44
Pull-up
1: No
0: Yes
P43
Pull-up
1: No
0: Yes
P42
Pull-up
1: No
0: Yes
P41
Pull-up
1: No
0: Yes
P40
Pull-up
1: No
0: Yes
0001CH
P57
Pull-up
1: No
0: Yes
P56
Pull-up
1: No
0: Yes
P55
Pull-up
1: No
0: Yes
P54
Pull-up
1: No
0: Yes
P53
Pull-up
1: No
0: Yes
P52
Pull-up
1: No
0: Yes
P51
Pull-up
1: No
0: Yes
P50
Pull-up
1: No
0: Yes
Vacancy
P76
Pull-up
1: No
0: Yes
P75
Pull-up
1: No
0: Yes
P74
Pull-up
1: No
0: Yes
P73
Pull-up
1: No
0: Yes
P72
Pull-up
1: No
0: Yes
P71
Pull-up
1: No
0: Yes
Vacancy
Vacancy
P86
Pull-up
1: No
0: Yes
P85
Pull-up
1: No
0: Yes
P84
Pull-up
1: No
0: Yes
P83
Pull-up
1: No
0: Yes
P82
Pull-up
1: No
0: Yes
P81
Pull-up
1: No
0: Yes
P80
Pull-up
1: No
0: Yes
Vacancy
Vacancy
P95
Pull-up
1: No
0: Yes
P94
Pull-up
1: No
0: Yes
P93
Pull-up
1: No
0: Yes
P92
Pull-up
1: No
0: Yes
P91
Pull-up
1: No
0: Yes
P90
Pull-up
1: No
0: Yes
PA7
Pull-up
1: No
0: Yes
PA6
Pull-up
1: No
0: Yes
PA5
Pull-up
1: No
0: Yes
PA4
Pull-up
1: No
0: Yes
PA3
Pull-up
1: No
0: Yes
PA2
Pull-up
1: No
0: Yes
PA1
Pull-up
1: No
0: Yes
PA0
Pull-up
1: No
0: Yes
00000H
00020H
00024H
00028H
0002CH
Note: Write data “1” to the vacant bit and the adress other than above.
17
MB90640A Series
■ BLOCK DIAGRAM
X0, X1
RST
HST
MD0 to MD2
7
CPU
F2MC-16L family core
Clock control
circuit
Interrupt controller
RAM
8/16-bit PPG
(output switching) × 1channel
PPG0
PPG1
2
2
2
SIN0, SIN1
SOT0, SOT1
SCK0, SCK1
A00 to A23
D00 to D15
ALE
RD
WRL, WRH
HRQ
HAK
RDY
CLK
Internal data bus
Communication prescaler
UART
24
ROM
INT0 to INT7
16
2
External bus Interface
16-bit reload timer
Chip select functions
I/O ports
Ohter pins
AD00 to AD15, C,
VCC, VSS
18
8
DTP/external interrupts
8
8
8
8
8
8
8
6
7
6
8
P00
to
P07
P10
to
P17
P20
to
P27
P30
to
P37
P40
to
P47
P50
to
P57
P60
to
P67
P71
to
P76
P80
to
P86
P90
to
P95
PA0
to
PA7
5
8
TIM0 to TIM4
CS0 to CS7
MB90640A Series
■ MEMORY MAP
Single chip mode
Internal ROM/
external bus mode
ROM area
ROM area
ROM area
(FF bank image)
ROM area
(FF bank image)
External ROM/
external bus mode
FFFFFFH
FF0000H
F00000H
00FFFFH
004000H
002000H
Address #1
RAM
Registers
RAM
Registers
RAM
Registers
000100H
0000C0H
Peripherals
Peripherals
Peripherals
000000H
Type
Address #1
MB90641A
000900H
MB90P641A
000900H
: Internal access memory
: External access memory
: No access
Note: When disable output upper address A23 to A16 of MB90640A series, the maximum acceptable size
becomes 64 Kbytes.
19
MB90640A Series
■ F2MC-16L CPU PROGRAMMING MODEL
• Dedicated registers
AH
AL
Accumulator
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
DPR
Direct page register
PCB
Program bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8 bits
16 bits
32 bits
• General-purpose registers
32 banks (max.)
R7
R6
RW7
R5
R4
RW6
R3
R2
RW5
R1
R0
RW4
RL3
RL2
RW3
RL1
RW2
RW1
RL0
RW0
000180 H + RP × 10 H →
16 bits
• Processor status (PS)
ILM
RP
—
I
S
T
N
CCR
20
Z
V
C
MB90640A Series
■ I/O MAP
Address
Name
Register
Read/
write*4,*5
Resource name
Initial value
000000H PDR0
Port 0 data register
R/W*
Port 0*8
XXXXXXXX
B
000001H PDR1
Port 1 data register
R/W*
Port 1*7
XXXXXXXX
B
*6
XXXXXXXX
B
000002H PDR2
Port 2 data register
R/W*
Port 2
000003H PDR3
Port 3 data register
R/W*
Port 3*6
XXXXXXXX
B
000004H PDR4
Port 4 data register
R/W
Port 4
XXXXXXXX
B
XXXXXXXX
B
*8
000005H PDR5
Port 5 data register
R/W
Port 5
000006H PDR6
Port 6 data register
R/W
Port 6
11111111
B
000007H PDR7
Port 7 data register
R/W
Port 7
–XXXXXXX
B
000008H PDR8
Port 8 data register
R/W
Port 8
–XXXXXXX
B
000009H PDR9
Port 9 data register
R/W
Port 9
– –XXXXXX
B
00000AH PDRA
Port A data register
R/W
XXXXXXX–
B
00000BH
to 0FH
Vacancy
—
Port A
*8
*3
—
—
000010H DDR0
Port 0 direction register
R/W*
Port 0*8
00000000
B
000011H DDR1
Port 1 direction register
R/W*
Port 1
*7
00000000
B
*6
00000000
B
000012H DDR2
Port 2 direction register
R/W*
Port 2
000013H DDR3
Port 3 direction register
R/W*
Port 3*6
00000000
B
000014H DDR4
Port 4 direction register
R/W
Port 4
00000000
B
000015H DDR5
Port 5 direction register
R/W
Port 5
00000000
B
000016H DDR6
Port 6 direction register
R/W
Port 6
11111111
B
000017H DDR7
Port 7 direction register
R/W
Port 7
–000000–
B
000018H DDR8
Port 8 direction register
R/W
Port 8
–0000000
B
000019H DDR9
Port 9 direction register
R/W
Port 9
––000000
B
00001AH DDRA
Port A direction register
R/W
Port A*8
00000000
B
00001BH
to 1FH
Vacancy
—
*3
000020H SMR0
Serial mode register 0
R/W!
000021H SCR0
Serial control register 0
R/W!
—
UART0 (SCI)
—
00000000
B
00000100
B
XXXXXXXX
B
Input data register 0/
output data register 0
R/W
000023H SSR0
Serial status register 0
R/W!
00001–00
B
000024H SMR1
Serial mode register 1
R/W!
00000000
B
000025H SCR1
Serial control register 1
R/W!
00000100
B
XXXXXXXX
B
00001–00
B
000022H
000026H
SIDR0/
SODR0
*8
SIDR1/
SODR1
000027H SSR1
Input data register 1/
output data register 1
R/W
Serial status register 1
R/W!
UART1 (SCI)
(Continued)
21
MB90640A Series
Address
Name
Register
Read/
write*4,*5
000028H ENIR
Interrupt/DTP enable register
R/W
000029H EIRR
Interrupt/DTP request register
R/W
Interrupt level setting register
R/W
00002AH
00002BH
00002CH
to 2FH
ELVR
—
Vacancy
*3
Resource name
DTP/external
interrupt
—
Initial value
00000000
B
XXXXXXXX
B
00000000
B
00000000
B
—
000030H PPGC0
PPG0 operation mode control
register
R/W
8/16-bit PPG0
0–000001
B
000031H PPGC1
PPG1 operation mode control
register
R/W
8/16-bit PPG1
00000001
B
000032H,
33H
Vacancy
—
000034H PRLL0/
000035H PRLH0
PPG0 reload register
000036H PRLL1/
000037H PRLH1
PPG1 reload register
000038H
000039H
TMCSR0 Timer control status register
00003AH TMR0/
00003BH TMRLR0
00003CH
00003DH
16-bit timer register/
16-bit reload register
TMCSR1 Timer control status register
00003EH TMR1/
00003FH TMRLR1
16-bit timer register/
16-bit reload register
000040H
to 47H
Vacancy
—
*3
R/W
R/W
—
8/16-bit PPG0
8/16-bit PPG1
R/W!
16-bit reload
timer 0
R/W
R/W!
16-bit reload
timer 1
R/W
*3
—
—
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
00000000
B
––––0000
B
XXXXXXXX
B
XXXXXXXX
B
00000000
B
––––0000
B
XXXXXXXX
B
XXXXXXXX
B
—
000048H CSCR0
Chip select control register 0
R/W
––––0000
B
000049H CSCR1
Chip select control register 1
R/W
––––0000
B
00004AH CSCR2
Chip select control register 2
R/W
––––0000
B
00004BH CSCR3
Chip select control register 3
R/W
––––0000
B
00004CH CSCR4
Chip select control register 4
R/W
––––0000
B
00004DH CSCR5
Chip select control register 5
R/W
––––0000
B
00004EH CSCR6
Chip select control register 6
R/W
––––0000
B
00004FH CSCR7
Chip select control register 7
R/W
––––0000
B
000050H
Vacancy
*3
UART0 (SCI) machine clock division
control register
W
—
000051H CDCR0
Chip select
function
—
UART0 (SCI)
—
––––1111
B
(Continued)
22
MB90640A Series
Address
Name
000052H
—
Register
Read/
write*4,*5
Vacancy
*3
000053H CDCR1
UART1 (SCI) machine clock division
control register
W
000054H
to 57H
Vacancy
*3
000058H
000059H
—
TMCSR2 Timer control status register
00005AH TMR2/
00005BH TMRLR2
00005CH
00005DH
TMCSR3 Timer control status register
00005EH TMR3/
00005FH TMRLR3
000060H
000061H
16-bit timer register/
16-bit reload register
16-bit timer register/
16-bit reload register
TMCSR4 Timer control status register
000062H TMR4/
000063H TMRLR4
16-bit timer register/
16-bit reload register
Resource name
Initial value
—
—
UART1 (SCI)
—
R/W!
16-bit reload
timer 2
R/W
R/W!
16-bit reload
timer 3
R/W
R/W!
16-bit reload
timer 4
R/W
000064H
000065H TPCR
Timer pin control register
R/W
16-bit reload
timer
000066H
000067H
to 6EH
—
—
––––1111
—
00000000
B
––––0000
B
XXXXXXXX
B
XXXXXXXX
B
00000000
B
––––0000
B
XXXXXXXX
B
XXXXXXXX
B
00000000
B
––––0000
B
XXXXXXXX
B
XXXXXXXX
B
00010000
B
00110010
B
––––0100
B
Vacancy
*3
00006FH ROMM
ROM mirror functional selection
module
W
000070H
to 8FH
—
Vacancy
*3
—
—
000090H
to 9EH
—
Reserved system area
*1
—
—
Delayed interrupt
generation module
ROM
mirror function*9
00009FH DIRR
Delayed interrupt generation/
release register
R/W
0000A0H LPMCR
Low power consumption mode
control register
R/W!
0000A1H CKSCR
Clock selection register
R/W!
Low power
consumption
controller circuits
0000A2H
to A4H
Vacancy
*3
—
Auto-ready function selection
register
W
External bus pin
controller circuits
—
0000A5H ARSR
B
—
––––––– *
B
–––––––0
B
00011000
B
11111100
B
—
0011––00
B
(Continued)
23
MB90640A Series
(Continued)
Address
Name
Read/
write*4,*5
Register
Resource name
Initial value
External bus pin
controller circuits
00000000
B
–00 * 0000
B
0000A6H HACR
External address output control
register
W
0000A7H ECSR
Bus control signal selection register
W
0000A8H WDTC
Watchdog timer control register
R/W!
Watchdog timer
XXXXX 1 1 1
B
0000A9H TBTC
Timebase timer control register
R/W!
Timebase timer
1––00100
B
0000AAH
to AFH
Vacancy
—
*3
—
—
0000B0H ICR00
Interrupt control register 00
R/W!
00000111
B
0000B1H ICR01
Interrupt control register 01
R/W!
00000111
B
0000B2H ICR02
Interrupt control register 02
R/W!
00000111
B
0000B3H ICR03
Interrupt control register 03
R/W!
00000111
B
0000B4H ICR04
Interrupt control register 04
R/W!
00000111
B
0000B5H ICR05
Interrupt control register 05
R/W!
00000111
B
0000B6H ICR06
Interrupt control register 06
R/W!
00000111
B
0000B7H ICR07
Interrupt control register 07
R/W!
00000111
B
0000B8H ICR08
Interrupt control register 08
R/W!
00000111
B
0000B9H ICR09
Interrupt control register 09
R/W!
00000111
B
0000BAH
Vacancy
*3
—
R/W!
00000111
*3
—
—
0000BBH ICR11
Interrupt control register 11
0000BCH
Vacancy
—
Interrupt
controller
B
0000BDH ICR13
Interrupt control register 13
R/W!
00000111
B
0000BEH ICR14
Interrupt control register 14
R/W!
00000111
B
0000BFH ICR15
Interrupt control register 15
R/W!
00000111
B
0000C0H
to FFH
(External area)*2
Initial values
0: The initial value for this bit is “0”.
1: The initial value for this bit is “1”.
*: The initial value for this bit is “1” or “0”. (Determined by the level of the MD0 to MD2 pins.)
X: The initial value for this bit is undefined.
–: This bit is not used. The initial value is undefined.
*1: Access prohibited.
*2: This is the only external access area in the area below address 0000FFH. Access this address as an external
I/O area.
*3: Areas marked as “Vacancy” in the I/O map are reserved areas. These areas are accessed by internal access.
No access signals are output on the external bus.
*4: The R/W! symbol in the read/write column indicates that some bits are read-only or write-only. See the resource’s
register list for details.
(Continued)
24
MB90640A Series
(Continued)
*5: Using a read-modify-write instruction (such as the bit set instruction) to access one of the registers indicated
by R/W!, R/W*, or W in the read/write column sets the specified bit to the desired value. However, this can
cause misoperation if the other register bits include write-only bits. Therefore, do not use read-modify-write
instructions to access these registers.
*6: This register is only available when the address/data bus is in multiplex mode and in single-chip mode. Access
to the register is prohibited in non-multiplex mode.
*7: This register is only available when the external data bus is in 8-bit mode and in single-chip mode. Access to
the register is prohibited in 16-bit mode.
*8: All bits of DDR0/PDR0, 6-bit/7-bit of DDR5/PDR5 and 0-bit of DDRA/PDRA are available only in single-chip
mode.
*9: The initial value of this register in MB90V640A is “0” and that of in MB90P641A, MB90641A is “1”.
Note: The initial values listed for write-only bits are the initial values set by a reset. Take attention that they are not
the values returned by a read.
Also, LPMCR/CKSCR/WDTC are sometimes initialized and sometimes not initialized, depending on the reset
type. The listed initial values are for when these registers are initialized.
25
MB90640A Series
■ INTERRUPT VECTOR AND INTERRUPT CONTROL REGISTER
ASSIGNMENTS TO INTERRUPT SOURCES
Interrupt source
I2OS
support
Interrupt vector
Number
Interrupt control register
Address
ICR
Address
Reset
×
#08
08H
FFFFDCH
—
—
INT 9 instruction
×
#09
09H
FFFFD8H
—
—
Exception
×
#10
0AH
FFFFD4H
—
—
DTP/external interrupt #0
#11
0BH
FFFFD0H
ICR00
0000B0H
DTP/external interrupt #1
#13
0DH
FFFFC8H
ICR01
0000B1H
DTP/external interrupt #2
#15
0FH
FFFFC0H
ICR02
0000B2H
DTP/external interrupt #3
#17
11H
FFFFB8H
ICR03
0000B3H
16-bit reload timer #2
#18
12H
FFFFB4H
DTP/external interrupt #4
#19
13H
FFFFB0H
ICR04
0000B4H
16-bit reload timer #3
#20
14H
FFFFACH
DTP/external interrupt #5
#21
15H
FFFFA8H
ICR05
0000B5H
16-bit reload timer #4
#22
16H
FFFFA4H
DTP/external interrupt #6
#23
17H
FFFFA0H
ICR06
0000B6H
UART0 • send complete
#24
18H
FFFF9CH
DTP/external interrupt #7
#25
19H
FFFF98H
ICR07
0000B7H
UART1 • send complete
#26
1AH
FFFF94H
ICR08
0000B8H
ICR09
0000B9H
8/16-bit PPG #0
×
#27
1BH
FFFF90H
8/16-bit PPG #1
×
#28
1CH
FFFF8CH
16-bit reload timer #0
#29
1DH
FFFF88H
16-bit reload timer #1
#30
1EH
FFFF84H
Vacancy
#31
1FH
FFFF80H
ICR10
0000BAH
Timebase timer interval interrupt
×
#34
22H
FFFF74H
ICR11
0000BBH
Vacancy
—
#35
23H
FFFF70H
ICR12
0000BCH
UART1 • receive complete
#37
25H
FFFF68H
ICR13
0000BDH
UART0 • receive complete
#39
27H
FFFF60H
ICR14
0000BEH
#42
2AH
FFFF54H
ICR15
0000BFH
Delayed interrupt generation module
×
: indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (no stop request).
: indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (with stop request).
× : indicates that the interrupt request flag is not cleared by the I2OS interrupt clear signal.
Note: Do not specify I2OS activation in interrupt control registers that do not support I2OS.
26
MB90640A Series
■ PERIPHERAL RESOURCES
1. Parallel Port
The MB90640A series has 75 I/O pins, and 8 open-drain output pins.
Ports 0 to 5 and ports 7 to 9 and A are I/O ports. The ports are inputs when the corresponding direction register
bit is “0” and outputs when the corresponding bit is “1”.
Port 0 is only available in single-chip mode.
Port 1 is only available when in data bus 8-bit mode of non-multiplex mode or in single-chip mode.
Ports 2 and 3 are only available when the address/data bus is in multiplex mode and single-chip mode.
Port 6 is an open-drain port.
(1) Register Details
• Port data registers
• Port data register
Address : PDR1: 000001H
PDR3: 000003H
PDR5: 000005H
PDR7: 000007H
PDR9: 000009H
Address : PDR0 : 000000H
PDR2 : 000002H
PDR4 : 000004H
PDR6 : 000006H
PDR8 : 000008H
PDRA: 00000AH
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
PDx7
PDx6
PDx5
PDx4
PDx3
PDx2
PDx1
PDx0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
PDx7
PDx6
PDx5
PDx4
PDx3
PDx2
PDx1
PDx0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Readable and writable
X : Indeterminate
Note: No register bit is provided for bits 0, 7 of port 7.
No register bit is provided for bit 7 of port 8.
No register bits are provided for bits 7, 6 of port 9.
Port 0 is only available in single-chip mode.
Bits 7, 6 of port 5 and bit 0 of port A are only available in single-chip mode.
Port 1 is only available when the external data bus is in 8-bit mode and single-chip mode.
Ports 2, 3 are only available in multiplex mode and single-chip mode.
Each port pin except port 6 can be specified as either an input or output by its corresponding direction register
when the pin is not set for use by a peripheral. When a port is set as an input, reading the data register always
reads the value corresponding to the pin level. When a port is set as an output, reading the data register reads the
data register latch value. The same applies when reading using a read-modify-write instruction.
When used as control outputs, reading the data register reads the control output value, irrespective of the direction
register value.
27
MB90640A Series
Notes: • If read-modify-write instructions (bit set instruction, etc.) are used to access this register, the bit that is the
focus of the instruction is set to the prescribed value, but the contents of the output register corresponding
to any other bits for which the input setting has been made are overwritten with the current input value of
the corresponding pin. Therefore, when switching a pin that was being used for input over to output, first
write the desired value to PDR, and then set the data DDR as output direction.
• Reading and writing an I/O port differs from reading and writing memory as follows:
Input mode
Reads: The read data is the level of the corresponding pin.
Writes: The write data is stored in the output latch. The data is not output to the pin.
Output mode
Reads: The read data is the value stored in the PDR.
Writes: The write data is both stored in the output latch and output to the pin.
• Take attention that the operation of R/W in port 6 is different from that of in other port.
Port 6 (P67 to P60) is an general-purpose I/O port with an open-drain output. When port 6 is used as a generalpurpose port, always be sure to set the corresponding bits in DDR6 to “0”.
When port 6 is used as an input port, it is necessary set the output port data register value to “1” in order to turn
off the open-drain output transistor; it is also necessary to connect a pull-up resistor to the external pins.
In addition, depending on the instruction used to read these bits, one of the following two different operations is
performed:
• When read by a read-modify-write instruction:
The contents of the output port data register are read. Even if pins are forcibly set to “0” externally, the contents
of the bits not specified by the instruction do not change.
• When read by any other instruction:
The pin level can be read.
When used as output ports, the pin values can be changed by writing the desired value to the corresponding
output port data register.
In addition, the pin which corresponds to the bit of which port 6 direction register is set to “1” can be read “0”.
• Port direction registers
• Port direction register
Address : DDR1 : 000011H
DDR3 : 000013H
DDR5 : 000015H
DDR7 : 000017H
DDR9 : 000019H
Address : DDR0 : 000010H
DDR2 : 000012H
DDR4 : 000014H
DDR8 : 000018H
DDRA: 00001AH
R/W : Readable and writable
28
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
DDx7
DDx6
DDx5
DDx4
DDx3
DDx2
DDx1
DDx0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
DDx7
DDx6
DDx5
DDx4
DDx3
DDx2
DDx1
DDx0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MB90640A Series
Note: No register bit is provided for bits 0, 7 of port 7.
No register bit is provided for bit 7 of port 8.
No register bits are provided for bits 6, 7 of port 9.
Port 1 is only available in single-chip mode.
Port 1 is only available when the external data bus is in 8-bit mode and single-chip mode.
Ports 2, 3 are only available in multiplex mode and single-chip mode.
When pins are used as ports, the register bits control the corresponding pins as follows.
0: Input mode
1: Output mode
Bits are set to “0” by a reset.
• Port 6 direction register
• Port 6 direction register
bit 15
Address : DDR6 : 000016H
bit 8
Initial value
DD67 DD66 DD65 DD64 DD63 DD62 DD61 DD60
11111111B
R/W
bit 14
R/W
bit 13
R/W
bit 12
R/W
bit 11
R/W
bit 10
R/W
bit 9
R/W
R/W
R/W: Readable and writable
Controls each pin of port 6 as follows.
0: Port input mode
1: Analog input mode
Bits are set to “1” by a reset.
29
MB90640A Series
(2) Block Diagrams
• I/O port
Internal data bus
Data register read
Data register
Pin
Data register write
Direction register
Direction register write
Direction register read
• Open-drain port
RMW
(Read-modify-write instruction)
Pin
Internal data bus
Data register read
Data register
Data register write
DDR6
DDR6 register write
DDR6 register read
30
MB90640A Series
(3) Port Pin Allocation
Ports 1, 4, and 5 on the MB90640A series share pins with the external bus. The pin functions are determined
by the bus mode and register settings.
Function
Pin name
Non-multiplex mode
Multiplex mode
External address control
External address control
Enable (address)
Disable (port)
Enable (address)
Disable (port)
External bus width
External bus width
External bus width
External bus width
8 bits
8 bits
8 bits
16 bits
D07 to D00/
16 bits
16 bits
D07 to D00
AD07 to AD00
P17 to P10/
D15 to D08/
8 bits
Port
D15 to D08
Port
16 bits
AD07 to AD00
D15 to D08 A15 to A08 AD15 to AD08 A15 to A08 AD15 to AD08
AD15 to AD08
P27 to P20/
A07 to A00
A07 to A00
P37 to P30/
A15 to A08
A15 to A08
P47 to P40/
A23 to A16
Port
A23 to A16
Port
A23 to A16
Port
P57/ALE
ALE
ALE
RD
RD
RD
WRL
WRL
P55/WRL
P54/WRH
Port
WRH
Port
WRH
Port
WRH
Port
P53/HRQ
HRQ
HRQ
P52/HAK
HAK
HAK
P51/RDY
RDY
RDY
P50/CLK
CLK
CLK
WRH
Notes: • The upper address, WRL, WRH, HAK, HRQ, RDY, and CLK can be set for use as ports by function selection.
• The pins mentioned above can be used as a port in single-chip mode.
31
MB90640A Series
2. UART0, 1 (SCI)
UART0, 1 are serial I/O ports that can be used for CLK asynchronous (start-stop synchronization) or CLK
synchronous (I/O expansion serial) data transfer. The ports have the following features.
• Full duplex, double buffered
• Supports CLK asynchronous (start-stop synchronization) and CLK synchronous (I/O expansion serial) data
transfer
• Multi-processor mode support
• Built-in dedicated baud rate generator
CLK asynchronous: 62500 bps/31250 bps/19230 bps/9615 bps/4808 bps/2404 bps/1202 bps
CLK synchronous: 2 Mbps/1 Mbps/500 kbps/250 kbps
• Supports flexible baud rate setting using an external clock
• Error detect function (parity, framing, and overrun)
• NRZ type transmission signal
• Intelligent I/O service support
(1)
Register Configuration
• Serial mode register 0, 1
Address : SMR0 : 000020H
SMR1 : 000024H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
MD1
MD0
CS2
CS1
CS0
—
SCKE
SOE
00000-00B
R/W
R/W
W
W
W
—
R/W
R/W
• Serial control register 0, 1
Address : SCR0: 000021H
SCR1: 000025H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
PEN
P
SBL
CL
A/D
REC
RXE
TXE
00000100B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Input data register 0, 1/output data register 0, 1
Address : SIDR0 (read) /
SODR0 (write)
: 000022H
SIDR1 (read) /
SODR1 (write)
: 000026H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Serial status register 0, 1
Address : SSR0: 000023H
SSR1: 000027H
bit 15
bit 14
bit 13
bit 12
PE
ORE
FRE
RDRF TDRE
R
R
R
R
bit 11
R
bit 10
bit 9
bit 8
Initial value
00001- 00B
—
RIE
TIE
—
R/W
R/W
• Machine clock division control register for UART0, 1 (SCI)
Address : CDCR0: 000051H
CDCR1: 000053H
R/W : Readable and writable
R : Read only
W : Write only
— : Unused
X : Indeterminate
32
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
—
—
—
—
DIV3
DIV2
DIV1
DIV0
- - - -1111B
—
—
—
—
W
W
W
W
MB90640A Series
(2) Block Diagram
Control signals
Receive interrupt
(to CPU)
Dedicated baud
rate generator
SCK
16-bit timer 0
(Internal connection)
Transmit interrupt
(to CPU)
Transmit clock
Clock select
circuit
Receive clock
External clock
SIN
Receive control circuit
Transmit control circuit
Start bit
detect circuit
Transmit start circuit
Receive bit counter
Transmit bit counter
Receive parity
counter
Transmit parity
counter
SOT
Receive status
evaluation circuit
Receive error
indication signal
for EI2OS (to CPU)
Receive shifter
Transmit shifter
Receive
complete
Transmit
start
SODR
SIDR
Internal data bus
SMR
register
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
SCR
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
Control signals
33
MB90640A Series
3. 8/16-bit PPG
8/16-bit PPG contains the 8-bit reload timer module. The block performs PPG output in which the pulse output
is controlled by the operation of the timer.
The hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two
external pulse output pins, and two interrupt outputs. The PPG has the following functions.
• 8-bit PPG output in 2-channel independent operation mode: Two independent PPG output channels are
available.
• 16-bit PPG output operation mode: One 16-bit PPG output channel is available.
• 8+8-bit PPG output operation mode: Variable-period 8-bit PPG output operation is available by using the
output of channel 0 as the clock input to channel 1.
• PPG output operation: Outputs pulse waveforms with variable period and duty ratio.
Can be used as a D/A converter in conjunction with an external circuit.
(1)
Register Configuration
• PPG0 operation mode control register
Address : PPGC0: 000030H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
PEN0
—
POE0
PIE0
PUF0 PCM1 PCM0 Reserved
R/W
—
R/W
R/W
R/W
R/W
bit 1
R/W
bit 0
Initial value
0-000001B
—
• PPG1 operation mode control register
bit 15
Address : PPGC1: 000031H
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
PEN1 PCS1 POE1
PIE1
PUF1
MD1
MD0 Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
00000001B
• PPG0, PPG1 reload register H
Address : PRLH0: 000035H
PRLH1: 000037H
Initial value
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• PPG0, PPG1 reload register L
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address : PRLL0: 000034H
PRLL1: 000036H
XXXXXXXXB
R/W
R/W : Readable and writable
— : Unused
X : Indeterminate
34
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MB90640A Series
(2) Block Diagram
• 8/16-bit PPG (channel 0)
Output enable
PPG0
Peripheral clock divided by 16
Peripheral clock divided by 4
Peripheral clock
PPG0
output latch
Invert
Clear
PEN0
Count clock
selection
Timebase counter output
Main clock divided by 512
S
R Q
PCNT (down-counter)
IRQ
Reload
ch.1 borrow
L/H select
L/H selector
PRLL0
PRLBH0
PIE 0
PRLH0
PUF0
L-side data bus
H-side data bus
PPGC0
(Operation mode control)
35
MB90640A Series
• 8/16-bit PPG (channel 1)
Output enable
PPG1
Peripheral clock
PPG1
output latch
Invert
Count clock
selection
Clear
PEN1
channel 0 borrow
Timebase counter output
Main clock divided by 512
S
R Q
PCNT (down-counter)
IRQ
Reload
L/H select
L/H selector
PRLL1
PRLBH1
PIE1
PRLH1
PUF1
L-side data bus
H-side data bus
PPGC1
(Operation mode control)
36
MB90640A Series
4. 16-bit Reload Timer (with Event Count Function)
The 16-bit reload timers consists of a 16-bit down-counter, a 16-bit reload register, input pin (TIN), output pin
(TOT), and a control register. The input clock can be selected from one external clock and three types of internal
clock. The output (TOT) outputs a toggle waveform in reload mode and a rectangular waveform during counting
in one-shot mode. The input (TIN) functions as the event input in event count mode and as the trigger input or
gate input in internal clock mode.
Input and output of timer pin TIM0 to TIM4 are set by way of the timer pin control register.
This product has five internal 16-bit reload timer channels.
(1)
Register Configuration
• Timer control status register upper
Address : TMCSR0: 000039H
TMCSR1: 00003DH
TMCSR2: 000059H
TMCSR3: 00005DH
TMCSR4: 000061H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
—
—
—
—
CSL1
CSL0 MOD2 MOD1
—
—
—
—
R/W
R/W
R/W
bit 8
Initial value
- - - -0000B
R/W
• Timer control status register lower
Address : TMCSR0: 000038H
TMCSR1: 00003CH
TMCSR2: 000058H
TMCSR3: 00005CH
TMCSR4: 000060H
bit 7
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
MOD0 OUTE OUTL RELD
INTE
UF
CNTE
TRG
00000000B
R/W
R/W
R/W
R/W
R/W
bit 6
R/W
bit 5
R/W
R/W
• 16-bit timer register upper/16-bit reload register upper
Address : TMR0/TMRLR0 : 00003BH
TMR1/TMRLR1 : 00003FH
TMR2/TMRLR2 : 00005BH
TMR3/TMRLR3 : 00005FH
TMR4/TMRLR4 : 000063H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• 16-bit timer register lower/16-bit reload register lower
Address : TMR0/TMRLR0 : 00003AH
TMR1/TMRLR1 : 00003EH
TMR2/TMRLR2 : 00005AH
TMR3/TMRLR3 : 00005EH
TMR4/TMRLR4 : 000062H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
XXXXXXXXB
R/W : Readable and writable
— : Unused
X : Indeterminate
37
MB90640A Series
• Timer pin control register upper
bit 7
bit 6
bit 5
bit 4
—
—
—
—
—
—
Address : TPCR : 000066H
bit 3
bit 2
bit 0
Initial value
—
OTE4 CSC4 CSB4 CSA4
- - - -0100B
—
R/W
R/W
bit 1
R/W
R/W
• Timer pin control register middle
bit 15
Address : TPCR : 000065H
bit 8
Initial value
OTE3 CSC3 CSB3 CSA3 OTE2 CSC2 CSB2 CSA2
00110010B
R/W
bit 14
R/W
bit 13
R/W
bit 12
R/W
bit 11
R/W
bit 10
R/W
bit 9
R/W
R/W
• Timer pin control register lower
bit 7
Address : TPCR : 000064H
bit 0
Initial value
OTE1 CSC1 CSB1 CSA1 OTE0 CSC0 CSB0 CSA0
00010000B
R/W
R/W : Readable and writable
— : Unused
X : Indeterminate
38
bit 6
R/W
bit 5
R/W
bit 4
R/W
bit 3
R/W
bit 2
R/W
bit 1
R/W
R/W
MB90640A Series
(2) Block Diagram
16
16-bit reload register
8
Reload
RELD
16
16-bit down-counter
OUTE
UF
OUTL
Internal data bus
2
OUT
CTL
GATE
INTE
UF
IRQ
CSL1
Clock selector
CNTE
CSL0
TRG
2
Clear
I2OSCLR
Re-trigger
IN CTL
TIN0 to TIN4
EXCK
φ φ
— —
21 23
φ
—
25
Output enable
3
Prescaler
Clear
TOT0 to TOT4
MOD2
Serial baud rate
A/D converter
MOD1
Peripheral clock
MOD0
3
TIN0
TOT0
TIM0
16-bit reload timer 1
TIN1
TOT1
TIM1
16-bit reload timer 2
TIN2
TOT2
16-bit reload timer 3
TIN3
TOT3
TIM3
16-bit reload timer 4
TIN4
TOT4
TIM4
Selector
16-bit reload timer 0
TIM2
Note: Timer channel and direction (I/O) can be selected for each pin.
39
MB90640A Series
5. Chip Select Function
This module generates chip select signals to simplify connection of memory or I/O devices.
The module has 8 chip select output pins. The hardware outputs the chip select signals from the pins when it
detects access of an address in the areas specified in the pin registers.
(1)
Register Configuration
• Chip select control register 1, 3, 5, 7
Address : CSCR1 : 000049H
CSCR3 : 00004BH
CSCR5 : 00004DH
CSCR7 : 00004FH
bit 15
bit 14
bit 13
bit 12
—
—
—
—
R/W
R/W
R/W
R/W
bit 11
bit 8
Initial value
ACTL OPEL CSA1 CSA0
- - - -0000B
R/W
bit 10
R/W
bit 9
R/W
R/W
• Chip select control register 0, 2, 4, 6
Address : CSCR0 : 000048H
CSCR2 : 00004AH
CSCR4 : 00004CH
CSCR6 : 00004EH
bit 7
bit 6
bit 5
bit 4
—
—
—
—
R/W
R/W
R/W
R/W
bit 3
bit 2
bit 0
Initial value
ACTL OPEL CSA1 CSA0
- - - -0000B
R/W
R/W
bit 1
R/W
R/W
R/W : Readable and writable
— : Unused
(2)
Block Diagram
Address (from CPU)
A23
A16 A15
A08 A07
Address decoder
A00
Address decoder
Decode signal
Program area
Decode
CS0
(For the program ROM area)
40
Chip select control register 0
Selection setting
Selector
Chip select control register 1
Selection setting
Selector
CS1
Chip select control register 6
Selection setting
Selector
CS6
Chip select control register 7
Selection setting
Selector
CS7
MB90640A Series
6. DTP/External Interrupts
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16L
CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the
requests to the F2MC-16L CPU to activate the extended intelligent I/O service or interrupt processing. Two
request levels (“H” and “L”) are provided for extended intelligent I/O service. For external interrupt requests,
generation of interrupts on a rising or falling edge as well as on “H”, “L” levels can be selected, giving a total of
four types.
(1)
Register Configuration
• Interrupt/DTP enable register
Address : ENIR : 000028H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Interrupt/DTP source register
Address : EIRR : 000029H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Request level setting register upper
Address : ELVR: 00002BH
• Request level setting register lower
Address : ELVR: 00002AH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Readable and writable
X : Indeterminate
(2)
Block Diagram
8
Interrupt input
Internal data bus
8
8
8
Interrupt/DTP enable register
Gate
Request F/F
Edge detect circuit
8
Request input
Interrupt/DTP register
Request level setting register
41
MB90640A Series
7. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to
the F2MC-16L CPU can be generated and cleared by software using this module.
(1)
Register Configuration
• Delayed interrupt generation/release register
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
—
—
—
—
—
—
—
R0
- - - - - - - 0B
—
—
—
—
—
—
—
R/W
Address : DIRR: 00009FH
R/W : Readable and writable
— : Unused
Block Diagram
Internal data bus
(2)
42
Delayed interrupt generation/release
register
Interrupt latch
MB90640A Series
8. ROM Mirror Functional Selection Module
ROM mirror function selecting module can be refered to the upper 48 Kbytes of FF bank which is wired ROM
at 00 bank by selecting the resister setting.
(1)
Register Configuration
• ROM mirror functional selection module
Address : ROMM: 00006FH
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
—
—
—
—
—
—
—
MI
-------*B
—
—
—
—
—
—
—
W
W : Write only
— : Unused
* : “1” or “0” (determined owing to the MD0 to MD2 pin level)
Notes: • The initial value of MB90V640A is “0” and that of MB90P641A, MB90641A is “1”.
• Not to access to this register while address 04000H to 00FFFFH are in operation.
Block Diagram
ROM mirror functional selection module
Internal data bus
(2)
Address area
Address
Data
FF bank
00 bank
ROM
43
MB90640A Series
9. Watchdog Timer and Timebase Timer
The watchdog timer consists of a 2-bit watchdog counter, a control register, and a watchdog reset controller.
The watchdog counter uses the carry-up signal from the 18-bit timebase timer as its clock source.
In addition to the 18-bit timer, the timebase timer contains an interval interrupt control circuit. The timebase
timer uses the main clock, regardless of the value of the MCS bit in the CKSCR register.
(1)
Register Configuration
• Watchdog timer control register
bit 7
Address : WDTC: 0000A8H
bit 6
bit 3
bit 2
bit 1
bit 0
Initial value
PONR STBR WRST ERST SRST
WTE
WT1
WT0
XXXXX111B
W
W
W
R
bit 5
R
bit 4
R
R
R
• Timebase timer control register
Address : TBTC : 0000A9H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
Reserved
—
—
TBIE
TBOF
TBR
—
—
—
R/W
R/W
W
bit 9
bit 8
Initial value
TBC1 TBC0
1- - 00100B
R/W
R/W
R/W : Readable and writable
R : Read only
W : Write only
— : Unused
X : Indeterminate
(2)
Block Diagram
Main clock
(OSC oscillator)
TBTC
TBC1
Selector
TBC0
Clock input
212
214
Timebase timer
216
219
212 214 216 219
TBTRES
TBR
TBIE
AND
Q
S
R
Internal data bus
TBOF
Timebase
interrupt
WDTC
WT1
Selector
WT0
2-bit counter
OF
CLR
Watchdog reset
activation circuit
CLR
WDGRST
To internal reset
activation circuit
WTE
PONR
From power-on detection
STBR
From hardware standby
control circuit
WRST
44
ERST
RST pin
SRST
From the RST bit of the
STBYC register
MB90640A Series
10. Low-power Control Circuits (CPU Intermittent Operation Function, Oscillation Stabilization
Delay Time, and Clock Multiplier Function)
The following operation modes are available: PLL clock mode, PLL sleep mode, timer mode, main clock mode,
main sleep mode, stop mode, and hardware standby mode. Operation modes other than PLL clock mode are
classified as low-power consumption modes.
In main clock mode and main sleep mode, the device operates on the main clock only (OSC oscillator clock).
The PLL clock (VCO oscillator clock) is stopped in these modes and the main clock divided by 2 is used as the
operating clock.
In PLL sleep mode and main sleep mode, the CPU’s operating clock only is stopped and other elements continue
to operate.
In timer mode, only the timebase timer operates.
Stop mode and hardware standby mode stop the oscillator. These modes maintain existing data with minimum
power consumption.
The CPU intermittent operation function provides an intermittent clock to the CPU when register, internal memory,
internal resource, or external bus access is performed. This function reduces power consumption by lowering
the CPU execution speed while still providing a high-speed clock to internal resources.
The PLL clock multiplier ratio can be set to 1, 2, 3, 4 by the CS1, CS0 bits.
The WS1, WS0 bits set the delay time to wait for the main clock oscillation to stabilize when recovering from
stop mode or hardware standby mode.
(1)
Register Configuration
• Low-power consumption mode control register
Address : LPMCR: 0000A0H
bit 7
bit 6
bit 5
bit 4
bit 3
STP
SLP
SPL
RST Reserved CG1
W
W
R/W
W
—
bit 2
R/W
bit 1
bit 0
CG0 Reserved
R/W
Initial value
00011000B
—
• Clock select register
bit 15
Address : CKSCR: 0000A1H
bit 14
bit 13
bit 12
bit 10
bit 9
bit 8
Initial value
Reserved MCM
WS1
WS0 Reserved MCS
CS1
CS0
11111100B
R/W
R/W
R/W
R/W
—
R
bit 11
—
R/W
R/W : Readable and writable
R : Read only
W : Write only
45
MB90640A Series
(2)
Block Diagram
CKSCR
MCM
MCS
PLL multiplier
circuit
1 2 3 4
Main clock
(OSC oscillator)
CPU clock
1/2
CPU clock
generator
CKSCR
CS1
CS0
CPU
clock selector
0/9/17/33
Intermittent
cycle selection
LPMCR
CG1
Internal data bus
CG0
Cycle selection circuit
for the CPU intermittent
operation function
LPMCR
SLP
Standby control circuit
STP
RST Release HST activate
Peripheral
clock
generator
Peripheral clock
HST pin
CKSCR
WS1
WS0
Interrupt request
or RST
Oscillation
stabilization
delay time
selector
24
213
215
218
Clock input
Timebase clock
Timebase timer
12
2
2
14
2
16
19
2
LPMCR
SPL
LPMCR
RST
Pin high impedance control circuit
Pin Hi-Z
Internal reset
generation circuit
Internal RST
RST pin
To watchdog timer
WDGRST
46
MB90640A Series
• State transition diagram for clock selection
Power-on
Main
MCS = 1
MCM = 1
CS1/0 = XX
(1)
Main → PLLX
MCS = 0
MCM = 1
(6) CS1/0 = XX
(2)
(3)
(7)
PLL1 → Main
MCS = 1
MCM = 0
CS1/0 = 00
PLL multiplier = 1
MCS = 0
MCM = 0
(6)
CS1/0 = 00
PLL2 → Main
MCS = 1
MCM = 0
(7)
CS1/0 = 01
PLL multiplier = 2
MCS = 0
MCM = 0
CS1/0 = 01
(7)
(6)
(4)
PLL3 → Main
PLL multiplier = 3
(5) MCS = 0
(7) MCS = 1
MCM = 0
CS1/0 = 10
PLL4 → Main
MCS = 1
MCM = 0
CS1/0 = 11
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(6)
(6)
MCM = 0
CS1/0 = 10
PLL multiplier = 4
MCS = 0
MCM = 0
CS1/0 = 11
MCS bit cleared
PLL clock oscillation stabilization delay complete and CS1/0 = 00
PLL clock oscillation stabilization delay complete and CS1/0 = 01
PLL clock oscillation stabilization delay complete and CS1/0 = 10
PLL clock oscillation stabilization delay complete and CS1/0 = 11
MCS bit set (including a hardware standby or watchdog reset)
PLL clock and main clock synchronized timing
47
MB90640A Series
11. Interrupt Controller
The interrupt control registers are located in the interrupt controller. An interrupt control register is provided for
each I/O with an interrupt function. The registers have the following three functions.
• Set the interrupt level of the corresponding peripheral.
• Select whether to treat interrupts from the corresponding peripheral as standard interrupts or activate the
extended intelligent I/O service.
• Select the extended intelligent I/O service channel.
(1)
Register Configuration
• Interrupt control register 01, 03, 05, 07, 09, 11, 13, 15
Address : ICR01: 0000B1H
ICR03: 0000B3H
ICR05: 0000B5H
ICR07: 0000B7H
ICR09: 0000B9H
ICR11: 0000BBH
ICR13: 0000BDH
ICR15: 0000BFH
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
ICS3
ICS2
ICS1
or
S1
ICS0
or
S0
ISE
IL2
IL1
IL0
00000111B
W
W
R/W
R/W
R/W
R/W
R/W
R/W
• Interrupt control register 00, 02, 04, 06, 08, 10, 12, 14
Address : ICR00: 0000B0H
ICR02: 0000B2H
ICR04: 0000B4H
ICR06: 0000B6H
ICR08: 0000B8H
ICR14: 0000BEH
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
ICS3
ICS2
ICS1
or
S1
ICS0
or
S0
ISE
IL2
IL1
IL0
00000111B
W
W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
R/W : Readable and writable
W : Write only
Note: Do not access these registers using read-modify-write instructions as this can cause misoperation.
48
MB90640A Series
(2) Block Diagram
4
I SE
I L2
I L1
IL0
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
I2OS selection
Internal data bus
4
I CS3 I CS2
I CS1 I C S 0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
I2OS vector selection
Interrupt
/I2OS request
(peripheral resource)
3
(CPU)
Interrupt level
4
I2OS vector
(CPU)
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
4
32
Determine priority
of interrupt or I2OS
4
4
4
S1
S0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Detect I2OS
completion condition
2
I2OS completion condition
49
MB90640A Series
12. External Bus Terminal Control Circuit
This circuit controls the external bus terminals intended to extend outwardly the CPU’s address/data bus.
(1)
Register Configuration
• Register for selection of AUTO ready function
Address : ARSR: 0000A5H
bit 15
bit 14
IOR1
IOR0
W
W
bit 13
bit 12
bit 11
bit 10
—
—
—
—
HMR1 HMR0
W
W
bit 9
bit 8
Initial value
LMR1 LMR0
0011- - 00B
W
W
• Register for control of external address output
Address : HACR: 0000A6H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
E23
E22
E21
E20
E19
E18
E17
E16
00000000B
W
W
W
W
W
W
W
W
• Register for selection of bus control signal
Address : ECSR: 0000A7H
bit 15
bit 14
bit 13
—
LMBS
WRE
—
W
W
bit 12
bit 11
HMBS IOBS
W
W
bit 10
bit 9
bit 8
Initial value
HDE
RYE
CKE
-00*0000B
W
W
W
W : Write only
— : Unused
X : Indeterminate
* : “1” or “0” (determined owing to the MD0 to MD2 pin level)
(2)
Block Diagram
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Port 0 data register
Port 0 direction register
RB
Data control
Access control
Access control
50
Access control
Port 5 pin
Port 4 pin
Port 3 pin
Port 2 pin
Port 1 pin
Port 0 pin
MB90640A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Rating
(VSS = AVSS = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min.
Max.
VCC
VSS – 0.3
VSS + 6.0
V
Input voltage*
VI
VSS – 0.3
VCC + 0.3
V
Output voltage*1
VO
VSS – 0.3
VCC + 0.3
V
IOL
—
15
mA
“L” level average output current*
IOLAV
—
4
mA
“L” level total maximum output current
ΣIOL
—
100
mA
“L” level total average output current*4
ΣIOLAV
—
50
mA
IOH
—
–15
mA
“H” level average output current*
IOHAV
—
–4
mA
“H” level total maximum output current
ΣIOH
—
–100
mA
“H” level total average output current*4
ΣIOHAV
—
–50
mA
Power consumption
PD
—
+150
mW
MB90641A
—
+400
mW
MB90P641A
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
Power supply voltage
1
“L” level maximum output current*2
3
“H” level maximum output current*
2
3
*1:
*2:
*3:
*4:
VI and VO must not exceed VCC + 0.3 V.
The maximum output current must not be exceeded at any individual pin.
The average output current is the operating current running through an appropriate pin × the operating rate.
The average total output current is the operating current running through all the appropriate pins × the operating
rate.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
51
MB90640A Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V)
Parameter
Power supply voltage
“H” level input voltage
“L” level input voltage
Symbol
Value
Unit
Remarks
Min.
Max.
VCC
4.5
5.5
V
For normal operation
VCC
3.5
5.5
V
To maintain statuses in stop mode
VIH
2.2
VCC + 0.3
V
TTL level input pins
VIHC
0.7 VCC
VCC + 0.3
V
CMOS level input pins
VIHS
0.8 VCC
VCC + 0.3
V
Hysteresis input pins*
VIHM
VCC – 0.3
VCC + 0.3
V
MD input pin
VIL
VSS – 0.3
0.8
V
TTL level input pins
VILC
VSS – 0.3
0.3 VCC
V
CMOS level input pins
VILS
VSS – 0.3
0.2 VCC
V
Hysteresis input pins*
VILM
VSS – 0.3
VSS + 0.3
V
MD input pin
Use the ceramic capacitor or the
capacitor which has the similar
frequency characteristic as ceramic
capacitor.
When attach the smoothing capacitor
to VCC, use the capacitor whose
capacitance is larger than CS.
Smoothing capacitor
CS
0.1
1.0
µF
Operating temperature
TA
–40
+85
°C
* : Target pins are P60 to P67, P71 to P76, P80 to P86, P90 to P95, HST, and RST. (When used as general purpose
pins)
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
52
MB90640A Series
3. DC Characteristics
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin name
Condition
Value
Unit Remarks
Min.
Typ.
Max.
VCC – 0.5
—
—
V
“H” level output
VOH
voltage
Other than
P60 to P67
VCC = 4.5 V,
IOH = –4.0 mA
“L” level output
VOL
voltage
All output
pins
VCC = 4.5 V,
IOL = 4.0 mA
—
—
0.4
V
Input leakage
current
Other than
P60 to P67
VCC = 5.5 V,
VSS < VI < VCC
–5
—
5
µA
IIL
Open-drain
output leakage Ileak
current
P60 to P67
—
—
0.1
5
µA
Pull-up
resistance
RUP
—
—
15
50
100
kΩ
Pull-down
resistance
RDOWN
—
—
15
50
200
kΩ
Internal 16 MHz operation
Normal operation
—
50
70
mA
MB90V640A/
P641A
—
15
20
mA
MB90641A
Internal 16 MHz operation
Sleep mode
—
25
30
mA
MB90V640A/
P641A
—
5
10
mA
MB90641A
TA = +25°C
Stop mode
—
0.1
10
µA
MB90V640A/
P641A
—
5
20
µA
MB90641A
—
10
—
pF
ICC
Power supply
current*
ICCS
VCC = 5.0 V
ICCH
Input
capacitance
CIN
Other than
VCC, VSS, C
—
* : Because the current values are tentative values, they are subject to change without notice due to our efforts to
improve the characteristics of these devices.
53
MB90640A Series
4. AC Characteristics
(1) Clock Timing
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol Pin name
Conditions
Value
Min.
Max.
Unit
Source oscillation frequency
FC
X0, X1
—
3
17
MHz
Source oscillation cycle time
tC
X0, X1
—
58.8
333
ns
Frequency variation ratio*
(when locked)
∆f
—
—
—
5
%
Input clock pulse width
PWH
PWL
X0
—
10
—
ns
Input clock rise time and fall
time
tcr
tcf
X0
—
—
5
ns
Internal operating clock
frequency
fCP
—
—
1.5
17
MHz
Internal operating clock cycle
time
tCP
—
—
58.8
666
ns
Remarks
The duty ratio
should be in the
range 30 to 70%
* : The frequency variation ratio is the maximum variation from the specified central frequency when the multiplier
PLL is locked. The value is expressed as a proportion.
∆f =
ıαı
f0
+α
× 100 (%)
Central frequency f0
–α
• Clock timing
tC
0.8 VCC
0.2 VCC
PWH
PWL
tcf
54
tcr
MB90640A Series
• PLL operation assurance range
Power supply VCC (V)
Relationship between the internal operating clock frequency and supply voltage
5.5
4.5
1.5
8
4
17
Internal clock fCP (MHz)
: Normal operation assurance range
: PLL operation assurance range
Relationship between the oscillation frequency and internal operating clock frequency
17
16
Multiply Multiply
by 4
by 3
Internal Clock fCP (MHz)
Multiply by 2
Multiply by 1
12
9
8
No multiplier
4
3 4
8
16 17
Oscillation clock FC (MHz)
55
MB90640A Series
The AC characteristics are for the following measurement reference voltages.
• Input signal waveform
• Output signal waveform
Hysteresis input pins
Output pins
0.8 VCC
2.4 V
0.2 VCC
0.8 V
Other than hysteresis/MD input pins
0.7 VCC
0.3 VCC
(2)
Clock Output Timing
Parameter
Symbol
Cycle time
tCYC
CLK ↑ → CLK ↓
tCHCL
Pin name
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Conditions
Unit Remarks
Min.
Max.
CLK
—
tCP
—
ns
tCP/2 – 20
tCP/2 + 20
ns
tCP: See “ (1) Clock Timing.”
tCYC
tCHCL
2.4 V
CLK
56
2.4 V
0.8 V
MB90640A Series
(3)
Recommended Resonator Manufacturers
• Sample application of piezoelectric resonator (FAR family)
X0
X1
R
FAR
*2
C1
C2
*2
*1
*1: Fujitsu Acoustic Resonator
FAR part number
Frequency Dumping
(built-in capacitor type)
(MHz)
resistor
Initial deviation of
FAR frequency
(TA = +25°C)
Temperature
Loading
characteristics of
FAR frequency
capacitors*2
(TA = –20°C to +60°C)
FAR-C4CC-02000-L20
2.00
1 kΩ
±0.5%
±0.5%
FAR-C4CA-04000-M01
4.00
—
±0.5%
±0.5%
FAR-C4CB-08000-M02
8.00
—
±0.5%
±0.5%
FAR-C4CB-10000-M02
10.00
—
±0.5%
±0.5%
FAR-C4CB-16000-M02
16.00
—
±0.5%
±0.5%
Built-in
Inquiry: FUJITSU LIMITED
57
MB90640A Series
• Sample application of ceramic resonator
X0
X1
*
R
C1
Resonator
manufacturer*
Kyocera
Corporation
C2
Resonator
KBR-2.0MS
PBRC2.00A
KBR-4.0MSA
KBR-4.0MKS
PBRC4.00A
PBRC4.00B
KBR-6.0MSA
KBR-6.0MKS
PBRC6.00A
PBRC6.00B
KBR-8.0M
PBRC8.00A
PBRC8.00B
KBR-10.0M
PBRC10.00B
KBR-12.0M
PBRC12.00B
Frequency
(MHz)
2.00
4.00
6.00
8.00
10.00
12.00
C1 (pF)
C2 (pF)
R
150
150
33
Built-in
33
Built-in
33
Built-in
33
Built-in
33
33
Built-in
33
Built-in
33
Built-in
150
150
33
Built-in
33
Built-in
33
Built-in
33
Built-in
33
33
Built-in
33
Built-in
33
Built-in
Not required
Not required
680 Ω
680 Ω
680 Ω
680 Ω
Not required
Not required
Not required
Not required
560 Ω
Not required
Not required
330 Ω
680 Ω
330 Ω
680 Ω
(Continued)
58
MB90640A Series
(Continued)
Resonator
manufacturer
Murata Mfg. Co.,
Ltd.
Resonator
CSA2.00MG040
CST2.00MG040
CSA4.00MG040
CST4.00MGW040
CSA6.00MG
CST6.00MGW
CSA8.00MTZ
CST8.00MTW
CSA10.00MTZ
CST10.00MTW
CSA12.00MTZ
CST12.00MTW
CSA16.00MXZ040
CST16.00MXW0C3
CSA20.00MXZ040
CSA24.00MXZ040
CSA32.00MXZ040
Frequency
(MHz)
2.00
4.00
6.00
8.00
10.00
12.00
16.00
20.00
24.00
32.00
C1 (pF)
C2 (pF)
R
100
Built-in
100
Built-in
30
Built-in
30
Built-in
30
Built-in
30
Built-in
15
Built-in
10
5
5
100
Built-in
100
Built-in
30
Built-in
30
Built-in
30
Built-in
30
Built-in
15
Built-in
10
5
5
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Inquiry: Kyocera Corporation
• AVX Corporation
North American Sales Headquarters: TEL 1-803-448-9411
• AVX Limited
European Sales Headquarters: TEL 44-1252-770000
• AVX/Kyocera H.K. Ltd.
Asian Sales Headquarters: TEL 852-363-3303
Murata Mfg. Co., Ltd.
• Murata Electronics North America, Inc.: TEL 1-404-436-1300
• Murata Europe Management GmbH: TEL 49-911-66870
• Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233
59
MB90640A Series
(4)
Reset and Hardware Standby Inputs
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol Pin name
Conditions
Value
Min.
Max.
Unit
Reset input time
tRSTL
RST
—
16 tCP
—
ns
Hardware standby input time
tHSTL
HST
—
16 tCP
—
ns
Remarks
tCP: See “ (1) Clock Timing.”
tRSTL, tHSTL
RST
HST
0.2 VCC
0.2 VCC
• Conditions for measurement of AC reference
Pin
CL: Load capacity during testing
For CLK and ALE, CL = 30 pF
For address and data buses (AD15 to AD00), RD and WR, CL = 80 pF
CL
60
MB90640A Series
(5)
Power on Supply Specifications (Power-on Reset)
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol Pin name
Conditions
Value
Min.
Max.
Unit
Power supply rise time
tR
VCC
—
0.05
30
ms
Power supply cut-off time
tOFF
VCC
—
50
—
ms
Remarks
For repetition of
the operation
* : VCC should be lower than 0.2 V before power supply rise.
Notes: • The above values are the values required for a power-on reset.
• When HST = “L”, this standard must be followed to turn on power supply for power-on reset whether or
not necessary.
• The device has built-in registers which are initialized only by power-on reset. For possible initialization of
these registers, turn on power supply according to this standard.
tR
tOFF
2.7 V
VCC
0.2 V
0.2 V
0.2 V
Abrupt changes in the power supply voltage may cause a power-on reset.
When changing the power supply voltage during operation, the change should be
as smooth as possible, as shown in the following figure.
5.0 V
VCC
3.5 V
Holding RAM data
The gradient should be no
more than 50 mV/ms.
VSS
61
MB90640A Series
(6)
Bus Timing (Read)
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Conditions
Value
Min.
Max.
Unit
ALE
—
tCP/2 – 20
—
ns
Valid address → ALE ↓ time tAVLL
Address
—
tCP/2 – 20
—
ns
ALE ↓ → address valid time tLLAX
Address
—
tCP/2 – 15
—
ns
Valid address → RD ↓ time
tAVRL
Address
—
tCP – 15
—
ns
Valid address → valid data
input
tAVDV
Address/
data
—
—
5 tCP/2 – 60
ns
RD pulse width
tRLRH
RD
—
3 tCP/2 – 20
—
ns
RD ↓ → valid data input
tRLDV
Data
—
—
3 tCP/2 – 60
ns
RD ↑ → data hold time
tRHDX
Data
—
0
—
ns
RD ↑ → ALE ↑ time
tRHLH
RD, ALE
—
tCP/2 – 15
—
ns
RD ↑ → address valid time
tRHAX
Address,
RD
—
tCP/2 – 10
—
ns
Valid address → CLK ↑ time tAVCH
Address,
CLK
—
tCP/2 – 20
—
ns
RD ↓ → CLK ↑ time
tRLCH
RD, CLK
—
tCP/2 – 20
—
ns
ALE ↓ → RD ↓ time
tLLRL
ALE, RD
—
tCP/2 – 15
—
ns
ALE pulse width
tCP: See “ (1) Clock Timing.”
62
Symbol Pin name
tLHLL
Remarks
MB90640A Series
tAVCH
tRLCH
2.4 V
CLK
tLLAX
tAVLL
ALE
2.4 V
2.4 V
tRHLH
2.4 V
0.8 V
tLHLL
2.4 V
tAVRL
tRLRH
2.4 V
RD
0.8 V
Multiplex mode
tRHAX
tLLRL
A23 to
A16
2.4 V
0.8 V
2.4 V
0.8 V
tRLDV
tAVDV
2.4 V
Address
0.8 V
tRHDX
2.4 V
2.2 V
0.8 V
0.8 V
Read data
0.8 V
Non-multiplex mode
A23 to
A00
tRHAX
2.4 V
0.8 V
2.4 V
0.8 V
tAVDVtAVDV
D15 to
D00
2.2 V
tRLDV
tRHDX
2.2 V
0.8 V
Read data
2.2 V
0.8 V
63
MB90640A Series
(7)
Bus Timing (Write)
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin name
Conditions
Value
Min.
Max.
Unit
Remarks
Valid address → WR ↓ time tAVWL
Address
—
tCP – 15
—
ns
WR pulse width
tWLWH
WRL, WRH
—
3 tCP/2 – 20
—
ns
Valid data output → WR ↑
time
tDVWH
Data
—
3 tCP/2 – 20
—
ns
20
—
ns
Multiplex
mode
30
—
ns
Non-multiplex
mode
tCP/2 – 10
—
ns
tCP/2 – 15
—
ns
tCP/2 – 20
—
ns
WR ↑ → data hold time
tWHDX
Data
WR ↑ → address valid time tWHAX
Address
WR ↑ → ALE ↑ time
tWHLH
WRL, WRH,
ALE
WR ↓ → CLK ↑ time
tWLCH
WRL, WRH,
CLK
—
—
tCP: See “ (1) Clock Timing.”
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tWLWH
tAVWL
2.4 V
WR
(WRL, WRH)
0.8 V
Multiplex mode
A23 to
A16
tWHAX
2.4 V
2.4 V
0.8 V
0.8 V
tDVWH
AD15 to
AD00
2.4 V
0.8 V
Address
2.4 V
0.8 V
0.8 V
tWHAX
2.4 V
2.4 V
0.8 V
0.8 V
tDVWH
D15 to
D00
64
2.4 V
Write data
Non-multiplex mode
A23 to
A00
tWHDX
2.4 V
0.8 V
Write data
tWHDX
tWHDX
2.4 V
0.8 V
MB90640A Series
(8)
Ready Input Timing
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
RDY setup time
tRYHS
RDY hold time
tRYHH
Pin name
RDY
Conditions
Value
Unit
Min.
Max.
VCC = 5.0 V ±10%
45
—
ns
—
0
—
ns
Remarks
Note: Use the auto-ready function if the setup time at fall of the RDY is too short.
2.4 V
CLK
2.4 V
ALE
RD/WR
tRYHS
tRYHS
RDY
(Wait cycle)
0.2 VCC
0.2 VCC
tRYHS
RDY
(No wait cycle)
0.8 VCC
0.8 VCC
tRYHH
65
MB90640A Series
(9)
Hold Timing
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin name
Conditions
Value
Min.
Max.
Unit
Pin floating → HAK ↓ time
tXHAL
HAK
—
30
tCP
ns
HAK ↑ → pin valid time
tHAHV
HAK
—
tCP
2 tCP
ns
tCP: See “ (1) Clock Timing.”
Note: After reading HRQ, more than one cycle is required before changing HAK.
2.4 V
HAK
0.8 V
tXHAL
Pin
66
tHAHV
High impedance
Remarks
MB90640A Series
(10) I/O Extended Serial Timing
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Min.
Max.
8 tCP
—
ns
–80
80
ns
100
—
ns
Serial clock cycle time
tSCYC
SCK0, SCK1
SCK ↓ → SOT delay time
tSLOV
SCK0, SCK1
SOT0, SOT1
Valid SIN → SCK ↑
tIVSH
SCK0, SCK1
SIN0, SIN1
SCK ↑ → valid SIN hold time tSHIX
SCK0, SCK1
SIN0, SIN1
60
—
ns
Serial clock “H” pulse width
tSHSL
SCK0, SCK1
4 tCP
—
ns
Serial clock “L” pulse width
tSLSH
SCK0, SCK1
4 tCP
—
ns
SCK ↓ → SOT delay time
tSLOV
SCK0, SCK1
SOT0, SOT1
—
150
ns
Valid SIN → SCK ↑
tIVSH
SCK0, SCK1
SIN0, SIN1
60
—
ns
SCK ↑ → valid SIN hold time tSHIX
SCK0, SCK1
SIN0, SIN1
60
—
ns
Notes: •
•
•
•
CL = 80 pF + 1 TTL
for the internal shift
clock mode output
pin.
CL = 80 pF + 1 TTL
for the external shift
clock mode output
pin.
Remarks
These are the AC characteristics for CLK synchronous mode.
CL is the load capacitance connected to the pin at testing.
tCP is the machine cycle period (unit: ns).
The values in the upper table are targets.
67
MB90640A Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
tSLOV
0.8 V
2.4 V
0.8 V
SOT
tIVSH
tSHIX
0.8 VCC
0.2 VCC
SIN
0.8 VCC
0.2 VCC
• External shift clock mode
tSLSH
tSHSL
SCK
0.2 VCC
tSLOV
SOT
0.2 VCC
2.4 V
0.8 V
tIVSH
SIN
68
0.8 VCC
0.8 VCC
0.8 VCC
0.2 VCC
tSHIX
0.8 VCC
0.2 VCC
MB90640A Series
(11) Timer Input Timing
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
tTIWH
tTIWL
Input pulse width
Pin name
Conditions
TIM0 to TIM4
—
Value
Min.
Max.
4 tCP
—
Unit
Remarks
ns
tCP: See “ (1) Clock Timing.”
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tTIWH
tTIWL
(12) Timer Output Timing
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
CLK ↑ → TOUT change timing tTO
CLK
TOUT
Pin name
Conditions
TIM0 to TIM4
—
Value
Min.
Max.
30
—
Unit
Remarks
ns
2.4 V
2.4 V
0.8 V
tTO
69
MB90640A Series
(13) Trigger Input Timing
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Input pulse width
tTRGL
Pin name
Conditions
INT0 to INT7
—
Value
Min.
Max.
5 tCP
—
Unit
Remarks
ns
tCP: See “ (1) Clock Timing.”
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tTRGH
tTRGL
(14) Chip Select Output Timing
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Conditions
Value
Min.
Max.
Unit
Chip select enabled →
Valid data input time
tSVDV
CS0 to CS7
D15 to D00
—
—
5 tCP/2 – 60
ns
RD ↑ →
Chip select enabled time
tRHSV
CS0 to CS7
RD
—
tCP/2 – 10
—
ns
WR ↑ →
Chip select enabled time
tWHSV
CS0 to CS7
WR
—
tCP/2 – 10
—
ns
Enabled chip select →
CLK ↑ time
tSVCH
CS0 to CS7
CLK
—
tCP/2 – 20
—
ns
tCP: See “ (1) Clock Timing.”
70
Pin name
Remarks
MB90640A Series
tSVCH
2.4 V
CLK
2.4 V
RD
tRHSV
A23 to A00
CS0 to CS7
2.4 V
0.8 V
tSVDV
D15 to D00
2.4 V
Read data
0.8 V
tWHSV
2.4 V
WR
(WRL, WRH)
D15 to D00
Write data
71
MB90640A Series
■ EXAMPLES CHARACTERISTICS
1. MB90641A
(1) “H” Level Output Voltage
(2) “L” Level Output Voltage
VCC - VOH vs. IOH
VCC - VOH (V)
0.45
0.4 TA = +25°C
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0.0
–2
–3
VOL (V)
0.45
0.4 TA = +25°C
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0.0
2
3
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
–4
–5
–6
IOH (mA)
(3) “H” Level Input Voltage/“L” Level Input
Voltage (CMOS Input)
VIN (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3
VIN (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3
TA = +25°C
4
4.5
5
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
4
5
6
IOL (mA)
(4) “H” Level Input Voltage/“L” Level Input
Voltage (Hysteresis Input)
VIN vs. VCC
3.5
VOL vs. IOL
VIN vs. VCC
TA = +25°C
VIHS
VILS
3.5
4
4.5
5
5.5
VCC (V)
VIHS : Thershold when input voltage in hysteresis
characteristics is set to “H” level
VILS : Thershold when input voltage in hysteresis
characteristics is set to “L” level
5.5
VCC (V)
(5) Power Supply Current (fCP = Internal Frequency)
ICC vs. VCC
ICC (mA)
24
22
20
18
16
14
12
10
8
6
4
2
0
TA = +25°C
TA = +25°C
6
fCP = 16 MHz
5
fCP = 16 MHz
4
3
fCP = 8 MHz
fCP = 8 MHz
2
fCP = 4 MHz
fCP = 2 MHz
fCP = 4 MHz
fCP = 2 MHz
1
0
3.0
72
ICCS vs. VCC
ICCS (mA)
4.0
5.0
6.0
VCC (V)
3.0
4.0
5.0
6.0
VCC (V)
MB90640A Series
2. MB90P641A
(1) “H” Level Output Voltage
VOH vs. IOH
VOH (V)
1.0
0.9 TA = +25°C
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
–2
–4
–6
(2) “L” Level Output Voltage
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
–8
IOH (mA)
(3) “H” Level Input Voltage/“L” Level Input
Voltage (CMOS Input)
VIN vs. VCC
VIN (V)
5.0
TA = +25°C
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2
3
4
5
6
VCC (V)
VOL vs. IOL
VOL (V)
1.0
0.9 TA = +25°C
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
2
4
6
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
8
IOL (mA)
(4) “H” Level Input Voltage/“L” Level Input
Voltage (Hysteresis Input)
VIN (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2
VIN vs. VCC
TA = +25°C
VIHS
VILS
3
4
5
6
VCC (V)
VIHS : Thershold when input voltage in hysteresis
characteristics is set to “H” level
VILS : Thershold when input voltage in hysteresis
characteristics is set to “L” level
73
MB90640A Series
(5)
Power Supply Current (fCP = internal frequency)
ICC (mA)
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
ICC vs. VCC
TA = +25°C
fCP = 12.5 MHz
fCP = 8 MHz
fCP = 4 MHz
3.0
(6)
fCP = 16 MHz
4.0
5.0
6.0
VCC (V)
ICCS (mA)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
3.0
ICCS vs. VCC
TA = +25°C
fCP = 16 MHz
fCP = 12.5 MHz
fCP = 8 MHz
fCP = 4 MHz
4.0
Pull-up Resistance
R vs. VCC
R (kΩ)
1000
TA = +25°C
100
10
2.5
74
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VCC (V)
5.0
6.0
VCC (V)
MB90640A Series
■ INSTRUCTIONS (340 INSTRUCTIONS)
Table 1
Explanation of Items in Tables of Instructions
Item
Mnemonic
Meaning
Upper-case letters and symbols: Represented as they appear in assembler.
Lower-case letters:
Replaced when described in assembler.
Numbers after lower-case letters: Indicate the bit width within the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
m : When branching
n : When not branching
See Table 4 for details about meanings of other letters in items.
RG
B
Operation
Indicates the number of accesses to the register during execution of the instruction.
It is used calculate a correction value for intermittent operation of CPU.
Indicates the correction value for calculating the number of actual cycles during execution of the
instruction. (Table 5)
The number of actual cycles during execution of the instruction is the correction value summed
with the value in the “~” column.
Indicates the operation of instruction.
LH
Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.
Z : Transfers “0”.
X : Extends with a sign before transferring.
– : Transfers nothing.
AH
Indicates special operations involving the upper 16 bits in the accumulator.
* : Transfers from AL to AH.
– : No transfer.
Z : Transfers 00H to AH.
X : Transfers 00H or FFH to AH by signing and extending AL.
I
S
T
N
Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit),
N (negative), Z (zero), V (overflow), and C (carry).
* : Changes due to execution of instruction.
– : No change.
S : Set by execution of instruction.
R : Reset by execution of instruction.
Z
V
C
RMW
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that
reads data from memory, etc., processes the data, and then writes the result to memory.)
* : Instruction is a read-modify-write instruction.
– : Instruction is not a read-modify-write instruction.
Note: A read-modify-write instruction cannot be used on addresses that have different
meanings depending on whether they are read or written.
75
MB90640A Series
Table 2
Explanation of Symbols in Tables of Instructions
Symbol
A
Meaning
32-bit accumulator
The bit length varies according to the instruction.
Byte : Lower 8 bits of AL
Word : 16 bits of AL
Long : 32 bits of AL:AH
AH
AL
Upper 16 bits of A
Lower 16 bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
Program bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
Ri
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Compact direct addressing
addr16
addr24
ad24 0 to 15
ad24 16 to 23
Direct addressing
Physical direct addressing
Bit 0 to bit 15 of addr24
Bit 16 to bit 23 of addr24
io
imm4
imm8
imm16
imm32
ext (imm8)
disp8
disp16
bp
I/O area (000000H to 0000FFH)
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data signed and extended from 8-bit immediate data
8-bit displacement
16-bit displacement
Bit offset
vct4
vct8
Vector number (0 to 15)
Vector number (0 to 255)
( )b
Bit address
(Continued)
76
MB90640A Series
(Continued)
Symbol
Meaning
rel
Branch specification relative to PC
ear
eam
Effective addressing (codes 00 to 07)
Effective addressing (codes 08 to 1F)
rlst
Register list
Table 3
Code
00
01
02
03
04
05
06
07
Notation
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
Effective Address Fields
Address format
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Number of bytes in address
extension *
Register direct
“ea” corresponds to byte, word, and
long-word types, starting from the
left
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
Register indirect
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
Register indirect with post-increment
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit
displacement
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit
displacement
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
—
0
0
1
2
0
0
2
2
Note: The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes)
column in the tables of instructions.
77
MB90640A Series
Table 4
Number of Execution Cycles for Each Type of Addressing
(a)
Code
Operand
Number of execution cycles
for each type of addressing
Number of register
accesses for each type of
addressing
Listed in tables of instructions
Listed in tables of instructions
00 to 07
Ri
RWi
RLi
08 to 0B
@RWj
2
1
0C to 0F
@RWj +
4
2
10 to 17
@RWi + disp8
2
1
18 to 1B
@RWj + disp16
2
1
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
4
4
2
1
2
2
0
0
Note: “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.
Table 5
Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles
(b) byte
Operand
(c) word
(d) long
Number Number Number Number Number Number
of cycles of access of cycles of access of cycles of access
Internal register
+0
1
+0
1
+0
2
Internal memory even address
Internal memory odd address
+0
+0
1
1
+0
+2
1
2
+0
+4
2
4
Even address on external data bus (16 bits)
Odd address on external data bus (16 bits)
+1
+1
1
1
+1
+4
1
2
+2
+8
2
4
External data bus (8 bits)
+1
1
+4
2
+8
4
Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value) in the
tables of instructions.
• When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
Table 6
Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
—
+2
External data bus (16 bits)
—
+3
External data bus (8 bits)
+3
—
Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
• Because instruction execution is not slowed down by all program fetches in actuality, these correction
values should be used for “worst case” calculations.
78
MB90640A Series
Table 7
Mnemonic
#
~
Transfer Instructions (Byte) [41 Instructions]
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A, @RLi+disp8
A, #imm4
3
2
4
3
2
1
2
2
2+ 3+ (a)
3
2
2
2
3
2
10
3
1
1
0
0
1
1
0
0
0
0
2
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– *
– *
– *
– *
– *
– *
– *
– *
– *
– R
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
3
2
A, dir
4
3
A, addr16
2
2
A, Ri
2
2
A, ear
2+ 3+ (a)
A, eam
3
2
A, io
2
2
A, #imm8
3
2
A, @A
5
A,@RWi+disp8 2
10
A, @RLi+disp8 3
0
0
1
1
0
0
0
0
1
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
X
X
X
X
X
X
X
X
X
X
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
/MOV
dir, A
addr16, A
Ri, A
ear, A
eam, A
io, A
@RLi+disp8, A
Ri, ear
Ri, eam
ear, Ri
eam, Ri
Ri, #imm8
io, #imm8
dir, #imm8
ear, #imm8
eam, #imm8
@AL, AH
@A, T
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
3
4
2
2
3+ (a)
3
10
3
4+ (a)
4
5+ (a)
2
5
5
2
4+ (a)
3
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi) +disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
XCH
XCH
XCH
XCH
A, ear
A, eam
Ri, ear
Ri, eam
4
2
2+ 5+ (a)
7
2
2+ 9+ (a)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
2
0 2× (b)
0
4
2 2× (b)
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
79
MB90640A Series
Table 8
Mnemonic
#
Transfer Instructions (Word/Long Word) [38 Instructions]
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
A, dir
A, addr16
A, SP
A, RWi
A, ear
A, eam
A, io
A, @A
A, #imm16
A, @RWi+disp8
A, @RLi+disp8
3
2
4
3
1
1
2
1
2
2
2+ 3+ (a)
3
2
3
2
2
3
5
2
10
3
0
0
0
1
1
0
0
0
0
1
2
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
–
–
–
–
–
–
–
–
–
word (A) ← ((RWi) +disp8) –
word (A) ← ((RLi) +disp8) –
*
*
*
*
*
*
*
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
dir, A
addr16, A
SP, A
RWi, A
ear, A
eam, A
io, A
@RWi+disp8, A
@RLi+disp8, A
RWi, ear
RWi, eam
ear, RWi
eam, RWi
RWi, #imm16
io, #imm16
ear, #imm16
eam, #imm16
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
3
4
1
2
2
3+ (a)
3
5
10
3
4+ (a)
4
5+ (a)
2
5
2
4+ (a)
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
(0)
(c)
0
(c)
0
(c)
0
(c)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
–
–
–
–
–
–
–
word ((RWi) +disp8) ← (A) –
word ((RLi) +disp8) ← (A) –
–
word (RWi) ← (ear)
–
word (RWi) ← (eam)
–
word (ear) ← (RWi)
–
word (eam) ← (RWi)
–
word (RWi) ← imm16
–
word (io) ← imm16
–
word (ear) ← imm16
–
word (eam) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVW AL, AH
/MOVW @A, T
2
3
0
(c)
word ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
XCHW
XCHW
XCHW
XCHW
4
2
2+ 5+ (a)
7
2
2+ 9+ (a)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A, ear
A, eam
RWi, ear
RWi, eam
0
2
0 2× (c)
0
4
2 2× (c)
MOVL A, ear
MOVL A, eam
MOVL A, #imm32
2
4
2
2+ 5+ (a) 0
0
3
5
0
(d)
0
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
MOVL ear, A
MOVL eam, A
2
4
2
2+ 5+ (a) 0
0
(d)
long (ear) ← (A)
long (eam) ← (A)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
80
MB90640A Series
Table 9
Mnemonic
ADD
A,#imm8
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
A, dir
A, ear
A, eam
ear, A
eam, A
A
A, ear
A, eam
A
SUB
A, #imm8
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A, dir
A, ear
A, eam
ear, A
eam, A
A
A, ear
A, eam
A
ADDW A
ADDW A, ear
ADDW A, eam
ADDW
A, #imm16
ADDW ear, A
ADDW eam, A
ADDCW A, ear
ADDCW A, eam
SUBW A
SUBW A, ear
SUBW A, eam
SUBW
A, #imm16
SUBW ear, A
SUBW eam, A
SUBCW A, ear
SUBCW A, eam
ADDL
ADDL
A, ear
A, eam
ADDL
A, #imm32
SUBL
SUBL
A, ear
A, eam
SUBL
A, #imm32
Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]
#
~
2
2
2
2+
2
2+
1
2
2+
1
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
2
5
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
byte (A) ← (A) +imm8
0
0
(b) byte (A) ← (A) +(dir)
0
byte (A) ← (A) +(ear)
0
1
(b) byte (A) ← (A) +(eam)
0
byte (ear) ← (ear) + (A)
0
2
0 2× (b) byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
0
0
byte (A) ← (A) + (ear) + (C)
0
1
(b) byte (A) ← (A) + (eam) + (C)
0
byte (A) ← (AH) + (AL) + (C) (decimal)
0
0
0
0
byte (A) ← (A) –imm8
(b) byte (A) ← (A) – (dir)
0
0
1
byte (A) ← (A) – (ear)
(b) byte (A) ← (A) – (eam)
0
0
2
byte (ear) ← (ear) – (A)
0 2× (b) byte (eam) ← (eam) – (A)
0
0
byte (A) ← (AH) – (AL) – (C)
0
1
byte (A) ← (A) – (ear) – (C)
(b) byte (A) ← (A) – (eam) – (C)
0
byte (A) ← (AH) – (AL) – (C) (decimal)
0
0
Z
Z
Z
Z
–
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
–
Z
Z
Z
Z
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
3
4+ (a)
2
3
5+ (a)
3
4+ (a)
2
3
4+ (a)
2
3
5+ (a)
3
4+ (a)
word (A) ← (AH) + (AL)
0
0
word (A) ← (A) +(ear)
0
1
(c) word (A) ← (A) +(eam)
0
word (A) ← (A) +imm16
0
0
word (ear) ← (ear) + (A)
0
2
0 2× (c) word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
0
1
(c) word (A) ← (A) + (eam) + (C)
0
word (A) ← (AH) – (AL)
0
0
word (A) ← (A) – (ear)
0
1
(c) word (A) ← (A) – (eam)
0
word (A) ← (A) –imm16
0
0
word (ear) ← (ear) – (A)
0
2
0 2× (c) word (eam) ← (eam) – (A)
word (A) ← (A) – (ear) – (C)
0
1
(c) word (A) ← (A) – (eam) – (C)
0
RG
2
6
2
2+ 7+ (a) 0
0
4
5
2
6
2
2+ 7+ (a) 0
0
4
5
B
0
(d)
0
0
(d)
0
Operation
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) +imm32
long (A) ← (A) – (ear)
long (A) ← (A) – (eam)
long (A) ← (A) –imm32
LH AH
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
81
MB90640A Series
Table 10
Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]
Mnemonic
#
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
INC
INC
ear
eam
byte (ear) ← (ear) +1
0
2
2
2
2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DEC
DEC
ear
eam
byte (ear) ← (ear) –1
0
2
3
2
2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
INCW
INCW
ear
eam
2
3
2
0
word (ear) ← (ear) +1
2+ 5+ (a) 0 2× (c) word (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DECW ear
DECW eam
2
3
2
0
word (ear) ← (ear) –1
2+ 5+ (a) 0 2× (c) word (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
INCL
INCL
ear
eam
long (ear) ← (ear) +1
0
4
7
2
2+ 9+ (a) 0 2× (d) long (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DECL
DECL
ear
eam
long (ear) ← (ear) –1
0
4
7
2
2+ 9+ (a) 0 2× (d) long (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 11
Mnemonic
#
Compare Instructions (Byte/Word/Long Word) [11 Instructions]
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
CMP
CMP
CMP
CMP
A
A, ear
A, eam
A, #imm8
1
1
2
2
2+ 3+ (a)
2
2
0
1
0
0
0
0
(b)
0
byte (AH) – (AL)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW
CMPW
CMPW
CMPW
A
A, ear
A, eam
A, #imm16
1
1
2
2
2+ 3+ (a)
2
3
0
1
0
0
0
0
(c)
0
word (AH) – (AL)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPL
CMPL
CMPL
A, ear
A, eam
A, #imm32
2
6
2
2+ 7+ (a) 0
0
3
5
0
(d)
0
word (A) ← (ear)
word (A) ← (eam)
word (A) ← imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
82
MB90640A Series
Table 12
Mnemonic
Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]
#
~
RG
1
*1
0
0 word (AH) /byte (AL)
–
2
*2
1
0 word (A)/byte (ear)
2+ *3
0
2
*4
B
Operation
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
*6 word (A)/byte (eam)
–
–
–
–
–
–
–
*
*
–
1
0 long (A)/word (ear)
–
–
–
–
–
–
–
*
*
–
2+ *5
0
*7 long (A)/word (eam)
–
–
–
–
–
–
–
*
*
–
A
A, ear
A, eam
1 *8
2 *9
2+ *10
0 0 byte (AH) *byte (AL) → word (A)
1 0 byte (A) *byte (ear) → word (A)
0 (b) byte (A) *byte (eam) → word (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MULUW A
MULUW A, ear
MULUW A, eam
1 *11
2 *12
2+ *13
0 0 word (AH) *word (AL) → long (A)
1 0 word (A) *word (ear) → long (A)
0 (c) word (A) *word (eam) → long (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DIVU
DIVU
DIVU
DIVUW
DIVUW
MULU
MULU
MULU
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
*10:
*11:
*12:
*13:
A
A, ear
A, eam
A, ear
A, eam
Quotient → byte (AL) Remainder → byte (AH)
Quotient → byte (A) Remainder → byte (ear)
Quotient → byte (A) Remainder → byte (eam)
Quotient → word (A) Remainder → word (ear)
Quotient → word (A) Remainder → word (eam)
LH AH
3 when the result is zero, 7 when an overflow occurs, and 15 normally.
4 when the result is zero, 8 when an overflow occurs, and 16 normally.
6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally.
4 when the result is zero, 7 when an overflow occurs, and 22 normally.
6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally.
(b) when the result is zero or when an overflow occurs, and 2 × (b) normally.
(c) when the result is zero or when an overflow occurs, and 2 × (c) normally.
3 when byte (AH) is zero, and 7 when byte (AH) is not zero.
4 when byte (ear) is zero, and 8 when byte (ear) is not zero.
5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.
3 when word (AH) is zero, and 11 when word (AH) is not zero.
4 when word (ear) is zero, and 12 when word (ear) is not zero.
5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
83
MB90640A Series
Table 13
Mnemonic
#
~
Logical 1 Instructions (Byte/Word) [39 Instructions]
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
AND
AND
AND
AND
AND
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
3
2
2+ 4+ (a)
3
2
2+ 5+ (a)
0
0
0
1
(b)
0
0
2
0 2× (b)
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
byte (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
OR
OR
OR
OR
OR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
3
2
2+ 4+ (a)
3
2
2+ 5+ (a)
0
0
0
1
(b)
0
0
2
0 2× (b)
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
byte (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
XOR
XOR
XOR
XOR
XOR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
3
2
2+ 4+ (a)
3
2
2+ 5+ (a)
0
0
0
1
(b)
0
0
2
0 2× (b)
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
byte (eam) ← (eam) xor (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
NOT
NOT
NOT
A
ear
eam
byte (A) ← not (A)
0
0
2
1
byte (ear) ← not (ear)
0
2
3
2
2+ 5+ (a) 0 2× (b) byte (eam) ← not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
ANDW
ANDW
ANDW
ANDW
ANDW
ANDW
2
1
A
2
A, #imm16 3
3
2
A, ear
2+ 4+ (a)
A, eam
3
2
ear, A
2+ 5+ (a)
eam, A
0
0
0
0
0
1
(c)
0
0
2
0 2× (c)
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
word (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
ORW
ORW
ORW
ORW
ORW
ORW
2
1
A
2
A, #imm16 3
3
2
A, ear
2+ 4+ (a)
A, eam
3
2
ear, A
2+ 5+ (a)
eam, A
0
0
0
0
0
1
(c)
0
0
2
0 2× (c)
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
word (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
XORW
XORW
XORW
XORW
XORW
XORW
2
1
A
2
A, #imm16 3
3
2
A, ear
2+ 4+ (a)
A, eam
3
2
ear, A
2+ 5+ (a)
eam, A
0
0
0
0
0
1
(c)
0
0
2
0 2× (c)
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
word (eam) ← (eam) xor (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
NOTW A
NOTW ear
NOTW eam
word (A) ← not (A)
0
0
2
1
word (ear) ← not (ear)
0
2
3
2
2+ 5+ (a) 0 2× (c) word (eam) ← not (eam)
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
84
MB90640A Series
Table 14
Mnemonic
#
Logical 2 Instructions (Long Word) [6 Instructions]
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
ANDL A, ear
ANDL A, eam
2
6
2
2+ 7+ (a) 0
0
(d)
long (A) ← (A) and (ear)
long (A) ← (A) and (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
ORL
ORL
A, ear
A, eam
2
6
2
2+ 7+ (a) 0
0
(d)
long (A) ← (A) or (ear)
long (A) ← (A) or (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
XORL A, ea
XORL A, eam
2
6
2
2+ 7+ (a) 0
0
(d)
long (A) ← (A) xor (ear)
long (A) ← (A) xor (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
Table 15
Mnemonic
Sign Inversion Instructions (Byte/Word) [6 Instructions]
#
~
RG
B
Operation
2
0
0
byte (A) ← 0 – (A)
NEG
A
1
NEG
NEG
ear
eam
byte (ear) ← 0 – (ear)
0
2
3
2
2+ 5+ (a) 0 2× (b) byte (eam) ← 0 – (eam)
0
0
2
word (A) ← 0 – (A)
NEGW A
1
NEGW ear
NEGW eam
word (ear) ← 0 – (ear)
0
2
3
2
2+ 5+ (a) 0 2× (c) word (eam) ← 0 – (eam)
Table 16
Mnemonic
NRML A, R0
LH AH
I
S
T
N
Z
V
C
RMW
X
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
Normalize Instruction (Long Word) [1 Instruction]
#
~
RG
B
Operation
2
*1
1
0
long (A) ← Shift until first digit is “1”
byte (R0) ← Current shift count
LH AH
–
–
I
S
T
N
Z
V
C
RMW
–
–
–
–
*
–
–
–
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
85
MB90640A Series
Table 17
Mnemonic
RORC A
ROLC A
Shift Instructions (Byte/Word/Long Word) [18 Instructions]
#
~
RG
B
2
2
2
2
0
0
0
0
3
0
2
0 2× (b)
0
2
0 2× (b)
Operation
byte (A) ← Right rotation with carry
byte (A) ← Left rotation with carry
LH AH
I
S
T
N
Z
V
C RMW
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
*
*
–
–
byte (ear) ← Right rotation with carry –
–
–
byte (ear) ← Left rotation with carry
byte (eam) ← Left rotation with carry –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
*
*
*
–
*
–
*
RORC
RORC
ROLC
ROLC
ear
eam
ear
eam
2
2+
2
2+
ASR
LSR
LSL
A, R0
A, R0
A, R0
2
2
2
*1
*1
*1
1
1
1
0
0
0
byte (A) ← Arithmetic right barrel shift (A, R0)
byte (A) ← Logical right barrel shift (A, R0)
byte (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRW A
LSRW A/SHRW A
LSLW A/SHLW A
1
1
1
2
2
2
0
0
0
0
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
word (A) ← Logical right shift (A, 1 bit)
word (A) ← Logical left shift (A, 1 bit)
–
–
–
–
–
–
–
–
–
–
–
–
* *
* R
– *
*
*
*
–
–
–
*
*
*
–
–
–
ASRW A, R0
LSRW A, R0
LSLW A, R0
2
2
2
*1
*1
*1
1
1
1
0
0
0
word (A) ← Arithmetic right barrel shift (A, R0)
word (A) ← Logical right barrel shift (A, R0)
word (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRL A, R0
LSRL A, R0
LSLL A, R0
2
2
2
*2
*2
*2
1
1
1
0
0
0
long (A) ← Arithmetic right shift (A, R0)
long (A) ← Logical right barrel shift (A, R0)
long (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
5+ (a)
3
5+ (a)
byte (eam) ← Right rotation with carry
*1: 6 when R0 is 0, 5 + (R0) in all other cases.
*2: 6 when R0 is 0, 6 + (R0) in all other cases.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
86
MB90640A Series
Table 18
Mnemonic
BZ/BEQ
BNZ/BNE
BC/BLO
BNC/BHS
BN
rel
BP
rel
BV
rel
BNV
rel
BT
rel
BNT
rel
BLT
rel
BGE
rel
BLE
rel
BGT
rel
BLS
rel
BHI
rel
BRA
rel
rel
rel
rel
rel
#
~
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
Branch 1 Instructions [31 Instructions]
RG
B
*
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Branch when (Z) = 1
Branch when (Z) = 0
Branch when (C) = 1
Branch when (C) = 0
Branch when (N) = 1
Branch when (N) = 0
Branch when (V) = 1
Branch when (V) = 0
Branch when (T) = 1
Branch when (T) = 0
0
0
0
(c)
0
(d)
0
word (PC) ← (A)
word (PC) ← addr16
word (PC) ← (ear)
word (PC) ← (eam)
JMP
JMP
JMP
JMP
JMPP
JMPP
JMPP
@A
addr16
@ear
@eam
@ear *3
@eam *3
addr24
1
3
2
2+
2
2+
4
2
3
3
4+ (a)
5
6+ (a)
4
0
0
1
0
2
0
0
CALL
CALL
CALL
CALLV
CALLP
@ear *4
@eam *4
addr16 *5
#vct4 *5
@ear *6
2
2+
3
1
2
6
7+ (a)
6
7
10
(c)
1
0 2× (c)
(c)
0
0 2× (c)
2 2× (c)
CALLP @eam *6
2+ 11+ (a)
CALLP addr24 *7
4
*1:
*2:
*3:
*4:
*5:
*6:
*7:
10
0
*2
0 2× (c)
Operation
LH AH
Branch when (V) xor (N) = 1
Branch when (V) xor (N) = 0
Branch when ((V) xor (N)) or (Z) = 1
Branch when ((V) xor (N)) or (Z) = 0
Branch when (C) or (Z) = 1
Branch when (C) or (Z) = 0
Branch unconditionally
word (PC) ← (ear), (PCB) ← (ear +2)
word (PC) ← (eam), (PCB) ← (eam +2)
word (PC) ← ad24 0 to 15,
(PCB) ← ad24 16 to 23
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← addr16
Vector call instruction
word (PC) ← (ear) 0 to 15
(PCB) ← (ear) 16 to 23
word (PC) ← (eam) 0 to 15
(PCB) ← (eam) 16 to 23
word (PC) ← addr0 to 15,
(PCB) ← addr16 to 23
I
S
T
N
Z
V
C RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
4 when branching, 3 when not branching.
(b) + 3 × (c)
Read (word) branch address.
W: Save (word) to stack; R: read (word) branch address.
Save (word) to stack.
W: Save (long word) to W stack; R: read (long word) R branch address.
Save (long word) to stack.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
87
MB90640A Series
Table 19
Mnemonic
#
~
Branch 2 Instructions [19 Instructions]
RG
B
3 *
4 *1
0
0
0
0
*2
*3
*4
*3
1
0
1
0
0
(b)
0
(c)
DBNZ ear, rel
3 *5
2
0
DBNZ
Operation
Branch when byte (A) ≠ imm8
LH AH
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
Branch when byte (ear) ≠ imm8 –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
–
–
3+ *6
Branch when byte (ear) =
(ear) – 1, and (ear) ≠ 0
2 2× (b) Branch when byte (eam) =
(eam) – 1, and (eam) ≠ 0
–
–
–
–
–
*
*
*
–
*
DWBNZ ear, rel
3 *5
2
–
–
–
–
–
*
*
*
–
–
DWBNZ eam, rel
3+ *6
–
–
–
–
–
*
*
*
–
*
INT
INT
INTP
INT9
RETI
#vct8
addr16
addr24
2
3
4
1
1
20
16
17
20
15
0
0
0
0
0
8× (c)
6× (c)
6× (c)
8× (c)
6× (c)
–
–
–
–
–
–
–
–
–
–
R
R
R
R
*
S
S
S
S
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
–
LINK
#local8
2
6
0
(c)
–
–
–
–
–
–
–
–
–
UNLINK
1
5
0
(c)
–
At constant entry, save old
frame pointer to stack, set
new frame pointer, and
allocate local pointer area
–
At constant entry, retrieve
old frame pointer from stack.
–
–
–
–
–
–
–
–
–
RET *7
RETP *8
1
1
4
6
0
0
(c)
(d)
Return from subroutine
Return from subroutine
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CBNE
A, #imm8, rel
CWBNE A, #imm16, rel
CBNE
CBNE
CWBNE
CWBNE
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
ear, #imm8, rel
eam, #imm8, rel*9
ear, #imm16, rel
eam, #imm16, rel*9
eam, rel
1
4
4+
5
5+
Branch when word (A) ≠ imm16
Branch when byte (eam) ≠ imm8
Branch when word (ear) ≠ imm16
Branch when word (eam) ≠ imm16
0
Branch when word (ear) =
(ear) – 1, and (ear) ≠ 0
2 2× (c) Branch when word (eam) =
(eam) – 1, and (eam) ≠ 0
Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
–
–
5 when branching, 4 when not branching
13 when branching, 12 when not branching
7 + (a) when branching, 6 + (a) when not branching
8 when branching, 7 when not branching
7 when branching, 6 when not branching
8 + (a) when branching, 7 + (a) when not branching
Retrieve (word) from stack
Retrieve (long word) from stack
In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
88
MB90640A Series
Table 20
Mnemonic
Other Control Instructions (Byte/Word/Long Word) [36 Instructions]
#
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
PUSHW
PUSHW
PUSHW
PUSHW
A
AH
PS
rlst
1
1
1
2
4
4
4
*3
0
0
0
*5
(c)
(c)
(c)
*4
word (SP) ← (SP) –2, ((SP)) ← (A)
word (SP) ← (SP) –2, ((SP)) ← (AH)
word (SP) ← (SP) –2, ((SP)) ← (PS)
(SP) ← (SP) –2n, ((SP)) ← (rlst)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
POPW
POPW
POPW
POPW
A
AH
PS
rlst
1
1
1
2
3
3
4
*2
0
0
0
*5
(c)
(c)
(c)
*4
word (A) ← ((SP)), (SP) ← (SP) +2
word (AH) ← ((SP)), (SP) ← (SP) +2
word (PS) ← ((SP)), (SP) ← (SP) +2
–
–
–
–
*
–
–
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
–
–
JCTX
@A
1
14
0 6× (c) Context switch instruction
–
–
*
*
*
*
*
*
*
–
AND
OR
CCR, #imm8
CCR, #imm8
2
2
3
3
0
0
0
0
byte (CCR) ← (CCR) and imm8 –
byte (CCR) ← (CCR) or imm8 –
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
2
2
2
2
0
0
0
0
byte (RP) ←imm8
byte (ILM) ←imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
1
0
0
0
0
0
0
word (RWi) ←ear
word (RWi) ←eam
word (A) ←ear
word (A) ←eam
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV RP, #imm8
MOV ILM, #imm8
2
MOVEA RWi, ear
3
MOVEA RWi, eam 2+ 2+ (a)
2
MOVEA A, ear
1
2+ 1+ (a)
MOVEA A, eam
(rlst) ← ((SP)), (SP) ← (SP) +2n
ADDSP #imm8
ADDSP #imm16
2
3
3
3
0
0
0
0
word (SP) ← (SP) +ext (imm8)
word (SP) ← (SP) +imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
2
2
*1
1
0
0
0
0
byte (A) ← (brgl)
byte (brg2) ← (A)
Z
–
*
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
No operation
Prefix code for accessing AD space
Prefix code for accessing DT space
Prefix code for accessing PC space
Prefix code for accessing SP space
Prefix code for no flag change
Prefix code for common register bank
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
NOP
ADB
DTB
PCB
SPB
NCC
CMR
A, brgl
brg2, A
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB, DPR
: 2 states
*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)
*3: 29 + (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register)
*4: Pop count × (c), or push count × (c)
*5: Pop count or push count.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
89
MB90640A Series
Table 21
Mnemonic
Bit Manipulation Instructions [21 Instructions]
#
~
RG
B
3
4
3
5
5
4
0
0
0
(b)
(b)
(b)
MOVB io:bp, A
3
4
3
7
7
6
SETB
SETB
SETB
dir:bp
addr16:bp
io:bp
3
4
3
CLRB dir:bp
CLRB addr16:bp
CLRB io:bp
BBC
dir:bp, rel
BBC
addr16:bp, rel
BBC
io:bp, rel
BBS
dir:bp, rel
BBS
addr16:bp, rel
BBS
SBBS
Operation
byte (A) ← (dir:bp) b
byte (A) ← (addr16:bp) b
byte (A) ← (io:bp) b
LH AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
0 2× (b) bit (dir:bp) b ← (A)
0 2× (b) bit (addr16:bp) b ← (A)
0 2× (b) bit (io:bp) b ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
7
7
7
0 2× (b) bit (dir:bp) b ← 1
0 2× (b) bit (addr16:bp) b ← 1
0 2× (b) bit (io:bp) b ← 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
3
4
3
7
7
7
0 2× (b) bit (dir:bp) b ← 0
0 2× (b) bit (addr16:bp) b ← 0
0 2× (b) bit (io:bp) b ← 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
4
5
4
*1
*1
*2
0
0
0
(b)
(b)
(b)
Branch when (dir:bp) b = 0
Branch when (addr16:bp) b = 0
Branch when (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
io:bp, rel
4
5
4
*1
*1
*2
0
0
0
(b)
(b)
(b)
Branch when (dir:bp) b = 1
Branch when (addr16:bp) b = 1
Branch when (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
addr16:bp, rel
5
*3
0 2× (b)
Branch when (addr16:bp) b = 1, bit = 1
–
–
–
–
–
–
*
–
–
*
WBTS io:bp
3
*4
0
*5
Wait until (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
WBTC io:bp
3
*4
0
*5
Wait until (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
MOVB A, dir:bp
MOVB
A, addr16:bp
MOVB A, io:bp
MOVB dir:bp, A
MOVB
*1:
*2:
*3:
*4:
*5:
addr16:bp, A
8 when branching, 7 when not branching
7 when branching, 6 when not branching
10 when condition is satisfied, 9 when not satisfied
Undefined count
Until condition is satisfied
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
90
MB90640A Series
Table 22
Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]
Mnemonic
#
~
RG
B
SWAP
SWAPW/XCHW AL, AH
EXT
EXTW
ZEXT
ZEXTW
1
1
1
1
1
1
3
2
1
2
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Table 23
Mnemonic
Operation
byte (A) 0 to 7 ↔ (A) 8 to 15
word (AH) ↔ (AL)
byte sign extension
word sign extension
byte zero extension
word zero extension
LH AH
–
–
X
–
Z
–
–
*
–
X
–
Z
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
R
R
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I
S
T
N
Z
V
C
RMW
String Instructions [10 Instructions]
#
~
MOVS/MOVSI
MOVSD
2
2
2
*
*2
5
*
*5
*
*3
Byte transfer @AH+ ← @AL+, counter = RW0
Byte transfer @AH– ← @AL–, counter = RW0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SCEQ/SCEQI
SCEQD
2
2
*1
*1
*5
*5
*4
*4
Byte retrieval (@AH+) – AL, counter = RW0
Byte retrieval (@AH–) – AL, counter = RW0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
FISL/FILSI
2 6m +6 *5
*3
Byte filling @AH+ ← AL, counter = RW0
–
–
–
–
–
*
*
–
–
–
MOVSW/MOVSWI
2
2
*2
*2
*8
*8
*6
*6
Word transfer @AH+ ← @AL+, counter = RW0
Word transfer @AH– ← @AL–, counter = RW0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SCWEQD
2
2
*1
*1
*8
*8
*7
*7
Word retrieval (@AH+) – AL, counter = RW0
Word retrieval (@AH–) – AL, counter = RW0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
FILSW/FILSWI
2 6m +6 *8
*6
Word filling @AH+ ← AL, counter = RW0
–
–
–
–
–
*
*
–
–
–
MOVSWD
SCWEQ/SCWEQI
RG
B
3
Operation
LH AH
m: RW0 value (counter value)
n: Loop count
*1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs
*2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case
*3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) separately
for each.
*4: (b) × n
*5: 2 × (RW0)
*6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c) separately
for each.
*7: (c) × n
*8: 2 × (RW0)
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
91
MB90640A Series
■ ORDERING INFORMATION
Part number
92
Package
MB90641APFV
MB90P641APFV
100-pin Plastic LQFP
(FPT-100P-M05)
MB90641APF
MB90P641APF
100-pin Plastic QFP
(FPT-100P-M06)
Remarks
MB90640A Series
■ PACKAGE DIMENSIONS
100-pin Plastic LQFP
(FPT-100P-M05)
+0.20
16.00±0.20(.630±.008)SQ
75
1.50 −0.10 (Mounting height)
+.008
.059 −.004
51
14.00±0.10(.551±.004)SQ
76
50
12.00
(.472)
REF
15.00
(.591)
NOM
Details of "A" part
0.15(.006)
INDEX
100
0.15(.006)
26
0.15(.006)MAX
LEAD No.
"B"
25
1
0.40(.016)MAX
"A"
+0.08
0.50(.0197)TYP
0.18 −0.03
+.003
.007 −.001
+0.05
0.08(.003)
0.127 −0.02
+.002
.005 −.001
M
Details of "B" part
0.10±0.10
(STAND OFF)
(.004±.004)
0.50±0.20(.020±.008)
0.10(.004)
C
0~10˚
Dimensions in mm (inches)
1995 FUJITSU LIMITED F100007S-2C-3
100-pin Plastic QFP
(FPT-100P-M06)
23.90±0.40(.941±.016)
3.35(.132)MAX
(Mounting height)
80
20.00±0.20(.787±.008)
0.05(.002)MIN
(STAND OFF)
51
81
50
14.00±0.20
(.551±.008)
17.90±0.40
(.705±.016)
12.35(.486)
REF
16.30±0.40
(.642±.016)
INDEX
31
100
"A"
LEAD No.
1
30
0.65(.0256)TYP
0.30±0.10
(.012±.004)
0.13(.005)
0.15±0.05(.006±.002)
M
Details of "A" part
0.25(.010)
Details of "B" part
"B"
0.10(.004)
18.85(.742)REF
22.30±0.40(.878±.016)
C
1994 FUJITSU LIMITED F100008-3C-2
0.30(.012)
0.18(.007)MAX
0.53(.021)MAX
0 10°
0.80±0.20
(.031±.008)
Dimensions in mm (inches)
93
MB90640A Series
MEMO
94
MB90640A Series
MEMO
95
MB90640A Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9803
 FUJITSU LIMITED Printed in Japan
96
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.