CD74FCT573AT was not acquired from Harris Semiconductor. Data sheet acquired from Harris Semiconductor SCHS260A January 1997 Features ED MEND S M O C N E IG NOT R NEW DES ology n h Tec FOR MOS Use C • Buffered Inputs • Typical Propagation Delay: 3.9ns at VCC = 5V, TA = 25oC, CL = 50pF (CD74FCT573AT) • SCR Latchup Resistant BiCMOS Process and Circuit Design • FCTXXX Types - Speed of Bipolar FAST™/AS/S • FCTXXXAT Types - 30% Faster than FAST™/AS/S with Significantly Reduced Power Consumption • • • • • 48mA Output Sink Current Output Voltage Swing Limited to 3.7V at VCC = 5V Controlled Output Edge Rates Input/Output Isolation to VCC BiCMOS Technology with Low Quiescent Power CD74FCT573, CD74FCT573AT BiCMOS FCT Interface Logic, Octal Transparent Latches, Three-State Description The CD74FCT573 and CD74FCT573AT octal transparent latches use a small geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output HIGH level to two diode drops below VCC. This resultant lowering of output swing (0V to 3.7V) reduces power bus ringing (a source of EMI) and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 milliamperes. The CD74FCT573 and CD74FCT573AT outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enable (OE) controls the three-state outputs. When the Output Enable (OE) is HIGH, the outputs are in the high impedance state. The latch operation is independent of the state of the Output Enable. Ordering Information PART NUMBER TEMP. RANGE (oC) PKG. NO. PACKAGE CD74FCT573ATE 0 to 70 20 Ld PDIP E20.3 CD74FCT573M 0 to 70 20 Ld SOIC M20.3 CD74FCT573SM 0 to 70 20 Ld SSOP M20.209 NOTE: When ordering the suffix M and SM packages, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. Pinout CD74FCT573, CD74FCT573AT (PDIP, SOIC, SSOP) TOP VIEW OE 1 D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 Q3 D4 6 15 Q4 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 GND 10 11 LE 20 VCC CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a trademark of Fairchild Semiconductor. Copyright © Harris Corporation 1997 8-1 File Number 2304.2 CD74FCT573, CD74FCT573AT Functional Diagram D0 D1 D2 D3 D4 D5 D6 D7 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 Q1 Q2 Q3 Q4 Q5 Q6 Q7 1 11 LE OE Q0 GND = PIN 10 VCC = PIN 20 TRUTH TABLE (Note 1) OUTPUT ENABLE LATCH ENABLE DATA OUTPUT L H H H L H L L L L l L L L h H H X X Z NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level l = Low voltage level one set up time prior to the high to low latch enable transition. h = High voltage level one set up time prior to the high to low latch enable transition. X = Irrelevant Z = High Impedance IEC Logic Symbol CD74FCT573, CD74FCT573AT 1 11 2 EN C1 19 1D 3 18 4 17 5 16 6 15 7 14 8 13 9 12 8-2 CD74FCT573, CD74FCT573AT Absolute Maximum Ratings Thermal Information DC Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK (For VI < -0.5V) . . . . . . . . . . . . . -20mA DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . . . . . -50mA DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . . 70mA DC Output Source Current per Output Pin, IO . . . . . . . . . . . . -30mA DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140mA DC Ground Current (IGND). . . . . . . . . . . . . . . . . . . . . . . . . . . 400mA Thermal Resistance (Typical, Note 2) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC and SSOP-Lead Tips Only) Operating Conditions Operating Temperature Range (TA) . . . . . . . . . . . . . . . .0oC to 70oC Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V DC Input Voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC DC Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ VCC Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Commercial Temperature Range 0oC to 70oC, VCC Max = 5.25V, VCC Min = 4.75V (Note 5) AMBIENT TEMPERATURE (TA) 25oC TEST CONDITIONS PARAMETER SYMBOL VI (V) IO (mA) VCC (V) MIN 0oC TO 70oC MAX MIN MAX UNITS High Level Input Voltage VIH 4.75 to 5.25 2 - 2 - V Low Level Input Voltage VIL 4.75 to 5.25 - 0.8 - 0.8 V High Level Output Voltage VOH VIH or VIL -15 Min 2.4 - 2.4 - V Low Level Output Voltage VOL VIH or VIL 48 Min - 0.55 - 0.55 V High Level Input Current IIH VCC Max - 0.1 - 1 µA Low Level Input Current IIL GND Max - -0.1 - -1 µA IOZH VCC Max - 0.5 - 10 µA IOZL GND Max - -0.5 - -10 µA Input Clamp Voltage VIK VCC or GND Min - -1.2 - -1.2 V Short Circuit Output Current (Note 3) IOS VO = 0 VCC or GND Max -60 - -60 - mA Quiescent Supply Current, MSI ICC VCC or GND Max - 8 - 80 µA ∆ICC 3.4V (Note 4) Max - 1.6 - 1.6 mA Three-State Leakage Current Additional Quiescent Supply Current per Input Pin TTL Inputs High, 1 Unit Load -18 0 NOTES: 3. Not more than one output should be shorted at one time. Test duration should not exceed 100ms. 4. Inputs that are not measured are at VCC or GND. 5. FCT Input Loading: All inputs are 1 unit load. Unit load is ∆ICC limit specified in Electrical Specifications table, e.g., 1.6mA Max. at 70oC. 8-3 CD74FCT573, CD74FCT573AT Switching Specifications Over Operating Range FCT Series tr, tf = 2.5ns, CL = 50pF, RL (Figure 4) (Note 6) 25oC 0oC TO 70oC SYMBOL VCC (V) TYP MIN MAX UNITS CD74FCT573 tPLH, tPHL 5 5 1.5 8 ns CD74FCT573AT tPLH, tPHL 5 3.9 1.5 5.7 ns CD74FCT573 tPLH, tPHL 5 9 2 13 ns CD74FCT573AT tPLH, tPHL 5 4.4 2 7 ns CD74FCT573 tPZL, tPZH 5 7 1.5 12 ns CD74FCT573AT tPZL, tPZH 5 6 1.5 8 ns CD74FCT573 tPLZ, tPHZ 5 6 1.5 7.5 ns CD74FCT573AT tPLZ, tPHZ 5 4 1.5 5.8 ns CPD (Note 7) - 34 - - pF Minimum (Valley) VOHV During Switching of Other Outputs (Output Under Test Not Switching) VOHV (Figure 1) 5 0.5 - - V Maximum (Peak) VOLP During Switching of Other Outputs (Output Under Test Not Switching) VOLP (Figure 1) 5 1 - - V Input Capacitance CI - - - 10 pF Three-State Output Capacitance CO - - - 15 pF PARAMETER Propagation Delays Data to Outputs LE to Outputs Output Enable Times Output Disable Times Power Dissipation Capacitance NOTES: 6. 5V: Min is at 5.25V for 0oC to 70oC, Max is at 4.75V for 0oC to 70oC, Typ is at 5V. 7. CPD, measured per flip-flop, is used to determine the dynamic power consumption. PD (per package) = VCC ICC + Σ(VCC2 fI CPD + VO2 fO CL + VCC ∆ICC D) where: VCC = supply voltage ∆ICC = flow through current x unit load CL = output load capacitance D = duty cycle of input high fO = output frequency fI = input frequency Prerequisite for Switching 25oC PARAMETER 0oC TO 70oC SYMBOL VCC (V) TYP MIN MAX UNITS Data to Latch Enable Setup Time tSU 5 (Note 8) - 2 - ns Data to Latch Enable Hold Time tH 5 - 1.5 - ns CD74FCT573 tW 5 - 6 - ns CD74FCT573AT tW 5 - 5 - ns Latch Enable Pulse Width NOTE: 8. 5V: Minimum is at 4.75V for 0oC to 70oC, Typical is at 5V. 8-4 CD74FCT573, CD74FCT573AT Test Circuits and Waveforms VCC tr, tf = 2.5ns (NOTE 9) VI 3V 0 PULSE ZO GEN SWITCH POSITION 7V 500Ω RL V0 DUT CL 50pF RT RT = ZO 500Ω RL 9. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; ZOUT ≤ 50Ω; tf, tr ≤ 2.5ns. FIGURE 1. TEST CIRCUIT tPLZ, tPZL, Open Drain Closed tPHZ, tPZH, tPLH, tPHL Open 3V 1.5V 0V DATA INPUT tH 3V 1.5V 0V TIMING INPUT tREM ASYNCHRONOUS CONTROL SWITCH DEFINITIONS: CL = Load capacitance, includes jig and probe capacitance. RT = Termination resistance, should be equal to ZOUT of the Pulse Generator. VIN = 0V to 3V. Input: tr = tf = 2.5ns (10% to 90%), unless otherwise specified NOTE: tSH TEST 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. 3V 1.5V 0V tH tSH HIGH-LOW-HIGH PULSE FIGURE 2. SETUP, HOLD, AND RELEASE TIMING ENABLE 1.5V FIGURE 3. PULSE WIDTH DISABLE 3V 3V SAME PHASE INPUT TRANSITION 1.5V CONTROL INPUT 0V 3.5V OUTPUT NORMALLY LOW SWITCH CLOSED SWITCH OPEN tPHL 3.5V VOH 1.5V 1.5V VOL OUTPUT 0.3V tPZH OUTPUT NORMALLY HIGH tPLH tPLZ tPZL 1.5V tPHZ 0.3V VOL tPLH tPHL VOH 3V OPPOSITE PHASE INPUT TRANSITION 1.5V 0V 0V 0V 1.5V 0V FIGURE 4. ENABLE AND DISABLE TIMING FIGURE 5. PROPAGATION DELAY 8-5 Test Circuits and Waveforms (Continued) VOH OTHER OUTPUTS VOL VOH OUTPUT UNDER TEST VOHV VOLP VOL NOTES: 10. VOLP is measured with respect to a ground reference near the output under test. VOHV is measured with respect to VOH. 11. Input pulses have the following characteristics: PRR ≤ 1MHz, tr = 2.5ns, tf = 2.5ns, skew 1ns. 12. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1µF capacitor. Scope and probes require 700MHz bandwidth. FIGURE 6. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS 8-6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated