TI DRV401AMDWPREP

DRV401-EP
www.ti.com............................................................................................................................................................................................... SBVS104 – JANUARY 2008
SENSOR SIGNAL CONDITIONING IC FOR
CLOSED-LOOP MAGNETIC CURRENT SENSOR
FEATURES
1
• Designed For Sensors From
VACUUMSCHMELZE (VAC)
• Single Supply: 5 V
• Power Output: H-Bridge
• Designed For Driving Inductive Loads
• Excellent DC Precision
• Wide System Bandwidth
• High-Resolution, Low-Temperature Drift
• Built-In Degauss System
• Extensive Fault Detection
• External High-Power Driver Option
23
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
APPLICATIONS
•
•
•
•
•
Generator/Alternator Monitoring and Control
Frequency and Voltage Inverters
Motor Drive Controllers
System Power Consumption
Photovoltaic Systems
(1)
Custom temperature ranges available
DESCRIPTION/ORDERING INFORMATION
The DRV401 is designed to control and process signals from specific magnetic current sensors made by
VACUUMSCHMELZE GmbH & Co. KG (VAC). A variety of current ranges and mechanical configurations are
available. Combined with a VAC sensor, the DRV401 monitors both ac and dc currents to high accuracy.
Provided functions include: probe excitation, signal conditioning of the probe signal, signal loop amplifier, an
H-bridge driver for the compensation coil, and an analog signal output stage that provides an output voltage
proportional to the primary current. It offers overload and fault detection, as well as transient noise suppression.
The DRV401 can directly drive the compensation coil or connect to external power drivers. Therefore, the
DRV401 combines with sensors to measure small to very large currents.
To maintain the highest accuracy, the DRV401 can demagnetize (degauss) the sensor at power-up and on
demand.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
DRV401-EP
SBVS104 – JANUARY 2008............................................................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
(2)
PRODUCT
PACKAGE-LEAD
PACKAGE DESIGNATOR (2)
PACKAGE MARKING
DRV401
SO-20
DWP
DRV401M
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Patents Pending.
Compensation
PWM
PWM
Compensation Winding
Primary Winding
RS
ICOMP1
ICOMP2
DRV401
Diff
Amp
Magnetic Core
Field Probe
IS2
IP
VOUT
REFIN
IS1
Probe
Interface
Integrator
Filter
Timing, Error Detection,
and Power Control
H−Bridge
Driver
Degauss
VREF
VREF
+5V GND
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage
Voltage
(2)
Differential amplifier (3)
Signal Input
terminals:
V
–0.5
VDD + 0.5
V
–10
+10
V
±75
mA
Current at IS1 and IS2
Storage temperature
ESD rating
(1)
(2)
(3)
(4)
2
±25
mA
+250
mA
–55
+150
°C
–55
(4)
Operating junction temperature
Human body model
(HBM)
UNIT
+7
Current (pins other than IS1 and IS2) (2)
ICOMP short circuit
MAX
+150
°C
Pins IAIN1 and IAIN2 only
1
kV
All other pins
4
kV
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must
be current limited, except for the differential amplifier input pins.
These inputs are not internally protected against over voltage. The differential amplifier input pins must be limited to 5 mA, max or
±10 V, max.
Power-limited; observe maximum junction temperature.
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ELECTRICAL CHARACTERISTICS (1)
Boldface limits apply over the specified temperature range: TJ = –55°C to +125°C.
At TA = +25°C and VDD1 = VDD2 = +5 V with external 100 kHz filter BW, and zero output current ICOMP, unless otherwise noted.
PARAMETER
CONDITIONS
DRV401
MIN
TYP
MAX
±0.01
±0.1
UNITS
RL = 10 kΩ to 2.5 V,
VREFIN = 2.5 V
DIFFERENTIAL AMPLIFIER
OFFSET VOLTAGE
VOS
Offset voltage, RTO (2) (3)
dVOS/dT
Drift, RTO
VOS
Offset voltage, RTO (2) (3)
Gain 4 V/V
CMRR
vs common-mode, RTO
–1 V to +6 V, VREF = 2.5 V
PSRR
vs power-supply, RTO
VREF not included
Gain 4 V/V
(3)
mV
µV/°C
±0.1
±0.17
mV
±50
±280
µV/V
±4
±50
µV/V
SIGNAL INPUT
Common-mode voltage range
–1
(VDD) + 1
V
SIGNAL OUTPUT
Signal over-range indication
(OVER-RANGE), Delay (3)
Voltage output swing from negative rail
OVER-RANGE trip level
VIN = 1 V step (3)
(3)
Voltage putput swing from positive rail (3),
OVER-RANGE trip level
ISC
Short-circuit current
(3)
,
(4)
I = +2.5 mA, CMP trip level
I = –2.5 mA, CMP trip level
VDD – 85
+85
mV
mV
VOUT connected to GND
–18
mA
VOUT connected to VDD
+20
mA
4
Gain error
±0.02
Gain error drift
(1)
(2)
(3)
(4)
+48
VDD – 48
Gain, VOUT/VIN_DIFF
Linearity error
µs
2.5 to 3.5
V/V
＝0.3
±0.1
RL = 1 kΩ
10
%
ppm/°C
ppm
For Electromigration derating curves, please refer to http://focus.ti.com/pdfs/hirel/mltry/EP_Reliability_Information.pdf.
Parameter value referred to output (RTO).
See Typical Characteristics curves.
Total input resistance and comparator threshold current are inversely related. See Figure 2a.
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ELECTRICAL CHARACTERISTICS (continued)
Boldface limits apply over the specified temperature range: TJ = –55°C to +125°C.
At TA = +25°C and VDD1 = VDD2 = +5 V with external 100 kHz filter BW, and zero output current ICOMP, unless otherwise noted.
PARAMETER
CONDITIONS
DRV401
MIN
TYP
MAX
UNITS
FREQUENCY RESPONSE
BW–3dB
SR
Bandwidth (5)
Slew rate
(5)
Settling time, large-signal
(5)
Settling time (5)
2
MHz
CMVR = –1 V to = +4 V
6.5
V/µs
dV ± 2 V to 1%,
No external filter
0.9
µs
dV ± 0.4 V to 0.01%
14
µs
INPUT RESISTANCE
Differential
16.5
20
23.5
kΩ
Common-mode
41
50
59
kΩ
External reference input
41
50
59
kΩ
NOISE
Output voltage noise density, f = 1 kHz,
RTO (5)
en
Compensation loop disabled
170
nV/√Hz
COMPENSATION LOOP
PSRR
DC STABILITY
Probe f = 250 kHz,
RLOAD = 20 Ω
Offset error (6)
Deviation from 50% PWM,
Pin gain = L
0.03
%
Offset error drift (5)
Deviation from 50% PWM,
Pin gain = L
7.5
ppm/°C
Gain, pin gain = L (5)
|VICOMP1| – |VICOMP2|
Power-supply rejection ratio
Probe loop f = 250 kHz
–200
25
200
500
ppm/V
ppm/V
FREQUENCY RESPONSE
Open-loop gain, two modes, 7.8 kHz
Pin gain H/L
24/32
dB
–0.7
–0.7 to VDD
V
47
59
71
Ω
60
75
90
Ω
300
1500
PROBE COIL LOOP
Input voltage clamp range
Internal resistor, IS1 or IS2 to VDD1
Field probe current < 50 mA
(5)
RHIGH
Internal resistor, IS1 or IS2 to GND1 (5)
RLOW
Resistance mismatch between IS1 and
IS2 (5)
ppm of RHIGH + RLOW
Total input resistance (7)
ppm
134
200
Ω
Comparator threshold current (7)
22
28
34
mA
Minimum probe loop half-cycle (5)
250
280
310
ns
Probe loop minimum frequency
250
No oscillation detect (error) suppression
kHz
µs
35
COMPENSATION COIL DRIVER, H-BRIDGE
Peak current (5)
VICOMP1 – VICOMP2 = 4.0VPP
Voltage swing
20 Ω load
250
Output common-mode voltage
Wire break detect, threshold current
mA
4.2
VPP
VDD2/2
(8)
ICOMP1 and ICOMP2 railed
V
33
57
2.5
2.505
mA
VOLTAGE REFERENCE
(5)
(6)
(7)
(8)
4
Voltage (5)
No load
Drift (5)
No load
2.495
±5
V
ppm/°C
See Typical Characteristics curves.
For VAC sensors, 0.2% of PWM offset approximately corresponds to 10 mA primary current offset per winding.
Total input resistance and comparator threshold current are inversely related. See Figure 2a.
See Compensation Driver section in Applications Information.
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ELECTRICAL CHARACTERISTICS (continued)
Boldface limits apply over the specified temperature range: TJ = –55°C to +125°C.
At TA = +25°C and VDD1 = VDD2 = +5 V with external 100 kHz filter BW, and zero output current ICOMP, unless otherwise noted.
PARAMETER
CONDITIONS
Drift (5)
No load
DRV401
MIN
2.491
PSRR (5)
ISC
TYP
±15
MAX
UNITS
2.509
V
±200
µV/V
Load regulation (5)
Load to GND/VDD,
dl = 0 mA to 5 mA
0.15
mV/mA
Short-circuit current
REFOUT connected to VDD
+20
mA
REFOUT connected to GND
–18
mA
See Timing Diagram
106
DEMAGNETIZATION
Duration
130 (7)
ms
DIGITAL I/O
LOGIC INPUTS (DEMAG, GAIN, and
CCdiag Pins)
CMOS Type Levels
Pull-up high current (CCdiag)
3.5 < VIN < VDD
Pull-up low current (CCdiag)
0 < VIN < 1.5
Logic input leakage current
0 < VIN < VDD
µA
160
µA
5
0.01
Logic level, input: L/H
Hysteresis
5
µA
2.1/2.8
V
0.7
V
0.3
V
OUTPUTS (ERROR AND OVER-RANGE
Pins)
Logic level, output: L
4 mA sink
Logic level, output: H
No Internal Pull-Up
OUTPUTS (PWM and PWM Pins)
Push-pull type
Logic level L
4 mA sink
Logic level H
4 mA source
0.2
V
(VDD) – 0.4
V
POWER SUPPLY
VDD
Specified voltage range
VRST
Power-on reset threshold
IQ
Quiescent current [I(VDD1) + I(VDD2)]
4.5
5
5.5
1.8
ICOMP = 0 mA,
Sensor not connected
V
6.8
Brownout voltage level (9)
Brownout indication delay
V
mA
5
V
135
µs
TEMPERATURE RANGE
TJ
Specified range
TJ
Operating range
θJA
Package thermal resistance
SO PowerPAD
surface-mount (10)
–40
+125
°C
–50
+150
°C
27
°C/W
(9) See Typical Characteristics curves.
(10) See Applications Information section for information on power dissipation, layout considerations, and proper PCB soldering and
heat-sinking technique.
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PIN CONFIGURATIONS
Top View
DWP
PWM
1
20
IS1
PWM
2
19
GND1
ERROR
3
18
IS2
DEMAG
4
17
VDD1
GAIN
5
16
OVER- RANGE
REFOUT
6
15
CCdiag
REFIN
7
14
VDD2
VOUT
8
13
ICOMP1
IAIN2
9
12
ICOMP2
IAIN1
10
11
GND2
Exposed
Thermal Pad
on Underside,
Connect
to GND1
Wide- Body SO- 20
PIN ASSIGNMENTS
TERMINAL
NAME
NO.
DESCRIPTION
ERROR
1
Error flag: open-drain output, see the Error Conditions section.
DMAG
2
Control input, see the Demagnetization section.
GAIN
3
Control input for open-loop gain: low = normal, high = –8 dB.
REFOUT
4
Output for internal 2.5 V reference voltage.
REFIN
5
Input for zero reference to differential amplifier.
VOUT
6
Output for differential amplifier.
IAIN2
7
Noninverting input of differential amplifier.
IAIN1
8
Inverting input of differential amplifier.
GND2
9
Ground connection. Connect to GND1.
ICOMP2
10
Output 2 of compensation coil driver.
ICOMP1
11
Output 1 of compensation coil driver.
VDD2
12
Supply voltage. Connect to VDD1.
CCdiag
13
Control input for wire-break detection: high = enable.
OVER-RANGE
14
Open-drain output for over-range indication: low = over-range.
VDD1
15
Supply voltage.
IS2
16
Probe connection 2.
GND1
17
Ground connection.
IS1
18
Probe connection 1.
PWM
19
PWM output from probe circuit (inverted).
PWM
20
PWM output from probe circuit.
Exposed Thermal Pad
–
Connect to GND1.
6
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TYPICAL CHARACTERISTICS
At TA = +25°C and VDD1 = VDD2 = +5 V with external 100 kHz filter BW, unless otherwise noted.
DRV401 AND SENSOR:
OUTPUT VOLTAGE NOISE DENSITY
(Sensor M4645−X080, RSHUNT = 10Ω, Mode = Low)
DRV401 AND SENSOR:
OFFSET vs SUPPLY VOLTAGE
0.04
100
0.03
60Hz Line Frequency and Multiples
(measured in a 60Hz environment)
M4645−X211
M4645−X211
0.01
VN (µV/√Hz)
IPRIM (A)
0.02
0
M4645−X080
−0.01
−0.02
Divided Field
Probe Frequency
10
−0.03
−0.04
4.1
4.3
4.5
4.7
4.9
5.1
5.3
5.5
5.7
5.9
6.1
0.1
0.1
VDD (V)
1
10
100
1k
10k
100k
Frequency (Hz)
DRV401 AND SENSOR: ABSOLUTE ERROR
(Soldered DWP−20 with 1 Square−Inch Copper Pad)
(Measurements by Vacuumschmelza GmbH)
0.3
1.20
T = −50_ C
T = +25_C
T = +85_C
T = +125_ C
DRV401 with M4645−X600 Sensor
DRV401 with M4645−X211 Sensor
DRV401 with M4645−X080 Sensor
1.15
1.10
Normalized Gain
0.2
Absolute Error (A)
GAIN FLATNESS vs FREQUENCY
(Measurements by Vacuumschmelze GmbH)
0.1
0
−0.1
1.05
1.00
0.95
0.90
0.85
−0.2
TC (RSHUNT) ±25ppm/_ C.
−0.3
−300
−200
0.80
10
−100
0
100
200
100
300
1k
10k
100k
1M
Frequency (Hz)
Primary Current (A)
DIFFERENTIAL AMPLIFIER:
VOLTAGE OFFSET PRODUCTION DISTRIBUTION
3A ICOMP OVERLOAD RECOVERY
(Measurements by Vacuumschmelze GmbH)
RTO
Over−Range
2000A/div
2V/div
VOUT
VOUT
ERROR
Population
Over−Range
ERROR
0
20
40
60
80
100 120 140 160 180 200
Time (µs)
IPRIM
−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
5
10
15
20
25
30
35
40
45
50
IPRIM
NOTE: IPRIM = 3000A corresponds to ICOMP = 3A.
Voltage Offset (µV)
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VDD1 = VDD2 = +5 V with external 100 kHz filter BW, unless otherwise noted.
DIFFERENTIAL AMPLIFIER:
GAIN vs FREQUENCY
DIFFERENTIAL AMPLIFIER:
OFFSET VOLTAGE vs TEMPERATURE, RTO
20
20
16
15
10
8
Gain (dB)
Input VOS (µV)
12
4
Sample Average
0
−4
−8
5
0
−5
−10
−12
−15
−16
−20
−50
−20
−25
25
0
75
50
100
125
10
150
100
1k
10k
DIFFERENTIAL AMPLIFIER:
PSRR AND CMRR vs FREQUENCY
DIFFERENTIAL AMPLIFIER:
OUTPUT VOLTAGE vs OUTPUT CURRENT
5.0
−40_ C
PSRR
+25_C
Output Voltage (V)
CMRR
80
60
40
+125_ C
4.8
+85_C
4.7
0.3
+85_ C
+125_C
0.2
20
0.1
0
0
−40_ C
+25_ C
10
100
1k
10k
100k
1M 2M
0
1
2
3
4
5
6
25
1000
Short−Circuit Current (mA)
Noise Density (nV/√Hz)
100
Autozero Frequency = 69kHz
Sensor Not Running
en = 162nV/√Hz (average over 250Hz to 50kHz)
10k
9
10
VOUT Shorted to 5V
20
1k
8
DIFFERENTIAL AMPLIFIER:
SHORT−CIRCUIT CURRENT vs TEMPERATURE
DIFFERENTIAL AMPLIFIER:
OUTPUT NOISE DENSITY
100
7
Load Current (mA)
Frequency (Hz)
100k
15
10
5
0
−5
−10
−15
−20
1M
−25
−50
VOUT Shorted to 0V
−25
Frequency (Hz)
8
10M
4.9
100
10
1M
Frequency (Hz)
120
PSRR and CMRR (dB)
100k
Temperature (_C)
0
25
50
75
100
125
150
Temperature (_ C)
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VDD1 = VDD2 = +5 V with external 100 kHz filter BW, unless otherwise noted.
DIFFERENTIAL AMPLIFIER:
TA = +25_C LARGE−SIGNAL STEP RESPONSE
3.8
3.8
3.6
3.4
3.6
3.2
3.4
3.2
3.0
3.0
Voltage (V)
Voltage (V)
DIFFERENTIAL AMPLIFIER:
TA = −50_C LARGE−SIGNAL STEP RESPONSE
2.8
2.6
2.4
2.8
2.6
2.4
2.2
2.2
2.0
2.0
1.8
1.6
1.8
1.6
1.4
1.4
1µs/div
1µs/div
DIFFERENTIAL AMPLIFIER:
OVER−RANGE DELAY vs TEMPERATURE
3.8
3.5
3.6
3.4
3.4
3.2
3.3
Over−Range Delay (µs)
Voltage (V)
DIFFERENTIAL AMPLIFIER:
TA = +150_C LARGE−SIGNAL STEP RESPONSE
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
At 5.0V
VIN Step 0V to ±1V
3.2
Negative Over−Range
3.1
3.0
2.9
Positive Over−Range
2.8
2.7
2.6
2.5
1.4
1µs/div
−50
−25
0
25
50
75
100
125
150
Temperature (_ C)
DIFFERENTIAL AMPLIFIER:
NEGATIVE SLEW RATE vs TEMPERATURE
DIFFERENTIAL AMPLIFIER:
POSITIVE SLEW RATE vs TEMPERATURE
−6.5
At 5.0V
7.4
−6.6
7.3
−6.7
7.2
−6.8
Slew Rate (V/µs)
Slew Rate (V/µs)
7.5
7.1
7.0
6.9
6.8
−6.9
−7.0
−7.1
−7.2
6.7
−7.3
6.6
−7.4
6.5
−50
−25
0
25
50
75
100
125
150
At 5.0V
−7.5
−50
−25
0
25
50
75
100
125
150
Temperature (_ C)
Temperature (_ C)
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VDD1 = VDD2 = +5 V with external 100 kHz filter BW, unless otherwise noted.
Gain VPWMAVERAGE /(VICOMP1, VICOMP2) (dB)
DIFFERENTIAL AMPLIFIER:
REFIN RESISTANCE vs TEMPERATURE
50.250
RREF IN (kΩ )
50.125
50.000
49.875
49.750
49.625
−50
−25
0
25
50
75
100
125
COMPENSATION LOOP:
SMALL−SIGNAL GAIN
70
60
50
Pin Gain = Low
40
Pin Gain = High
30
20
10
0
100
150
1k
100k
COMPENSATION LOOP:
DC GAIN: DUTY CYCLE ERROR CHANGE
COMPENSATION LOOP:
DUTY CYCLE ERROR vs TEMPERATURE
2000
VICOMP1 − VICOMP2 = 4.2V
ILOAD = 210mA
1500
Gain Pin Low
1000
500
Population
Duty Cycle Error (ppm)
10k
Frequency (Hz)
Temperature (_ C)
0
At 250kHz, 5.0V
−500
−1000
At 400kHz, 5.0V
−2000
−50
−25
0
25
50
75
100
125
−200
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
200
−1500
150
Temperature (_ C)
Gain (ppm/V)
ICOMP OUTPUT SWING TO RAIL
vs OUTPUT CURRENT
5.00
4.75
+125_C
Output Swing (V)
4.50
−50_ C
+25_ C
4.25
4.00
1.00
0.75
0.50
+125_C +25_ C
−50_ C
0.25
0
0
50
100
150
200
250
300
Probe Comparator Threshold Current (mA)
PROBE COMPARATOR THRESHOLD
CURRENT vs TEMPERATURE
35.0
32.5
30.0
27.5
25.0
−50
−25
10
0
25
50
75
100
125
150
Temperature (_ C)
Output Current (mA)
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VDD1 = VDD2 = +5 V with external 100 kHz filter BW, unless otherwise noted.
OUTPUT IMPEDANCE MISMATCH OF IS1 AND IS2
vs TEMPERATURE
PROBE DRIVER:
INTERNAL RESISTOR vs TEMPERATURE
90
Output Impedance Mismatch (Ω)
0.10
85
80
Resistance (Ω)
Driver L
75
70
65
60
Driver H
55
50
45
−50
−25
0.08
0.06
0.04
0.02
0
0
25
50
75
100
125
150
−50
−25
0
Temperature (_ C)
25
50
75
100
125
150
Temperature (_ C)
VOLTAGE REFERENCE PRODUCTION DISTRIBUTION
VOLTAGE REFERENCE vs LOAD CURRENT
2.5010
2.5008
2.5006
Population
VREF (V)
2.5004
2.5002
2.5000
2.4998
2.4996
2.4994
2.4990
−6
−4
−2
0
2
4
2.4950
2.4955
2.4960
2.4965
2.4970
2.4975
2.4980
2.4985
2.4990
2.4995
2.5000
2.5005
2.5010
2.5015
2.5020
2.5025
2.5030
2.5035
2.5040
2.5045
2.5050
2.4992
6
ILOAD (mA)
VREF (V)
VOLTAGE REFERENCE vs TEMPERATURE
VOLTAGE REFERENCE DRIFT
PRODUCTION DISTRIBUTION
2.525
2.520
2.515
Population
VREF (V)
2.510
2.505
2.500
2.495
2.490
2.485
2.480
−50
0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
27.5
30.0
32.5
35.0
37.5
40.0
42.5
45.0
47.5
50.0
2.475
−25
0
25
50
75
100
125
150
Temperature (_ C)
Voltage Reference Drift (ppm/_ C)
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VDD1 = VDD2 = +5 V with external 100 kHz filter BW, unless otherwise noted.
OSCILLATOR PRODUCTION DISTRIBUTION
250
253
256
259
262
265
268
271
274
277
280
283
286
289
292
295
298
301
304
307
310
200
150
175
100
125
50
75
0
25
−25
−75
−50
−125
−100
−175
−150
−200
Population
Population
VOLTAGE REFERENCE POWER−SUPPLY REJECTION
PRODUCTION DISTRIBUTION
Minimum Probe Loop Half−Cycle (ns)
PSR (µV/V)
OSCILLATOR vs SUPPLY VOLTAGE
OSCILLATOR vs TEMPERATURE
310
Minimum Probe Loop Half−Cycle (ns)
Minimum Probe Loop Half−Cycle (ns)
310
305
300
295
290
285
280
275
270
265
260
255
250
−50
−25
0
25
50
75
100
125
305
300
295
290
285
280
275
270
265
260
255
250
4.3
150
4.6
4.9
Temperature (_C)
5.2
5.5
5.8
6.0
VDD (V)
BROWN−OUT VOLTAGE vs TEMPERATURE
4.20
Brown−Out Voltage (V)
4.15
4.10
4.05
4.00
3.95
3.90
3.85
3.80
−50
−25
0
25
50
75
100
125
150
Temperature (_ C)
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APPLICATION INFORMATION
FUNCTIONAL PRINCIPLE OF CLOSED-LOOP CURRENT SENSORS WITH MAGNETIC PROBE
USING THE DRV401
Closed-loop current sensors measure current over wide frequency ranges, including dc. These types of devices
offer a contact-free method as well as excellent galvanic isolation performance combined with high resolution,
accuracy, and reliability.
At dc and in low-frequency ranges, the magnetic field induced from the current in the primary winding is
compensated by a current flowing through a compensation winding. A magnetic field probe, located in the
magnetic core loop, detects the magnetic flux. This probe delivers the signal to the amplifier that drives the
current through the compensation coil, bringing the magnetic flux back to zero. This compensation current is
proportional to the primary current, relative to the winding ratio.
In higher frequency ranges, the compensation winding acts as the secondary winding in the current transformer,
while the H-bridge compensation driver is rolled off and provides low output impedance.
A difference amplifier senses the voltage across a small shunt resistor that is connected to the compensation
loop. This difference amplifier generates the output voltage that is referenced to REFIN and is proportional to the
primary current. Figure 1 shows the DRV401 used as a compensation current sensor.
Compensation
RS
ICOMP1
Compensation Winding
Primary Winding
ICOMP2
DRV401
Diff
Amp
Magnetic Core
Field Probe
IS2
IP
VOUT
REFIN
IS1
Probe
Interface
Integrator
Filter
Timing, Error Detection,
and Power Control
H−Bridge
Driver
Degauss
VREF
VREF
+5V GND
Figure 1. Principle of Compensation Current Sensor With the DRV401
FUNCTIONAL DESCRIPTION
The DRV401 operates from a single +5 V supply. It is a complete sensor signal conditioning circuit that directly
connects to the current sensor, providing all necessary functions for the sensor operation. The DRV401 provides
magnetic field probe excitation, signal conditioning, and compensation coil driver amplification. In addition, it
detects error conditions and handles overload situations. A precise differential amplifier allows translation of the
compensation current into an output voltage using a small shunt resistor. A buffered voltage reference can be
used for comparator, analog-to-digital converter (ADC), or bipolar zero reference voltages.
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Dynamic error correction ensures high dc precision over temperature and long-term accuracy. The DRV401 uses
analog signal conditioning; the internal loop filter and integrator are switched capacitor-based circuits. Therefore,
the DRV401 allows combination with high-precision sensors for exceptional accuracy and resolution. The typical
characteristic curve, DRV401 and Sensor Linearity, shows an example of the linearity and temperature stability
achieved by the device.
A demagnetization cycle can be initiated on demand or on power-up. This cycle reduces offset and restores high
performance after a strong overload condition. An internal clock and counter logic generate the degauss function.
The same clock controls power-up, overload detection and recovery, error, and time-out conditions.
The DRV401 is built on a highly reliable CMOS process. Unique protection cells at critical connections enable the
design to handle inductive energy.
MAGNETIC PROBE (SENSOR) INTERFACE
The magnetic field probe consists of an inductor wound on a soft magnetic core. The probe is connected
between pins IS1 and IS2 of the probe driver that applies approximately +5 V (the supply voltage) through
resistors across the probe coil (see Figure 2a).
The probe core reaches saturation at a current of typically 28 mA (see Figure 2a). The comparator is connected
to VREF by approximately 0.5 V. A current comparator detects the saturation and inverts the excitation voltage
polarity, causing the probe circuit to oscillate in a frequency range of 250 kHz to 550 kHz. The oscillating
frequency is a function of the magnetic properties of the probe core and its coil.
The current rise rate is a function of the coil inductance: dI = L × V × dT. However, the inductance of the field
probe is low while its core material is in saturation (the horizontal part of the hysteresis curve) and is high at the
vertical part of the hysteresis curve. The resulting inductance and the series resistance determine the output
voltage and current versus time performance characteristic.
Without external magnetic influence, the duty cycle is exactly 50% because of the inherent symmetry of the
magnetic hysteresis; the probe inductor is driven from –B saturation through the high inductance range to +B
saturation and back again in a time-symmetric manner (see Figure 2b).
If the core material is magnetized in one direction, a long and a short charge time result because the probe
current through the inductors generates a field that either subtracts or adds to the flux in the probe core, either
driving the probe core out of saturation or further into saturation (see Figure 2c). The current into the probe is
limited by the voltage drops across the probe driver resistors.
The DRV401 continuously monitors the logic magnetic flux polarity state. In the case of distortion noise and
excessive overload that could fully saturate the probe, the overload control circuit recovers the probe loop.
During an overload condition, the probe oscillation frequency increases to approximately 1.6 MHz until limited by
the internal timing control.
In an overload condition, the compensation current (ICOMP) driver cannot deliver enough current into the sensor
secondary winding, and the magnetic flux in the sensor main core becomes uncompensated.
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VDD1
Probe
55Ω
55Ω
IS2
IS1
CMP
18Ω
PWM
VREF = 0.5V
NOTE: MOS components function as switches only.
a) Simplified probe interface circuit.
The probe is connected between S1 and S2.
B
B
H
2V/div
V (IS1)
2V/div
V (IS1)
500mV/div
V (PWM)/10
500mV/div
H
V (PWM)/10
500ns/div
500ns/div
b) Without an external magnetic field, the hysteresis curve is
symmetrical and the probe loop generates 50% duty cycle.
c) An external magnetic flux (H) generated from the primary current
(IPRIM) shifts the hysteresis curve of the magnetic field probe in the
H-axis and the probe loop generates a nonsymmetrical duty cycle.
Figure 2. Magnetic Probe, Hysteresis, and Duty Cycle
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The transition from normal operation to overload happens relatively slowly, because the inherent sensor
transformer characteristics induce the initial primary current step, as shown in Figure 3. As the
transformer-induced secondary current starts to decay, the compensation feedback driver increases its output
voltage to maintain the sensor core flux compensation at zero.
When the system compensation loop reaches its driving limit, the rising magnetic flux causes one of the probe
PWM half-periods to become shorter. The minimum half-period of the probe oscillation is limited by the internal
timing to 280 ns, based on the properties of the VAC magnetic sensors. After three consecutive cycles of the
same half-period being shorter than 280 ns, the DRV401 goes into overload-latch mode. The device stores the
ICOMP driver output signal polarity and continues producing the skewed-duty cycle PWM signal. This action
prevents the loss of compensation signal polarity information during very strong overloads. In this case, both
PWM half-periods are short and approximately equal, because the field probe stays completely in one of the
saturated regions.
The overload-latch condition is removed after the primary current goes low enough for the ICOMP driver to
compensate, and both half-periods of the probe driver oscillation become longer than 280ns (the field probe
comes out of the saturated region).
Peak voltages and currents can be generated during normal operations as well as overload conditions.
Therefore, both probe connection pins are internally protected against coupled energy from the magnetic core.
Wiring between probe and IC inputs should be short and guarded against interference; see Layout
Considerations.For reliable operation, error detection circuits monitor the probe operation:
1. If the probe driver comparator (CMP) output stays low longer than 32 µs, the ERROR flag asserts active, and
the compensation current (ICOMP) is set to zero.
2. If the probe driver period is less than 275 ns on three consecutive pulses, the ERROR flag asserts active.
See the Error Conditions section for more details.
PWM PROCESSING
The outputs PWM and PWM represent the probe output signal as a differential PWM signal. It can drive external
circuitry or be used for synchronous ripple reduction. The PWM signal from the probe excitation and sense stage
is internally connected to a high-performance, switched-capacitor integrator followed by an
integrating-differentiating filter. This filter converts the PWM signal into a filtered delta signal and prepares it for
driving the analog compensation coil driver. The gain roll-off frequency of the filter stage is set to provide high dc
gain and loop stability. If additional gain is added from external circuitry, the internal gain can be reduced by
8 dB, asserting the GAIN pin high (see the External Compensation Coil Driver section).
V(1Ω× IPRIM/10)
1
I COMP1
3
4
Sensor: 4 x 100
RSH = 10Ω
Step Response
2kHz In
V(Gain) = Low
ICOMP2
Channel 1: 2V/div
Channels 2−4: 500mV/div
2
VOUT
50µs/div
A current pulse of 0A to 18A (Ch 1) generates the two ICOMP signals (Ch 3 and Ch 4). Ch 2 shows the resulting output signal,
VOUT. This test uses the M4645-X030 sensor, no bandwidth limitation, but a 20-sample average.
Figure 3. Primary Current Step Response
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COMPENSATION DRIVER
The compensation coil driver provides the driving current for the compensation coil. A fully differential driver
stage offers high signal voltages to overcome the wire resistance of the coil with only +5 V supply. The
compensation coil is connected between ICOMP1 and ICOMP2, both generating an analog voltage across the coil
(see Figure 3) that turns into current from the wire resistance (and eventually from the inductance). The
compensation current represents the primary current transformed by the turns ratio. A shunt resistor is connected
in this loop and the high-precision difference amplifier translates the voltage from this shunt to an output voltage.
Both compensation driver outputs provide low impedance over a wide frequency range to ensure smooth
transitions between the closed-loop compensation frequency range and the high-frequency range, where the
primary winding directly couples the primary current into the compensation coil at a rate set by the winding ratio.
The two compensation driver outputs are designed with protection circuitry to handle inductive energy. However,
additional external protection diodes might be necessary for high current sensors.
For reliable operation, a wire break in the compensation circuit can be detected. If the feedback loop is broken,
the integrating filter drives the outputs ICOMP1 and ICOMP2 to the opposite rails. With one of these pins coming
within 300 mV to ground, a comparator tests for a minimum current flowing between ICOMP1 and ICOMP2. If this
current stays below the threshold current level for at least 100 µs, the ERROR pin is asserted active (low). The
threshold current level for this test is less than 57 mA at 25°C and 65 mA at –40°C, if the ICOMP pins are fully
railed (see the Typical Characteristics). For sensors with high winding resistance (compensation coil resistance +
RSHUNT) or connected to an external compensation driver, this function should be disabled by pulling the CCdiag
pin low.
V
R MAX + OUT
65mA
Where:
VOUT equals the peak voltage between ICOMP1 and ICOMP2 at a 65mA drive current.
RMAX equals the sum of the coil and the shunt resistance.
EXTERNAL COMPENSATION COIL DRIVER
An external driver for the compensation coil can be connected to the ICOMP1 and ICOMP2 outputs. To prevent a
wire break indication, CCdiag has to be asserted low.
An external driver can provide both a higher drive voltage and more drive current. It also moves the power
dissipation to the external transistors, thereby allowing a higher winding resistance in the compensation coil and
more current. Figure 4 shows a block diagram of an external compensation coil driver. To drive the buffer, either
one or both ICOMP outputs can be used. Note, however, that the additional voltage gain could cause instability of
the loop. Therefore, the internal gain can be reduced by approximately 8 dB by asserting the GAIN pin high.
RSHUNT is connected to GND to allow for a single-ended external compensation driver. The differential amplifier
can continue to sense the voltage, and used for the gain and over-range comparator or ERROR flag.
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V+
DRV401
ICOMP1
External
Buffer
Compensation
Coil
ICOMP2
V−
RSHUNT
Figure 4. DRV401 With External Compensation Coil Driver and RSHUNT Connected to GND
SHUNT SENSE AMPLIFIER
The differential (H-bridge) driver arrangement for the compensation coil requires a differential sense amplifier for
the shunt voltage. This differential amplifier offers wide bandwidth and a high slew rate for fast current sensors.
Excellent dc stability and accuracy result from an auto-zero technique. The voltage gain is 4 V/V, set by precisely
matched and stable internal SiCr resistors.
Both inputs of the differential amplifier are normally connected to the current shunt resistor. This resistor adds to
the internal (10 kΩ) resistor, slightly reducing the gain in this leg. For best common-mode rejection (CMR), a
dummy shunt resistor (R5) is placed in series with the REFIN pin to restore matching of both resistor dividers, as
shown in Figure 5a.
For gains of 4 V/V:
R
R4 ) R5
4+ 2+
R1
RSHUNT ) R3
With R2/R1 = R4/R3 = 4; R5 = RSHUNT × 4
Typically, the gain error resulting from the resistance of RSHUNT is negligible; for 70 dB of common-mode
rejection, however, the match of both divider ratios needs to be better than 1/3000.
The amplifier output can drive close to the supply rails, and is designed to drive the input of a SAR-type ADC;
adding an RC low-pass filter stage between the DRV401 and the ADC is recommended. This filter not only limits
the signal bandwidth but also decouples the high-frequency component of the converter input sampling noise
from the amplifier output. For RF and CF values, refer to the specific converter recommendations in the specific
product data sheet. Empirical evaluation may be necessary to obtain optimum results.
The output can drive 100 pF directly and shows 50% overshoot with approximately 1 nF capacitance. Adding RF
allows much larger capacitive loads, as shown in Figure 5b and Figure 5c. Note that with RF of only 20 Ω, the
load capacitor should be either smaller than 1 nF or larger than 33 nF to avoid overshoot; with RF of 50 Ω this
transient area is avoided.
The reference input (REFIN) is the reference node for the exact output signal (VOUT). Connecting REFIN to the
reference output (REFOUT) results in a live zero reference voltage of 2.5 V. Using the same reference for REFIN
and the ADC avoids mismatch errors that exist between two reference sources.
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ICOMP2
DRV401 Differential Amplifier Section
R1
10kΩ
R2
40kΩ
Decoupling, Low−Pass Filter
RF
50Ω
VOUT
R SHUNT
ADC
Differential
Amplifier
R3
10kΩ
K2
R4
40kΩ
REFIN
R5
Dummy
Shunt
CF
10nF
Compensated
REFIN
NOTE: R5 is a dummy shunt resistor equal to 4x RSHUNT to compensate for RSHUNT and provide best CMR.
20mV/div
20mV/div
a) Internal difference amplifier with an example of a decoupling filter.
10µs/div
10µs/div
b) VOUT of Figure 5a with R5 = 20Ω and CD = 100nF.
c) VOUT of Figure 5a with R5 = 50Ω and CD = 10nF.
Figure 5. Internal Difference Amplifier With Example of a Decoupling Filter
OVER-RANGE COMPARATOR
High peak current can overload the differential amplifier connected to the shunt. The OVER-RANGE pin, an
open-drain output, indicates an over-voltage condition for the differential amplifier by pulling low. The output of
this flag is suppressed for 3 µs, preventing unwanted triggering from transients and noise. This pin returns to
high as soon as the overload condition is removed (external pull-up required to return the pin high).
This ERROR flag not only provides a warning about a signal clipping condition, but is also a window comparator
output for actively shutting off circuits in the system. The value of the shunt resistor defines the operating window
for the current. It sets the ratio between the nominal signal and the trip level of the Over-Range flag. The trip
current of this window comparator is calculated using the following example:
With a 5 V supply, the output voltage swing is approximately ±2.45 V (load and supply
voltage-dependent).
The gain of 4 V/V allows an input swing of ±0.6125 V.
Thus, the clipping current is IMAX = 0.6125 V/RSHUNT.
See the differential amplifier curve of the Typical Characteristics, Output Voltage vs Output Current.
The over-range condition is internally detected as soon as the amplifier exceeds its linear operating range, not
just a set voltage level. Therefore, the error or the over-range comparator level is reliably indicated in fault
conditions such as output shorts, low load or low supply conditions. As soon as the output cannot drive the
voltage higher, the flag is activated. This configuration is a safety improvement over a voltage level comparator.
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NOTE:
The internal resistance of the compensation coil may prevent high compensation
current from flowing because of ICOMP driver overload. Therefore, the differential
amplifier may not overload with this current. However, a fast rate of change of the
primary current would be transmitted through transformer action and safely trigger the
overload flag.
VOLTAGE REFERENCE
The precision 2.5 V reference circuit offers low drift (typically 10 ppm/K) and is used for internal biasing; it is also
connected to the REFOUT pin. The circuit is intended as the reference point of the output signal to allow a bipolar
signal around it. This output is buffered for low impedance and tolerates sink and source currents of ±5 mA.
Capacitive loads can be directly connected, but generate ringing on fast load transients. A small series resistor of
a few ohms improves the response, especially for a capacitive load in the range of 1 µF. Figure 6 shows the
transient load regulation with 1 nF direct load.
The reference source is part of the integrated circuit and referenced to GND2. Large current pulses driving the
compensation coil can generate a voltage drop in the GND connection that would add on to the reference
voltage. Therefore, a low impedance GND layout is critical to handle the currents and the high bandwidth of this
IC.
Test Circuit:
±5V
1nF
10mV/div
10kΩ
REFOUT
+2.5V
2.5µs/div
Figure 6. Pulse Response Test Circuit and Scope Shot of Reference
DEMAGNETIZATION
Iron cores are not immune to residual (remanence) magnetism. The residual remanence can produce a signal
offset error, especially after strong current overload, which goes along with high magnetic field density.
Therefore, the DRV401 includes a signal generator for a demagnetization cycle. The digital control pin, DEMAG,
starts this cycle on demand after this pin is held high for at least 25.6 µs. Shorter pulses are ignored. The cycle
lasts for approximately 110 ms. During this time, the Error flag is asserted low to indicate that the output is not
valid. When DEMAG is high during power-on, a demagnetization cycle immediately initiates (12 µs) after
power-on (VDD > 4 V). Holding DEMAG low avoids this cycle at power-up (see the Power-On and Brownout
section).
The probe circuit is in normal operation and oscillates during the demagnetization cycle. The outputs PWM and
PWM are active accordingly.
A demagnetization cycle can be aborted by pulling DEMAG low, filtered by 25 µs to ignore glitches (see
Figure 7). In a typical circuit, the DEMAG pin may be connected to the positive supply, which enables a degauss
cycle every time the unit is powered on.
The degauss cycle is based on an internal clock and counter logic. The maximum current is limited by the
resistance of the connected coil in series with the shunt resistor. The DEMAG logic input requires a +5 V
CMOS-compatible signal.
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POWER-ON AND BROWNOUT
Power-on is detected with the supply voltage going higher than 4 V at VDD1. When DEMAG is high, a degauss
cycle is started (see Figure 7a). During this time the ERROR flag remains low, indicating the not ready condition.
Maintaining DEMAG low prevents this cycle, and the DRV401 starts operation approximately 32 µs after
power-up. If no probe error conditions are detected within four full cycles (that is, the probe half-periods are
shorter than 32 µs and longer than 280 ns), the compensation driver starts and the ERROR pin indicates the
ready condition by going high, typically about 42 µs after power-up.
NOTE:
An external pull-up resistor is required to pull the ERROR pin high.
Both supply pins (VDD1 and VDD2) should not differ by more than 100 mV for proper device operation. They are
normally connected together or separately filtered (see Layout Considerations).
The DRV401 tests for low supply voltage with a brown-out voltage level of +4 V; proper power conditions must
be supplied. Good power-supply and low ESR bypass capacitors are required to maintain the supply voltage
during the large current pulses that the DRV401 can drive.
A critical voltage level is derived from the proper operation of the probe driver. The probe interface relies on a
peak current flowing through the probe to trip the comparator. The probe resistance plus the internal resistance
of the driver (see Electrical Characteristics specification, Probe Coil Loop, Internal Resistor) sets the lower limit
for the acceptable supply voltage. Voltage drops lasting less than 31 ms are ignored. The probe error detection
activates the ERROR pin as soon as proper oscillation fails for more than 32 µs.
A low supply voltage condition, or brown-out, is detected at +4 V. Short and light voltage drops of less than
100 µs are ignored, provided the probe circuit continues to operate. If the probe no longer operates, the ERROR
pin goes active. Signal overload recovery is only provided if the probe loop was not discontinued.
A supply drop lasting longer than 100 µs generates power-on reset. A voltage dip down to +1.8 V (for VDD1) also
initiates a power-on reset.
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VDD1
5V/div
V(ERROR)
106ms
1
4
V(ICOMP2)
RSH = 10Ω
2V/div
2
VOUT
3
20ms/div
a) Demagnetization cycle on power-up. With power-up, the VOUT across the compensation coil centers around half the supply and then
starts the cycle after the 4V threshold is exceeded. The ERROR flag resets to H after the cycle is completed.
VDD1
V(DEMAG)
42µs
1
5V/div
5V/div
1
V(ERROR)
4
4
106ms
V(IS1)
V(ERROR)
V(ICOMP2)
2
V(ICOMP2)
Initial setting upon
closing of feedback loop.
3
RSH = 10Ω
2V/div
2V/div
2
VOUT
3
20ms/div
20ms/div
c) Demagnetization cycle on command.
b) Power-up without demagnetization. The probe oscillation V(IS1)
starts just before ERROR resets — 15µs after the supply voltage
crosses the 4V threshold.
V(DEMAG)
5V/div
1
V(ERROR)
4
V(ICOMP2)
RSH = 10Ω
2
2V/div
3.4ms
VOUT
3
500µs/div
d) Abort of demagnetization cycle. The ERROR flag resets to H (as shown) and the output settles back to normal operation.
Figure 7. Demagnetization and Power-On Timing
22
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ERROR CONDITIONS
In addition to the Over-Range flag that indicates signal clipping in the output amplifier (differential amplifier), a
system error flag is provided. The ERROR flag indicates conditions when the output voltage does not represent
the primary current. It is active during a demagnetization cycle, during a power-fail or brown-out. It also goes
active with an open or short-circuit in the probe loop. As soon as the error condition is no longer present and the
circuit has returned to normal operation, the flag resets.
Both the ERROR and Over-Range flags are open-drain logic outputs. They can be connected together for a
wired-OR and require an external pull-up resistor for proper operation.
The following conditions result in ERROR flag activation (ERROR asserts low):
1. The probe comparator stays low for more than 32 µs. This condition occurs either if the probe coil connection
is open or if the supply voltage dips to the level where the required saturation current cannot be reached.
During the 32 µs timeout, the ICOMP driver remains active but goes inactive thereafter. In case of recovery,
ERROR is low and the ICOMP driver remains in reset for another 3.3 ms.
2. The probe driver pulse-width is less than 280 ns for three consecutive periods. This condition indicates either
a shorted field probe coil or a fully-saturated sensor at start-up. If this condition persists longer than 25 µs
and then recovers, the ERROR flag remains low and ICOMP is in reset for another 3.3 ms. If the condition
lasts less than 25 µs, the ERROR flag recovers immediately and the ICOMP driver is not interrupted.
3. During demagnetization, if the cycle is aborted early by pulling DEMAG low, the ERROR flag stays low for
another 3.3 ms (ICOMP is disabled during this time).
4. An open compensation coil is detected (longer than 100 µs). Note: the probe driver, the PWM signal filter
and the ICOMP driver continue to function in normal mode—only the ERROR flag is asserted in this case. This
condition indicates that not enough current is flowing in the ICOMP driver output; this condition might be the
result of a high-resistance compensation coil or the connection of an external driver. Detection of this
condition can be disabled by setting the CCdiag pin low.
5. At power-on after VDD1 crosses the +4 V threshold, the ERROR flag is low for approximately 42 µs.
6. A supply voltage low (brown-out) condition lasts longer than 100 µs. Recovery is the same as power-up,
either with or without a demag cycle.
PROTECTION RECOMMENDATIONS
The inputs IAIN1 and IAIN2 require external protection to limit the voltage swing beyond 10 V of the supply voltage.
The driver outputs ICOMP1 and ICOMP2 can handle high current pulses protected by internal clamp circuits to the
supply voltage. If repeated over-currents of large magnitudes are expected, connect external Schottky diodes to
the supply rails. This external protection prevents current flowing into the die.
The probe connections IS1 and IS2 are protected with diode clamps to the supply rails. In normal applications,
no external protection is required. The maximum current must be limited to ±75 mA.
All other pins offer standard protection-see the Absolute Maximum Ratings table.
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BASIC CONNECTION EXAMPLE
The circuit shown in Figure 8 offers an axample of a fully-connected current sensor system.
IP
Primary Winding
Current Sensor Module
Probe
Core
Main Core
Probe Coil
S1
Compensation Coil
K1
S2
K2
+5V
IS2
ICOMP
R3
R4
C4
D1
C3
R2
D2
R1
+5V
IS1
IS2
PWM
GAIN
PWM
CCdiag
ICOMP1
ICOMP2
(PWM is in
phase with IS1.)
+5V
VDD1
C2
Probe Coil
Driver and
Comparator
IAIN2
IAIN1
Amp
V=4
+5V
R6
Integrator
OVER−RANGE
H−Bridge
Driver
VSW
R5
GND1
VOUT
REFIN
VSW
2.5V
Bandgap
Reference
REFOUT
10MHz
DEMAG
Logic: Timing, Error Detection, and Demagnetize
Oscillator Reset
Power Valid
DRV401
R7
ERROR
VDD2
GND2
C4
+5V
+5V
Figure 8. Basic Connection Circuit
24
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The connection example in Figure 8 illustrates the few external components required for optimal performance.
Each component is described in the following list:
• IP is the primary current to be measured; K1 and K2 connect to the compensation coil. S1 and S2 connect to
the magnetic field probe. The dots indicate the winding direction on the sensor main core.
• R1 and R2 form the shunt resistor RSHUNT. This resistance is split into two to allow for adjustments to the
required RSHUNT value. The accuracy and temperature stability of these resistors are part of the final system
performance.
• R3 and R4, together with C3 and C4, form a network that reduces the remaining probe oscillator ripple in the
output signal. The component values depend on the sensor type and are tailored for best results. This
network is not required for normal operation.
• R5 is the dummy shunt (RD) resistor used to restore the symmetry of both differential amplifier inputs. R5 = 4
× RSHUNT, but the accuracy is less important.
• R6 and R7 are pull-up resistors connected to the logic outputs.
• C1 and C2 are decoupling capacitors. Use low ESR-type capacitors connected close to the pins. Use low
impedance printed circuit board (PCB) traces, either avoiding vias (plated-through holes) or using multiple
vias. A combination of a large(> 1 µF) and a small (< 4.7 nF) capacitor are suggested. When selecting
capacitors, make sure to consider the large pulse currents handled from the DRV401.
• D1 and D2 are protection diodes for the differential amplifier input. They are needed only if the voltage drop at
RSHUNT exceeds 10 V at the maximum possible peak current.
LAYOUT CONSIDERATIONS
The DRV401 operates with relatively large currents and fast current pulses, and offers wide-bandwidth
performance. It is often exposed to large distortion energy from both the primary signal and the operating
environment. Therefore, the wiring layout must provide shielding and low-impedance connections between critical
points.
Use low ESR capacitors for power-supply decoupling. Use a combination of a small capacitor and a large
capacitor of 1 µF or larger. Use low-impedance tracks to connect the capacitors to the pins.
Both grounds should be connected to a local ground plane. Both supplies can be connected together; however,
best results are achieved with separate decoupling (to the local GND plane) and ferrite beads in series with the
main supply. The ferrite beads decouple the DRV401, reducing interaction with other circuits powered from the
same supply voltage source.
The reference output is referred to GND2. A low-impedance, star-type connection is required to avoid the driver
current and the probe current modulating the voltage drop on the ground track.
The connection wires of the difference amplifier to the shunt must be low resistance and of equal length. For best
accuracy, avoid current in this connection. Consider using a Kelvin Contact-type connection. The required
resistance value can be set using two resistors.
Wires and PCB traces for S1 and S2 should be very close or twisted. ICOMP1 and ICOMP2 should also be wired
close together. To avoid capacitive coupling, run a ground shield between the S1/S2 and ICOMP wire pair or
keep them distant from each other.
The compensation driver outputs (ICOMP) are low frequency only; however, the primary signal (with
high-frequency content present) is coupled into the compensation winding, the shunt, and the difference
amplifier. Therefore, careful layout is recommended.
The output of REFOUT and VOUT can drive some capacitive loads, but avoid large direct capacitive loads; these
loads increase internal pulse currents. Given the wide bandwidth of the differential amplifier, isolate any large
capacitive load with a small series resistor. A small capacitor in the pF range can improve the transient response
on a high resistive load.
The exposed thermal pad on the bottom of the package must be soldered to GND because it is internally
connected to the substrate, which must be connected to the most negative potential. It is also necessary to
solder the exposed pad to the PCB to provide structural integrity and long-term reliability.
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POWER DISSIPATION
Using the thermally-enhanced PowerPAD™ SO package dramatically reduces the thermal impedance from
junction to case. This package is constructed using a down-set lead frame upon which the die is mounted, as
shown in Figure 9a and Figure 9b. This arrangement results in the lead frame being exposed as a thermal pad
on the underside of the package. Figure 9 shows the SO-20 package as an example. Because this thermal pad
has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good
thermal path away from the thermal pad.
The two outputs ICOMP1 and ICOMP2 are linear outputs. Therefore, the power dissipation on each output is
proportional to the current multiplied by the internal voltage drop on the active transistor. For ICOMP1 and ICOMP2,
this internal voltage drop is the voltage drop to VDD2 or GND, according to the current-conducting side of the
output.
Output short-circuits are particularly critical for the driver because the full supply voltage can be seen across the
conducting transistor, and the current is not limited by anything other than the current density limitation of the
FET. Permanent damage to the device can occur.
The DRV401 does not include temperature protection or thermal shut-down.
THERMAL PAD
Packages with an exposed thermal pad are specifically designed to provide excellent power dissipation, but
board layout greatly influences overall heat dissipation. Table 1 shows the thermal resistance (TJA) for the two
packages with the exposed thermal pad soldered to a normal PCB, as described in Technical Brief SLMA002,
PowerPAD Thermally-Enhanced Package. Documents are available for download at www.ti.com.
Table 1. θJA/JP Estimations According to EIA/JED51-7
SO–20
θJP (1)
9
θJA (2) Still Air
35
θJA with Forced Airflow (150lfm (3))
32
(1)
(2)
(3)
θJP = junction-to-pad thermal resistance,
θJA = junction-to-ambient thermal resistance,
lfm = linear foot per minute.
NOTE:
All thermal models have an accuracy 9≈20%.
Measuring the temperature as close as possible to the exposed thermal pad is recommended. The relatively low
thermal impedance, θJP, of less than 10°C/W (with some additional °C/W to the temperature test point on the
PCB) allows good estimation of the junction temperature in the application.
The thermal pad on the PCB should contain nine or more vias for the SO package, where the solder pad on the
PCB
can
be
larger
than
the
exposed
pad
(for
example,
6.6
mm
×
18 mm) as recommended in the application literature noted previously.
Component population, layout of traces, layers, and air flow strongly influence heat dissipation. Worst-case load
conditions should be tested in the real environment to ensure proper thermal conditions. Minimize thermal stress
for proper long-term operation with a junction temperature well below +125°C.
26
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DIE
Side View (a)
Exposed
Thermal
Pad
DIE
Bottom View (c)
End View (b)
Figure 9. SO-20 Package Example of Thermally Enhanced PowerPAD
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Jul-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DRV401AMDWPREP
ACTIVE
SO
Power
PAD
DWP
20
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
V62/08630-01XE
ACTIVE
SO
Power
PAD
DWP
20
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DRV401AMDWPREP
Package Package Pins
Type Drawing
SO
Power
PAD
DWP
20
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.8
13.0
2.7
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV401AMDWPREP
SO PowerPAD
DWP
20
1000
346.0
346.0
41.0
Pack Materials-Page 2
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